using STMicroelectronics VIPower Technology,
intended for replacement of standard power
MOSFETS in DC to 50 KHz applications.
Built-in thermal shut-down, linear current limi-
BLOCK DIAG RAM
3
2
1
TO-220
tation and overvoltage clamp protect the chip
in harsh enviroments.
Fault feedback can be detected by monitoring the
Thermal Resistance Junction-case Max
Thermal Resistance Junction-ambient Max
1.5
62.5
o
o
o
C
o
C
o
C
C/W
C/W
ELECTRICAL CHARACTERISTICS (T
= 25 oC unless otherwise specified)
case
OFF
SymbolParameterTest ConditionsMin.Typ.Max.Unit
V
CLAMP
Drain-source Clamp
ID = 200 mA V
= 0364248 V
in
Voltage
V
CLTH
Drain-source Clamp
ID = 2 mA V
= 035V
in
Threshold Voltage
V
INCL
Input-Source Reverse
I
= -1 mA-1-0.3V
in
Clamp Voltage
I
I
DSS
ISS
Zero Input Voltage
Drain Current (V
in
Supply Current from
= 0)
= 13 V V
V
DS
V
= 25 V V
DS
= 0
in
= 0
in
50
200
VDS = 0 V Vin = 10 V250500µA
Input Pin
ON (∗)
SymbolParameterTest ConditionsMin.Typ.Max.Unit
V
IN(th)
Input Threshold
V
= Vin ID + Iin = 1 mA0.83V
DS
Voltage
R
DS(on)
Static Drain-source On
Resistance
Vin = 10 V ID = 14 A
V
= 5 V ID = 14 A
in
0.035
0.05
DYNAMIC
µA
µA
Ω
Ω
SymbolParameterTest ConditionsMin.Typ.Max.Unit
g
(∗)Forward
fs
V
= 13 V ID = 14 A1418S
DS
Transconductance
C
Output CapacitanceV
oss
= 13 V f = 1 MHz V
DS
= 0700900pF
in
2/11
VNP28N04
ELECTRICAL CHARACTERISTICS (continued)
SWITCHING (∗∗)
SymbolParameterTest ConditionsMin.Typ.Max.Unit
t
d(on)
t
t
d(off)
t
t
d(on)
t
t
d(off)
t
(di/dt)
Q
Turn-on Delay Time
Rise Time
r
Turn-off Delay Time
Fall Time
f
Turn-on Delay Time
Rise Time
r
Turn-off Delay Time
Fall Time
f
Turn-on Current SlopeV
on
Total Input ChargeVDD = 12 V ID = 10 A V
i
V
= 15 V Id = 14 A
DD
V
= 10 V R
gen
(see figure 3)
V
= 15 V Id = 14 A
DD
V
= 10 V R
gen
(see figure 3)
= 15 V ID = 14 A
DD
V
= 10 V R
in
gen
gen
gen
= 10 Ω
= 1000 Ω
= 10 Ω
= 10 V60nC
in
100
330
400
155
450
1.7
7.5
3.4
35A/µs
SOURCE DRAIN DIO DE
SymbolParameterTest ConditionsMin.Typ.Max.Unit
V
(∗)Forward On VoltageISD = 14 A Vin = 01.6V
SD
trr (∗∗)
Q
rr
I
RRM
(∗∗)
(∗∗)
Reverse Recovery
Time
Reverse Recovery
Charge
Reverse Recovery
Current
I
= 14 A di/dt = 100 A/µs
SD
V
= 30 V Tj = 25 oC
DD
(see test circuit, figure 5)
180
0.45
200
600
700
300
700
3
10
5
7
ns
ns
ns
ns
ns
µs
µs
µs
ns
µC
A
PROTECTION
SymbolParameterTest ConditionsMin.Typ.Max.Unit
I
lim
t
dlim
T
jsh
T
jrs
I
(∗∗)Fault Sink CurrentVin = 10 V VDS = 13 V
gf
E
as
(∗) Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %
(∗∗) Parameters guaranteed by design/characterizat i on
Drain Current LimitVin = 10 V VDS = 13 V
V
= 5 V VDS = 13 V
in
(∗∗) Step Response
Current Limit
Vin = 10 V
V
= 5 V
in
(∗∗) Overtemperature
20
20
150
Shutdown
(∗∗)Overtemperature Reset135
V
= 5 V VDS = 13 V
in
(∗∗)Single Pulse
Avalanche Energy
starting Tj = 25 oC VDD = 20 V
V
= 10 V R
in
= 1 KΩ L = 10 mH
gen
2.5J
28
28
25
70
50
20
40
40
40
120
A
A
µs
µs
o
C
o
C
mA
mA
3/11
VNP28N04
PROTECTION FEATURES
During normal operation, the Input pin is
electrically connected to the gate of the internal
power MOSFET. The device then behaves like a
standard power MOSFET and can be used as a
switch from DC to 50 KHz. The only difference
from the user’s standpoint is that a small DC
current (I
) flows into the Input pin in order to
iss
supply the internal circuitry.
The device integrates:
- OVERVOLTAGE CLAMP PROTECTION:
internally set at 42V, along with the rugged
avalanche characteristics of the Power
MOSFET stage give this device unrivalled
ruggedness and energy handling capability.
This feature is mainly important when driving
inductive loads.
- LINEAR CURRENT LIMITER CIRCUIT: limits
the drain current Id to Ilim whatever the Input
pin voltage. When the current limiter is active,
the device operates in the linear region, so
power dissipation may exceed the capability of
the heatsink. Both case and junction
temperatures increase, and if this phase lasts
long enough, junction temperature may reach
the overtemperature threshold T
jsh
.
- OVERTEMPERATURE AND SHORT CIRCUIT
PROTECTION: these are based on sensing
the chip temperature and are not dependent on
the input voltage. The location of the sensing
element on the chip in the power stage area
ensures fast, accurate detection of the junction
temperature. Overtemperature cutout occurs at
minimum 150
restarted when the chip temperature falls
below 135
o
C. The device is automatically
o
C.
- STATUS FEEDBACK: In the case of an
overtemperature fault condition, a Status
Feedback is provided through the Input pin.
The internal protection circuit disconnects the
input from the gate and connects it instead to
ground via an equivalent resistance of 100 Ω.
The failure can be detected by monitoring the
voltage at the Input pin, which will be close to
ground potential.
Additional features of this device are ESD
protection according to the Human Body model
and the ability to be driven from a TTL Logic
circuit (with a small increase in R
DS(on)
).
4/11
VNP28N04
Thermal Impedance
Output Characteris tics
Derating Curve
Transconductance
Static Drain-Sourc e On Resistance vs Input
Voltage
Static Drain-Source On Resistance
5/11
VNP28N04
Static Drain-Source On Resist ance
Capacitance Variations
Input Charge vs Input Voltage
Normalized Input Threshold Voltage vs
Temperature
Normalized On Resist ance vs Temperat ure
6/11
Normalized On Resistance vs Temperat ure
VNP28N04
Turn-on Current Slope
Turn-off Drain-Source Voltage Slope
Turn-on Current Slope
Turn-off Drain-Source Voltage Slope
Switching Time Resistive Load
Switching Time Resistive Load
7/11
VNP28N04
Switching Time Resistive Load
Step Response Current Limit
Current Limit vs Junction Temperat ure
Source Drain Diode Forward Characteris tic s
8/11
VNP28N04
Fig. 1: Unclamped Inductive Load Test Circuits
Fig. 3: Switching Times Test Circuits For
Resistive Load
Fig. 2: Unclamped Inductive Waveforms
Fig. 4: Input Charge Test Circuit
Fig. 5: Test Circuit For Inductive Load Switching
And Diode Recovery Times
Fig. 6: Waveforms
9/11
VNP28N04
TO-220 MECHANICAL DATA
DIM.
MIN.TYPMAX.
A4.404.60
b0.610.88
b11.151.70
c0.490.70
D15.2515.75
E1010.40
e2.402.70
e14.955.15
F1.231.32
H16.206.60
J12.402.72
L1314
L13.503.93
L2016.40
L3028.90
mm.
∅P3.753.85
Q2.652.95
Package Weight1.9Gr. (T yp .)
10/11
VNP28N04
Information furnished is believed to be accurate and reliable. Ho wev er, STMicroelectr onics assumes no r es ponsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. No license is
granted by implication or otherwise under any patent or patent r ights of STMicr oelectronics . Specifications mentioned in this publication are
subject to c hange withou t notice. This publicatio n s upersedes an d r eplaces all information previously supplied. STM icroelectr on ics product s
are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
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Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A.
The ST logo is a trademark of ST M ic r oelectronic s
2004 STMicroelectronics - Printed in ITALY- All Rights Reserved.
STMicroelectronics GROUP OF COMPANIES
http://www.st.com
11/11
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