ST VNN7NV04P-E, VNS7NV04P-E User Manual

VNN7NV04P-E, VNS7NV04P-E

OMNIFET II fully autoprotected Power MOSFET

Features

	Type	RDS(on)	Ilim	Vclamp
	VNN7NV04P-E	60 mΩ	6 A	40 V
	VNS7NV04P-E

■Linear current limitation

■Thermal shutdown

■Short circuit protection

■Integrated clamp

■Low current drawn from input pin

■Diagnostic feedback through input pin

■ESD protection

■Direct access to the gate of the Power MOSFET (analog driving)

■Compatible with standard Power MOSFET in compliance with the 2002/95/EC European Directive

2

		3
	1	2
		SO-8
	SOT-223

Description

The VNN7NV04P-E, VNS7NV04P-E, are monolithic devices designed in STMicroelectronics VIPower™ M0-3 Technology, intended for replacement of standard Power MOSFETs from DC up to 50 kHz applications. Built in thermal shutdown, linear current limitation and overvoltage clamp protect the chip in harsh environments.

Fault feedback can be detected by monitoring the voltage at the input pin.

Table 1.	Device summary
Package		Order codes
		Tube	Tape and reel
SOT-223		-	VNN7NV04PTR-E
SO-8		VNS7NV04P-E	VNS7NV04PTR-E

July 2011

Doc ID 15632 Rev 3

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www.st.com

Contents	VNN7NV04P-E, VNS7NV04P-E

Contents

1	Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. 5
2	Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		6
	2.1	Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	6
	2.2	Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	7
	2.3	Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	7
3	Protection features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		9
	3.1	Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	12
	3.2	SO-8 maximum demagnetization energy . . . . . . . . . . . . . . . . . . . . . . . . .	16
	3.3	SOT-223 maximum demagnetization energy . . . . . . . . . . . . . . . . . . . . . .	17
4	Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		18
	4.1	SO-8 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	18
	4.2	SOT-223 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	20
5	Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		23
	5.1	SOT-223 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	23
	5.2	SO-8 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	24
	5.3	SOT-223 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	26
	5.4	SO-8 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	27
6	Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		28

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VNN7NV04P-E, VNS7NV04P-E	List of tables

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Table 2. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Table 3. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 4. Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 5. SO-8 thermal parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 6. SOT-223 thermal parameter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 7. SOT-223 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Table 8. SO-8 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Table 9. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

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List of figures	VNN7NV04P-E, VNS7NV04P-E

List of figures

Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 2. Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 3. Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 4. Switching time test circuit for resistive load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 5. Test circuit for diode recovery times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 6. Unclamped inductive load test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 7. Input charge test circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 8. Unclamped inductive waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 9. Derating curve . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 10. Transconductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 11. Static drain-source on resistance vs input voltage (part 1/2) . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 12. Static drain-source on resistance vs input voltage (part 2/2) . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 13. Source-drain diode forward characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 14. Static drain source on resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 15. Turn-on current slope (part 1/2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 16. Turn-on current slope (part 2/2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 17. Transfer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 18. Static drain-source on resistance vs Id. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 19. Input voltage vs input charge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 20. Turn-off drain source voltage slope (part 1/2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 21. Turn-off drain source voltage slope (part 2/2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 22. Capacitance variations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 23. Output characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 24. Normalized on resistance vs temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 25. Switching time resistive load (part 1/2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 26. Switching time resistive load (part 2/2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 27. Normalized input threshold voltage vs temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 28. Normalized current limit vs junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 29. Step response current limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 30. SO-8 maximum turn-off current versus load inductance. . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 31. SO-8 demagnetization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 32. SOT-223 maximum turn-off current versus load inductance . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 33. SOT-223 demagnetization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 34. SO-8 PC board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 35. Rthj-amb vs PCB copper area in open box free air condition. . . . . . . . . . . . . . . . . . . . . . . 18 Figure 36. SO-8 thermal impedance junction ambient single pulse. . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 37. Thermal fitting model of an OMNIFET II in SO-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 38. SOT-223 PC board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 39. Rthj-amb vs PCB copper area in open box free air condition. . . . . . . . . . . . . . . . . . . . . . . 20 Figure 40. SOT-223 thermal impedance junction ambient single pulse. . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 41. Thermal fitting model of an OMNIFET II in SOT-223 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 42. SOT-223 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 43. SO-8 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 44. SOT-223 tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 45. SO-8 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 46. SO-8 tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

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VNN7NV04P-E, VNS7NV04P-E	Block diagram and pin description

1 Block diagram and pin description

Figure 1. Block diagram

			DRAIN
			2
			Overvoltage
			Clamp
INPUT		Gate
	1
		Control
			Linear
		Over	Current
			Limiter
		Temperature
			3
			SOURCE

FC01000

Figure 2. Configuration diagram (top view)

SO-8 Package(1)

SOURCE			1	8	DRAIN
SOURCE					DRAIN
SOURCE			4		DRAIN
INPUT				5	DRAIN

1. For the pins configuration related to SOT-223 see outlines at page 1.

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Electrical specifications	VNN7NV04P-E, VNS7NV04P-E

2 Electrical specifications

Figure 3. Current and voltage conventions

ID

VDS

DRAIN

IIN RIN

INPUT

SOURCE

VIN

2.1Absolute maximum ratings

Table 2.	Absolute maximum ratings
Symbol	Parameter	Value			Unit
		SOT-223		SO-8
VDS	Drain-source voltage (VIN = 0 V)	Internally clamped			V
VIN	Input voltage	Internally clamped			V
IIN	Input current	+/-20			mA
RIN MIN	Minimum input series impedance	150			Ω
ID	Drain current	Internally limited			A
IR	Reverse DC output current	-10.5			A
VESD1	Electrostatic discharge (R = 1.5 KΩ,	4000			V
	C = 100 pF)
VESD2	Electrostatic discharge on output pin only	16500			V
	(R = 330 Ω, C = 150 pF)
Ptot	Total dissipation at Tc = 25 °C	7		4.6	W
	Maximum switching energy (L = 0.7 mH;
EMAX	RL = 0 Ω; Vbat = 13.5 V; Tjstart = 150 °C;	40			mJ
	IL = 9 A)
	Maximum switching energy (L = 0.6 mH;
EMAX	RL = 0 Ω; Vbat = 13.5 V; Tjstart = 150 °C;			37	mJ
	IL = 9 A)
Tj	Operating junction temperature	Internally limited			°C
Tc	Case operating temperature	Internally limited			°C
Tstg	Storage temperature	-55 to 150			°C

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VNN7NV04P-E, VNS7NV04P-E	Electrical specifications

2.2Thermal data

Table 3.	Thermal data
Symbol	Parameter	Value			Unit
		SOT-223		SO-8
Rthj-case	Thermal resistance junction-case max	18			°C/W
Rthj-lead	Thermal resistance junction-lead max			27	°C/W
Rthj-amb	Thermal resistance junction-ambient max	96(1)		90(1)	°C/W

1.When mounted on a standard single-sided FR4 board with 0.5 mm2 of Cu (at least 35 µm thick) connected to all DRAIN pins.

2.3Electrical characteristics

-40 °C < Tj < 150 °C, unless otherwise specified.

Table 4.	Electrical characteristics
Symbol	Parameter				Test conditions			Min	Typ	Max	Unit
Off
VCLAMP	Drain-source clamp	VIN = 0 V; ID = 3.5 A						40	45	55	V
	voltage
VCLTH	Drain-source clamp	VIN = 0 V; ID = 2 mA						36			V
	threshold voltage
VINTH	Input threshold voltage	VDS = VIN; ID = 1 mA						0.5		2.5	V
I	Supply current from input	V	DS	= 0 V; V	IN		= 5 V		100	150	µA
ISS	pin
VINCL	Input-source clamp	IIN = 1 mA						6	6.8	8	V
	voltage	IIN = -1 mA						-1.0		-0.3	V
IDSS	Zero input voltage drain	VDS = 13 V; VIN = 0 V; Tj = 25 °C								30	µA
	current (VIN = 0 V)	VDS = 25 V; VIN = 0 V								75	µA
On
RDS(on)	Static drain-source on	VIN = 5 V; ID = 3.5 A; Tj = 25 °C								65	mΩ
	resistance	VIN = 5 V; ID = 3.5 A								130	mΩ
Dynamic (Tj = 25 °C, unless otherwise specified)
g (1)	Forward	V	DD	= 13 V; I		D	= 3.5 A		9		S
	transconductance
fs
COSS	Output capacitance	VDS = 13 V; f = 1 MHz; VIN = 0 V							220		pF

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Electrical specifications			VNN7NV04P-E, VNS7NV04P-E
Table 4.	Electrical characteristics (continued)
Symbol	Parameter	Test conditions		Min	Typ	Max	Unit
Switching (Tj = 25 °C, unless otherwise specified)
td(on)	Turn-on delay time				100	300	ns
		VDD = 15 V; ID = 3.5 A;
tr	Rise time				470	1500	ns
		Vgen = 5 V; Rgen = RIN MIN = 150 Ω;
td(off)	Turn-off delay time				500	1500	ns
		(see figure Figure 4)
tf	Fall time				350	1000	ns
td(on)	Turn-on delay time				0.75	2.3	µs
		VDD = 15 V; ID = 3.5 A;
tr	Rise time				4.6	14.0	µs
		Vgen = 5 V; Rgen = 2.2 KΩ;
td(off)	Turn-off delay time				5.4	16.0	µs
		(see figure Figure 4)
tf	Fall time				3.6	11.0	µs
(dI/dt)on	Turn-on current slope	VDD = 15 V; ID = 3.5 A; Vgen = 5 V;			6.5		A/µs
		Rgen = RIN MIN = 150 Ω
Qi	Total input charge	VDD = 12 V; ID = 3.5 A; VIN = 5 V;			18		nC
		Igen = 2.13 mA (see figure Figure 7)
Source drain diode (Tj = 25 °C, unless otherwise specified)
(1)	Forward on voltage	ISD = 3.5 A; VIN = 0 V			0.8		V
VSD
trr	Reverse recovery time	ISD = 3.5 A; dI/dt = 20 A/µs;			220		ns
Qrr	Reverse recovery charge	VDD = 30 V; L = 200 µH;			0.28		µC
		(see test circuit, figure Figure 5)
IRRM	Reverse recovery current				2.5		A
Protections (-40 °C < Tj < 150 °C, unless otherwise specified)
Ilim	Drain current limit	VIN = 5 V; VDS = 13 V		6	9	12	A
tdlim	Step response current	VIN = 5 V; VDS = 13 V			4.0		µs
	limit
Tjsh	Overtemperature			150	175	200	°C
	shutdown
Tjrs	Overtemperature reset			135			°C
Igf	Fault sink current	VIN = 5 V; VDS = 13 V; Tj = Tjsh			15		mA
	Single pulse avalanche	starting Tj = 25 °C; VDD = 24 V; VIN = 5 V;
Eas	energy	Rgen = RIN MIN = 150 Ω; L = 24 mH;		200			mJ
		(see Figure 6 and Figure 8)

1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %

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VNN7NV04P-E, VNS7NV04P-E	Protection features

3 Protection features

During normal operation, the input pin is electrically connected to the gate of the internal Power MOSFET through a low impedance path.

The device then behaves like a standard Power MOSFET and can be used as a switch from DC up to 50 kHz. The only difference from the user’s standpoint is that a small DC current IISS (typ. 100µA) flows into the input pin in order to supply the internal circuitry.

The device integrates:

●Overvoltage clamp protection: internally set at 45 V, along with the rugged avalanche characteristics of the Power MOSFET stage give this device unrivalled ruggedness and energy handling capability. This feature is mainly important when driving inductive loads.

●Linear current limiter circuit: limits the drain current ID to Ilim whatever the input pin voltages. When the current limiter is active, the device operates in the linear region, so power dissipation may exceed the capability of the heatsink. Both case and junction temperatures increase, and if this phase lasts long enough, junction temperature may reach the overtemperature threshold Tjsh.

●Overtemperature and short circuit protection: these are based on sensing the chip temperature and are not dependent on the input voltage. The location of the sensing element on the chip in the power stage area ensures fast, accurate detection of the junction temperature. Overtemperature cutout occurs in the range 150 to 190 °C, a typical value being 170 °C. The device is automatically restarted when the chip temperature falls of about 15 °C below shutdown temperature.

●Status feedback: in the case of an overtemperature fault condition (Tj > Tjsh), the device tries to sink a diagnostic current Igf through the input pin in order to indicate fault condition. If driven from a low impedance source, this current may be used in order to warn the control circuit of a device shutdown. If the drive impedance is high enough so

that the input pin driver is not able to supply the current Igf, the input pin falls to 0 V. This however not affects the device operation: no requirement is put on the current capability of the input pin driver except to be able to supply the normal operation drive current

IISS.

Additional features of this device are ESD protection according to the Human Body model and the ability to be driven from a TTL logic circuit.

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