ST VNI8200XP User Manual

VNI8200XP

Octal high-side smart power solid state relay with serial/parallel selectable interface on chip

Features

Type	V	(1)	R	(1)	I	(1)	V	CC
		demag		DS(on)		out
VNI8200XP	VCC-45 V			0.11 Ω	0.7 A		45 V

1. Per channel

■Output current: 0.7 A per channel

■Serial/parallel selectable interface

■Short-circuit protection

■8-bit and 16-bit SPI Interface for IC command and control diagnostic

■Channel overtemperature detection and protection

■Thermal independence of separate channels

■Drives all type of loads (resistive, capacitive, inductive load)

■Loss of GND protection

■Power Good diagnostic

■Undervoltage shutdown with hysteresis

■Overvoltage protection (VCC clamping)

■Very low supply current

■Common fault open drain output

■IC warning temperature detection

■Channels output enable

■100 mA high efficiency step-down switching regulator with integrated boot diode

■Adjustable regulator output

■Switching regulator disable

■5 V and 3.3 V compatible I/Os

■Channel outputs status LED driving 4 x 2 multiplexed array

Datasheet − preliminary data

PowerSSO-36

Applications

■Programmable logic control

■Industrial PC peripheral input/output

■Numerical control machines

	Table 1.	Device summary
	Part number		Package	Packing
	VNI8200XP		PowerSSO-36	Tube
	VNI8200XPTR			Tape and reel

■Fast demagnetization of inductive loads

■ESD protection

■Designed to meet IEC 61131-2, IEC61000-4-4, and IEC61000-4-5

June 2012

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This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to	www.st.com
change without notice.

Contents	VNI8200XP

Contents

1	Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		4
2	Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		5
3	Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		6
4	Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		8
	4.1	Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	9
5	Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		9

5.1 Power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5.2 SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5.3 Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5.4 Logic inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5.5 Protection and diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5.6 Step-down switching regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.7 LED driving array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

6	Functional pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .								14
	6.1	SPI/parallel selection mode (SEL2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .							14
	6.2	Serial data in (SDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .							14
	6.3	Serial data out (SDO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .							14
	6.4	Serial data clock (CLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .							15
	6.5	Slave select							15
			(SS)
	6.6	8/16-bit selection (SEL1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .							15
	6.7	Output enable (OUT_EN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .							16
	6.8	IC warning case temperature detection							16
							(TWARN)
	6.9	Fault indication							17
				(FAULT)
	6.10	Power Good (PG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .							17
	6.11	Programmable watchdog counter reset (WD) . . . . . . . . . . . . . . . . . . . . .							18

7	SPI operation (SEL2 = H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	19
	7.1 8-bit SPI mode (SEL1 = L) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	19

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VNI8200XP		Contents
	7.2 16-bit SPI mode (SEL1 = H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . 19
8	LED driving array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . 21
9	Step-down switching regulator . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . 22
10	Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . 23
11	Thermal management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . 25
	11.1 Thermal behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . 26
12	Interface timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . 27
13	Switching parameters test conditions . . . . . . . . . . . . . . . . . . . . .	. . . . 27
14	Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . 29
15	Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . 33

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Description	VNI8200XP

1 Description

The VNI8200XP is a monolithic 8-channel driver featuring a very low supply current, with integrated SPI interface and high efficiency 100 mA micropower step-down switching regulator peak current control loop mode. The IC, realized in STMicroelectronics™ VIPower™ technology, is intended for driving any kind of load with one side connected to ground.

Active channel current limitation combined with thermal shutdown, independent for each channel, and automatic restart, protect the device against overload.

Additional embedded functions are: loss of GND protection that automatically turns off the device outputs in case of ground disconnection, undervoltage shutdown with hysteresis, Power Good diagnostic for valid supply voltage range recognition, output enable function for immediate power outputs ON/OFF, and programmable watchdog function for microcontroller safe operation; case overtemperature protection to control the IC case temperature.

The device embeds a four-wire SPI serial peripheral with selectable 8 or 16-bit operations; through a select pin the device can also operate with a parallel interface.

Both the 8-bit and 16-bit SPI operations are compatible with daisy chain connection.

The SPI interface allows command of the output driver by enabling or disabling each channel featuring, in 16-bit format, a parity check control for communication robustness. It also allows the monitoring of the status of the IC signaling Power Good, overtemperature condition for each channel, IC pre-warning temperature detection.

Built-in thermal shutdown protects the chip from overtemperature and short-circuit. In overload condition, the channel turns OFF and ON again automatically after the IC temperature decreases below a threshold fixed by a temperature hysteresis so that junction temperature is controlled. If this condition makes case temperature reaching case temperature limit, TCSD, overloaded channels are turned OFF and restart, nonsimultaneously, when case and junction temperature decrease below their own reset threshold. If the case of thermal reset, the channels loaded are not switched on until the junction temperature reset event. Non-overloaded channels continue to operate normally. Case temperature above TCSD is reported through the TWARN open drain pin.

An internal circuit provides a not latched common FAULT indicator reporting if one of the following events occurs: channel OVT (overtemperature), parity check fail. The Power Good diagnostic warns the controller that the supply voltage is below a fixed threshold.

The watchdog function is used to detect the occurrence of a software fault of the host controller. The watchdog circuitry generates an internal reset on expiry of the internal watchdog timer. The watchdog timer reset can be achieved by applying a negative pulse on the WD pin. The watchdog function can be disabled by the WD_EN dedicated pin. This pin also allows the programming of a wide range of watchdog timings.

An internal LED matrix driver circuitry (4 rows, 2 columns) allows the detection of the status of the single outputs. An integrated step-down voltage regulator provides supply voltage to the internal LED matrix driver and logic output buffers and can be used to supply the external optocouplers if the application requires isolation. The regulator is protected against short-circuit or overload conditions by means of pulse-by-pulse current limit with a peak current control loop.

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VNI8200XP	Block diagram

2 Block diagram

Figure 1.	Block diagram
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Pin connection	VNI8200XP

3 Pin connection

Figure 2. Pin connection (top view)

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Table 2.				Pin description
Pin			Name		Type	Description
1			SEL2		Logic input	SPI/parallel selection mode
2		SEL1/IN1			Logic input	8/16-bit SPI selection mode/channel 1 input
3	WD_EN/ IN2				Logic/analog input	Watchdog enable_setting/channel 2 input
4	OUT_EN /IN3				Logic input	Output enable/channel 3 input
5		WD/IN4			Logic input	Watchdog input. The internal watchdog counter is
						cleared on the falling edges/channel 4 input.
6		SDI/IN5			Logic input	Serial data input/channel 5 input
7		CLK/IN6			Logic input	Serial clock/channel 6 input
8					Logic input	Slave select/channel 7 input
			SS/IN7
9		SDO/IN8			Logic input/output	Serial data output/channel 8 input
10			VREG		Power supply	SPI/inputs/LED supply voltage
11			COL0		Open source output	LED source output
12			COL1		Open source output	LED source output
13		DCVDD			Analog output	Internally generated DC-DC low voltage supply. (To be
						connected to external 10 nF capacitor).
14			VREF		Analog output	Internally generated DC-DC voltage reference. (To be
						connected to external 10 nF capacitor).

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VNI8200XP								Pin connection
	Table 2.			Pin description (continued)
	Pin			Name			Type	Description
	15		ROW0				Open drain output	Status channel 1-2
	16		ROW1				Open drain output	Status channel 3-4
	17		ROW2				Open drain output	Status channel 5-6
	18		ROW3				Open drain output	Status channel 7-8
	19			PG			Open drain output	Power Good diagnostic - active low
	20						Open drain output	Fault indication - active low
				FAULT
	21						Open drain output	IC case warning temperature detection - active low
			TWARN
								Step-down feedback input. Connecting the output
	22			FB			Analog input	voltage directly to this pin results in an output voltage
								of 3.3 V. An external resistor divider is required for
								higher output voltages.
	23			GND				Ground
	24		PHASE				Power output	Step-down output
								Step-down bootstrap voltage. Used to provide a drive
	25			BOOT			Power output	voltage, higher than the supply voltage, to power the
								switch of the step-down regulator.
	26			NC				Not connected
	27			OUT8			Power output	Channel 8 power output
	28			OUT7			Power output	Channel 7 power output
	29			OUT6			Power output	Channel 6 power output
	30			OUT5			Power output	Channel 5 power output
	31			OUT4			Power output	Channel 4 power output
	32			OUT3			Power output	Channel 3 power output
	33			OUT2			Power output	Channel 2 power output
	34			OUT1			Power output	Channel 1 power output
	35			NC				Not connected
	36			NC				Not connected
	TAB			TAB			Power supply	Exposed tab internally connected to VCC

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Maximum ratings	VNI8200XP

4 Maximum ratings

Table 3.

Absolute maximum ratings

Symbol

Parameter

Value

Unit

VCC

Power supply voltage

45

V

-VCC

Reverse supply voltage

-0.3

V

VREG

Logic supply voltage

-0.3 to +6

V

VFAULT

VTWARN

Voltage range at pins

TWARN,

FAULT,

PG

-0.3 to +6

V

VPG

VBOOT

Bootstrap peak voltage VPHASE = Vcc

VCC+6

V

VROW

Voltage range at ROW pins

-0.3 to +6

V

VCOL

Voltage range at COL pins

-0.3 to +6

V

Vdig

Voltage level range at logic input pins

-0.3 to +6

V

I

Output current (continuous)

Internally limited (1)

A

OUT

IR

Reverse output current (per channel)

-5

A

IGND

DC ground reverse current

-250

mA

IREG

VREG input current

-1/10

mA

IFAULT

ITWARN,

Current range at pins

TWARN,

FAULT,

PG

-1 to +10

mA

IPG

IIN

Input current range

-1 to +10

mA

IROW

Current range at ROW pins (ROW in ON state)

+20

mA

Current range at ROW pins (ROW in OFF state)

-1 to +10

mA

ICOL

Current range at COL pins (COL in ON state)

-10

mA

Current range at COL pins (COL in OFF state)

-1 to +10

mA

VESD

Electrostatic discharge (R = 1.5 kΩ; C = 100 pF)

2000

V

EAS

Single pulse avalanche energy per channel not

300

mJ

simultaneously

P

TOT

Power dissipation at T = 25 °C

Internally limited(1)

W

c

TJ

Junction operating temperature

Internally limited

° C

TSTG

Storage temperature

-55 to 150

° C

1.Protection functions are intended to avoid IC damage in fault conditions and are not intended for continuous operation. Continuous and repetitive operation of protection functions may reduce the IC lifetime.

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VNI8200XP	Electrical characteristics

4.1Thermal data

Table 4.	Thermal data
Symbol	Parameter		Value	Unit
R	Thermal resistance junction-case (1)	Max.	2	°C/W
th(JC)
R	Thermal resistance junction-ambient (2)	Max.	52	°C/W
th(JA)

1.Per channel.

2.When mounted using minimum recommended pad size on FR-4 board (for details refer to Section 11).

5 Electrical characteristics

5.1Power section

10.5 V < VCC < 36 V; -40 °C < TJ < 125 °C; unless otherwise specified.

Table 5.			Power section
Symbol			Parameter	Test conditions	Min.	Typ.	Max.	Unit
	Vcc		Supply voltage		10.5		36	V
VccClamp			Clamp on Vcc		45	50	52	V
RDS(ON)			On state resistance	IOUT = 0.5 A at TJ = 25 °C		0.11		Ω
				IOUT = 0.5 A			0.2
				All channels in OFF state, DC-
				DC in OFF state, VREG=5 V,		1		mA
	IS		Vcc supply current	SPI OFF(1)
				All channels in ON state, DC-
				DC in ON state VREG=5 V, SPI		TBD	TBD	mA
				ON (2)
				DC-DC OFF VREG= 5 V SPI		TBD		mA
	IDS		VREG supply current	OFF WD_EN=0
				DC-DC ON VREG=5 V SPI ON		TBD		mA
				WD_EN=VREG
ILGND			Output current at	All pins at 24 V except VOUT =			0.5	mA
			GND disconnection	0 V
VOUT(OFF)			OFF state output	VIN = 0 V, IOUT = 0 A			3	V
			voltage
IOUT(OFF)			OFF state output	VIN = VOUT = 0 V	0		5	µA
			current
	FCP		Charge pump	Channel in ON state (3)		1.45		MHz
			frequency

1.SS signal high, NO communication.

2.SS signal low, communication ON.

3.To cover EN55022 class A and class B normatives.

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Electrical characteristics	VNI8200XP

5.2SPI characteristics

10.5 V < VCC < 36 V; 2.7 V < VREG < 5 V; -40 <Tj <125; unless otherwise specified.

Table 6.

SPI characteristics

Symbol

Parameter

Test conditions

Min.

Typ.

Max.

Unit

fCLK

SPI clock frequency

-

5

MHz

tr(CLK),

SPI clock rise/fall time

-

20

ns

tf(CLK)

tsu

setup time

120

-

ns

(SS)

SS

th

hold time

120

-

ns

(SS)

SS

tw(CLK)

CLK high time

80

-

ns

tsu(SDI)

Data input setup time

100

-

ns

th(SDI)

Data input hold time

100

-

ns

ta(SDO)

Data output access time

-

100

ns

tdis(SDO)

Data output disable time

-

200

ns

tv(SDO)

Data output valid time

-

100

ns

th(SDO)

Data output hold time

0

-

ns

VSDO

Voltage on serial data output

ISDO = 15 mA

VREG-0.8

-

V

ISDO = -4 mA

-

0.8

V

5.3Switching

VCC = 24 V; -40 °C < TJ < 125 °C.
Table 7.	Switching
Symbol	Parameter	Test condition	Min.	Typ.	Max.	Unit
td(ON)	Turn-ON delay time	IOUT = 0.5 A, resistive load,	-	5	-	µs
		input rise time < 0.1 µs
tr	Rise time	IOUT = 0.5 A, resistive load,	-	5	-	µs
		input rise time < 0.1 µs
td(OFF)	Turn-OFF delay time	IOUT = 0.5 A, resistive load,	-	10	-	µs
		input rise time < 0.1 µs
tf	Fall time	IOUT = 0.5 A, resistive load,	-	5	-	µs
		input rise time < 0.1 µs
dV/dt(ON)	Turn-ON voltage slope	IOUT = 0.5 A, resistive load,	-	3	-	V/µs
		input rise time < 0.1 µs
dV/dt(off)	Turn-OFF voltage	IOUT = 0.5 A, resistive load,	-	4	-	V/µs
	slope	input rise time < 0.1 µs

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VNI8200XP	Electrical characteristics

5.4Logic inputs

10.5 V < VCC < 36 V; -40 °C < TJ < 125 °C; unless otherwise specified.

Table 8.	Logic inputs
Symbol	Parameter	Test conditions	Min.	Typ.	Max.	Unit
VIL	Input low level voltage				0.8	V
VIH	Input high level voltage		2.20			V
VI(HYST)	Input hysteresis			0.15		V
	voltage
IIN	Input current	VIN = 5 V	8			A

5.5Protection and diagnostic

10.5 V < VCC < 36 V; -40 °C < TJ < 125 °C; unless otherwise specified.

Table 9.

Protection and diagnostic

Symbol

Parameter

Test conditions

Min.

Typ.

Max.

Unit

VPGH1

Power Good diagnostic

16.6

17.5

18.4

ON threshold

VPGH2

Power Good diagnostic

15.6

16.5

17.4

V

OFF threshold

VPGHYS

Power Good diagnostic

1

hysteresis

Undervoltage ON

9.5

10.5

V

protection

VUSD

Undervoltage OFF

9

V

protection

VUSDHYS

Undervoltage

0.4

0.5

V

hysteresis

V

demag

Output voltage at turn-

I

OUT

= 0.5 A; L

LOAD

≥ 1 mH

V -52

V

CC

-50

V

CC

-45

V

OFF

CC

pin low-state

ITWARN = 3 mA (active

VTWARN

TWARN

0.6

V

output voltage

condition)

pin low-state

VFAULT

FAULT

IFAULT = 3 mA (fault condition)

0.6

V

output voltage

VPG

PG pin low-state output

IPG = 3 mA (active condition)

0.7

V

voltage

VREG=3.3 V VCC=0

IPEAK

Maximum DC output

1.4

A

current

ILIM

Short-circuit current

RLOAD = 0

0.7

1.1

1.7

A

limitation per channel

Hyst

ILIM tracking limits

RLOAD = 0

0.3

A

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