VNH3ASP30-E
Automotive fully integrated H-bridge motor driver
Features
Type |
RDS(on) |
Iout |
Vccmax |
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VNH3ASP30-E |
42mΩ max |
30A |
41V |
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(per leg) |
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■5V logic level compatible inputs
■Undervoltage and overvoltage shutdown
■Overvoltage clamp
■Thermal shut down
■Cross-conduction protection
■Linear current limiter
■Very low standby power consumption
■PWM operation up to 20 kHz
■Protection against loss of ground and loss of VCC
■Current-sense output proportional to motor current
■Package: ECOPACK®
Description
The VNH3ASP30-E is a full-bridge motor driver intended for a wide range of automotive applications. The device incorporates a dual monolithic high-side driver (HSD) and two lowside switches. The HSD switch is designed using STMicroelectronics proprietary VIPower™ M0 technology that efficiently integrates a true Power MOSFET with an intelligent signal/protection circuit on the same die.
MultiPowerSO-30™
The low-side switches are vertical MOSFETs manufactured using STMicroelectronics proprietary EHD (“STripFET™”) process.The three circuits are assembled in a MultiPowerSO30 package on electrically isolated lead frames. This package, specifically designed for the harsh automotive environment, offers improved thermal performance thanks to exposed die pads. Moreover, its fully symmetrical mechanical design provides superior manufacturability at board level. The input signals INA and INB can directly interface with the microcontroller to select the motor direction and the brake condition. Pins DIAGA/ENA or DIAGB/ENB, when connected to an external pull-up resistor, enable one leg of the bridge. They also provide a feedback digital diagnostic signal. The normal condition operation is explained in Table 12: Truth table in normal operating conditions on page 14. The CS pin monitors the motor current by delivering a current proportional to its value. The speed of the motor can be controlled in all possible conditions by the PWM up to 20 kHz. In all cases, a low level state on the PWM pin will turn off both the LSA and LSB switches. When PWM rises to a high level, LSA or LSB turn on again depending on the input pin state.
Package |
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Tube |
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Tape & reel |
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MultiPowerSO-30 |
VNH3ASP30-E |
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VNH3ASP30TR-E |
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February 2008 |
Rev 5 |
1/33 |
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www.st.com |
Contents |
VNH3ASP30-E |
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Contents
1 |
Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. 5 |
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2 |
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
8 |
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2.1 |
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
8 |
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2.2 |
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
9 |
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2.3 |
Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
16 |
3 |
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
20 |
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3.1 |
Reverse battery protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
21 |
4 |
Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
25 |
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4.1 |
MultiPowerSO-30 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
25 |
4.1.1Thermal calculation in clockwise and anti-clockwise operation in Steadystate mode 26
4.1.2Thermal resistances definition (values according to the PCB heatsink area) 26
4.1.3 Thermal calculation in Transient mode . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.1.4Single pulse thermal impedance definition (values according to the PCB heatsink area) 26
5 |
Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
29 |
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5.1 |
ECOPACK® packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
29 |
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5.2 |
MultiPowerSO-30 package mechanical data . . . . . . . . . . . . . . . . . . . . . . |
29 |
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5.3 |
Packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
31 |
6 |
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
32 |
2/33
VNH3ASP30-E |
List of tables |
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List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Table 2. Block description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Table 3. Pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Table 4. Pin functions description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 5. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Table 6. Power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Table 7. Logic inputs (INA, INB, ENA, ENB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Table 8. PWM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 9. Switching (VCC = 13V, RLOAD = 1 Ω ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Table 10. Protection and diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 11. Current sense (9V < VCC < 16V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Table 12. Truth table in normal operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 13. Truth table in fault conditions (detected on OUTA). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 14. Electrical transient requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 15. Thermal calculation in clockwise and anti-clockwise operation in Steady-state mode . . . . 26 Table 16. Thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 17. MultiPowerSO-30 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 18. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3/33
List of figures |
VNH3ASP30-E |
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List of figures
Figure 1. |
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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Figure 2. |
Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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Figure 3. |
Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . 8 |
Figure 4. |
Definition of the delay times measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . 11 |
Figure 5. |
Definition of the low-side switching times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . 12 |
Figure 6. |
Definition of the high-side switching times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . 12 |
Figure 7. |
Definition of dynamic cross conduction current during a PWM operation. . . . . . . . . . . |
. . . 13 |
Figure 8. |
On state supply current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . 16 |
Figure 9. |
Off state supply current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . 16 |
Figure 10. |
High-level input current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . 16 |
Figure 11. |
Input clamp voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . 16 |
Figure 12. |
Input high-level voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . 16 |
Figure 13. |
Input low-level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . 16 |
Figure 14. |
Input hysteresis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . 17 |
Figure 15. |
High-level enable pin current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . 17 |
Figure 16. |
Delay time during change of operation mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . 17 |
Figure 17. |
Enable clamp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . 17 |
Figure 18. |
High-level enable voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . 17 |
Figure 19. |
Low-level enable voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . 17 |
Figure 20. |
PWM high-level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . 18 |
Figure 21. |
PWM low-level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . 18 |
Figure 22. |
PWM high-level current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . 18 |
Figure 23. |
Overvoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . 18 |
Figure 24. |
Undervoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . 18 |
Figure 25. |
Current limitation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . 18 |
Figure 26. |
On state high-side resistance vs Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . 19 |
Figure 27. |
On state low-side resistance vs Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . 19 |
Figure 28. |
On state high-side resistance vs VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . 19 |
Figure 29. |
On state low-side resistance vs VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . 19 |
Figure 30. |
Output voltage rise time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . 19 |
Figure 31. |
Output voltage fall time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . 19 |
Figure 32. |
Typical application circuit for DC to 20 kHz PWM operation short circuit protection |
. . . . 20 |
Figure 33. |
Half-bridge configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . 21 |
Figure 34. |
Multi-motors configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . 22 |
Figure 35. |
Waveforms in full-bridge operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . 23 |
Figure 36. |
Waveforms in full-bridge operation (continued ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . 24 |
Figure 37. |
MultiPowerSO-30™ PC board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . 25 |
Figure 38. |
Chipset configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . 25 |
Figure 39. |
Auto and mutual RthJA vs PCB copper area in open box free air condition. . . . . . . . . |
. . . 25 |
Figure 40. |
MultiPowerSO-30 HSD thermal impedance junction ambient single pulse . . . . . . . . . |
. . . 27 |
Figure 41. |
MultiPowerSO-30 LSD thermal impedance junction ambient single pulse. . . . . . . . . . |
. . . 27 |
Figure 42. |
Thermal fitting model of an H-bridge in MultiPowerSO-30 . . . . . . . . . . . . . . . . . . . . . . |
. . . 28 |
Figure 43. |
MultiPowerSO-30 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . 29 |
Figure 44. |
MultiPowerSO-30 suggested pad layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . 30 |
Figure 45. |
MultiPowerSO-30 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . 31 |
Figure 46. |
MultiPowerSO-30 tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . |
. . . 31 |
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VNH3ASP30-E |
Block diagram and pin description |
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VCC |
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OVERTEMPERATURE A |
OV + UV |
OVERTEMPERATURE B |
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CLAMP HSA |
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CLAMP HSB |
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HSA |
DRIVER |
LOGIC |
DRIVER |
HSB |
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HSA |
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HSB |
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CURRENT |
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CURRENT |
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LIMITATION A |
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LIMITATION B |
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OUTA |
1/K |
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1/K |
OUTB |
CLAMP LSA |
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CLAMP LSB |
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LSA |
DRIVER |
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DRIVER |
LSB |
LSA |
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LSB |
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GND |
DIAGA/ENA INA |
CS |
PWM |
INB DIAGB/ENB |
GND |
A |
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B |
Table 2. |
Block description |
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Name |
Description |
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Logic control |
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Allows the turn-on and the turn-off of the high-side and the low-side switches |
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according to the truth table |
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Overvoltage + |
Shuts down the device outside the range [5.5V..16V] for the battery voltage |
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undervoltage |
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High-side and low- |
Protect the high-side and the low-side switches from the high voltage on the |
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side clamp voltage |
battery line in all configurations for the motor |
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High-side and low- |
Drives the gate of the concerned switch to allow a good RDS(on) for the leg of |
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side driver |
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the bridge |
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Linear current limiter |
Limits the motor current by reducing the high-side switch gate source voltage |
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when short-circuit to ground occurs |
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Overtemperature |
In case of short-circuit with the increase of the junction’s temperature, shuts |
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protection |
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down the concerned high side to prevent its degradation and to protect the die |
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Fault detection |
Signals an abnormal behavior of the switches in the half-bridge A or B by |
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pulling low the concerned ENx/DIAGx pin |
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5/33
Block diagram and pin description |
VNH3ASP30-E |
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Figure 2. Configuration diagram (top view) |
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OUTA |
1 |
30 |
OUTA |
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Nc |
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OUTA |
Nc |
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VCC |
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GNDA |
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Heat Slug3 |
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Nc |
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GNDA |
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INA |
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GNDA |
ENA/DIAGA |
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OUTA |
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Nc |
VCC |
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Nc |
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PWM |
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VCC |
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Heat Slug1 |
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CS |
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Nc |
EN |
/DIAG |
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OUTB |
B |
B |
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INB |
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OUTB |
GNDB |
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Nc |
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GND |
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Heat Slug2 |
B |
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VCC |
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GNDB |
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Nc |
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Nc |
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OUTB |
15 |
16 |
OUTB |
Table 3. |
Pin definitions and functions |
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Pin No. |
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Symbol |
Function |
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1, 25, 30 |
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OUTA, Heat Slug3 |
Source of high-side switch A / Drain of low-side switch A |
2, 4, 7, 12, 14, |
NC |
Not connected |
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17, 22, 24, 29 |
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3, 13, 23 |
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VCC, Heat Slug1 |
Drain of high-side switches and power supply voltage |
5 |
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INA |
Clockwise input |
6 |
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ENA/DIAGA |
Status of high-side and low-side switches A; open drain output |
8 |
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PWM |
PWM input |
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9 |
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CS |
Output of current sense |
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10 |
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ENB/DIAGB |
Status of high-side and low-side switches B; open drain output |
11 |
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INB |
Counter clockwise input |
15, 16, 21 |
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OUTB, Heat Slug2 |
Source of high-side switch B / Drain of low-side switch B |
26, 27, 28 |
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GND |
Source of low-side switch A(1) |
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A |
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18, 19, 20 |
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GNDB |
Source of low-side switch B(1) |
1. GNDA and GNDB must be externally connected together.
6/33
VNH3ASP30-E |
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Block diagram and pin description |
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Table 4. |
Pin functions description |
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Name |
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Description |
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VCC |
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Battery connection |
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GNDA, GNDB |
Power grounds; must always be externally connected together |
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OUTA, OUTB |
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Power connections to the motor |
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Voltage controlled input pins with hysteresis, CMOS compatible: These two pins |
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INA, INB |
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control the state of the bridge in normal operation according to the truth table (brake |
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to VCC, brake to GND, clockwise and counterclockwise). |
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Voltage controlled input pin with hysteresis, CMOS compatible: Gates of low-side |
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PWM |
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FETs are modulated by the PWM signal during their ON phase allowing speed |
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control of the motor. |
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Open drain bidirectional logic pins. These pins must be connected to an external pull |
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ENA/DIAGA, |
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up resistor. When externally pulled low, they disable half-bridge A or B. In case of |
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fault detection (thermal shutdown of a high-side FET or excessive ON state voltage |
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ENB/DIAGB |
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drop across a low-side FET), these pins are pulled low by the device (see truth table |
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in fault condition). |
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Analog current-sense output. This output sources a current proportional to the motor |
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CS |
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current. The information can be read back as an analog voltage across an external |
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resistor. |
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7/33
Electrical specifications |
VNH3ASP30-E |
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IS |
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IINA |
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VCC |
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VCC |
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IOUTA |
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INA |
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OUTA |
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IINB |
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IOUTB |
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INB |
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OUT |
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IENA |
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B |
ISENSE |
VOUTA |
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CS |
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DIAGA/ENA |
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IENB |
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VSENSE |
VOUTB |
VINA |
DIAGB/ENB |
GNDA |
GNDB |
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PWM |
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VINB |
Ipw |
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VENA |
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GND |
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VENB |
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IGND |
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Vpw |
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2.1Absolute maximum ratings
Table 5. |
Absolute maximum ratings |
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Symbol |
Parameter |
Value |
Unit |
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VCC |
Supply voltage |
+41 |
V |
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Imax |
Maximum output current (continuous) |
30 |
A |
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IR |
Reverse output current (continuous) |
-30 |
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||||
IIN |
Input current (INA and INB pins) |
±10 |
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IEN |
Enable input current (DIAGA/ENA and DIAGB/ENB pins) |
±10 |
mA |
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IPW |
PWM input current |
±10 |
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VCS |
Current-sense maximum voltage |
-3/+15 |
V |
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|
Electrostatic discharge (R = 1.5kΩ, C = 100pF) |
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VESD |
– CS pin |
2 |
kV |
|
– logic pins |
4 |
kV |
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||||
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– output pins: OUTA, OUTB, VCC |
5 |
kV |
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TJ |
Junction operating temperature |
Internally limited |
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TC |
Case operating temperature |
-40 to 150 |
°C |
|
Tstg |
Storage temperature |
-55 to 150 |
|
8/33
VNH3ASP30-E |
Electrical specifications |
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|
VCC = 9V up to 16 V; -40°C < TJ < 150°C, unless otherwise specified.
Table 6. |
Power section |
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Symbol |
Parameter |
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Test conditions |
Min |
Typ |
Max |
Unit |
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VCC |
Operating supply |
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5.5 |
|
16 |
V |
voltage |
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Off state: |
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INA = INB = PWM = 0; TJ = 25°C; VCC = 13V |
|
12 |
30 |
µA |
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I |
Supply current |
INA = INB = PWM = 0; |
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60 |
µA |
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S |
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On state: |
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INA or INB = 5V, no PWM |
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10 |
mA |
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RONHS |
Static high-side |
IOUT = 12A; TJ = 25°C |
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30 |
mΩ |
||
resistance |
IOUT = 12A; TJ = -40 to 150°C |
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60 |
||||
RONLS |
Static low-side |
IOUT = 12A TJ = 25°C |
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12 |
mΩ |
||
resistance |
IOUT = 12A; TJ = -40 to 150°C |
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24 |
||||
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High-side |
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Vf |
freewheeling diode |
If |
= 12A |
|
0.8 |
1.1 |
V |
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forward voltage |
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IL(off) |
High-side off-state |
TJ = 25°C; VOUTX = ENX = 0V; VCC = 13V |
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3 |
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||
output current |
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|
µA |
|
TJ = 125°C; VOUTX = ENX = 0V; VCC = 13V |
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5 |
|||||
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(per channel) |
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IRM |
Dynamic cross- |
IOUT = 12A (see Figure 7) |
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1.7 |
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A |
||
conduction current |
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||||||
Table 7. |
Logic inputs (INA, INB, ENA, ENB) |
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Symbol |
Parameter |
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Test conditions |
Min |
Typ |
Max |
Unit |
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VIL |
Input low-level voltage |
|
Normal operation (DIAGX/ENX pin acts |
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1.25 |
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VIH |
Input high-level voltage |
|
3.25 |
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as an input pin) |
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VIhys |
Input hysteresis voltage |
|
0.5 |
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V |
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VICL |
Input clamp voltage |
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IIN = 1mA |
5.5 |
6.3 |
7.5 |
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IIN = -1mA |
-1.0 |
-0.7 |
-0.3 |
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IINL |
Input low current |
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VIN = 1.25 V |
1 |
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µA |
IINH |
Input high current |
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VIN = 3.25V |
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10 |
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||||
VDIAG |
Enable output low-level |
|
Fault operation (DIAGX/ENX pin acts as |
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0.4 |
V |
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voltage |
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an output pin); IEN = 1mA |
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9/33
Electrical specifications |
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VNH3ASP30-E |
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Table 8. |
PWM |
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Symbol |
Parameter |
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Test conditions |
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Min |
Typ |
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Max |
Unit |
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VPWL |
PWM low-level voltage |
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1.25 |
|
V |
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IPWL |
PWM low-level pin |
|
Vpw = 1.25 V |
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1 |
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µA |
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current |
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VPWH |
PWM high-level voltage |
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3.25 |
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V |
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IPWH |
PWM high-level pin |
|
Vpw = 3.25V |
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10 |
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µA |
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current |
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VPWhys |
PWM hysteresis voltage |
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0.5 |
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VPWCL |
PWM clamp voltage |
|
Ipw = 1mA |
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VCC + 0.3 |
VCC + 0.7 |
VCC + 1.0 |
V |
|||||||||
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Ipw = -1mA |
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-6.0 |
|
-4.5 |
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-3.0 |
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CINPW |
PWM pin input |
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VIN = 2.5V |
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25 |
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pF |
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capacitance |
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Table 9. |
Switching (VCC = 13V, RLOAD = 1 Ω ) |
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Symbol |
Parameter |
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Test conditions |
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Min |
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Typ |
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Max |
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Unit |
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fPW |
PWM frequency |
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0 |
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20 |
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kHz |
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td(on) |
Turn-on delay time |
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Input rise time < 1µs |
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250 |
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(see Figure 6) |
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td(off) |
Turn-off delay time |
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Input rise time < 1µs |
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250 |
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(see Figure 6) |
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µs |
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tr |
Rise time |
|
(see Figure 5) |
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1 |
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1.6 |
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tf |
Fall time |
|
(see Figure 5) |
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1 |
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2.4 |
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|||
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tDEL |
Delay time during change |
|
(see Figure 4) |
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300 |
|
600 |
|
1800 |
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|||||
|
of operating mode |
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||||||||||
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High-side freewheeling |
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trr |
diode reverse recovery |
|
(see Figure 7) |
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110 |
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ns |
|||
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time |
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Table 10. |
Protection and diagnostic |
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|||||||
|
Symbol |
Parameter |
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|
Test conditions |
Min |
|
Typ |
|
Max |
Unit |
|||||||
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VUV(sd) |
Undervoltage shutdown |
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5.5 |
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VUV(reset) |
Undervoltage reset |
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|
4.7 |
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|
V |
||
|
VOV(sd) |
Overvoltage shutdown |
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16 |
|
19 |
|
22 |
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|||
|
ILIM |
High-side current limitation |
|
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|
|
|
30 |
|
50 |
|
70 |
|
A |
|||||
|
VCLP |
Total clamp voltage (VCC to GND) |
IOUT = 12A |
|
43 |
|
48 |
|
54 |
|
V |
||||||||
|
Tth(sd) |
Thermal shutdown temperature |
VIN = 3.25V |
|
150 |
|
175 |
|
200 |
|
|
||||||||
|
Th(reset) |
Thermal reset temperature |
|
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135 |
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|
°C |
||||
|
Tth(hys) |
Thermal hysteresis |
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|
7 |
|
15 |
|
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|
10/33