ST VNH3ASP30-E User Manual

VNH3ASP30-E

Automotive fully integrated H-bridge motor driver

Features

Type

RDS(on)

Iout

Vccmax

VNH3ASP30-E

42mΩ max

30A

41V

(per leg)

 

 

 

 

 

 

 

5V logic level compatible inputs

Undervoltage and overvoltage shutdown

Overvoltage clamp

Thermal shut down

Cross-conduction protection

Linear current limiter

Very low standby power consumption

PWM operation up to 20 kHz

Protection against loss of ground and loss of VCC

Current-sense output proportional to motor current

Package: ECOPACK®

Description

The VNH3ASP30-E is a full-bridge motor driver intended for a wide range of automotive applications. The device incorporates a dual monolithic high-side driver (HSD) and two lowside switches. The HSD switch is designed using STMicroelectronics proprietary VIPower™ M0 technology that efficiently integrates a true Power MOSFET with an intelligent signal/protection circuit on the same die.

Table 1. Device summary

MultiPowerSO-30

The low-side switches are vertical MOSFETs manufactured using STMicroelectronics proprietary EHD (“STripFET™”) process.The three circuits are assembled in a MultiPowerSO30 package on electrically isolated lead frames. This package, specifically designed for the harsh automotive environment, offers improved thermal performance thanks to exposed die pads. Moreover, its fully symmetrical mechanical design provides superior manufacturability at board level. The input signals INA and INB can directly interface with the microcontroller to select the motor direction and the brake condition. Pins DIAGA/ENA or DIAGB/ENB, when connected to an external pull-up resistor, enable one leg of the bridge. They also provide a feedback digital diagnostic signal. The normal condition operation is explained in Table 12: Truth table in normal operating conditions on page 14. The CS pin monitors the motor current by delivering a current proportional to its value. The speed of the motor can be controlled in all possible conditions by the PWM up to 20 kHz. In all cases, a low level state on the PWM pin will turn off both the LSA and LSB switches. When PWM rises to a high level, LSA or LSB turn on again depending on the input pin state.

Package

 

Order codes

 

 

 

Tube

 

Tape & reel

 

 

 

 

 

 

MultiPowerSO-30

VNH3ASP30-E

 

VNH3ASP30TR-E

 

 

 

 

February 2008

Rev 5

1/33

 

 

 

 

 

 

 

www.st.com

Contents

VNH3ASP30-E

 

 

Contents

1

Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. 5

2

Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8

 

2.1

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8

 

2.2

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9

 

2.3

Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

16

3

Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

20

 

3.1

Reverse battery protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

21

4

Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

25

 

4.1

MultiPowerSO-30 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

25

4.1.1Thermal calculation in clockwise and anti-clockwise operation in Steadystate mode 26

4.1.2Thermal resistances definition (values according to the PCB heatsink area) 26

4.1.3 Thermal calculation in Transient mode . . . . . . . . . . . . . . . . . . . . . . . . . 26

4.1.4Single pulse thermal impedance definition (values according to the PCB heatsink area) 26

5

Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

29

 

5.1

ECOPACK® packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

29

 

5.2

MultiPowerSO-30 package mechanical data . . . . . . . . . . . . . . . . . . . . . .

29

 

5.3

Packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

31

6

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

32

2/33

VNH3ASP30-E

List of tables

 

 

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Table 2. Block description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Table 3. Pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Table 4. Pin functions description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 5. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Table 6. Power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Table 7. Logic inputs (INA, INB, ENA, ENB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Table 8. PWM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Table 9. Switching (VCC = 13V, RLOAD = 1 Ω ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Table 10. Protection and diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Table 11. Current sense (9V < VCC < 16V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Table 12. Truth table in normal operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 13. Truth table in fault conditions (detected on OUTA). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 14. Electrical transient requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 15. Thermal calculation in clockwise and anti-clockwise operation in Steady-state mode . . . . 26 Table 16. Thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 17. MultiPowerSO-30 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 18. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

3/33

List of figures

VNH3ASP30-E

 

 

List of figures

Figure 1.

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . 5

Figure 2.

Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . 6

Figure 3.

Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . 8

Figure 4.

Definition of the delay times measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . 11

Figure 5.

Definition of the low-side switching times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . 12

Figure 6.

Definition of the high-side switching times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . 12

Figure 7.

Definition of dynamic cross conduction current during a PWM operation. . . . . . . . . . .

. . . 13

Figure 8.

On state supply current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . 16

Figure 9.

Off state supply current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . 16

Figure 10.

High-level input current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . 16

Figure 11.

Input clamp voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . 16

Figure 12.

Input high-level voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . 16

Figure 13.

Input low-level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . 16

Figure 14.

Input hysteresis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . 17

Figure 15.

High-level enable pin current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . 17

Figure 16.

Delay time during change of operation mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . 17

Figure 17.

Enable clamp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . 17

Figure 18.

High-level enable voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . 17

Figure 19.

Low-level enable voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . 17

Figure 20.

PWM high-level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . 18

Figure 21.

PWM low-level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . 18

Figure 22.

PWM high-level current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . 18

Figure 23.

Overvoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . 18

Figure 24.

Undervoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . 18

Figure 25.

Current limitation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . 18

Figure 26.

On state high-side resistance vs Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . 19

Figure 27.

On state low-side resistance vs Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . 19

Figure 28.

On state high-side resistance vs VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . 19

Figure 29.

On state low-side resistance vs VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . 19

Figure 30.

Output voltage rise time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . 19

Figure 31.

Output voltage fall time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . 19

Figure 32.

Typical application circuit for DC to 20 kHz PWM operation short circuit protection

. . . . 20

Figure 33.

Half-bridge configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . 21

Figure 34.

Multi-motors configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . 22

Figure 35.

Waveforms in full-bridge operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . 23

Figure 36.

Waveforms in full-bridge operation (continued ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . 24

Figure 37.

MultiPowerSO-30™ PC board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . 25

Figure 38.

Chipset configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . 25

Figure 39.

Auto and mutual RthJA vs PCB copper area in open box free air condition. . . . . . . . .

. . . 25

Figure 40.

MultiPowerSO-30 HSD thermal impedance junction ambient single pulse . . . . . . . . .

. . . 27

Figure 41.

MultiPowerSO-30 LSD thermal impedance junction ambient single pulse. . . . . . . . . .

. . . 27

Figure 42.

Thermal fitting model of an H-bridge in MultiPowerSO-30 . . . . . . . . . . . . . . . . . . . . . .

. . . 28

Figure 43.

MultiPowerSO-30 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . 29

Figure 44.

MultiPowerSO-30 suggested pad layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . 30

Figure 45.

MultiPowerSO-30 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . 31

Figure 46.

MultiPowerSO-30 tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . .

. . . 31

4/33

VNH3ASP30-E

Block diagram and pin description

 

 

1 Block diagram and pin description

Figure 1. Block diagram

 

 

VCC

 

 

 

OVERTEMPERATURE A

OV + UV

OVERTEMPERATURE B

 

CLAMP HSA

 

 

CLAMP HSB

HSA

DRIVER

LOGIC

DRIVER

HSB

 

HSA

 

 

HSB

 

 

CURRENT

 

 

CURRENT

 

 

LIMITATION A

 

 

LIMITATION B

 

OUTA

1/K

 

 

1/K

OUTB

CLAMP LSA

 

 

CLAMP LSB

LSA

DRIVER

 

 

DRIVER

LSB

LSA

 

 

LSB

 

 

 

 

GND

DIAGA/ENA INA

CS

PWM

INB DIAGB/ENB

GND

A

 

 

 

 

B

Table 2.

Block description

Name

Description

 

 

 

Logic control

 

Allows the turn-on and the turn-off of the high-side and the low-side switches

 

according to the truth table

 

 

 

 

Overvoltage +

Shuts down the device outside the range [5.5V..16V] for the battery voltage

undervoltage

 

 

 

 

 

High-side and low-

Protect the high-side and the low-side switches from the high voltage on the

side clamp voltage

battery line in all configurations for the motor

 

 

High-side and low-

Drives the gate of the concerned switch to allow a good RDS(on) for the leg of

side driver

 

the bridge

 

 

Linear current limiter

Limits the motor current by reducing the high-side switch gate source voltage

 

 

when short-circuit to ground occurs

 

 

Overtemperature

In case of short-circuit with the increase of the junction’s temperature, shuts

protection

 

down the concerned high side to prevent its degradation and to protect the die

 

 

 

Fault detection

Signals an abnormal behavior of the switches in the half-bridge A or B by

pulling low the concerned ENx/DIAGx pin

 

 

5/33

ST VNH3ASP30-E User Manual

Block diagram and pin description

VNH3ASP30-E

 

 

Figure 2. Configuration diagram (top view)

 

 

OUTA

1

30

OUTA

 

Nc

 

OUTA

Nc

 

VCC

 

GNDA

 

 

Heat Slug3

 

Nc

 

 

GNDA

 

INA

 

 

GNDA

ENA/DIAGA

 

 

OUTA

 

Nc

VCC

 

Nc

 

PWM

 

VCC

 

Heat Slug1

 

 

CS

 

 

Nc

EN

/DIAG

 

 

OUTB

B

B

 

 

 

 

INB

 

OUTB

GNDB

 

Nc

 

GND

 

 

 

Heat Slug2

B

 

VCC

 

GNDB

 

 

 

 

Nc

 

 

Nc

 

OUTB

15

16

OUTB

Table 3.

Pin definitions and functions

Pin No.

 

Symbol

Function

 

 

 

 

1, 25, 30

 

OUTA, Heat Slug3

Source of high-side switch A / Drain of low-side switch A

2, 4, 7, 12, 14,

NC

Not connected

17, 22, 24, 29

 

 

3, 13, 23

 

VCC, Heat Slug1

Drain of high-side switches and power supply voltage

5

 

INA

Clockwise input

6

 

ENA/DIAGA

Status of high-side and low-side switches A; open drain output

8

 

PWM

PWM input

 

 

 

 

9

 

CS

Output of current sense

 

 

 

 

10

 

ENB/DIAGB

Status of high-side and low-side switches B; open drain output

11

 

INB

Counter clockwise input

15, 16, 21

 

OUTB, Heat Slug2

Source of high-side switch B / Drain of low-side switch B

26, 27, 28

 

GND

Source of low-side switch A(1)

 

 

A

 

18, 19, 20

 

GNDB

Source of low-side switch B(1)

1. GNDA and GNDB must be externally connected together.

6/33

VNH3ASP30-E

 

Block diagram and pin description

 

 

 

 

 

Table 4.

Pin functions description

 

 

 

 

 

Name

 

Description

 

 

 

 

 

VCC

 

Battery connection

 

GNDA, GNDB

Power grounds; must always be externally connected together

 

OUTA, OUTB

 

Power connections to the motor

 

 

 

Voltage controlled input pins with hysteresis, CMOS compatible: These two pins

 

INA, INB

 

control the state of the bridge in normal operation according to the truth table (brake

 

 

 

to VCC, brake to GND, clockwise and counterclockwise).

 

 

 

Voltage controlled input pin with hysteresis, CMOS compatible: Gates of low-side

 

PWM

 

FETs are modulated by the PWM signal during their ON phase allowing speed

 

 

 

control of the motor.

 

 

 

 

 

 

 

Open drain bidirectional logic pins. These pins must be connected to an external pull

 

ENA/DIAGA,

 

up resistor. When externally pulled low, they disable half-bridge A or B. In case of

 

 

fault detection (thermal shutdown of a high-side FET or excessive ON state voltage

 

ENB/DIAGB

 

drop across a low-side FET), these pins are pulled low by the device (see truth table

 

 

 

in fault condition).

 

 

 

 

 

 

 

Analog current-sense output. This output sources a current proportional to the motor

 

CS

 

current. The information can be read back as an analog voltage across an external

 

 

 

resistor.

 

 

 

 

7/33

Electrical specifications

VNH3ASP30-E

 

 

2 Electrical specifications

Figure 3. Current and voltage conventions

 

 

 

 

IS

 

 

IINA

 

 

 

VCC

 

VCC

 

 

IOUTA

 

INA

 

OUTA

 

 

IINB

 

 

IOUTB

 

INB

 

OUT

 

 

IENA

 

B

ISENSE

VOUTA

 

 

CS

 

DIAGA/ENA

 

 

 

 

IENB

 

 

VSENSE

VOUTB

VINA

DIAGB/ENB

GNDA

GNDB

PWM

 

 

 

 

 

VINB

Ipw

 

 

 

 

 

VENA

 

GND

 

 

 

VENB

 

IGND

 

 

 

Vpw

 

 

 

 

 

 

 

 

2.1Absolute maximum ratings

Table 5.

Absolute maximum ratings

 

 

Symbol

Parameter

Value

Unit

 

 

 

 

VCC

Supply voltage

+41

V

Imax

Maximum output current (continuous)

30

A

IR

Reverse output current (continuous)

-30

 

IIN

Input current (INA and INB pins)

±10

 

IEN

Enable input current (DIAGA/ENA and DIAGB/ENB pins)

±10

mA

IPW

PWM input current

±10

 

VCS

Current-sense maximum voltage

-3/+15

V

 

Electrostatic discharge (R = 1.5kΩ, C = 100pF)

 

 

VESD

– CS pin

2

kV

– logic pins

4

kV

 

 

– output pins: OUTA, OUTB, VCC

5

kV

TJ

Junction operating temperature

Internally limited

 

TC

Case operating temperature

-40 to 150

°C

Tstg

Storage temperature

-55 to 150

 

8/33

VNH3ASP30-E

Electrical specifications

 

 

2.2Electrical characteristics

VCC = 9V up to 16 V; -40°C < TJ < 150°C, unless otherwise specified.

Table 6.

Power section

 

 

 

 

 

 

 

Symbol

Parameter

 

 

Test conditions

Min

Typ

Max

Unit

 

 

 

 

 

 

 

 

 

VCC

Operating supply

 

 

 

5.5

 

16

V

voltage

 

 

 

 

 

 

Off state:

 

 

 

 

 

 

INA = INB = PWM = 0; TJ = 25°C; VCC = 13V

 

12

30

µA

I

Supply current

INA = INB = PWM = 0;

 

 

60

µA

S

 

 

 

 

 

 

 

 

 

 

On state:

 

 

 

 

 

 

INA or INB = 5V, no PWM

 

 

10

mA

RONHS

Static high-side

IOUT = 12A; TJ = 25°C

 

 

30

mΩ

resistance

IOUT = 12A; TJ = -40 to 150°C

 

 

60

RONLS

Static low-side

IOUT = 12A TJ = 25°C

 

 

12

mΩ

resistance

IOUT = 12A; TJ = -40 to 150°C

 

 

24

 

High-side

 

 

 

 

 

 

 

Vf

freewheeling diode

If

= 12A

 

0.8

1.1

V

 

forward voltage

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

IL(off)

High-side off-state

TJ = 25°C; VOUTX = ENX = 0V; VCC = 13V

 

 

3

 

output current

 

 

 

 

 

 

µA

TJ = 125°C; VOUTX = ENX = 0V; VCC = 13V

 

 

5

 

(per channel)

 

 

 

 

 

 

 

 

 

 

 

 

IRM

Dynamic cross-

IOUT = 12A (see Figure 7)

 

1.7

 

A

conduction current

 

 

Table 7.

Logic inputs (INA, INB, ENA, ENB)

 

 

 

 

Symbol

Parameter

 

 

Test conditions

Min

Typ

Max

Unit

 

 

 

 

 

 

 

 

VIL

Input low-level voltage

 

Normal operation (DIAGX/ENX pin acts

 

 

1.25

 

VIH

Input high-level voltage

 

3.25

 

 

 

 

as an input pin)

 

 

 

VIhys

Input hysteresis voltage

 

0.5

 

 

V

VICL

Input clamp voltage

 

 

IIN = 1mA

5.5

6.3

7.5

 

 

 

IIN = -1mA

-1.0

-0.7

-0.3

 

 

 

 

 

 

IINL

Input low current

 

 

VIN = 1.25 V

1

 

 

µA

IINH

Input high current

 

 

VIN = 3.25V

 

 

10

 

 

 

 

 

VDIAG

Enable output low-level

 

Fault operation (DIAGX/ENX pin acts as

 

 

0.4

V

voltage

 

 

an output pin); IEN = 1mA

 

 

 

 

 

 

 

 

 

9/33

Electrical specifications

 

 

 

 

 

 

 

 

 

 

 

VNH3ASP30-E

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Table 8.

PWM

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Symbol

Parameter

 

Test conditions

 

Min

Typ

 

 

Max

Unit

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VPWL

PWM low-level voltage

 

 

 

 

 

 

 

 

 

 

 

 

 

1.25

 

V

 

IPWL

PWM low-level pin

 

Vpw = 1.25 V

 

 

1

 

 

 

 

 

 

 

 

 

 

µA

 

current

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VPWH

PWM high-level voltage

 

 

 

 

 

3.25

 

 

 

 

 

 

 

 

 

 

V

 

IPWH

PWM high-level pin

 

Vpw = 3.25V

 

 

 

 

 

 

 

 

 

 

10

 

µA

 

current

 

 

 

 

 

 

 

 

 

 

 

 

 

VPWhys

PWM hysteresis voltage

 

 

 

 

 

0.5

 

 

 

 

 

 

 

 

 

 

 

 

VPWCL

PWM clamp voltage

 

Ipw = 1mA

 

 

VCC + 0.3

VCC + 0.7

VCC + 1.0

V

 

 

Ipw = -1mA

 

 

-6.0

 

-4.5

 

 

 

-3.0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CINPW

PWM pin input

 

VIN = 2.5V

 

 

 

 

 

 

 

 

 

 

25

 

pF

 

capacitance

 

 

 

 

 

 

 

 

 

 

 

 

 

Table 9.

Switching (VCC = 13V, RLOAD = 1 )

 

 

 

 

 

 

 

 

 

 

 

Symbol

Parameter

 

Test conditions

 

Min

 

Typ

 

 

Max

 

Unit

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

fPW

PWM frequency

 

 

 

 

 

 

0

 

 

 

 

 

20

 

kHz

 

td(on)

Turn-on delay time

 

Input rise time < 1µs

 

 

 

 

 

 

 

250

 

 

 

 

(see Figure 6)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

td(off)

Turn-off delay time

 

Input rise time < 1µs

 

 

 

 

 

 

 

250

 

 

 

 

(see Figure 6)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

µs

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tr

Rise time

 

(see Figure 5)

 

 

 

 

 

1

 

 

 

1.6

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tf

Fall time

 

(see Figure 5)

 

 

 

 

 

1

 

 

 

2.4

 

 

 

tDEL

Delay time during change

 

(see Figure 4)

 

 

 

300

 

600

 

1800

 

 

 

of operating mode

 

 

 

 

 

 

 

 

 

 

High-side freewheeling

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

trr

diode reverse recovery

 

(see Figure 7)

 

 

 

 

 

110

 

 

 

 

 

ns

 

 

time

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Table 10.

Protection and diagnostic

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Symbol

Parameter

 

 

 

Test conditions

Min

 

Typ

 

Max

Unit

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VUV(sd)

Undervoltage shutdown

 

 

 

 

 

 

 

 

 

 

 

 

 

5.5

 

 

 

VUV(reset)

Undervoltage reset

 

 

 

 

 

 

 

 

 

 

4.7

 

 

 

V

 

VOV(sd)

Overvoltage shutdown

 

 

 

 

 

 

 

16

 

19

 

22

 

 

 

ILIM

High-side current limitation

 

 

 

 

 

30

 

50

 

70

 

A

 

VCLP

Total clamp voltage (VCC to GND)

IOUT = 12A

 

43

 

48

 

54

 

V

 

Tth(sd)

Thermal shutdown temperature

VIN = 3.25V

 

150

 

175

 

200

 

 

 

Th(reset)

Thermal reset temperature

 

 

 

 

 

135

 

 

 

 

 

 

°C

 

Tth(hys)

Thermal hysteresis

 

 

 

 

 

 

 

7

 

15

 

 

 

 

10/33

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