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VND830SP
User Manual
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ST VND830SP User Manual

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Features
Type R
VND830SP 60mΩ
DS(on)
(1)
I
OUT
6A
(1)
V
CC
36V
VND830SP
Double channel high-side driver
10
1. Per each channel.
■ CMOS compatible inputs
■ Open Drain status outputs
■ Off-state open-load detection
■ Shorted load protection
■ Undervoltage and overvoltage shutdown
■ Loss of ground protection
■ Very low standby current
■ Reverse battery protection
1
PowerSO-10
Description
The VND830SP is a monolithic device designed in| STMicroelectronics™ VIPower™ M0-3 Technology. The VND830SP is intended for driving any type of multiple load with one side connected to ground.
The active V device against low energy spikes (see ISO7637 transient compatibility table). Active current limitation combined with thermal shutdown and automatic restart protects the device against overload.
The device detects the open-load condition in both the on-state and off-state. In the off-state the device detects if the output is shorted to V device automatically turns off in the case where the ground pin becomes disconnected.
pin voltage clamp protects the
CC
CC
. The

Table 1. Device summary

Order codes
Package
Tube Tape and reel
PowerSO-10 VND830SP VND830SP13TR
February 2011 Doc ID 7380 Rev 4 1/28
www.st.com
1
Contents VND830SP
Contents
1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.4 Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.1 GND protection network against reverse battery . . . . . . . . . . . . . . . . . . . 16
3.1.1 Solution 1: a resistor in the ground line (RGND only) . . . . . . . . . . . . . . 16
3.1.2 Solution 2: a diode (D
3.2 Load dump protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
) in the ground line . . . . . . . . . . . . . . . . . . . . 17
GND
3.3 MCU I/O protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.4 Open-load detection in off-state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.5 Maximum demagnetization energy (V
= 13.5V) . . . . . . . . . . . . . . . . . . 19
CC
4 Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.1 PowerSO-10 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5 Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.1 ECOPACK® packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.2 PowerSO-10 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.3 PowerSO-10 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2/27 Doc ID 7380 Rev 4
VND830SP List of tables
List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. Suggested connections for unused and not connected pins . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 3. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 4. Thermal data (per island) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 5. Power output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 6. Protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 7. V Table 8. Switching (V
Table 9. Logic inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 10. Status pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 11. Open-load detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 12. Truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 13. Electrical transient requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 14. Thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 15. PowerSO-10 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 16. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
- output diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
CC
= 13V; Tj = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
CC
Doc ID 7380 Rev 4 3/27
List of figures VND830SP
List of figures
Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 2. Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 3. Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 4. Status timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 5. Switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 6. Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 7. Off-state output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 8. High level input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 9. Input clamp voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 10. Turn-on voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 11. Overvoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 12. Turn-off voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 13. I Figure 14. On-state resistance vs V
Figure 15. Input high level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 16. Input hysteresis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 17. On-state resistance vs
Figure 18. Input low level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 19. Status leakage current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 20. Status low output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 21. Status clamp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 22. Open-load on-state detection threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 23. Open-load off-state detection threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 24. Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 25. Open-load detection in off-state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 26. Maximum turn-off current versus load inductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 27. PowerSO-10 PC board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 28. Rthj-amb vs PCB copper area in open box free air condition . . . . . . . . . . . . . . . . . . . . . . 20
Figure 29. Thermal impedance junction ambient single pulse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 30. Thermal fitting model of a double channel HSD in PowerSO-10 . . . . . . . . . . . . . . . . . . . . 21
Figure 31. PowerSO-10 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 32. PowerSO-10 suggested pad layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 33. PowerSO-10 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 34. PowerSO-10 tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
LIM
vs T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
case
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Tcase
4/27 Doc ID 7380 Rev 4
VND830SP Block diagram and pin description

1 Block diagram and pin description

Figure 1. Block diagram

V
cc
V
GND
INPUT1
STATUS1
INPUT2
STATUS2
cc
CLAMP
OVERT EMP. 1
OVERT EMP. 2
LOGIC
OVERVOLTAGE
UNDERVOLTAGE
CLAMP 1
DRIVER 1
CURRENT LIMITER 1
OPEN LOAD ON 1
OPEN LOAD OFF 1
CLAMP 2
DRIVER 2
CURRENT LIMITER 2
OPEN LOAD ON 2
OPEN LOAD OFF 2
OUTPUT1
OUTPUT2

Figure 2. Configuration diagram (top view)

GROUND INPUT 1 STATUS 1 STATUS 2 INPUT 2
10
6 7
8 9
5 4 3
2
1
OUTPUT 1 OUTPUT 1 N.C. OUTPUT 2 OUTPUT 2
11
V
CC

Table 2. Suggested connections for unused and not connected pins

Connection / pin Status N.C. Output Input
Floating X X X X
To ground X
Through 10KΩ
resistor
Doc ID 7380 Rev 4 5/27
Electrical specifications VND830SP

2 Electrical specifications

2.1 Absolute maximum ratings

Stressing the device above the rating listed in the “Absolute maximum ratings” table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality document.

Table 3. Absolute maximum ratings

Symbol Parameter Value Unit
V
-V
-I
I
-I
I
STAT
V
E
P
T
CC
CC
GND
OUT
OUT
I
IN
ESD
MAX
tot
T
j
T
c
stg
DC supply voltage 41 V
Reverse DC supply voltage - 0.3 V
DC reverse ground pin current - 200 mA
DC output current Internally limited A
Reverse DC output current - 6 A
DC input current +/- 10 mA
DC Status current +/- 10 mA
Electrostatic discharge (human body model: R = 1.5 KΩ; C=100pF)
–INPUT –STATUS –OUTPUT –V
CC
Maximum switching energy (L = 1.8 mH; R
=0Ω; V
L
=13.5V; T
bat
Power dissipation (per island) at T
= 150 °C; IL=9A)
jstart
=25°C 73.5 W
lead
4000 4000 5000 5000
100 mJ
V V V V
Junction operating temperature Internally limited °C
Case operating temperature - 40 to 150
Storage temperature - 55 to 150 °C
6/27 Doc ID 7380 Rev 4
VND830SP Electrical specifications

2.2 Thermal data

Table 4. Thermal data (per island)

Symbol Parameter Value Unit
R
thj-lead
R
thj-amb
1. When mounted on a standard single-sided FR-4 board with 0.5 cm2 of Cu (at least 35 µm thick) connected to all VCC pins. Horizontal mounting and no artificial air flow.
2. When mounted on a standard single-sided FR-4 board with 6 cm2 of Cu (at least 35 µm thick) connected to all VCC pins. Horizontal mounting and no artificial air flow.
Thermal resistance junction-lead 1.7 °C/W
Thermal resistance junction-ambient 51.7

2.3 Electrical characteristics

Values specified in this section are for 8 V < VCC<36V; -40°C<Tj< 150 °C, unless otherwise stated.

Figure 3. Current and voltage conventions

I
IN1
I
IN2
I
I
V
STAT2
STAT1
IN2
STAT2
V
IN1
V
STAT1
V
INPUT 1
STATUS 1
INPUT 2
STATUS 2
GND
V
CC
OUTPUT 1
OUTPUT 2
I
GND
(1)
I
V
F1
OUT2
(*)
V
I
OUT1
V
OUT2
(2)
37
OUT1
°C/W
I
S
V
CC
Note: V
Fn
= V
CCn
- V
during reverse battery condition.
OUTn
Doc ID 7380 Rev 4 7/27
Electrical specifications VND830SP

Table 5. Power output

Symbol Parameter Test conditions Min. Typ. Max. Unit
V
V
V
R
I
L(off1)
I
L(off2)
I
L(off3)
I
L(off4)

Table 6. Protections

Operating supply
CC
voltage
Undervoltage shutdown 3 4 5.5 V
USD
Overvoltage shutdown 36 V
OV
On-state resistance
ON
I
Supply current
S
Off-state output current VIN=V
Off-state output current VIN=0V; V
Off-state output current
Off-state output current
5.5 13 36 V
I
=2A; Tj=25°C 60 mΩ
OUT
=2A; V
I
OUT
Off-state; VCC=13V; VIN=V
OUT
Off-state; V V
IN=VOUT
On-state; V I
=0A
OUT
OUT
V
IN=VOUT
> 8 V 120 mΩ
CC
=0V
=13V;
CC
=0V; Tj=25°C
=13V; VIN=5V;
CC
12 40 µA
12 25 µA
57mA
=0V 0 50 µA
=3.5V -75 0 µA
OUT
=0V; VCC=13V;
Tj=125°C
V
IN=VOUT
=25°C
T
j
=0V; VCC=13V;
5µA
3µA
Symbol Parameter Test conditions Min. Typ. Max. Unit
T
T
t
SDL
I
V
demag
Shutdown temperature 150 175 200 °C
TSD
Reset temperature 135 °C
T
R
Thermal hysteresis 7 15 °C
hyst
Status delay in overload conditions
Current limitation
lim
Turn-off output clamp voltage I
> T
T
j
TSD
V
=13V 6 9 15 A
CC
5.5 V < V
OUT
< 36 V 15 A
CC
-41V
V
=2A; L=6mH
CC
CC
-48V
20 µs
-
CC
55
V
Note: To ensure long term reliability under heavy overload or short circuit conditions, protection
and related diagnostic signals must be used together with a proper software strategy. If the device is subjected to abnormal conditions, this software must limit the duration and number of activation cycles.

Table 7. VCC - output diode

Symbol Parameter Test conditions Min. Typ. Max. Unit
V
Forward on voltage -I
F
= 1.3 A; Tj=150°C — — 0.6 V
OUT
8/27 Doc ID 7380 Rev 4
VND830SP Electrical specifications
Table 8. Switching (V
Symbol Parameter Test conditions Min. Typ. Max. Unit
t
d(on)
t
d(off)
Turn-on delay time
Turn-off delay time
= 13V; Tj = 25°C)
CC
RL=6.5Ω from VIN rising edge to V (see Figure 5)
RL=6.5Ω from VIN falling edge to V (see Figure 5)
OUT
OUT
=1.3V
=11.7V
—30—µs
—30—µs
dV
/dt
OUT
dV
OUT

Table 9. Logic inputs

Turn-on voltage slope
(on)
/dt
Turn-off voltage slope
(off)
RL=6.5Ω from V to V
OUT
=10.4V
(see Figure 5)
R
=6.5Ω from V
L
to V
= 1.3 V (see Figure 5)
OUT
OUT
OUT
=1.3V
= 11.7 V
—
—
See
Figure 19
See
Figure 21
—V/µs
—V/µs
Symbol Parameter Test conditions Min. Typ. Max. Unit
V
I
V
I
V
I(hyst)
V

Table 10. Status pin

Input low level 1.25 V
IL
Low level input current VIN=1.25V 1 µA
IL
Input high level 3.25 V
IH
High level input current VIN= 3.25 V 10 µA
IH
Input hysteresis voltage 0.5 V
I
=1mA 6 6.8 8 V
Input clamp voltage
ICL
IN
=-1mA -0.7 V
I
IN
Symbol Parameter Test conditions Min. Typ. Max. Unit
V
STAT
I
LSTAT
C
STAT
V

Table 11. Open-load detection

Status low output voltage I
Status leakage current
Status pin Input capacitance
Status clamp voltage
SCL
=1.6mA 0.5 V
STAT
Normal operation;
=5V
V
STAT
Normal operation; V
=5V
STAT
I
=1mA 6 6.8 8 V
STAT
I
=- 1mA -0.7 V
STAT
10 µA
100 pF
Symbol Parameter Test conditions Min. Typ. Max. Unit
t
DOL(on)
t
DOL(off)
I
V
Open-load on-state detection threshold VIN= 5 V 50 100 200 mA
OL
Open-load on-state detection delay I
Open-load off-state voltage detection
OL
threshold
=0A 200 µs
OUT
=0V 1.5 2.5 3.5 V
V
IN
Open-load detection delay at turn-off 1000 µs
Doc ID 7380 Rev 4 9/27
Electrical specifications VND830SP

Figure 4. Status timings

OPEN LOAD STATUS TIMING (with external pull-up)
V
> V
OUT
V
INn
V
STATn
t
DOL(off)
I
OUT
OL
t
DOL(on)

Figure 5. Switching characteristics

< I
OVER TEMP STATUS TIMING
OL
V
INn
V
STATn
t
SDL
Tj > T
TSD
t
SDL
10/27 Doc ID 7380 Rev 4
VND830SP Electrical specifications

Table 12. Truth table

Conditions Input Output Status
Normal operation
L
H
L
Current limitation
H H
Overtemperature
Undervoltage
Overvoltage
Output voltage > V
Output current < I

Table 13. Electrical transient requirements

OL
OL
L
H
L
H
L
H
L
H
L
H
ISO T/R
Test level
L
H
L X X
L
L
L
L
L
L
H H
L H
(T
(T
< T
j
> T
j
H H
H
H
L
X X
H H
L
H
H
L
TSD
TSD
) H ) L
7637/1
Test pulse
1- 25V
2 + 25V
3a - 25V
3b + 25V
4- 4V
5+ 26.5V
1. All functions of the device are performed as designed after exposure to disturbance.
2. One or more functions of the device is not performed as designed after exposure and cannot be returned to proper operation without replacing the device.
I II III IV Delays and impedance
(1)
(1)
(1)
(1)
(1)
(1)
- 50V
+ 50V
- 50V
+ 50V
- 5V
+ 46.5V
(1)
(1)
(1)
(1)
(1)
(2)
- 75V
+ 75V
- 100V
+ 75V
- 6V
+ 66.5V
(1)
(1)
(1)
(1)
(1)
(2)
- 100V
+ 100V
- 150V
+ 100V
- 7V
+ 86.5V
(1)
(1)
(1)
(1)
(1)
(2)
2ms, 10Ω
0.2ms, 10Ω
0.1µs, 50Ω
0.1µs, 50Ω
100ms, 0.01Ω
400ms, 2Ω
Doc ID 7380 Rev 4 11/27
Electrical specifications VND830SP

Figure 6. Waveforms

NORMAL OPERATION
INPUT
n
LOAD VOLTAGE
STATUS
V
INPUT
n
CC
n
LOAD VOLTAGE
STATUS
V
CC
INPUT
n
LOAD VOLTAGE STATUS
n
n
UNDERVOLTAGE
V
USDhyst
V
USD
n
undefined
OVERVOLTAGE
VCC<V
OV
n
V
> V
CC
OV
INPUT
n
LOAD VOLTAGE
STATUS
INPUT
n
n
LOAD VOLTAGE
STATUS
T
INPUT
n
j
n
LOAD CURRENT
STATUS
n
OPEN LOAD with external pull-up
V
> V
n
V
OL
OUT
OL
OPEN LOAD without external pull-up
n
T
TSD
T
R
n
OVERTEMPERATURE
12/27 Doc ID 7380 Rev 4
VND830SP Electrical specifications

2.4 Electrical characteristics curves

Figure 7. Off-state output current Figure 8. High level input current
IL(off1) (uA)
2.5
2.25
2
1.75
1.5
1.25
1
0.75
0.5
0.25
0

Figure 9. Input clamp voltage Figure 10. Turn-on voltage slope

Figure 11. Overvoltage shutdown Figure 12. Turn-off voltage slope

Off state Vcc=36V
Vin=Vout=0V
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
Vicl (V)
8
7.8
7.6
7.4
7.2
7
6.8
6.6
6.4
6.2
6
Iin=1mA
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
Vov (V)
50
48
46
44
42
40
38
36
34
32
30
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
Iih (uA)
5
4.5
3.5
2.5
1.5
0.5
Vin=3.25V
4
3
2
1
0
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
dVout/dt(on) (V/ms)
800
700
600
500
400
300
200
100
Vcc=13V
Rl=6.5Ohm
0
-50 -25 0 25 50 75 100 125 150 175
Tc (ºC)
dVout/dt(off) (V/ms)
600
550
500
450
400
350
300
250
200
Vcc=13V
Rl=6.5Ohm
-50 -25 0 25 50 75 100 125 150 175
Tc (ºC)
Doc ID 7380 Rev 4 13/27
Electrical specifications VND830SP
Figure 13. I
Ilim (A)
20
18
16
14
12
10
8
6
4
2
0
-50 -25 0 25 50 75 100 125 150 175

Figure 15. Input high level Figure 16. Input hysteresis voltage

Vih (V)
3.6
3.4
3.2
3
2.8
2.6
2.4
2.2
-50 -25 0 25 50 75 100 125 150 175
LIM
Vcc=13V
vs T
case
Tc (°C)
Tc ( °C )
Figure 14. On-state resistance vs V
Ron (mOhm)
120
110
100
90
80
70
60
50
40
30
20
10
0
5 10152025303540
Tc=150°C
Tc=25°C
Tc= - 40°C
Iout=5A
Vcc (V)
Vhyst (V)
1.5
1.4
1.3
1.2
1.1
1
0.9
0.8
0.7
0.6
0.5
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
CC
Figure 17. On-state resistance vs T
Ron (mOhm)
160
140
120
100
80
60
40
20
0
-50 -25 0 25 50 75 100 125 150 175
Iout=2A
Vcc=8V; 13V & 36V
case

Figure 18. Input low level

Vil (V)
2.6
2.4
2.2
1.8
1.6
1.4
1.2
Tc (°C)
14/27 Doc ID 7380 Rev 4
2
1
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
VND830SP Electrical specifications

Figure 19. Status leakage current Figure 20. Status low output voltage

Ilstat (uA)
0.05
0.04
Vstat=5V
0.03
0.02
0.01
0
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
Vstat (V)
0.8
0.7
Istat=1.6mA
0.6
0.5
0.4
0.3
0.2
0.1
0
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)

Figure 21. Status clamp voltage Figure 22. Open-load on-state detection

threshold
Iol (mA)
150
140
130
120
110
100
90
80
70
60
50
Vcc=13V
Vin=5V
-50 -25 0 25 50 75 100 125 150 175
Tc (ºC)
Vscl (V)
8
7.8
7.6
7.4
7.2
6.8
6.6
6.4
6.2
Istat=1mA
7
6
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
Figure 23. Open-load off-state detection
threshold
Vol (V)
5
4.5
4
3.5
3
2.5
2
1.5
1
0.5
0
Vin=0V
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
Doc ID 7380 Rev 4 15/27
Application information VND830SP

3 Application information

Figure 24. Application schematic

+5V
+5V
+5V
μ
R
prot
C
R
prot
R
prot
R
prot
STATUS1
INPUT1
STATUS2
INPUT2
V
CC
D
ld
OUTPUT1
V
GND
GND
R
GND
D
OUTPUT2
GND

3.1 GND protection network against reverse battery

This section provides two solutions for implementing a ground protection network against reverse battery.
3.1.1 Solution 1: a resistor in the ground line (R
This can be used with any type of load.
The following show how to dimension the R
1. R
2. R
where - I
≤ 600 mV / 2 (I
GND
≥ (-VCC) / (-I
GND
is the DC reverse ground pin current and can be found in the absolute
GND
S(on)max
GND
)
)
maximum rating section of the device datasheet.
GND
resistor:
GND
only)
Power dissipation in R
P
= (-VCC)2/ R
D
GND
GND
(when V
< 0 during reverse battery situations) is:
CC
This resistor can be shared amongst several different HSDs. Please note that the value of this resistor should be calculated with formula (1) where I maximum on-state currents of the different devices.
16/27 Doc ID 7380 Rev 4
S(on)max
becomes the sum of the
VND830SP Application information
Please note that, if the microprocessor ground is not shared by the device ground, then the R
will produce a shift (I
GND
S(on)max
* R
) in the input thresholds and the status output
GND
values. This shift will vary depending on how many devices are ON in the case of several high-side drivers sharing the same R
GND
.
If the calculated power dissipation requires the use of a large resistor, or several devices have to share the same resistor, then ST suggests using solution 2 below.
3.1.2 Solution 2: a diode (D
A resistor (R
= 1 kΩ) should be inserted in parallel to D
GND
) in the ground line
GND
an inductive load. This small signal diode can be safely shared amongst several different HSD. Also in this case, the presence of the ground network will produce a shift (≈600 mV) in the input threshold and the status output values if the microprocessor ground is not common with the device ground. This shift will not vary if more than one HSD shares the same diode/resistor network. Series resistor in INPUT and STATUS lines are also required to prevent that, during battery voltage transient, the current exceeds the Absolute Maximum Rating. Safest configuration for unused INPUT and STATUS pin is to leave them unconnected.

3.2 Load dump protection

Dld is necessary (voltage transient suppressor) if the load dump peak voltage exceeds the V
maximum DC rating. The same applies if the device is subject to transients on the VCC
CC
line that are greater than those shown in the ISO T/R 7637/1 table.

3.3 MCU I/O protection

If a ground protection network is used and negative transients are present on the VCC line, the control pins will be pulled negative. ST suggests to insert a resistor (R prevent the microcontroller I/O pins from latching up.
if the device will be driving
GND
) in line to
prot
The value of these resistors is a compromise between the leakage current of microcontroller and the current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of microcontroller I/Os:
- V
CCpeak
/ I
latchup
≤ R
prot
≤ (V
OHμC
- V
IH
- V
GND
) / I
IHmax
Example
For the following conditions:
V
CCpeak
I
latchup
V
OHμC
5kΩ ≤ R
Recommended values are:
R
prot
= -100 V
≥ 20 mA
≥ 4.5 V
prot
= 10 kΩ
≤ 65 kΩ.
Doc ID 7380 Rev 4 17/27
Application information VND830SP

3.4 Open-load detection in off-state

Off-state open-load detection requires an external pull-up resistor (RPU) connected between OUTPUT pin and a positive supply voltage (V microprocessor.
The external resistor has to be selected according to the following requirements:
1. No false open-load indication when load is connected: in this case we have to avoid
V
to be higher than V
OUT
V
= (V
OUT
PU
/ (RL + RPU))RL < V
; this results in the following condition
Olmin
Olmin.
2. No misdetection when load is disconnected: in this case the V
V
Because I up resistor R
; this results in the following condition R
OLmax
may significantly increase if V
s(OFF)
should be connected to a supply that is switched OFF when the module is in
PU
standby.

Figure 25. Open-load detection in off-state

) like the +5V line used to supply the
PU
has to be higher than
< (V
PU
is pulled high (up to several mA), the pull-
out
V batt. VPU
V
CC
PU
- V
OUT
OLmax
) / I
L(off2)
.
INPUT
STATUS
DRIVER
+
LOGIC
+
-
VOL
GROUND
R
PU
I
L(off2)
OUT
R
RL
18/27 Doc ID 7380 Rev 4
VND830SP Application information
3.5 Maximum demagnetization energy (V

Figure 26. Maximum turn-off current versus load inductance

I
LM AX (A)
100
10
1
0,1 1 10 100
L( mH )
= 13.5V)
CC
A
B
C
A = single pulse at T
Jstart
B= repetitive pulse at T
C= repetitive pulse at T
VIN, I
L
Demagnetization
Note: Values are generated with R
In case of repetitive pulses, T must not exceed the temperature specified above for curves B and C.
= 150ºC
= 100ºC
Jstart
= 125ºC
Jstart
Demagnetization
= 0 Ω.
L
(at beginning of each demagnetization) of every pulse
jstart
Demagnetization
t
Doc ID 7380 Rev 4 19/27
Package and PCB thermal data VND830SP

4 Package and PCB thermal data

4.1 PowerSO-10 thermal data

Figure 27. PowerSO-10 PC board

Note: Layout condition of R
thickness = 2 mm, Cu thickness = 35 µm, Copper areas: from minimum pad lay-out to
2
8cm
).
Figure 28. R
thj-amb
RTHj_amb (°C/W)
55
50
45
40
35
30
0246810
and Zth measurements (PCB FR4 area = 58 mm x 58 mm, PCB
th
vs PCB copper area in open box free air condition
Tj-Tamb=50°C
PCB Cu heatsink area (cm^2)
20/27 Doc ID 7380 Rev 4
VND830SP Package and PCB thermal data

Figure 29. Thermal impedance junction ambient single pulse

Equation 1: pulse calculation formula
Z
where
THδ
RTHδ Z
δ tpT⁄=
THtp
1 δ–()+⋅=

Figure 30. Thermal fitting model of a double channel HSD in PowerSO-10

Tj_1
Pd1
Tj_2
C1
C1 C2
R1
Pd2
C3 C4
R3R1 R6R5R2
R2
R4
T_amb
C5 C6C2
Doc ID 7380 Rev 4 21/27
Package and PCB thermal data VND830SP

Table 14. Thermal parameters

Area / island (cm2) Footprint 6
R1 (°C/W) 0.15
R2 (°C/W) 0.8
R3 (°C/W) 0.7
R4 (°C/W) 0.8
R5 (°C/W) 12
R6 (°C/W) 37 22
C1 (W.s/°C) 0.0006
C2 (W.s/°C) 2.1E-03
C3 (W.s/°C) 0.013
C4 (W.s/°C) 0.3
C5 (W.s/°C) 0.75
C6 (W.s/°C) 3 5
22/27 Doc ID 7380 Rev 4
VND830SP Package and packing information

5 Package and packing information

5.1 ECOPACK® packages

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK
®
packages, depending on their level of environmental compliance. ECOPACK®
®
is an ST trademark.

5.2 PowerSO-10 package information

Figure 31. PowerSO-10 package dimensions

10
HE
h
A
F
A1
1
eB
0.25
D
= =
D1
= =
E2
DETAIL "A"
B
0.10 A
E
SEATING
PLANE
A
C
B
E4
SEATING PLANE
A1
DETAIL "A"
L
α
Doc ID 7380 Rev 4 23/27
Package and packing information VND830SP

Table 15. PowerSO-10 mechanical data

mm.
DIM.
Min. Typ. Max.
A 3.35 3.65
(1)
A
A1 0 0.10
B 0.40 0.60
(1)
B
C 0.35 0.55
(1)
C
D 9.40 9.60
D1 7.40 7.60
E 9.30 9.50
3.4 3.6
0.37 0.53
0.23 0.32
E2 7.20 7.60
(1)
E2
E4 5.90 6.10
(1)
E4
e1.27
F 1.25 1.35
(1)
F
H 13.80 14.40
(1)
H
h0.50
L 1.20 1.80
(1)
L
α 0° 8°
(1)
α
1. Muar only POA P013P.
7.30 7.50
5.90 6.30
1.20 1.40
13.85 14.35
0.80 1.10
2° 8°
24/27 Doc ID 7380 Rev 4
VND830SP Package and packing information

5.3 PowerSO-10 packing information

Figure 32. PowerSO-10 suggested
pad layout
Figure 33. PowerSO-10 tube shipment
(no suffix)
C
B
A
All dimensions are in mm.
Base Q.ty Bulk Q.ty Tube length (± 0.5) A B C (± 0.1)
Casablanca 50 1000 532 10.4 16.4 0.8
Muar 50 1000 532 4.9 17.2 0.8

Figure 34. PowerSO-10 tape and reel shipment (suffix “TR”)

Reel dimensions
Base Q.ty 600 Bulk Q.ty 600 A (max) 330 B (min) 1.5 C (± 0.2) 13 F 20.2 G (+ 2 / -0) 24.4 N (min) 60 T (max) 30.4
MUARCASABLANCA
A
B
C
Tape dimensions
According to Electronic Industries Association (EIA) Standard 481 rev. A, Feb. 1986
Tape width W 24 Tape Hole Spacing P0 (± 0.1) 4 Component Spacing P 24 Hole Diameter D (± 0.1/-0) 1.5 Hole Diameter D1 (min) 1.5 Hole Position F (± 0.05) 11.5 Compartment Depth K (max) 6.5 Hole Spacing P1 (± 0.1) 2
All dimensions are in mm.
Doc ID 7380 Rev 4 25/27
Top
cover
tape
End
500mm min
Empty components pock ets saled with cover tape.
User direction of feed
Start
No componentsNo components Components
500mm min
Revision history VND830SP

6 Revision history

Table 16. Document revision history

Date Revision Changes
09-Sep-2004 1 Initial release.
Current and voltage convention update (page 2). Configuration diagram (top view) & suggested connections for unused
and n.c. pins insertion (page 2).
03-Mar-2008 2
09-Dec-2008 3
07-Feb-2011 4
6 cm2 Cu condition insertion in thermal data table (page 3).
- output diode section update (page 4).
V
CC
Protections note insertion (page 4). Revision history table insertion (page 18). Disclaimers update (page 19).
Document reformatted and restructured. Added contents, list of tables and figures.
®
Added Section 5.1: ECOPACK
packages information.
Changed document template. Updated Figure 5: Switching characteristics Updated Table 8: Switching (V
= 13V; Tj = 25°C)
CC
26/27 Doc ID 7380 Rev 4
VND830SP
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Doc ID 7380 Rev 4 27/27
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