ST VND830PEP-E User Manual

VND830PEP-E

Double channel high side driver

Features

Type	RDS(on)	IOUT	VCC
VND830PEP-E	60mΩ(1)	6A(1)	36V

1. Per each channel.

■CMOS compatible inputs

■Open drain status outputs

■On-state open load detection

■Off-state open load detection

■Shorted load protection

■Undervoltage and overvoltage shutdown

■Protection against loss of ground

■Very low standby current

■Reverse battery protection (see Application schematic on page 16)

■In compliance with the 2002/95/EC european directive

PowerSSO-24

Description

The VND830PEP-E is a monolithic device designed in STMicroelectronics VIPower™ M0-3 Technology, intended for driving any kind of load with one side connected to ground.

Active VCC pin voltage clamp protects the device against low energy spikes (see ISO7637 transient compatibility table).

Active current limitation combined with thermal shutdown and automatic restart protects the device against overload. The device detects open load condition both in on and off-state. Output shorted to VCC is detected in the off-state. Device automatically turns off in case of ground pin disconnection.

Table 1.	Device summary
	Package		Order codes
		Tube		Tape and reel
	PowerSSO-24	VND830PEP-E		VND830PEPTR-E

July 2009

Doc ID 10826 Rev 5

1/25

www.st.com

Contents	VND830PEP-E

Contents

1	Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. 5
2	Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. 6
	2.1	Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	6
	2.2	Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	6
	2.3	Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	7
	2.4	Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	13
3	Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		16
	3.1	GND protection network against reverse battery . . . . . . . . . . . . . . . . . . .	16

3.1.1 Solution 1: a resistor in the ground line (RGND only) . . . . . . . . . . . . . . 16

3.1.2 Solution 2: a diode (DGND) in the ground line . . . . . . . . . . . . . . . . . . . . 17

3.2 Load dump protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.3 MCU I/O protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.4 Open-load detection in off-state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4	Package and PC board thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . .		19
	4.1	PowerSSO-24 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	19
5	Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		22
	5.1	ECOPACK® packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	22
	5.2	PowerSSO-24 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	22
6	Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		24

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VND830PEP-E	List of tables

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Table 2. Suggested connections for unused and not connected pins . . . . . . . . . . . . . . . . . . . . . . . . 5 Table 3. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Table 4. Thermal data (per island) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Table 5. Power output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 6. Switching (VCC = 13V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Table 7. VCC - output diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Table 8. Status pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Table 9. Logic inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Table 10. Protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Table 11. Open-load detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Table 12. Truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Table 13. Electrical transient requirements on VCC pin (part 1/3). . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table 14. Electrical transient requirements on VCC pin (part 2/3). . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table 15. Electrical transient requirements on VCC pin (part 3/3). . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table 16. Thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 17. PowerSSO-24 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Table 18. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

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List of figures	VND830PEP-E

List of figures

Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 2. Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 3. Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 4. Open-load status timing (with external pull-up) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 5. Over temperature status timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 6. Switching time waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 7. Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 8. Off-state output current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 9. High level input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 10. Input clamp voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 11. Status leakage current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 12. Status low output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 13. Status clamp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 14. Turn-on voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 15. Turn-off voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 16. On-state resistance vs Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 17. On-state resistance vs VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 18. ILIM vs Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 19. Input high level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 20. Open-load on-state detection threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 21. Open-load off-state detection threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 22. Input hysteresis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 23. Input low level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 24. Overvoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 25. Undervoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 26. Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 27. Open-load detection in off-state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 28. PowerSSO-24 PC board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 29. Rthj-amb vs PCB copper area in open box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 30. PowerSSO-24 thermal impedance junction ambient single pulse . . . . . . . . . . . . . . . . . . . 20 Figure 31. Thermal fitting model of a double channel HSD in PowerSSO-24 . . . . . . . . . . . . . . . . . . . 20 Figure 32. PowerSSO-24 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

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VND830PEP-E	Block diagram and pin description

1 Block diagram and pin description

Figure 1. Block diagram

Figure 2. Configuration diagram (top view)

VCC

OUTPUT2

GND

OUTPUT2

NC

OUTPUT2

INPUT2

OUTPUT2

NC

OUTPUT2

INPUT1

OUTPUT2

NC

OUTPUT1

C.SENSE1

OUTPUT1

NC

OUTPUT1

C.SENSE2

OUTPUT1

NC

OUTPUT1

VCC

OUTPUT1

TAB = VCC

Table 2.	Suggested connections for unused and not connected pins
Connection / pin		Current sense	N.C.	Output	Input
Floating			X	X	X
To ground		Through 1KΩ	X		Through 10KΩ
		resistor			resistor

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Electrical specifications	VND830PEP-E

2 Electrical specifications

2.1Absolute maximum ratings

Stressing the device above the rating listed in the “Absolute maximum ratings” table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality document.

Table 3.	Absolute maximum ratings
Symbol	Parameter	Value	Unit
VCC	DC supply voltage	41	V
- VCC	Reverse DC supply voltage	- 0.3	V
- IGND	DC reverse ground pin current	- 200	mA
IOUT	DC output current	Internally limited	A
-IOUT	Reverse DC output current	- 6	A
IIN	DC input current	+/- 10	mA
Istat	DC status current	+/- 10	mA
	Electrostatic discharge (human body model:R=1.5KΩ; C=100pF)
	– Input	4000	V
VESD	– Status	4000	V
	– Output	5000	V
	– VCC	5000	V
Ptot	Power dissipation TC = 25°C	54	W
Tj	Junction operating temperature	Internally limited	°C
Tc	Case operating temperature	- 40 to 150	°C
Tstg	Storage temperature	- 55 to 150	°C

2.2Thermal data

Table 4.	Thermal data (per island)
Symbol	Parameter	Value			Unit
Rthj-case	Thermal resistance junction-case (max)		2.3		°C/W
Rthj-amb	Thermal resistance junction-ambient (one chip ON) (max)	57(1)		42(2)	°C/W

1.When mounted on a standard single-sided FR-4 board with 0.5cm2 of Cu (at least 35µm thick) connected to all VCC pins.

2.When mounted on a standard single-sided FR-4 board with 8cm2 of Cu (at least 35µm thick) connected to all VCC pins.

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VND830PEP-E	Electrical specifications

2.3Electrical characteristics

Values specified in this section are for 8V < VCC < 36V; -40°C < Tj < 150°C, unless otherwise stated.

Figure 3. Current and voltage conventions

Note:	VFn = VCCn - VOUTn during reverse battery condition.
	Table 5.	Power output
	Symbol	Parameter	Test conditions	Min.	Typ.	Max.	Unit
	VCC	Operating supply voltage		5.5	13	36	V
	VUSD	Undervoltage shutdown		3	4	5.5	V
	VOV	Overvoltage shutdown		36			V
	RON	On-state resistance	IOUT = 2A; Tj = 25°C			60	mΩ
			IOUT = 2A; Tj = 125°C			120	mΩ
			Off-state; VCC = 13V;
			VIN = VOUT = 0V		12	40	µA
	IS	Supply current	Off-state; VCC = 13V;
			VIN = VOUT = 0V; Tj = 25°C		12	25	µA
			On-state; VCC = 13V; VIN = 5V;
			IOUT = 0A		5	7	mA
	IL(off1)	Off-state output current	VIN = VOUT = 0V	0		50	µA
	IL(off2)	Off-state output current	VIN = 0V; VOUT = 3.5V	-75		0	µA
	IL(off3)	Off-state output current	VIN = VOUT = 0V; VCC = 13V;			5	µA
			Tj = 125°C
	IL(off4)	Off-state output current	VIN = VOUT = 0V; VCC = 13V;			3	µA
			Tj = 25°C

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Electrical specifications

VND830PEP-E

Table 6.

Switching (VCC = 13V)

Symbol

Parameter

Test conditions

Min.

Typ.

Max.

Unit

td(on)

Turn-on delay time

RL = 6.5Ω from VIN rising

-

30

-

µs

edge to VOUT = 1.3V

td(off)

Turn-off delay time

RL = 6.5Ω from VIN falling

-

30

-

µs

edge to VOUT = 11.7V

dVOUT/dt(on)

Turn-on voltage slope

RL = 6.5Ω from VOUT = 1.3V to

-

See

-

V/µs

VOUT = 10.4V

Figure 14

dVOUT/dt(off)

Turn-off voltage slope

RL = 6.5Ω from VOUT = 11.7V

-

See

-

V/µs

to VOUT = 1.3V

Figure 13

Table 7.

VCC - output diode

Symbol

Parameter

Test conditions

Min.

Typ.

Max.

Unit

VF

Forward on voltage

- IOUT = 1.3A; Tj = 150°C

-

-

0.6

V

Table 8.

Status pin

Symbol

Parameter

Test conditions

Min.

Typ.

Max.

Unit

VSTAT

Status low output volt-

ISTAT= 1.6 mA

0.5

V

age

ILSTAT

Status leakage current

Normal operation; VSTAT= 5V

10

µA

CSTAT

Status pin input

Normal Operation; VSTAT= 5V

100

pF

capacitance

VSCL

Status clamp voltage

ISTAT= 1mA

6

6.8

8

V

ISTAT= - 1mA

-0.7

V

Table 9.

Logic inputs

Symbol

Parameter

Test conditions

Min.

Typ.

Max.

Unit

VIL

Input low level

1.25

V

IIL

Low level input current

VIN = 1.25V

1

µA

VIH

Input high level

3.25

V

IIH

High level input current

VIN = 3.25V

10

µA

VI(hyst)

Input hysteresis voltage

0.5

V

VICL

Input clamp voltage

IIN = 1mA

6

6.8

8

V

IIN = -1mA

- 0.7

V

Table 10.

Protections(1)

Symbol

Parameter

Test conditions

Min.

Typ.

Max.

Unit

TTSD

Shutdown temperature

150

175

200

°C

TR

Reset temperature

135

°C

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