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VND5E050MCJ-E
User Manual
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ST VND5E050MCJ-E, VND5E050MCK-E User Manual

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Double-channel high-side driver with analog current sense
Features
Max transient supply voltage V
Operating voltage range V
Max on-state resistance (per ch.) R
Current limitation (typ) I
Off-state supply current I
1. Typical value with all loads connected.
– Inrush current active management by
power limitation – Very low standby current – 3.0 V CMOS compatible inputs – Optimized electromagnetic emissions – Very low electromagnetic susceptibility – Compliance with European directive
2002/95/EC – Very low current sense leakage
■ Diagnostic functions
– Proportional load current sense – High-precision current sense for wide
currents range – Current sense disable – Overload and short to ground (power
limitation) indication – Thermal shutdown indication
■ Protections
– Undervoltage shutdown – Overvoltage clamp – Load current limitation – Self limiting of fast thermal transients – Protection against loss of ground and loss
of V
CC
– Overtemperature shutdown with auto
restart (thermal shutdown) – Reverse battery protected
CC
CC
ON
LIMH
S
4.5 V to 28 V
50 mΩ
2 µA
41 V
27 A
(1)
VND5E050MCJ-E
VND5E050MCK-E
for automotive applications
PowerSSO-12
– Electrostatic discharge protection
Applications
■ All types of resistive, inductive and capacitive
loads
■ Suitable as LED driver
Description
The VND5E050MCJ-E and VND5E050MCK-E are double channel high-side drivers manufactured using ST proprietary VIPower M0-5 technology and housed in PowerSSO-12 and PowerSSO-24 packages. The devices are designed to drive 12 V automotive grounded loads, and to provide protection and diagnostics. They also implement a 3 V and 5 V CMOS­compatible interface for the use with any microcontroller.
The devices integrate advanced protective functions such as load current limitation, inrush and overload active management by power limitation, overtemperature shut-off with auto-restart and overvoltage active clamp. A dedicated analog current sense pin is associated with every output channel providing enhanced diagnostic functions including fast detection of overload and short-circuit to ground through power limitation indication and overtemperature indication.
The current sensing and diagnostic feedback of the whole device can be disabled by pulling the CS_DIS pin high to share the external sense resistor with similar devices.
PowerSSO-24
®
November 2011 Doc ID 022514 Rev 1 1/40
www.st.com
1
Contents VND5E050MCJ-E, VND5E050MCK-E
Contents
1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.4 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.5 Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.1 GND protection network against reverse battery . . . . . . . . . . . . . . . . . . . 22
3.1.1 Solution 1: resistor in the ground line (RGND only) . . . . . . . . . . . . . . . . 22
3.1.2 Solution 2: diode (DGND) in the ground line . . . . . . . . . . . . . . . . . . . . . 23
3.2 Load dump protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.3 MCU I/Os protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.4 Current sense and diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.5 Maximum demagnetization energy (V
= 13.5 V) . . . . . . . . . . . . . . . . . 25
CC
4 Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.1 PowerSSO-12 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.2 PowerSSO-24 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5 Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.1 ECOPACK® . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.2 PowerSSO-12 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.3 PowerSSO-24 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5.4 PowerSSO-12 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
5.5 PowerSSO-24 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
7 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
2/40 Doc ID 022514 Rev 1
VND5E050MCJ-E, VND5E050MCK-E List of tables
List of tables
Table 1. Pin function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 2. Suggested connections for unused and not connected pins . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 3. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 4. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 5. Power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 6. Switching (VCC = 13 V, Tj = 25 °C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 7. Logic inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 8. Protections and diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 9. Current sense (8 V < V
Table 10. Truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 11. Electrical transient requirements (part 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 12. Electrical transient requirements (part 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 13. Electrical transient requirements (part 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 14. Thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 15. Thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 16. PowerSSO-12 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 17. PowerSSO-24 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 18. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 19. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
< 18 V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
CC
Doc ID 022514 Rev 1 3/40
List of figures VND5E050MCJ-E, VND5E050MCK-E
List of figures
Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 2. Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 3. Current and voltage conventions
Figure 4. Current sense delay characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 5. Switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 6. Delay response time between rising edge of output current and rising edge of current
sense (CS enabled) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 7. Output voltage drop limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 8. I
OUT/ISENSE
vs I
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
OUT
Figure 9. Maximum current sense ratio drift vs load current
Figure 10. Normal operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 11. Overload or short to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 12. Intermittent overload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 13. T
evolution in overload or short to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
J
Figure 14. OFF-state output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 15. High-level input current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 16. Input voltage clamp. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 17. Low-level input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 18. High-level input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 19. Hysteresis input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 20. ON-state resistance vs Tcase. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 21. ON-state resistance vs VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 22. Undervoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 23. Turn-on voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 24. ILIMH vs Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 25. Turn-off voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 26. High-level CS_DIS voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 27. CS_DIS voltage clamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 28. Low-level CS_DIS voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 29. Application schematic
(1)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 30. Current sense and diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 31. Maximum turn-off current versus inductance (for each channel) . . . . . . . . . . . . . . . . . . . . 25
Figure 32. PowerSSO-12 PC board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 33. Rthj-amb vs PCB copper area in open box free air condition (one channel on). . . . . . . . . 26
Figure 34. PowerSSO-12 thermal impedance junction ambient single pulse (one channel on) . . . . . 27
Figure 35. Thermal fitting model of a double-channel HSD in PowerSSO-12
Figure 36. PowerSSO-24 PC board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 37. Rthj-amb vs PCB copper area in open box free air condition (one channel on). . . . . . . . . 29
Figure 38. PowerSSO-24 thermal impedance junction ambient single pulse (one channel on) . . . . . 30
Figure 39. Thermal fitting model of a double-channel HSD in PowerSSO-24
Figure 40. PowerSSO-12 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 41. PowerSSO-24 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 42. PowerSSO-12 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 43. PowerSSO-12 tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 44. PowerSS0-24
tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 45. PowerSSO-24 tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
(1)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
(1)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
. . . . . . . . . . . . . . . . . . . 27
. . . . . . . . . . . . . . . . . . . 30
4/40 Doc ID 022514 Rev 1
VND5E050MCJ-E, VND5E050MCK-E Block diagram and pin description

1 Block diagram and pin description

Figure 1. Block diagram

V
CC
Signal Cla mp
Undervoltage
IN1
IN2
CS_ DIS
CS1
CS2
LOGIC

Table 1. Pin function

Control & Diagnostic 1
DRIVER
Over
temp.
V
SENSEH
OVERLOAD PROTECTION
(ACTIVE POWER LIMITATION)
Current
Limitation
Current
Sense
Power Clamp
V
ON
Limitation
Name Function
V
OUT
GND
IN
CC
1,2
1,2
Battery connection.
Power output.
Ground connection. Must be reverse battery protected by an external diode/resistor network.
Voltage controlled input pin with hysteresis, CMOS compatible. Controls output switch state.
CH 1
GND
Channels 2
CONTROL & DIAGNOSTIC
CH 2
OUT2
OUT1
CS
1,2
Analog current sense pin, delivers a current proportional to the load current.
CS_DIS Active high CMOS compatible pin, to disable the current sense pin.
Doc ID 022514 Rev 1 5/40
Block diagram and pin description VND5E050MCJ-E, VND5E050MCK-E

Figure 2. Configuration diagram (top view)

TA B = V
GND
IN2
IN1
CS1 CS2
CS_DIS
cc
12
1 2 3 4 5
6
V
11 10
cc
OUT2 OUT2
9
OUT1
8
OUT1
7
V
cc
CURRENT SENSE1
CURRENT SENSE2
V
GND
N.C.
INPUT2
N.C.
INPUT1
N.C.
N.C.
CS_DIS.
V
CC
CC
OUTPUT2 OUTPUT2 OUTPUT2 OUTPUT2 OUTPUT2 OUTPUT2 OUTPUT1 OUTPUT1 OUTPUT1 OUTPUT1 OUTPUT1 OUTPUT1
TAB = V
CC
PowerSSO-12
PowerSSO-24

Table 2. Suggested connections for unused and not connected pins

Connection / pin Current sense N.C. Output Input CS_DIS
Floating Not allowed X X X X
To ground
Through 1 KΩ
resistor
XNot allowed
Through 10 KΩ
resistor
Through 10 KΩ
resistor
6/40 Doc ID 022514 Rev 1
VND5E050MCJ-E, VND5E050MCK-E Electrical specifications

2 Electrical specifications

Figure 3. Current and voltage conventions
I
CSD
V
CSD
I
IN1
V
IN1
I
IN2
V
IN2
CS_DIS
IN1
IN2
GND
1. V
= V
Fn
- VCC during reverse battery condition.
OUTn

2.1 Absolute maximum ratings

Stressing the device above the rating listed in cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to the conditions in table below for extended periods may affect device reliability.

Table 3. Absolute maximum ratings

Symbol Parameter Value Unit
(1)
I
S
V
CC
V
V
SENSE1
Fn
V
I
GND
OUT1
CS1
OUT2
CS2
I
OUT1
I
SENSE1
I
OUT2
I
SENSE2
V
SENSE2
V
OUT2
Table 3: Absolute maximum ratings
OUT1
V
may
CC
V
-V
-I
GND
I
OUT
-I
OUT
I
I
CSD
-I
CSENSE
V
CSENSE
DC supply voltage 41 V
CC
Reverse DC supply voltage 0.3 V
CC
DC reverse ground pin current 200 mA
DC output current Internally limited A
Reverse DC output current 20 A
DC input current -1 to 10 mA
IN
DC current sense disable input current -1 to 10 mA
DC reverse CS pin current 200 mA
Current sense maximum voltage V
- 41 to +V
CC
CC
V
Doc ID 022514 Rev 1 7/40
Electrical specifications VND5E050MCJ-E, VND5E050MCK-E
Table 3. Absolute maximum ratings (continued)
Symbol Parameter Value Unit
Maximum switching energy (single pulse)
E
V
V
MAX
ESD
ESD
(L = 3 mH, RL = 0 Ω, V
= I
(Typ.)
I
OUT
limL
)
= 13.5 V, T
bat
jstart
= 150 °C,
Electrostatic discharge (human body model: R = 1.5 KΩ, C = 100 pF) –IN –CS –CS_DIS –OUT –V
CC
Charge device model (CDM-AEC-Q100-011) 750 V
104 mJ
4000 2000 4000 5000 5000
V V V V V
T
T
Junction operating temperature -40 to 150 °C
j
Storage temperature -55 to 150 °C
stg

2.2 Thermal data

Table 4. Thermal data

Symbol Parameter
R
thj-case
R
thj-amb
Thermal resistance junction-case (with one channel on)
Thermal resistance junction-ambient See
Max. value
PowerSSO-12 PowerSSO-24
2.7 2.7 °C/W
Figure 33
See
Figure 37
Unit
°C/W
8/40 Doc ID 022514 Rev 1
VND5E050MCJ-E, VND5E050MCK-E Electrical specifications

2.3 Electrical characteristics

Values specified in this section are for 8 V < V
< 28 V, -40 °C < Tj < 150 °C, unless
CC
otherwise stated.

Table 5. Power section

Symbol Parameter Test conditions Min. Typ. Max. Unit
V
CC
V
USD
V
USDhyst
R
ON
V
clamp
I
S
I
L(off1)
V
F
1. For each channel.
2. Special characteristic according to ISO/TS 16949.
3. PowerMOS leakage included.
Operating supply voltage 4.5 13 28 V
Undervoltage shutdown 3.5 4.5 V
Undervoltage shutdown hysteresis
I
= 2 A, Tj = 25 °C 50
OUT
= 2 A, Tj = 150 °C 100
ON-state resistance
(2)
Clamp voltage IS = 20 mA 41 46 52 V
(1)
Supply current
(2)
OFF-state output current
Output-VCC diode voltage
(1)
(1)
I
OUT
I
= 2 A, V
OUT
T
= 25 °C
j
OFF-state: V T
= 25 °C,
j
= V
V
IN
OUT
ON-state: V V
= 5 V, I
IN
VIN = V
OUT
= 25 °C
T
j
VIN = V
OUT
= 125 °C
T
j
-I
= 4 A, Tj = 150 °C 0.7 V
OUT
CC
CC
= V
SENSE
= 13 V,
CC
= 0 A
OUT
= 0 V, V
= 0 V, V
= 5 V,
= 13 V,
CC
CC
= V
= 13 V,
= 13 V,
CSD
= 0 V
0.5 V
(3)
2
36mA
00.013
05
5
65
(3)
mΩ
µA
µA
Table 6. Switching (VCC=13 V, Tj=25 °C)
Symbol Parameter Test conditions Min. Typ. Max. Unit
= 6.5 Ω
R
t
d(on)
t
d(off)
/dt
dV
OUT
/dt
dV
OUT
Turn-on delay time
Turn-off delay time
Turn-on voltage slope RL = 6.5 Ω —
(on)
Turn-off voltage slope RL = 6.5 Ω —
(off)
L
(see
= 6.5 Ω
R
L
(see
Figure 5
Figure 5
)
)
—20—µs
—45—µs
See
Figure 23
See
Figure 25
—V/µs
—V/µs
Doc ID 022514 Rev 1 9/40
Electrical specifications VND5E050MCJ-E, VND5E050MCK-E
Table 6. Switching (VCC=13 V, Tj= 25 °C) (continued)
Symbol Parameter Test conditions Min. Typ. Max. Unit
W
ON
W
OFF

Table 7. Logic inputs

Switching energy losses during t
Switching energy losses during t
won
woff
RL = 6.5 Ω
Figure 5
(see
RL = 6.5 Ω
Figure 5
(see
)
)
—0.15—mJ
—0.3—mJ
Symbol Parameter Test conditions Min. Typ. Max. Unit
V
V
I
V
I(hyst)
V
V
CSDL
I
CSDL
V
CSDH
I
CSDH
I
Low-level input voltage 0.9 V
IL
Low-level input current V
IL
High-level input voltage 2.1 V
IH
High-level input current V
IH
= 0.9 V 1 µA
IN
= 2.1 V 10 µA
IN
Hysteresis input voltage 0.25 V
I
= 1 mA 5.5 7
Input voltage clamp
ICL
IN
= -1 mA -0.7
I
IN
Low-level CS_DIS voltage
Low-level CS_DIS current
High-level CS_DIS voltage
High-level CS_DIS current
V
= 0.9 V 1 µA
CSD
2.1 V
= 2.1 V 10 µA
V
CSD
0.9 V
V
V
CSD(hyst)
V
CSCL

Table 8. Protections and diagnostics

CS_DIS hysteresis voltage
CS_DIS voltage clamps
I
CSD
I
CSD
Symbol Parameter Test conditions Min. Typ. Max. Unit
V
I
limH
I
limL
T
TSD
T
T
T
HYST
DC short circuit current
Short circuit current during thermal cycling
(2)
Shutdown temperature 150 175 200 °C
Reset temperature T
R
Thermal reset of status 135 °C
RS
Thermal hysteresis (T
- TR)
TSD
CC
5 V < V
V
CC
T
R
10/40 Doc ID 022514 Rev 1
0.25 V
= 1 mA 5.5 7
= -1 mA -0.7
(1)
= 13 V 19 27 38 A
< 28 V 38 A
CC
= 13 V,
< Tj < T
TSD
RS
+ 1 T
7A
+ 5 °C
RS
7°C
V
VND5E050MCJ-E, VND5E050MCK-E Electrical specifications
Table 8. Protections and diagnostics
(1)
(continued)
Symbol Parameter Test conditions Min. Typ. Max. Unit
Turn-off output voltage
V
1. To ensure long term reliability under heavy overload or short circuit conditions, protection and related
2. Special characteristic according to ISO/TS 16949.
Table 9. Current sense (8 V < V
(2)
DEMAG
V
diagnostic signals must be used together with a proper software strategy. If the device is subjected to abnormal conditions, this software must limit the duration and number of activation cycles.
clamp
Output voltage drop
ON
limitation
I
OUT
= 2 A, V
IN
= 0,
L = 6 mH
I
= 0.1 A,
OUT
T
= -40 °C to +150 °C
j
(see
Figure 7
CC
)
< 18 V)
V
- 41 V
CC
CC
- 46 V
- 52 V
CC
25 mV
Symbol Parameter Test conditions Min. Typ. Max. Unit
I
K
K
dK1/K
K
I
0
1
2
OUT/ISENSE
I
OUT/ISENSE
Current sense ratio
(1)
1
drift
I
OUT/ISENSE
= 0.05 A, V
OUT
V
= 0 V, Tj = -40 °C to 150 °C
CSD
I
= 1 A, V
OUT
SENSE
Tj = -40 °C to 150 °C T
= 25°C...150°C
j
I
= 1 A, V
OUT
T
= -40 °C to 150 °C
j
I
= 2 A, V
OUT
T
= -40 °C to 150 °C
j
SENSE
SENSE
Tj = 25 °C to 150 °C
SENSE
= 4 V, V
= 4 V, V
= 4 V, V
= 0.5 V,
CSD
CSD
CSD
= 0 V,
= 0 V,
= 0 V,
1440 2250 3630
1740
2070
2820
1750
2070
2562
-15 15 %
1900
2000
2395
1899
2000
2282
= 2 A; V
dK
2/K2
K
3
Current sense ratio
(1)
drift
I
OUT/ISENSE
I
OUT
Tj = -40 °C to 150 °C
I
= 4 A, V
OUT
Tj = -40 °C to 150 °C Tj = 25 °C to 150 °C
= 4 A, V
3/K3
I
SENSE0
drift
Analog sense
(2)
leakage current
Current sense ratio
(1)
dK
Open load on-state
I
OL
V
SENSE
current detection threshold
Max analog sense output voltage
I
OUT
Tj = -40 °C to 150 °C
= 0 A, V
I
OUT
V
= 0 V, Tj = -40 °C to 150 °C
IN
= 0 A, V
I
OUT
= 5 V, Tj = -40 °C to 150 °C
V
IN
I
= 2 A, V
OUT
V
= 5 V, Tj = -40 °C to 150 °C
IN
= 5 V, 8 V < V
V
IN
I
= 5 µA
SENSE
I
= 4 A, V
OUT
= 4 V, V
SENSE
= 4 V, V
SENSE
= 4 V, V
SENSE
= 0 V, V
SENSE
= 0 V, V
SENSE
= 0 V, V
SENSE
< 18 V
CC
= 0 V 5 V
CSD
CSD
CSD
CSD
CSD
CSD
CSD
= 0 V,
= 0 V,
= 0 V,
= 5 V,
= 0 V,
= 5 V,
-9 9 %
1969
1990
1950
1990
-6 6 %
01
02
01
420mA
2210 2153
µA
Doc ID 022514 Rev 1 11/40
Electrical specifications VND5E050MCJ-E, VND5E050MCK-E
Table 9. Current sense (8 V < V
< 18 V) (continued)
CC
Symbol Parameter Test conditions Min. Typ. Max. Unit
Analog sense output
V
SENSEH
I
SENSEH
t
DSENSE1H
t
DSENSE1L
t
DSENSE2H
Δt
DSENSE2H
t
DSENSE2L
voltage in fault condition
Analog sense output current in fault condition
(3)
(3)
Delay response time from falling edge of CS_DIS pin
Delay response time from rising edge of CS_DIS pin
Delay response time from rising edge of INPUT pin
Delay response time between rising edge of output current and rising edge of current sense
Delay response time from falling edge of INPUT pin
V
= 13 V, R
CC
V
= 13 V, V
CC
V
SENSE
I
SENSE
(see
Figure 4
V
SENSE
I
SENSE
(see
Figure 4
V
SENSE
I
SENSE
(see
Figure 4
V
SENSE
I
SENSE
I
= 90% of I
OUT
I
OUTMAX
V
SENSE
I
SENSE
(see
Figure 4
SENSE
SENSE
< 4 V, 0.5 A < I
= 90% of I
SENSE max
)
< 4 V, 0.5 A < I
= 10% of I
SENSE max
)
< 4 V, 0.5 A < I
= 90% of I
SENSE max
)
<4 V,
= 90% of I
SENSEMAX,
OUTMAX
= 2 A (see
< 4 V, 0.5 A < I
= 10% of I
SENSE max
)
= 3.9 KΩ 8V
= 5 V 9 mA
< 4 A
OUT
40 100 µs
< 4 A
OUT
520µs
< 4 A
OUT
80 250 µs
40 µs
Figure 6
OUT
)
< 4 A
80 250 µs
1. Parameter guaranteed by design; it is not tested.
2. Special characteristic according to ISO/TS 16949.
3. Fault condition includes: power limitation and overtemperature.

Figure 4. Current sense delay characteristics

INPUT
CS_DIS
LOAD CURRENT
SENSE CURRENT
t
DSENSE2H
t
DSENSE1L
t
DSENSE1H
t
DSENSE2L
12/40 Doc ID 022514 Rev 1
VND5E050MCJ-E, VND5E050MCK-E Electrical specifications

Figure 5. Switching characteristics

V
OUT
t
Won
t
Woff
90%
t
f
dV
OUT
/dt
(off)
dV
OUT
/dt
(on)
80%
t
r
10%
t
INPUT
t
d(on)
t
d(off)
t
Figure 6. Delay response time between rising edge of output current and rising
edge of current sense (CS enabled)
V
IN
Δ
t
DSENSE2H
t
I
OUT
90% I
OUTMAX
I
OUTMAX
t
I
SENSE
90% I
I
SENSEMAX
SENSEMAX
t
Doc ID 022514 Rev 1 13/40
Electrical specifications VND5E050MCJ-E, VND5E050MCK-E

Figure 7. Output voltage drop limitation

Vcc-V
out
Figure 8. I
I
/ I
out
sense
3000
2800
2600
2400
OUT/ISENSE
A
B
V
vs I
on
OUT
Von/R
Tj=150oC
on(T)
T
=25oC
j
=-40oC
T
j
I
out
2200
C
2000
1800
D
1600
1400
1200
11,522,533,54
A: Max, Tj = -40 °C to 150 °C
C: Typical, T
14/40 Doc ID 022514 Rev 1
B: Max, T
= 25 °C to 150 °C
j
= -40 °C to 150 °C
j
I
OUT
(A)
D: Min, T E: Min, T
= 25 °C to 150 °C)
j
= -40 °C to 150 °C)
j
E
VND5E050MCJ-E, VND5E050MCK-E Electrical specifications
Figure 9. Maximum current sense ratio drift vs load current
dk/k(%)
20
15
A
10
5
0
-5
-10
B
-15
-20 1234
A: Max, Tj = -40 °C to 150 °C B: Min, Tj = 25 °C to 150 °C
I
OUT
(A)
(1)
1. Parameter guaranteed by design; it is not tested.

Table 10. Truth table

Conditions Input Output Sense (V
Normal operation
Overtemperature
Undervoltage
Overload
L H
L H
L H
H
(no power limitation)
H
L
H
L L
L L
X
Cycling
CSD
0
Nominal
0
V
SENSEH
0 0
Nominal
V
SENSEH
(power limitation)
Short circuit to GND (power limitation)
Negative output voltage clamp
1. If the V
CSD
and external circuit.
is high, the SENSE output is at a high-impedance, its potential depends on leakage currents
L H
L L
0
V
SENSEH
LL0
= 0 V)
(1)
Doc ID 022514 Rev 1 15/40
Electrical specifications VND5E050MCJ-E, VND5E050MCK-E

Table 11. Electrical transient requirements (part 1)

ISO 7637-2:
2004(E)
Test pulse
Test levels
(1)
Number of
pulses or
III IV Min. Max.
test times
Burst cycle/pulse
repetition time
Delays and Impedance
1 -75 V -100 V 5000 pulses 0.5 s 5 s 2 ms, 10 Ω
2a +37 V +50 V 5000 pulses 0.2 s 5 s 50 µs, 2 Ω
3a -100 V -150 V 1 h 90 ms 100 ms 0.1µs, 50 Ω
3b +75 V +100 V 1 h 90 ms 100 ms 0.1µs, 50 Ω
4 -6 V -7 V 1 pulse 100 ms, 0.01 Ω
(2)
5b
+65 V +87 V 1 pulse 400 ms, 2 Ω
1. The above test levels must be considered referred to VCC= 13.5 V except for pulse 5b.
2. Valid in case of external load dump clamp: 40 V maximum referred to ground.

Table 12. Electrical transient requirements (part 2)

ISO 7637-2:
Test level results
2004(E)
Test pulse
III IV
1C C
2a C C
3a C C
3b C C
4C C
(1)
5b
CC
1. Valid in case of external load dump clamp: 40 V maximum referred to ground.

Table 13. Electrical transient requirements (part 3)

Class Contents
C All functions of the device are performed as designed after exposure to disturbance.
E
One or more functions of the device are not performed as designed after exposure to disturbance and cannot be returned to proper operation without replacing the device.
16/40 Doc ID 022514 Rev 1
VND5E050MCJ-E, VND5E050MCK-E Electrical specifications

2.4 Waveforms

Figure 10. Normal operation

Normal operation
INPUT
Nominal load Nominal load
I
OUT
V
SENSE
V
CS_DIS

Figure 11. Overload or short to GND

Overload or Short to GND
INPUT
I
>
LimH
I
OUT
V
SENSE
V
CS_DIS
Power Limitation
I
LimL
Thermal cycling
>
Doc ID 022514 Rev 1 17/40
Electrical specifications VND5E050MCJ-E, VND5E050MCK-E

Figure 12. Intermittent overload

Intermittent Overload
INPUT
Overload
I
>
LimH
I
>
LimL
I
OUT
V
>
SENSEH
V
SENSE
V
CS_DIS

Figure 13. TJ evolution in overload or short to GND

TJ evolution in
Overload or Short to GND
Nominal load
INPUT
Self-limitation of fast thermal transients
T
J_START
T
J
I
>
LimH
I
OUT
18/40 Doc ID 022514 Rev 1
Power Limitation
T
T
TSD
R
< I
T
HYST
LimL
VND5E050MCJ-E, VND5E050MCK-E Electrical specifications

2.5 Electrical characteristics curves

Figure 14. OFF-state output current Figure 15. High-level input current

Iloff (nA)
550
500
450
400
350
300
250
200
150
100
50
0
-50 -25 0 25 50 75 100 125 150 175
Off State Vcc=13V
Vin=Vout=0V
Tc (°C)
Iih (µA)
5
4,5
3,5
2,5
1,5
0,5
Vin=2.1V
4
3
2
1
0
-50 -25 0 25 50 75 100 125 150 175

Figure 16. Input voltage clamp Figure 17. Low-level input voltage

Vicl (V)
7
6,8
6,6
6,4
6,2
6
5,8
5,6
5,4
5,2
5
lin=1mA
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
Vil (V)
2
1,8
1,6
1,4
1,2
1
0,8
0,6
0,4
0,2
0
-50 -25 0 25 50 75 100 125 150 175

Figure 18. High-level input voltage Figure 19. Hysteresis input voltage

Vih (V)
4
3,5
3
2,5
2
1,5
1
0,5
0
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
Vihyst (V)
1
0,9
0,8
0,7
0,6
0,5
0,4
0,3
0,2
0,1
0
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
Tc (°C)
Tc (°C)
Doc ID 022514 Rev 1 19/40
Electrical specifications VND5E050MCJ-E, VND5E050MCK-E
Figure 20. ON-state resistance vs T
Ron (mOhm)
300
250
200
150
100
50
0
Iout= 2A
Vcc=13V
-50 -25 0 25 50 75 100 125 150 175
case
Figure 21. ON-state resistance vs V
Ron (mOhm)
100
80
60
40
20
0
0 5 10 15 20 25 30 35 40
Tc (°C)

Figure 22. Undervoltage shutdown Figure 23. Turn-on voltage slope

(dVout/dt )On ( V/ms)
1000
900
800
700
600
500
400
300
200
100
0
-50 -25 0 25 50 75 100 125 150 175

Figure 25. Turn-off voltage slope

(dVout/dt )Off (V/m s)
600
550
500
450
400
350
300
250
200
150
100
50
0
-50 -25 0 25 50 75 100 125 150 175
Vusd (V)
16
14
12
10
8
6
4
2
0
-50 -25 0 25 50 75 100 125 150 175
Figure 24. I
Ilimh (A)
40
35
30
25
20
15
10
-50 -25 0 25 50 75 100 125 150 175
LIMH
Vcc=13V
vs T
Tc (°C)
case
Tc (°C)
Vcc (V)
Vcc=13V
RI=6.5 Ohm
Tc (°C)
Vcc=13V
RI= 6.5 Ohm
Tc (°C)
CC
Tc=150°C
Tc=125°C
Tc=25°C
Tc=-40°C
20/40 Doc ID 022514 Rev 1
VND5E050MCJ-E, VND5E050MCK-E Electrical specifications

Figure 26. High-level CS_DIS voltage Figure 27. CS_DIS voltage clamp

Vcsdh (V)
4
3,5
3
2,5
2
1,5
1
0,5
0
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
Vcsdcl(V)
10
9
8
Icsd = 1 mA
7
6
5
4
3
2
1
0
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)

Figure 28. Low-level CS_DIS voltage

Vcsdl (V)
3
2,5
2
1,5
1
0,5
0
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
Doc ID 022514 Rev 1 21/40
Application information VND5E050MCJ-E, VND5E050MCK-E

3 Application information

Figure 29. Application schematic
+5V
R
prot
Μ
CU
R
prot
R
prot
R
SENSE
C
EXT
(1)
CS_DIS
INPUT
CURRENT SENSE
V
CC
OUTPUT
GND
R
GND
GND
D
GND
V
1. Channel 2 has the same internal circuit as channel 1.

3.1 GND protection network against reverse battery

D
ld
This section provides two solutions for implementing a ground protection network against reverse battery.
3.1.1 Solution 1: resistor in the ground line (R
This can be used with any type of load.
The following is an indication of how to resize the R
1. R
2. R
where -I maximum rating section of the device datasheet.
Power dissipation in R
Equation 1
≤ 600 mV / (I
GND
≥ (−VCC) / (-I
GND
is the DC reverse ground pin current and can be found in the absolute
GND
S(on)max
GND
GND
)
)
(when VCC < 0: during reverse battery situations) is:
PD = (-VCC)2 / R
GND
GND
GND
only)
resistor.
22/40 Doc ID 022514 Rev 1
VND5E050MCJ-E, VND5E050MCK-E Application information
This resistor can be shared amongst several different HSDs. Please note that the value of this resistor should be calculated with formula (1) where I
S(on)max
becomes the sum of the
maximum on-state currents of the different devices.
Please note that if the microprocessor ground is not shared by the device ground then the R
produces a shift (I
GND
S(on)max
* R
) in the input thresholds and the status output
GND
values. This shift varies depending on how many devices are on in case of several high-side drivers sharing the same R
GND
.
If the calculated power dissipation leads to a large resistor or several devices have to share the same resistor then ST suggests to utilize Solution 2 (see
Section 3.1.2
).
3.1.2 Solution 2: diode (D
A resistor (R
= 1 kΩ) should be inserted in parallel to D
GND
) in the ground line
GND
inductive load.
This small signal diode can be safely shared amongst several different HSDs. Also in this case, the presence of the ground network produces a shift (≈600 mV) in the input threshold and in the status output values if the microprocessor ground is not common to the device ground. This shift not varies if more than one HSD share the same diode/resistor network.

3.2 Load dump protection

Dld is necessary (voltage transient suppressor) if the load dump peak voltage exceeds the V
maximum DC rating. The same applies if the device is subject to transients on the VCC
CC
line that are greater than the ones shown in the ISO 7637-2: 2004(E) table.

3.3 MCU I/Os protection

If a ground protection network is used and negative transients are present on the VCC line, the control pins are pulled negative.
ST suggests to insert a resistor (R latching-up.
The value of these resistors is a compromise between the leakage current of microcontroller and the current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of microcontroller I/Os:
if the device drives an
GND
) in line to prevent the microcontroller I/O pins from
prot
Equation 2
-V
CCpeak
/ I
latchup
≤ R
prot
≤ (V
OHμC
- V
IH
- V
GND
) / I
IHmax
Calculation example:
For V
5 kΩ ≤ R
Recommended values: R
CCpeak
= - 100 V, I
≤ 180 kΩ
prot
≥ 20 mA and V
latchup
=10 kΩ, C
prot
EXT
OHµC
= 10 nF.
≥ 4.5 V
Doc ID 022514 Rev 1 23/40
Application information VND5E050MCJ-E, VND5E050MCK-E

3.4 Current sense and diagnostic

The current sense pin performs a double function (see
diagnostic
● Current mirror of the load current in normal operation, delivering a current
):
proportional to the load current according to a known ratio K The current I external resistor R minimum (see parameter V
can be easily converted to a voltage V
SENSE
. Linearity between I
SENSE
SENSE
in
Table 9: Current sense (8 V < V
Figure 30: Current sense and
.
X
by means of an
SENSE
is ensured up to 5 V
SENSE
OUT
and V
CC
< 18 V)
). The current sense accuracy depends on the output current (refer to current sense electrical characteristics
● Diagnostic flag in fault conditions, delivering a fixed voltage V
maximum current I
Tr u t h t a bl e
Table 9: Current sense (8 V < V
SENSEH
in case of the following fault conditions (refer to
):
CC
< 18 V)
).
SENSEH
up to a
Table 10:
– Power limitation activation
–Overtemperature
A logic level high on CS_DIS pin sets at the same time all the current sense pins of the device in a high-impedance state, thus disabling the current monitoring and diagnostic detection. This feature allows multiplexing of the microcontroller analog inputs by sharing of sense resistance and ADC line among different devices.

Figure 30. Current sense and diagnostic

V
BAT
V
CC
41V
Overtemperature
Pwr_Lim
CS_DIS
I
OUT/KX
I
SENSEH
V
SENSEH
CURRENT
SENSEn
R
PROT
To uC ADC
R
SENSE
V
SENSE
Main MOSn
GND
OUTn
Load
24/40 Doc ID 022514 Rev 1
VND5E050MCJ-E, VND5E050MCK-E Application information

3.5 Maximum demagnetization energy (VCC = 13.5 V)

Figure 31. Maximum turn-off current versus inductance (for each channel)

100
A
B
C
10
I (A)
1
0,1 1 10 100L (mH)
A: T
B: T
C: T
V
, I
IN
= 150 °C single pulse
jstart
= 100 °C repetitive pulse
jstart
= 125 °C repetitive pulse
jstart
L
Demagnetization Demagnetization Demagnetization
t
1. Values are generated with RL = 0 Ω.In case of repetitive pulses, T demagnetization) of every pulse must not exceed the temperature specified above for curves A and B.
(at the beginning of each
jstart
Doc ID 022514 Rev 1 25/40
Package and PCB thermal data VND5E050MCJ-E, VND5E050MCK-E

4 Package and PCB thermal data

4.1 PowerSSO-12 thermal data

Figure 32. PowerSSO-12 PC board

1. Layout condition of Rth and Zth measurements (PCB: double layer, thermal vias, FR4 area = 77 mm x 86 mm, PCB thickness = 1.6 mm, Cu thickness = 70 µm (front and back side), copper areas: from minimum pad lay-out to 8 cm
2
).
Figure 33. R
thj-amb
on)
RTHj _amb(°C/ W)
70
65
60
55
50
45
40
35
30
0246810
vs PCB copper area in open box free air condition (one channel
PCB Cu heatsink area (cm^ 2)
26/40 Doc ID 022514 Rev 1
VND5E050MCJ-E, VND5E050MCK-E Package and PCB thermal data
Figure 34. PowerSSO-12 thermal impedance junction ambient single pulse (one
channel on)
ZTH (° C/ W)
100
Footprint
2 cm
8 cm
2
2
10
1
0,1
0,0001 0,001 0,01 0,1 1 10 100 1000
Time ( s)
Equation 3: pulse calculation formula
Z
THδ
R
TH
δ Z
THtp
1 δ–()+⋅=
where δ = tP/T

Figure 35. Thermal fitting model of a double-channel HSD in PowerSSO-12

1. The fitting model is a simplified thermal tool and is valid for transient evolutions where the embedded protections (power limitation or thermal cycling during thermal shutdown) are not triggered.
Doc ID 022514 Rev 1 27/40
Package and PCB thermal data VND5E050MCJ-E, VND5E050MCK-E

Table 14. Thermal parameters

Area/island (cm2)Footprint28
R1=R7 (°C/W) 0.7
R2=R8 (°C/W) 2.8
R3 (°C/W) 4
R4 (°C/W) 8 8 7
R5 (°C/W) 22 15 10
R6 (°C/W) 26 20 15
C1=C7 (W.s/°C) 0.001
C2=C8 (W.s/°C) 0.0025
C3 (W.s/°C) 0.05
C4 (W.s/°C) 0.2 0.1 0.1
C5 (W.s/°C) 0.27 0.8 1
C6 (W.s/°C) 3 6 9
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VND5E050MCJ-E, VND5E050MCK-E Package and PCB thermal data

4.2 PowerSSO-24 thermal data

Figure 36. PowerSSO-24 PC board

1. Layout condition of Rth and Zth measurements (PCB: double layer, Thermal vias, FR4 area = 77 mm x 86 mm, PCB thickness =1.6 mm, Cu thickness =70 µm (front and back side), Copper areas: from minimum pad lay-out to 8 cm
2
).
Figure 37. R
RTHj_amb(°C/W)
55
50
45
40
35
30
0246810
thj-amb
on)
vs PCB copper area in open box free air condition (one channel
PCB Cu heatsink area (cm^2)
Doc ID 022514 Rev 1 29/40
Package and PCB thermal data VND5E050MCJ-E, VND5E050MCK-E
Figure 38. PowerSSO-24 thermal impedance junction ambient single pulse (one
channel on)
Equation 4: pulse calculation formula
Z
THδ
R
TH
δ Z
THtp
1 δ–()+⋅=
where δ = tP/T

Figure 39. Thermal fitting model of a double-channel HSD in PowerSSO-24

1. The fitting model is a simplified thermal tool and is valid for transient evolutions where the embedded protections (power limitation or thermal cycling during thermal shutdown) are not triggered.
30/40 Doc ID 022514 Rev 1
VND5E050MCJ-E, VND5E050MCK-E Package and PCB thermal data

Table 15. Thermal parameters

Area / island (cm2)Footprint 2 8
R1 = R7 (°C/W) 0.4
R2 = R8 (°C/W) 2
R3 (°C/W) 6
R4 (°C/W) 7.7
R5 (°C/W) 9 9 8
R6 (°C/W) 28 17 10
C1 = C7 (W.s/°C) 0.001
C2 = C8 (W.s/°C) 0.0022
C3 (W.s/°C) 0.025
C4 (W.s/°C) 0.75
C5 (W.s/°C) 1 4 9
C6 (W.s/°C) 2.2 5 17
Doc ID 022514 Rev 1 31/40
Package and packing information VND5E050MCJ-E, VND5E050MCK-E

5 Package and packing information

5.1 ECOPACK
®
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK
®
packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com
ECOPACK
®
is an ST trademark.

5.2 PowerSSO-12 package information

Figure 40. PowerSSO-12 package dimensions

.
32/40 Doc ID 022514 Rev 1
VND5E050MCJ-E, VND5E050MCK-E Package and packing information

Table 16. PowerSSO-12 mechanical data

Symbol
Min. Typ. Max.
A1.25 1.62
A1 0 0.1
A2 1.10 1.65
B0.23 0.41
C0.19 0.25
D4.8 5.0
E3.8 4.0
e0.8
H5.8 6.2
h 0.25 0.5
L 0.4 1.27
Millimeters
k0° 8°
X1.9 2.5
Y3.6 4.2
ddd 0.1
Doc ID 022514 Rev 1 33/40
Package and packing information VND5E050MCJ-E, VND5E050MCK-E

5.3 PowerSSO-24 package information

Figure 41. PowerSSO-24 package dimensions

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VND5E050MCJ-E, VND5E050MCK-E Package and packing information

Table 17. PowerSSO-24 mechanical data

Symbol
Min. Typ. Max.
A2.15 2.47
A2 2.15 2.40
a1 0 0.075
b0.33 0.51
c0.23 0.32
D 10.10 10.50
E7.4 7.6
e0.8
e3 8.8
G 0.1
G1 0.06
Millimeters
H10.1 10.5
h 0.4
L0.55 0.85
N 10deg
X4.1 4.7
Y6.5 7.1
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Package and packing information VND5E050MCJ-E, VND5E050MCK-E

5.4 PowerSSO-12 packing information

Figure 42. PowerSSO-12 tube shipment (no suffix)

B
A
C

Figure 43. PowerSSO-12 tape and reel shipment (suffix “TR”)

Base q.ty 100 Bulk q.ty 2000 Tube length (± 0.5) 532 A1.85 B6.75 C (± 0.1) 0.6
All dimensions are in mm.
Reel dimensions
Base q.ty 2500 Bulk q.ty 2500 A (max) 330 B (min) 1.5 C (± 0.2) 13 F20.2 G (+ 2 / -0) 12.4 N (min) 60 T (max) 18.4
Tape dimensions
According to Electronic Industries Association (EIA) Standard 481 rev. A, Feb. 1986
Tape width W 12 Tape hole spacing P0 (± 0.1) 4 Component spacing P 8 Hole diameter D (± 0.05) 1.5 Hole diameter D1 (min) 1.5 Hole position F (± 0.1) 5.5 Compartment depth K (max) 4.5 Hole spacing P1 (± 0.1) 2
All dimensions are in mm.
36/40 Doc ID 022514 Rev 1
Top
cover
tape
End
500mm min
Empty components pockets saled with cover tape.
User direction of feed
Start
No componentsNo components Components
500mm min
VND5E050MCJ-E, VND5E050MCK-E Package and packing information

5.5 PowerSSO-24 packing information

Figure 44. PowerSS0-24 tube shipment (no suffix)

Base qty 49 Bulk qty 1225
C
B
A

Figure 45. PowerSSO-24 tape and reel shipment (suffix “TR”)

Tube length (±0.5) 532 A 3.5 B 13.8 C (±0.1) 0.6
All dimensions are in mm.
Reel dimensions
Base qty 1000 Bulk qty 1000 A (max) 330 B (min) 1.5 C (±0.2) 13 F 20.2 G (+2 / -0) 24.4 N (min) 100 T (max) 30.4
Tape dimensions
According to Electronic Industries Association (EIA) Standard 481 rev. A, Feb. 1986
Tape width W 24 Tape hole spacing P0 (±0.1) 4 Component spacing P 12 Hole diameter D (±0.05) 1.55 Hole diameter D1 (min) 1.5 Hole position F (±0.1) 11.5 Compartment depth K (max) 2.85 Hole spacing P1 (±0.1) 2
End
All dimensions are in mm.
Start
Top
cover
tape
500mm min
Empty components pockets sealed with cover tape.
No componentsNo components Components
500mm min
User direction of feed
Doc ID 022514 Rev 1 37/40
Order codes VND5E050MCJ-E, VND5E050MCK-E

6 Order codes

Table 18. Device summary

Order codes
Package
Tube Tape and reel
PowerSSO-12 VND5E050MCJ-E VND5E050MCJTR-E
PowerSSO-24 VND5E050MCK-E VND5E050MCKTR-E
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VND5E050MCJ-E, VND5E050MCK-E Revision history

7 Revision history

Table 19. Document revision history

Date Revision Changes
21-Nov-2011 1 Initial release.
Doc ID 022514 Rev 1 39/40
VND5E050MCJ-E, VND5E050MCK-E
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