|
VNP35N07FI |
|
VNB35N07/VNV35N07 |
|
ºOMNIFETº: |
|
FULLY AUTOPROTECTED POWER MOSFET |
TYPE |
Vclamp |
RDS( on) |
Ilim |
VNP35N07FI |
70 V |
0.028 Ω |
35 A |
VNB35N07 |
70 V |
0.028 Ω |
35 A |
VNV35N07 |
70 V |
0.028 Ω |
35 A |
■LINEAR CURRENT LIMITATION
■THERMAL SHUT DOWN
■SHORT CIRCUIT PROTECTION
■INTEGRATED CLAMP
■LOW CURRENT DRAWN FROM INPUT PIN
■DIAGNOSTIC FEEDBACK THROUGH INPUT PIN
■ESD PROTECTION
■DIRECT ACCESS TO THE GATE OF THE POWER MOSFET (ANALOG DRIVING)
■COMPATIBLE WITH STANDARD POWER MOSFET
DESCRIPTION
The VNP35N07FI, VNB35N07 and VNV35N07 are monolithic devices made using STMicroelectronics VIPower M0 Technology, intended for replacement of standard power MOSFETS in DC to 50 KHz applications. Built-in thermal shut-down, linear current limitation and overvoltage clamp protect the chip in harsh
BLOCK DIAGRAM ( )
ISOWATT220 3
2
1
|
10 |
1 |
3 |
1 |
|
D2PAK |
PowerSO-10 |
TO-263 |
|
enviroments.
Fault feedback can be detected by monitoring the voltage at the input pin.
( ) PowerSO-10 Pin Configuration : INPUT = 6,7,8,9,10; SOURCE = 1,2,4,5; DRAIN = TAB
June 1998 |
1/13 |
VNP35N07FI-VNB35N07-VNV35N07
ABSOLUTE MAXIMUM RATING
Symbol |
Parameter |
|
Val ue |
Unit |
|
|
Po werSO-10 |
ISOW AT T220 |
|
|
|
D2PAK |
|
|
VDS |
Drain-source Voltage (Vin = 0) |
Internally Clamped |
V |
|
Vin |
Input Voltage |
|
18 |
V |
ID |
Drain Current |
Internally Limited |
A |
|
IR |
Reverse DC Output Current |
|
-50 |
A |
Vesd |
Electrostatic Discharge (C= 100 pF, R=1.5 KΩ) |
|
2000 |
V |
Pto t |
Total Dissipation at Tc = 25 oC |
125 |
40 |
W |
Tj |
Operating Junction Temperature |
Internally Limited |
oC |
|
Tc |
Case Operating Temperature |
Internally Limited |
oC |
|
Tst g |
Storage Temperature |
-55 to 150 |
oC |
THERMAL DATA
|
|
|
|
|
ISOW ATT 220 |
Pow erSO -10 |
D2PAK |
|
Rt hj-ca se |
Thermal |
Resistance |
Junction-case |
Max |
3.12 |
1 |
1 |
oC/W |
Rt hj-a mb |
Thermal |
Resistance |
Junction-ambient |
Max |
62.5 |
50 |
62.5 |
oC/W |
ELECTRICAL CHARACTERISTICS (Tcase = 25 oC unless otherwise specified) OFF
Symb ol |
Parameter |
Test Cond ition s |
Mi n. Typ . Max. Un it |
||||
VCLAMP |
Drain-source Clamp |
ID = 200 mA |
Vin = 0 |
60 |
70 |
80 |
V |
|
Voltage |
|
|
|
|
|
|
VCL TH |
Drain-source Clamp |
ID = 2 mA |
Vin = 0 |
55 |
|
|
V |
|
Threshold Voltage |
|
|
|
|
|
|
VI NCL |
Input-Source Reverse |
Iin = -1 mA |
|
-1 |
|
-0.3 |
V |
|
Clamp Voltage |
|
|
|
|
|
|
IDSS |
Zero Input Voltage |
VDS = 13 V |
Vin = 0 |
|
|
50 |
μA |
|
Drain Current (Vin = 0) |
VDS = 25 V |
Vin = 0 |
|
|
200 |
μA |
II SS |
Supply Current from |
VDS = 0 V |
Vin = 10 V |
|
250 |
500 |
μA |
|
Input Pin |
|
|
|
|
|
|
ON ( )
Symb ol |
Parameter |
|
Test Cond ition s |
Mi n. Typ . Max. |
Un it |
|
VIN(th) |
Input Threshold |
VDS = Vin |
ID + Iin = 1 mA |
0.8 |
3 |
V |
|
Voltage |
|
|
|
|
|
RDS( on) |
Static Drain-source On |
Vi n = 10 V |
ID = 18 A |
|
0.028 |
Ω |
|
Resistance |
Vi n = 5 V |
ID = 18 A |
|
0.035 |
Ω |
DYNAMIC
Symb ol |
Parameter |
Test Cond ition s |
Mi n. Typ . Max. Un it |
|||
gfs ( ) Forward |
VDS = 13 V |
ID = 18 A |
20 |
25 |
S |
|
|
Transconductance |
|
|
|
|
|
Coss |
Output Capacitance |
VDS = 13 V |
f = 1 MHz Vin = 0 |
|
980 1400 |
pF |
2/13
VNP35N07FI-VNB35N07-VNV35N07
ELECTRICAL CHARACTERISTICS (continued)
SWITCHING ( )
Symb ol |
Parameter |
td(on) |
Turn-on Delay Time |
tr |
Rise Time |
td(of f) |
Turn-off Delay Time |
tf |
Fall Time |
td(on) |
Turn-on Delay Time |
tr |
Rise Time |
td(of f) |
Turn-off Delay Time |
tf |
Fall Time |
(di/dt)on |
Turn-on Current Slope |
Qi |
Total Input Charge |
Test Cond ition s |
Mi n. Typ . Max. |
Un it |
||
VDD = 28 V |
Id = 18 A |
100 |
200 |
ns |
Vgen = 10 V |
Rgen = 10 Ω |
350 |
600 |
ns |
(see figure 3) |
|
650 |
1000 |
ns |
|
|
200 |
350 |
ns |
VDD = 28 V |
Id = 18 A |
500 |
800 |
ns |
Vgen = 10 V |
Rgen = 1000 Ω |
2.7 |
4.2 |
μs |
(see figure 3) |
|
10 |
16 |
μs |
|
|
4.3 |
6.5 |
μs |
VDD = 28 V |
ID = 18 A |
60 |
|
A/μs |
Vi n = 10 V |
Rgen = 10 Ω |
|
|
|
VDD = 12 V |
ID = 18 A Vi n = 10 V |
100 |
|
nC |
SOURCE DRAIN DIODE
Symb ol |
Parameter |
Test Cond ition s |
Mi n. Typ . |
Max. |
Un it |
|
VSD ( ) |
Forward On Voltage |
ISD = 18 A |
Vin = 0 |
|
1.6 |
V |
tr r( ) |
Reverse Recovery |
ISD = 18 A |
di/dt = 100 A/μs |
250 |
|
ns |
Qr r( ) |
Time |
VDD = 30 V |
Tj = 25 oC |
|
|
μC |
Reverse Recovery |
(see test circuit, figure 5) |
1 |
|
|||
IRRM ( ) |
Charge |
|
|
|
|
|
Reverse Recovery |
|
|
8 |
|
A |
Current
PROTECTION
Symb ol |
Parameter |
|
Test Cond ition s |
Mi n. Typ . Max. Un it |
|||
Ilim |
Drain Current Limit |
Vi n = 10 V |
VDS = 13 V |
25 |
35 |
45 |
A |
|
|
Vi n = 5 V |
VDS = 13 V |
25 |
35 |
45 |
A |
tdl im( ) |
Step Response |
Vi n = 10 V |
|
|
35 |
60 |
μs |
|
Current Limit |
Vi n = 5 V |
|
|
70 |
140 |
μs |
Tj sh( ) Overtemperature |
|
|
150 |
|
|
oC |
|
|
Shutdown |
|
|
|
|
|
|
Tj rs( ) |
Overtemperature Reset |
|
|
Igf( ) |
Fault Sink Current |
Vi n = 10 V |
VDS = 13 V |
|
|
Vi n = 5 V |
VDS = 13 V |
Eas( ) |
Single Pulse |
starting Tj = 25 oC VDD |
|
|
Avalanche Energy |
Vi n = 10 V |
Rgen = 1 KΩ |
( ) Pulsed: Pulse duration = 300 μs, duty cycle 1.5 % ( ) Parameters guaranteed by design/characterization
|
135 |
oC |
|
50 |
mA |
|
20 |
mA |
= 20 V |
2.5 |
J |
L = 10 mH |
|
|
3/13
VNP35N07FI-VNB35N07-VNV35N07
PROTECTION FEATURES
During normal operation, the Input pin is electrically connected to the gate of the internal power MOSFET. The device then behaves like a standard power MOSFET and can be used as a switch from DC to 50 KHz. The only difference from the user's standpoint is that a small DC current (Iiss) flows into the Input pin in order to supply the internal circuitry.
The device integrates:
-OVERVOLTAGE CLAMP PROTECTION: internally set at 70V, along with the rugged avalanche characteristics of the Power MOSFET stage give this device unrivalled ruggedness and energy handling capability. This feature is mainly important when driving inductive loads.
-LINEAR CURRENT LIMITER CIRCUIT: limits the drain current Id to Ilim whatever the Input pin voltage. When the current limiter is active, the device operates in the linear region, so power dissipation may exceed the capability of the heatsink. Both case and junction temperatures increase, and if this phase lasts long enough, junction temperature may reach the overtemperature threshold Tjsh.
-OVERTEMPERATURE AND SHORT CIRCUIT PROTECTION: these are based on sensing the chip temperature and are not dependent on the input voltage. The location of the sensing element on the chip in the power stage area ensures fast, accurate detection of the junction
temperature. Overtemperature cutout occurs at minimum 150oC. The device is automatically
restarted when the chip temperature falls below 135oC.
-STATUS FEEDBACK: In the case of an overtemperature fault condition, a Status Feedback is provided through the Input pin. The internal protection circuit disconnects the
input from the gate and connects it instead to ground via an equivalent resistance of 100 Ω. The failure can be detected by monitoring the voltage at the Input pin, which will be close to ground potential.
Additional features of this device are ESD protection according to the Human Body model and the ability to be driven from a TTL Logic circuit (with a small increase in RDS(on)).
4/13