ST VIPer53EDIP - E, VIPer53ESP - E User Manual

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Features

■ Switching frequency up to 300kHz

■ Current mode control with adjustable limitation

■ Soft start and shut-down control

■ Automatic burst mode in standby condition

(“Blue Angel“ compliant )

■ Undervoltage lockout with Hysteresis

■ Integrated start-up current source

■ Over-temperature protection

■ Overload and short-circuit control

■ Overvoltage protection

■ In compliance with the 2002/95/EC European

Directive

Description

The VIPer53E combines an enhanced current
mode PWM controller with a high voltage
MDMesh Power MOSFET in the same package.

Block diagram

VIPer53EDIP - E

VIPer53ESP - E

OFF-line Primary Switch

DIP-8PowerSO-10

Typical applications cover offline power supplies
with a secondary power capability ranging u p to
30W in wide range input voltage, or 50W in single
European voltage range an d DIP-8 package and
40W in wide range input voltage, or 65W in single
European voltage range and PowerSO-10
package, with the following benefits:

– O verload and short -circuit events

controlled by feedback monitoring and
delayed device reset;

– Efficient standby mode by enhanced pulse

skipping.

– Int egrated start-up current source is

disabled during normal operation to reduce
the input power.

OSC DRAIN

ON/OFF

OSCILLATOR

PWM

LATCH

R1
R2

S

FF

R3 R4 R5

BLANKING TIME

150/400ns

BLANKING

SELECTION

PWM

COMPARATOR

STANDBY

COMPARATOR

OVERLOAD

COMPARATOR

Q

1V

0.5V

4.4V

0.5V

H

COMP

CURRENT

AMPLIFIER

Vcc

I

COMP

4.5V

COMP SOURCE

VDD

8.4/

11.5V

18V

UVLO

COMPARATOR

125k

OVERVOLTAGE

COMPARATOR

8V

TOVL

4V

OVERTEMP.

DETECTOR

January 2006 DocRev1 1/31

www.st.com

31

Contents VIPer53EDIP - E / VIPer53ESP - E

Contents

1 Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1.1 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

3 Pin connections and function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

4 Rectangular U-I Output characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 8

5 Secondary Feedback Configuration Example . . . . . . . . . . . . . . . . . . . . 9

6 Current Mode Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

7 Sta ndby Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

8 High Voltage Start-up Current Source . . . . . . . . . . . . . . . . . . . . . . . . . . 13

9 Short-Circuit and Overload Protection . . . . . . . . . . . . . . . . . . . . . . . . . 15

10 Regulation Loop Stability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

11 Special Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

12 Software Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

13 Operation pictures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

14 Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

15 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

16 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

2/31 DocRev1

VIPer53EDIP - E / VIPer53ESP - E Electrical data

1 Electrical data

1.1 Maximum rating

Stressing the device above the rating listed in the “Absolute Maximum Ratings” table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the Operating sections of
this specification is not implied. Exposure to Absolute Maximum Rating conditions for
extended periods may affect device reliability . Refer also to the STMicroelectronics SURE
Program and other relevant quality documents.

Table 1. Absolute maximum rating

Symbol Parameter Value Unit

V

V

V

OSC

I

COMP

I

TOVL

Continuous Drain Source Voltage (TJ= 25 ... 125°C)

DS

I

Continuous Drain Curr ent Internally limited A

D

Supply Voltage 0 ... 19 V

DD

OSC Input Voltage Range

COMP and TOVL Input Current Range

Electrost atic Discharge:

V

ESD

Machine Model (R = 0Ω; C = 200pF)
Charged Device Model

T
T

T

STG

1. In order to improve the ruggedness of the device versus eventual drain overvoltages, a resistance of 1kΩ
should be inserted in series with the TOVL pin.\

Junction Operating Temperature Internally li m ited °C

J

Case Operating Temperature -40 to 150 °C

C

St orage Temperature -55 to 150 °C

1.2 Thermal data

Tabl e 2. Thermal data

Symbol Parameter

(1)

(1)

PowerSO-10

-0.3 ... 62 0 V

0 ... V

DD

-2 ... 2 mA

200

1.5

(1)

DIP-8

(2)

V

V

kV

Unit

R
R

1. When mounted on a standard single-sided FR4 board with 50mm² of Cu (at least 35 mm thick) connected
to the DRAIN pin.

2. When mounted on a standard single-sided FR4 board with 50mm² of Cu (at least 35 mm thick) connected
to the device tab.

Thermal Resistance Junction-case Max 2 20 °C/W

thJC

Thermal Resistance Ambient-case Max 60 80 °C/W

thJA

DocRev1 3/31

Electrical characteristics VIPer53EDIP - E / VIPer53ESP - E

2 Electrical characteristics

TJ = 25°C, V

= 13V, unless otherwise specified

DD

Tabl e 3. Power section

Symbol Parameter Test conditions Min. Typ. Max. Unit

BV

I

DSS

R

DS(on)

C

C

1. On clamped inductive load

2. This parameter can be used to compute the energy dissipated at turn on E
to source voltage V

Drain-Source

DSS

Voltage
Off State Dr ain

Current

Static Drain-Source
On St ate Resistance

t

Fall Time

fv

t

Rise Time

rv

Drain Capacitance

oss

Effecti ve Output

Eon

Capacitance

and the following formula:

DSon

I

= 1mA; V

D

V

= 500V; V

DS

I

= 1A; V

D

T

= 25°C

J

= 100°C

T

J

I

= 0.2A; V

D

I

= 1A; V

D

V

= 25V

DS

200V < V

E

ton

1

⋅⋅⋅=

-- - C

2

COMP

COMP

IN

= 300V

IN

DSon

Eon

= 0V

= 0V; Tj = 125°C

COMP

= 4.5V; V

= 300V

(1)

(1)

< 400V

2

300

= 0V

TOVL

(2)

DSon

300

1.5

V

⎛⎞

----------------

⎝⎠

620 V

150 µA

0.9 1

1.7

100 ns

50 ns

170 pF

60 pF

accord ing to the initial drain

ton

Ω

Ω

Tabl e 4. Oscillator Section

Symbol Parame ter T est Conditions Min. T yp. Max. Unit

R

F

OSC1

F

OSC2

V

OSChi

V

OSClo

Oscillator Frequency
Initial Ac cu r ac y

Oscillator Frequency
Total Variation

Oscillator Peak
Voltage

Oscill ato r Valley
Voltage

4/31 DocRev1

= 8kΩ; CT = 2.2nF

T

Figure 15 on page 23

R

= 8kΩ; CT = 2.2nF

T

Figure 17 on page 24

= V

V

DD

T

= 0 ... 100°C

J

DDon

... V

DDovp

95 100 105 kHz

;

93 100 107 kHz

9V

4V

VIPer53EDIP - E / VIPer53ESP - E Electrical characteristics

Table 5. Supply Section

Symbol Parameter T est Conditions Min. Typ. Max. Unit

V

DSstart

I

DDch1

I

DDch2

I

DDchoff

I

DD0

I

DD1

V

DDoff

V

DDonVDD

V

DDhyst

V

DDovp

Drain Voltage Star ting
Threshold

Startup Charging Current

Startup Charging Current
Startup Charging Current

in Thermal Shutdown
Operating Suppl y Current

Not Switc h in g
Operating Suppl y Current

Switching
V

Undervoltage

DD

Shutdown Threshol d

Startup Threshold

VDD Threshold
Hysteresis

V

Overvoltage

DD

Shutdown Threshol d

V

= 5V; I

DD

= 0 ... 5V; V

V

DD

Figure 9 on page 22

V

= 10V; V

DD

V

= 5V; V

DD

> TSD - T

T

J

= 0kHz; V

F

sw

=100kHz

F

sw

= 0mA

DD

= 100V

DS

= 100VFigure 9.

DS

= 100VFigure 11.

DS

HYST

= 0V

COMP

34 50 V

-12 mA

-2 mA

0mA

811mA

9mA

Figure 9 on page 22 7.5 8.4 9.3 V

Figure 9. 10.2 11.5 12.8 V

Figure 9. 2.6 3.1 V

Figure 9. 17 18 19 V

Table 6. Pwm Comparator Section

Symbol Parameter Test Conditions Min. Typ. Max. Unit

V

= 1 ... 4 V Figure 14.

H

COMP

V

COMPosVCOMP

I

Dlim

I

Dmax

V

COMPbl

t
t

t

ONmin1

∆V

Peak Drain Current
Limitation

Drain Current
Capability

Current Sense Delay

t

d

to Turn-Off
V

COMP

Change Threshold
Blanking Ti m e V

b1

Blanking Ti m e V

b2

Minimum On Time V

/ ∆I

COMP

DPEAK

Off set

Blanking Ti me

COMP

/dt = 0 1.7 2 2.3 V/A

dI

D

dI

/dt = 0 Figure 14. 0.5 V

D

I

= 0mA; V

COMP

Figure 14.

dI

/dt = 0

D

V

= V

COMP

/dt = 0 1.6 1.9 2.3 A

dI

D

I

= 1A 250 ns

D

COMPovl

TOVL

; V

= 0V

= 0V

TOVL

1.7 2 2.3 A

Figure 10 on page 22 1V

COMP

COMP

COMP

< V
> V
< V

COMPBL

COMPBL

COMPBL

Figure 10. 300 400 500 ns
Figure 10. 100 150 200 ns

450 600 750 ns

DocRev1 5/31

Electrical characteristics VIPer53EDIP - E / VIPer53ESP - E

Table 6. Pwm Comparator Section

Symbol Parameter Test Conditions Min. Typ. Max. Unit

t

ONmin2

V

COMPoff

V

COMPhi

I

COMP

1. In order to ensure a correct stability of the internal current source, a 10nF capacitor (minimum value 8nF)
should always be present on the COMP pin.

Minimum On Time V
V

Shutdown

COMP

Threshold

V

High Level

COMP

COMP Pull Up Current V

COMP

> V

COMPBL

250 350 450 ns

Figure 13 on page 23 0.5 V

I

COMP

COMP

(1)

=0mA

4.5 V

= 2.5V 0.6 mA

Table 7. Overload Protection Section

Symbol Parameter Test Conditions Min. Typ. Max. Unit

I

V

COMPovl

V

DIFFovl

V

1. V

OVLth

t

OVL

COMPovl

V

Overload

COMP

Threshold

V

COMPhi

to V

COMPovl

Voltage Difference

V

Overload

TOVL

Threshold
Overload Delay

is always lower than V

COMPhi

= 0mA Figu re7 on page 20

TOVL

(1)

V

= V

DD

I

= 0mA

TOVL

Figure 7.

DDoff

(1)

... V

DDreg

;

4.35 V

50 150 250 mV

Figure 7. 4V

C

= 100nF Figure 7.

OVL

8ms

Table 8. Over temperature Protection Section

Symbol Parameter Test Conditions Min. Typ. Max. Unit

T

T

HYST

Thermal Shutdown

SD

Temperature
Thermal Shutdown

Hysteresis

Figure 11 on page 22 140 160 °C

Figure 11 on page 22 40 °C

Table 9. Typical Output Power Capability

Type

European

(195 - 265Vac)

VIPer53EDIP-E 50W 30W

VIPer53ESP-E 65W 40W

US / Wide range

(85 - 265Vac)

6/31 DocRev1

VIPer53EDIP - E / VIPer53ESP - E Pin conne ctions and function

S

IN

S

T

E

I

V

I

S

3 Pin connections and function

Figure 1. Pin connection (top view)

TOVLCOMP

8

VDD

7

6

NC

54

DRA

OSC

OURCE

OURCE

1

2

3

DIP-8 PowerSO-10

Figure 2. Current and voltage conventions

DD

VDD

I

OSC

OSC

15V

DD

I

V

OSC

TOVL

V

TOVL

DRAIN

NC
NC
NC

VDD

OVL

I

COMP

V

COMP

1
2
3
4
5

DRAIN

SOURCECOMPTOVL

10

D

V

D

SOURC

9

NC

8

NC

7

OSC

6

COMP

Table 10. Pin function

Pin Name Pin Function

Power supply of the control circuits. Also provides the chargin g current of the external
capacitor dur ing start- up.

V

DD

SOURCE Power MOSFET source and circuit ground reference.

DRAIN

COMP

TOVL

OSC Allows the setting of the switching frequency through an external Rt-Ct network.

The functions of this pin are managed by four threshold volt ages:

- VDDon: Volt age value at which the device starts switching (Typically 11.5 V).

- VDDoff: V oltage value at which the device stops swit ching (Typically 8.4 V).

- VDDovp: Trig geri ng voltage of the overvoltage protecti on (Trimmed to 18 V).

Power MOSFET drain. Also used by the internal high voltage current source during
the start-up phase, to charge the ext ernal V

capacitor.

DD

Allows the setting of the dynamic characteristic of the converter through an external
passive network. The useful voltage range extends from 0.5V to 4.5V. The Power
MOSFET is always off below 0.5V, and the overload prot ection is triggered if the
voltage exceed s 4.3 5V. This action is delayed by th e tim ing cap acitor conn ected to t he
TOVL pin.

Allows the connection of an external capacitor for delaying the overload protection,
which is triggered by a voltage on the COMP pin higher than 4.4V.

DocRev1 7/31

Rectangular U-I Output characteristics VIPer53EDIP - E / VIPer53ESP - E

T

4 Rectangular U-I Output characteristics

Figure 3. Off Li ne Powe r S upply With Opt ocoupler Fee dback

F1

AC IN

C1

R1

C4

T1

R3

OSC

C12

C5

10nF

VDD

D1

C2

R4

DRAIN

CONTROL

SOURCECOMP TOV L

R5

R9
1k

C7

C6

R2

C3

T2

D2

D3

D4

U2

U3

L1

C8

C10

R8

C9

C11

R7

R6

DC OU

8/31 DocRev1

VIPer53EDIP - E / VIPer53ESP - E Secondary Feedback Configuration Examp le

5 Secondary Feedback Configuration Example

The secondary feedback is implemented through an optocoupler driven by a programmable
zener diode (TL431 type) as shown in Figure 3 on page 8

The optocoupler is connected in parallel with the compensation network on the COMP pin
which delivers a constant biasing current of 0.6mA to the optotransistor. This current does
not depend on the compensation voltage, and so it does not depend on the output load
either. Consequently, the gain of the optocoupler ensures a constant biasing of the TL431
device (U3), which is responsible for secondary regulation. If the optocoupler gain is
sufficiently low, no additio nal components are required to a minimum current biasing of U3.
Additionally, the low biasing current protects the optocoupler from premature failure.

The constant current biasing can be used to simplify the secondary circuit: instead of a
TL431, a simple zener and resistance network in series with the optocoupler diode can
insure a good secondary regulation. Current flowing in this branch remains constant just as
it does by using a TL431, so typical load regulation of 1% can be achieved from zero to full
output current with this simple configuration.

Since the dynamic characteristics of the converter are set on the secondary side through
components associated to U3, the compensation network has only a role of gain
stabilization for the optocoupler, and it s value can be freely chosen. R5 can be set to a fixed
value of 2.2kΩ, offering the possibility of using C7 as a soft start capacitor: When starting up
the converter, t he V IPer53E dev ice delivers a constant current of 0.6mA on the COMP pin,
creating a constant voltage of 1.3V in R5 and a rising slope across C7. This voltage shape,
together with the operating range of 0.5V to 4.5V provides a soft startup of the converter.
The rising speed of the output voltage can be set through the value of C7. The C4 and C6
values must be adjusted accordingly in order to ensure a correct startup.

DocRev1 9/31

Current Mode Topology VIPer53EDIP - E / VIPer53ESP - E

6 Current Mode Topology

The VIPer53E implements the conventional current mode control method for regulating the
output voltage. This kind of feedback includes two nested regulation loops:

The inner loop controls the peak primary current cycle by cycle. When the Power MOSFET
output transistor is on, the inductor current (primary side of the transformer) is monitored
with a SenseFET technique and converted into a voltage. When V

S reaches V

power switch is turned off. This structure is completely integrated as shown on the Block
Diagram of Figure on page 1, with the current amplifier, t he PWM comparator, the blanking
time function and the PWM latch. The following formula gives the peak current in the Power
MOSFET according to the compensation voltage:

I

Dpeak

V

--------------------------------------------------=

–

COMPVCOMPos

H

COMP

The outer loop defines the level at which the inner loop regulates peak current in the power
switch. For this purpose, V

is driven by the feedback network (TL431 through an

COMP

optocoupler in secondary feedback configuration, see Figure 3 on page 8) and is sets
accordingly the peak drain current fo r each switch i n g cycle.

As the inner loop regulates the peak primary current in the primary side of the transformer,
all input voltage changes are compensated for before impacting the output voltage. This
results in an improved line regulation, instantaneous correction to line changes, and better
stability for the voltage regulation loop.

COMP

, the

Current mode topology also provides a good converter start-up control. The compensation
voltage can be controlled to increase slowly during the start-up phase, so the peak primary
current will follow this soft voltage slope to provide a smooth output voltage rise, without any
overshoot. The simpler voltage mode structure whic h only controls the duty cycle, leads
generally to high current at start-up with the risk of transformer saturation.

An integrated blanking filter inhibits the PWM comparator output for a short time after the
integrated Power MOSFET is switched on. This function prevents anomalous or premature
termination of the switching pulse in the case of current spikes caused by primary side
transformer capacitance or secondary side rectifier reverse recovery time when working in
continuous mode.

10/31 DocRev1

VIPer53EDIP - E / VIPer53ESP - E Standby Mode

7 Standby Mode

The device offers a special feature to address the low load condition. The corresponding
function described hereafter consists of reducing the switching frequency by going into burst
mode, with the following benefits:

– It reduces the switching losses, thus providing low consumption on the mains lines.

The device is compliant with “Blue Angel” and other similar standards, requiring less
than 0.5 W of input power when in standby.

– It allows the regulation of the output voltage, even if the load corresponds to a duty

cycle that the device is not able to generate because of the internal blanking time,
and associated minimum turn on.

For this purpose, a comparator monitores the COMP pin voltage, and maintains the PWM
latch and the Power MOSFET in the Off state as long as V
Block Diagram on page 2). If the output load requires a duty cycle below the one defined by
the minimum turn on of the device, the V

0.5V threshold (V

COMPoff

). The Power MOSFET can be completely Off for some cycles, and

resumes normal operation as soon as V

net decreases its voltage until it reaches this

COMP

is higher than 0.5V. The output voltage is

COMP

regulated in burst mode. The corresponding ripple is not higher than the nominal one at full
load.

remains below 0.5V (See

COMP

In addition, the minimum turn on time which defines the frontier between normal operation
and burst mode changes according to V

value. Below 1.0V (V

COMP

COMPbl

), the blanking
time increases to 400ns, whereas for higher voltages, it is 150ns Figure 10 on page 22 The
minimum turn on times resulting from these values are respectively 600 ns and 350 ns,
when taking into account internal propagation time. This brutal change induces an
hysteresis between normal operation and burst mode as shown on Figure 10 on page 22

When the output power decreases, the system reaches point 2 where V
V

COMPbl

. The minimum turn-on time passes immediately from 350ns to 600ns, exceeding

COMP

equals

the effective turn-on time that should be needed at this output power level. Therefore the
regulation loop will quickly drive V

COMP

to V

COMPoff

(Point 3) in order to pass into burst
mode and to control the output voltage. The corresponding hysteresis can be seen on the
switching frequency which passes from F

which is the normal switching frequency set

SWnom

by the components connected to the OSC pin and to FSWstby. Note: This frequency is
actually an equivalent number of switching pulses per second, rather than a fixed switching
frequency since the device is working in burst mode.

As long as the power remains below P
V

COMPsd

and the converter works in burst mode. Its “density” increases (i.e. the number of

missing cycles decreases) as the power approaches P

the output of the regulation loop remains stuck at

RST

and finally resumes normal

RST

operation at point 1. The hysteresis cannot be seen on the switching frequency, but it can be
seen in the sudden surge of the COMP pin voltage from point 3 to point 1 at that power
level.

The power points value P

RST

P

RST

and P

1

-- - F
2

are defined by the following formulas:

STBY

• tb1td+()•

SWnom

2

V2• IN

------ -•=

Lp

1

P

STBY

1

• Ip2V

-- - F

SWnom

2

DocRev1 11/31

()• Lp•=

COMPbl

Standby Mod e VIPer53EDIP - E / VIPer53ESP - E

P

ton

Where Ip(V
voltage of V

COMPbl2

COMPbl

) is the peak Power MOSFET current corresponding to a compensation
(1V). Note: The power point PSTBY where the converter is going into

burst mode does not depend on the input voltage.
The standby frequency F

SWstby

is given by:

P

SWstb y

STBY

----------------- F

•=

P

RST

SWnom

The ratio between the nominal and standby switching frequencies can be as high as 4,
depending on the Lp value and input voltage.

Figure 4. .Standby Mode Implementation

IN

RST

3

V

COMPsd

V

COMPoff

F

SWstby

1

2

V

V

COMPbl

1

3

2

F

SWnom

COMP

F

SW

600ns
Minimum
turn on

350ns

P

P

P

STBY

12/31 DocRev1

VIPer53EDIP - E / VIPer53ESP - E High Voltage Start-up Current Source

8 High V oltage Start-up Current Source

An integrated high voltage current source provides a bias current from the DRAIN pin during
the start-up phase. This current is partially absorbed by internal control circuits in standby
mode with reduced consumption, and also supplies the external capacitor connected to the
V

pin. As soon as the voltage on this pin reaches the high voltage threshold V

DD

UVLO logic, the device turns into active mode and starts switching. The start-up current
generator is switched off, and the converter should normally provide the needed current on
the V

pin through the auxiliary winding of the transformer, as shown on Figure3 on

DD

page 8.

DDon

of the

The external capacitor C

on the VDD pin must be sized according to the time needed by

VDD

the converter to start-up, when the device starts switching. This time tss depends on many
parameters, including transformer design, output capacitors, soft start feature, and
compensation network implemented on the COMP pin and poss ible secondary fee dback
circuit. The following formula can be used for defining the minimum capacitor needed:

I

tss⋅

VDD

DD1

------------------------>

V

DDhyst

starts from 0V with a charging

DD

is reached, the charging current is reduced

DDoff

, and the auxiliary winding delivers some

DDon

, and

SDU

C

Figure 9 on page 22 shows a typical start-up event. V

current I
down to I
rise. Device starts switching for V
energy to V

The charging current change at V

at about 9 mA. When about V

DDch1

which is about 0.6mA. This lower current leads to a slope change on the VDD

DDch2

capacitor after the start-up time tss.

DD

equal to V

DD

allows a fast co mplete start-u p time t

DDoff

maintains a low restart duty cycle. This is especially useful for short circuits and overloads
conditions, as described in the following section.

DocRev1 13/31

High Voltag e Start-up Current Source VIPer53EDIP - E / VIPer53ESP - E

Figure 5. Start-up Waveforms

I

DD

I

DD1

t

I

DDch2

I

DDch1

V

V

DDreg

V

V

DD

DDst

DDsd

tSS

tSU

t

14/31 DocRev1

VIPer53EDIP - E / VIPer53ESP - E Short-Circuit an d Overload Protection

9 Short-Circuit and Overload Protection

A V

COMPovl

threshold of about 4.4V has been implemented on the COMP pin. When V

COMP

goes above this level, the capacitor connected on the TOVL pin begins to charge. When
reaching typically V

(4V), the internal MOSFET driver is disabled and the device stops

OVLth

switching. This state is latched because of to the regulation loop which maintains the COMP
pin voltage above the V

COMPovl

energy from the auxiliary winding, its voltage drops down until it reaches V
device is reset, recharging the V

threshold. Since the VDD pin does not receive any more

off and the

capacitor for a new rest a r t cycle. Note: If VCOMP drops

DD

DD

below the VCOMPovl threshold for any reason during the VDD drop, the device resumes
switching immediately.

The device enters an endless restart sequence if the overload or short circuit condition is
maintained. The restart duty cycle D

is defined as the time ratio for which the device tries

RST

to restart, thus delivering its full power capability to the output. In order to keep the whole
converter in a safe state during this event, D

must be kept as low as possible, without

RST

compromising the real start-up of the converter. A typical value of about 10% is generally
sufficient. For this purpose, both V

and TOVL capacitors can be used to satisfy the

DD

following conditions:

C

VDD

810

C

Refer to the previous start-up section for the definition of tss, and C

12.5 106–tss⋅⋅>

OVL

4 1

⎛⎞

-------------- 1–

⎝⎠

D

RST

C

⋅

OVLIDDch2

------------------------------------⋅⋅ ⋅>

V

DDhyst

must also be

VDD

checked against the limit given in this section. The maximum value of the two calculus will
be adopted.

All this behavior can be observed on Figure 2 on page 7. In Figure 7 on page 20 the value of
the drain current Id for V
the drain current to take into account for design purposes. Since I

COMP

= V

COMPovl

is shown. The corresponding parameter I

represents the

Dmax

Dmax

is

maximum value for which the overload protection is not triggered, it defines the power
capability of the power supply.

DocRev1 15/31

Regulation Loop Stability VIPer53EDIP - E / VIPer53ESP - E

10 Regulation Loop Stability

The complete converter open loop transfer function can be built from both power cell and
the feedback network transfer functions. A theoretical example can be seen in Figure 11 on

page 22 for a discontinuous mode flyback loaded by a simple resistor.

A typical schematic corresponding to this situation can be seen on Figure 3 on page 8. The
transfer function of the power cell is represented as G(s) in .Figure 11 on page 22 It exhibits
a pole which depends on the output load and on the output capacitor value. As the load of a
converter may change, two curves are shown for two different values of output resistance
value, R
capacitor ESR. Note: The overall transfer function does not depend on the input voltage
because of the current mode control. A typical regulation loop is shown on Figure 3 on

page 8 and has a fixed behavior represented by F(s) on Figure 11 on page 22. A double

zero due to the R
and R

The total transfer function is shown as F(s). G(s) at the bottom of Figure 11 on page 22. For
maximum load (plain line), the load pole begins exactly where the zeros of the COMP pin
and the TL431 stop, and this results in a first order decreasing slope until it reaches the zero
of the output capacitor ESR. The point where the complete transfer function has a unity gain
is known as the regulation bandwidth and has a double interest:

– The higher it is, the faster the reaction will be to an eventual load change, and the

– The phase shift in the complete system at this point has to be less than 135° to

and RL2. A zero at higher frequency values then appears, due to the output

L1

network on the COMP pin and to the integrator built around the TL431

1-C1

is set at the same value as the maximum load RL2 pole.

2-C2

smaller the output voltage change will be.

ensure good stability. Ge nerally, a first-order slope gives 90° of phase shift, and a
second-order gives 180°.

In Figure 3 on page 8, the unity gain is reached in a first order slope, so the stability is
ensured.

The dynamic load regulation is improved by increasing the regulation bandwidth, but some
limitations have to be respected:

1. As the transfer function above zero due the ESR capacitor is not reliable (the ESR itself
is not well specified, and other parasitic effects may take place), the bandwidth should
always be lower than the minimum of FC and ESR zero

2. As the highest bandwidth is obtained with the highest output power (plain line with RL2
load in Figure 3, the above criteria will be checked for this condition and allows the
value of R4 i f R1 is set to a fixed value (e.g., (2.2kΩ).

As the highest bandwidth is obtained with the highest output power (Plain line with R

L2

load
in Figure 3), the above criteria will be checked for this condition and allows to define the
value of R

, if R1 is set fixed (2.2kΩ, for instance). The following formula can be derived:

4

with:

and:

P

MAX

R

---------------------

4

P

OUT2

P

OUT2

P

MAX

GOR

--------------------------------------------------------⋅=

F

⋅⋅

BW2RL2COUT

2

V

OUT

-----------------=

R

L2

2

1

-- - LPI

⋅⋅ ⋅=

LIM

2

⋅

1

F

SW

Go is the current transfer ratio of the optocoupler.

16/31 DocRev1

VIPer53EDIP - E / VIPer53ESP - E Regulation Loop Stability

The lowest load gives another condition for stability: The frequency F

must not

BW1

encounter the third order slope generated by the load pole, the R1-C1 network on the
COMP pin and the R2-C2 network at the level of the TL431 on secondary side. This
condition can be met by adjusting both C

C

C

2

with:

and C2 values:

1

RL1C

⋅

OUT

-------------------- -------------- -

1

G

O

6.3

-------- - R

⋅⋅

R

4

RL1C

⋅

-------------------- -------------------------- -

6.3

OUT

G

O

-------- - R1R

⋅⋅⋅

R

4

P

OUT1

P

OUT1

----------------- ----⋅>

P

2

MAX

1

P

OUT1

----------------- ----⋅>

P

MAX

2

2

V

OUT

-------------------=

R

L1

The above formula gives a minimum value for C1. It can be then increased to provide a
natural soft start function as this capacitor is charged by the current I

COMP

at start-up.

DocRev1 17/31

Special Recommendations VIPer53EDIP - E / VIPer53ESP - E

11 Special Recommendations

10nF capacitor (minimum value: 8nF) should always be connected to the COMP pin to
ensure correct stability of the internal current source Figure 12 on page 22.

In order to improve the ruggedness of the device versus eventual drain overvoltages, a
resistance of 1kΩ should be inserted in series with the TOVL pin, as shown on Figure 12 on

page 22

Note: This resistance does not impact the overload delay, as its value is negligible prior to the

Ω

internal pull-up resistance (about 125k

).

18/31 DocRev1

VIPer53EDIP - E / VIPer53ESP - E So ftware Implementation

12 Software Implementation

All the above considerations and some others are included included in ST design software
which provides all of the needed components around the VIPer device for specified output
configurations, and is available on www.st.com.

DocRev1 19/31

Operation pictures VIPer53EDIP - E / VIPer53ESP - E

V

13 Operation pictures

Figure 6. Rise and Fall time

I

D

C<<C

OSS

CLD

t

V

DS

90%

OSC

VDD

CONTROL

DRAIN

300

t

fv

10%

Figure 7. Overloaded Event

V

DD

V

DDon

V

DDoff

V

COMP

V

TOVL

V

OVLth

t

rv

Normal

operation

t

OVL

SOURCECOMP TOVL

t

Abnormal

operation

V

DIFFovl

V

DS

Switching

20/31 DocRev1

Not

switching

VIPer53EDIP - E / VIPer53ESP - E Operation pictures

Fig ure 8. Complet e Convert er Transfer Fu n ction

1

------------- ------------- --------- ------ -

π RL1C

⋅⋅

P

MAX

3.2

------------- --------⋅

P

OUT1

P

MAX

3.2

---------- ---------- -⋅

P

OUT2

OUT

1

------------ ------------- --------- ------- -

π RL2C

⋅⋅

OUT

1

1

------------- ------------- --------- --------- -------

2 π ESR C

⋅⋅ ⋅

OUT

FS

R

1

G

-------⋅

O

R

4

1

FS. GS

1

1

---------- ------------- --------- --------- ------------- --------- ---- -

2 π R

⋅⋅ ⋅

COMPCCOMP

FBW1

FBW2

F

C

DocRev1 21/31

Operation pictures VIPer53EDIP - E / VIPer53ESP - E

Figure 9. Start-up V

I

DD

I

I

DDch2

DD0

V

DDhyst

V

DDoff

current Figure 10. Blanking Time

DD

t

b

t

b1

V

V

DDon

DD

t

b2

VDS = 100 V

F

= 0 kHz

SW

I

DDch1

V

COMPbl

Figure 11. Thermal S hu tdow n Figure 12. Overvoltage Event

V

V

DD

DDovp

TSD-T

T

T

HYST

j

SD

V

COMPhi

V

COMP

V

V

COMP

V

DDon

DD

Automatic

startup

V

COMP

V

DS

Abnormal
operation

Switching

Not

switching

22/31 DocRev1

VIPer53EDIP - E / VIPer53ESP - E Operation pictures

t

t

t

Vcc

Figure 13. Shutdown Acti on Fig ure 14. C om p Pi n Gai n and Offset

V

OSC

V

OSChi

V

OSClo

I

Dpeak

V

COMP

V

COMPoff

I

D

Figure 15. Oscillator Schematic

Rt

VDD

I

Dlim

I

Dmax

V

COMPos

Slope = 1 / H

COMP

V

COMPovl

V

COMPhi

V

COMP

OSC

PWM

section

320 Ω

Ct

SOURCE

DocRev1 23/31

Operation pictures VIPer53EDIP - E / VIPer53ESP - E

0

Frequency (kHz)

R

(KΩ)

0

Normalised Frequency

Temperature (°C)

The switching frequency settings shown on the graphic here below is valid within the
following boundaries:

R

> 2kΩ

t

= 300kHz

F

SW

Figure 16. Oscillator Settings

300

100

2.2nF

4.7nF

10nF

22nF

10

11010

1nF

T

Figure 17. Typical Frequency Variation vs. Junction Temperature

24/31 DocRev1

1.04

1.02

1

0.98

0.96

-20 0 20 40 60 80 100 12

VIPer53EDIP - E / VIPer53ESP - E Operation pictures

0

Norm a lis ed ID lim

Temperature (°C)

Figure 18. Typ ic al Current Limitation vs. Junction Temperature

1.04

1.02

1

0.98

0.96

-20 0 20 40 60 80 100 12

DocRev1 25/31

Mechanical Data VIPer53EDIP - E / VIPer53ESP - E

14 Mechanical Data

In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second level interconnect. The category of
second Level Interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com.

26/31 DocRev1

VIPer53EDIP - E / VIPer53ESP - E Mechanical Data

Table 11. DIP8 Mechanical Data

Dimensions

Databook (mm )

Ref.

Nom. Min Max

A 5.33
A1 0.38
A2 2.92 3.30 4.95

b 0.36 0.46 0.56
b2 1.14 1.52 1.78

c 0.20 0.25 0.36

D 9.02 9.27 10.16
E 7.62 7.87 8.26

E1 6.10 6.35 7.11

e2.54
eA 7.62
eB 10.92

L 2.92 3.30 3.81

Package Weigh t Gr. 470

Figure 19. Package Dimensions

DocRev1 27/31

Mechanical Data VIPer53EDIP - E / VIPer53ESP - E

Tabl e 12. PowerSO-10 Mechanic al Data

Dimensions

Ref.

Nom. Min Max

A 3.35 3.65

A1 0.00 0.10

B 0.40 0.60

c 0.35 0.55

D 9.40 9.60

D1 7.40 7.60

E 9.30 9.50
E1 7.20 7.40
E2 7.20 7.60
E3 6.10 6.35
E4 5.90 6.10

e 1.27
F 1.25 1.35
H 13.80 14.40

h 0.50

L 1.20 1.80

q 1.70
α 0° 8°

Databook (mm )

Figure 20. Package Dimensions

28/31 DocRev1

VIPer53EDIP - E / VIPer53ESP - E Order codes

15 Order codes

Tabl e 13. Order codes

Part Number Package Shipment

VIPer53ESPTR - E PowerSO-10 Tape and reel

VIPer53ESP - E PowerSO-10 Tube

VIPer53EDIP - E DIP-8 Tube

DocRev1 29/31

Revision history VIPer53EDIP - E / VIPer53ESP - E

16 Revision history

Table 14. Document revision history

Date Revision Changes

12-Jan-2006 1 Initial releas e.

30/31 DocRev1

VIPer53EDIP - E / VIPer53ESP - E Revision history

I

s

o

d

b

t

t

t

nformation furnished is believed to be accurate and reliable. However, STMicroelectronic s assumes no responsibilit y for the consequence

f use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is grante

y implicatio n or otherwise under any patent or pat ent rights of STMicroelectroni cs. Specifications mentioned in this publicat i on are subjec

o change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are no

authorized for use as critical components in life support devices or sy stems without express writt en approval of STM i croelectronics.

The ST logo is a registered trademark of STM icroelectroni cs.

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DocRev1 31/31