查询USBLC6-4SC6供应商
®
ASD
(Application Specific Devices)
MAIN APPLICATIONS
■ USB2.0 ports up to 480Mb/s (high speed)
■ Backwards compatible with USB1.1 low and
full speed
■ Ethernet port: 10/100Mb/s
■ SIM card protection
■ Video line protection
■ Portable electronics
DESCRIPTION
The USBLC6-4SC6 is a monolithic Application
Specific Discrete dedicated to ESD protection of
high speed interfaces, such as USB2.0, Ethernet
links and Video lines.
Its very low line capacitance secures a high level
of signal integrity without compromising in
protecting sensitive chips against the most
stringent characterized ESD strikes.
USBLC6-4SC6
VERY LOW CAPACITANCE
ESD PROTECTION
SOT23-6L
Figure 1: Functional Diagram
FEATURES
■ 4 data lines protection
■ Protects V
■ Very low capacitance: 3pF typ.
■ SOT23-6L package
■ RoHS compliant
BUS
BENEFITS
■ Very low capacitance between lines to GND for
optimized data integrity and speed
■ Low PCB space consuming, 9mm² maximum
foot print
■ Enhanced ESD protection
■ IEC61000-4-2 level 4 compliance guaranteed
at device level, hence greater immunity at
system level
■ ESD protection of V
. Allows ESD current
BUS
flowing to Ground when ESD event occurs on
data line
■ High reliability offered by monolithic integration
■ Low leakage current for longer operation of
battery powered devices
■ Fast response time
■ Consistent D+ / D- signal balance:
- Best capacitance matching tolerance
I/O to GND = 0.015pF
- Compliant with USB 2.0 requirements < 1pF
1
1
I/O1 I/O4
2
GND V
3
I/O2 I/O3
6
5
BUS
4
Table 1: Order Code
Part Number Marking
USBLC6-4SC6 UL46
COMPLIES WITH THE FOLLOWING STANDARDS:
■ IEC61000-4-2 level4:
15kV (air discharge)
8kV (contact discharge)
February 2005
REV. 2
1/10
USBLC6-4SC6
Table 2: Absolute Ratings
Symbol Parameter Value Unit
At device level:
V
Peak pulse voltage
PP
IEC61000-4-2 air discharge
IEC61000-4-2 contact discharge
MIL STD883C-Method 3015-6
15
15
25
kV
T
T
T
Table 3: Electrical Characteristics (
Storage temperature range -55 to +150 °C
stg
Maximum junction temperature 125 °C
j
Lead solder temperature (10 seconds duration) 260 °C
L
= 25°C)
Tamb
Symbol Parameter Test Conditions
V
RM
I
RM
V
BR
V
V
CL
Reverse stand-off voltage
Leakage current
Breakdown voltage between V
and GND
Forward voltage
F
Clamping voltage
V
= 5V
RM
BUS
= 1mA
I
R
I
= 10mA
R
= 1A, tp = 8/20µs
I
PP
Any I/O pin to GND
I
= 5A, tp = 8/20µs
PP
Any I/O pin to GND
C
i/o-GND
∆C
C
∆C
i/o-GND
i/o-i/o
i/o-i/o
Capacitance between I/O and GND
Capacitance between I/O
= 1.65V 3 4
V
R
= 1.65V 1.85 2.7
V
R
Value
Unit
Min. Typ. Max.
5V
2µA
6V
0.86 V
12 V
17 V
pF
0.015
pF
0.04
2/10
USBLC6-4SC6
Figure 2: Capacitance versus voltage (typical
values)
C(pF)
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
C =I/O-GND
O
C =I/O-I/O
j
Data line voltage (V)
F=1MHz
V =30mV
OSC RMS
T =25°C
j
Figure 4: Relative variation of leakage current
versus junction temperature (typical values)
I[T
] / I [T
100
RM j
RM j
=25°C]
V =5V
BUS
Figure 3: Line capacitance versus frequency
(typical values)
C(pF)
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
1 10 100 1000
V =0V
CC
V =1.65V
CC
F(MHz)
V =30mV
OSC RMS
T =25°C
j
Figure 5: Frequency response
USBLC6-4SC6
0.00
S21(dB)
-5.00
(50 )Ω
10
T (°C)
1
25 50 75 100 125
j
-10.00
-15.00
-20.00
100.0k 1.0M 10.0M 100.0M 1.0G
F(Hz)
3/10
USBLC6-4SC6
TECHNICAL INFORMATION
1. SURGE PROTECTION
The USBLC6-4SC6 is particularly optimized to perform surge protection based on the rail to rail topology.
The clamping voltage V
with: V
= VT + Rd.I
F
(VF forward drop voltage) / (VT forward drop threshold voltage)
We assume that the value of the dynamic resistance of the clamping diode is typically:
= 1.4Ω and VT = 1.2V.
R
d
For an IEC61000-4-2 surge Level 4 (Contact Discharge: V
approximation, we assume that : I
So, we find:
V
CL
V
CL
Note: the calculations do not take into account phenomena due to parasitic inductances.
2. SURGE PROTECTION APPLICATION EXAMPLE
If we consider that the connections from the pin V
two tracks of 10mm long and 0.5mm large; we assume that the parasitic inductances Lw of these tracks
are about 6nH. So when an IEC61000-4-2 surge occurs, due to the rise time of this spike (tr=1ns), the
voltage V
has an extra value equal to Lw.dI/dt.
CL
The dI/dt is calculated as: dI/dt = Ip/tr = 24 A/ns
The overvoltage due to the parasitic inductances is: Lw.dI/dt = 6 x 24 = 144V
By taking into account the effect of these parasitic inductances due to unsuitable layout, the clamping
voltage will be :
V
CL
V
CL
We can reduce as much as possible these phenomena with simple layout optimization.
It’s the reason why some recommendations have to be followed (see paragraph “How to ensure a good
ESD protection”).
can be calculated as follow :
CL
+ = V
V
CL
V
- = - VF for negative surges
CL
p
+ VF for positive surges
BUS
= Vg / Rg = 24A.
p
+ = +39V
- = -34V
+ = +39 + 144 = 183V
- = -34 - 144 = -178V
=8kV, Rg=330Ω), V
g
to VCC and from GND to PCB GND are done by
BUS
= +5V, and if in first
BUS
Figure 6: ESD behavior; parasitic phenomena due to unsuitable layout
183V
di
Lw
dt
VV
+
CC F
-V
di
-Lw
dt
-178V
4/10
ESD
SURGE
VI/O
Lw
Lw
F
V+ =
CL
V- =
CL
Lw
di
dt
V +V +Lw
BUS F
di
-V -Lw
F
dt
+V
CC
di
surge >0
dt
surge <0
V
BUS
V
I/O
di
dt
GND
F
V
tr=1ns
tr=1ns
V
+
CL
POSITIVE
SURGE
NEGATIVE
SURGE
-
CL
t
t
USBLC6-4SC6
3. HOW TO ENSURE A GOOD ESD PROTECTION
While the USBLC6-4SC6 provides a high immunity to ESD surge, an efficient protection depends on the
layout of the board. In the same way, with the rail to rail topology, the track from the V
supply +V
and from the V
CC
pin to GND must be as short as possible to avoid overvoltages due to
BUS
parasitic phenomena (see figure 6).
It’s often harder to connect the power supply near to the USBLC6-4SC6 unlike the ground thanks to the
ground plane that allows a short connection.
To ensure the same efficiency for positive surges when the connections can’t be short enough, we
recommend to put close to the USBLC6-4SC6, between V
and ground, a capacitance of 100nF to
BUS
prevent from these kinds of overvoltage disturbances (see figure 7).
The add of this capacitance will allow a better protection by providing during surge a constant voltage.
The figures 8, 9 and 10 show the improvement of the ESD protection according to the recommendations
described above.
pin to the power
BUS
Figure 7: ESD behavior: optimized layout and
add of a capacitance of 100nF
V+
CL
ESD
SURGE
I/O
VI/O
REF1=GND
Lw
C=100nF
V+ V
V+= surge >0
CL CC F
VV
-- =
CL F
REF2=+V
surge <0
V-
CL
POSITIVE
SURGE
NEGATIVE
SURGE
t
t
CC
Figure 9: Remaining voltage after the
USBLC6-4SC6 during positive ESD surge
Figure 8: ESD behavior: measurements
conditions (with coupling capacitance)
ESD
SURGE
TEST BOARD
+5V
C=100nF
USBLC6-4SC6
Figure 10: Remaining voltage after the
USBLC6-4SC6 during negative ESD surge
IMPORTANT:
A main precaution to take is to put the protection device closer to the disturbance source (generally the
connector).
Note: The measurements have been done with the USBLC6-4SC6 in open circuit.
5/10
USBLC6-4SC6
4. CROSSTALK BEHAVIOR
4.1. Crosstalk phenomena
Figure 11: Crosstalk phenomena
R
V
G1
G1
R
G2
Line 1
Line 2
β
α
VG1V
+
R
L1
1
G2
12
V
G2
DRIVERS
R
L2
RECEIVERS
α
β
+
V
V
G2
G1
21
2
The crosstalk phenomena are due to the coupling between 2 lines. The coupling factor (β12 or β 21)
increases when the gap across lines decreases, particularly in silicon dice. In the example above the
expected signal on load R
This part of the V
signal represents the effect of the crosstalk phenomenon of the line 1 on the line 2.
G1
is α2VG2, in fact the real voltage at this point has got an extra value β21VG1.
L2
This phenomenon has to be taken into account when the drivers impose fast digital data or high frequency
analog signals in the disturbing line. The perturbed line will be more affected if it works with low voltage
signal or high load impedance (few kΩ).
Figure 12: Analog crosstalk measurements
TRACKING GENERATOR
50
Ω
Vg
TEST BOARD
USBLC6-4SC6
+5V
Vin
C=100nF
SPECTRUM ANALYSER
Vout
50
Ω
Figure 12 gives the measurement circuit for the analog application. In usual frequency range of analog
signals (up to 240MHz) the effect on disturbed line is less than -55 dB (please see figure 13).
Figure 13: Analog crosstalk results
-30.00
0.00
dB
Aplac 7.70 User: ST Microelectronics Oct 29 2004
USBLC6-4SC6
As the USBLC6-4SC6 is designed to protect high
speed data lines, it must ensure a good transmission of operating signals. The frequency response
(figure 5) gives attenuation information and shows
that the USBLC6-4SC6 is well suitable for data
line transmission up to 480 Mbit/s while it works
-60.00
as a filter for undesirable signals like GSM
(900MHz) frequencies, for instance.
-90.00
-120.00
100.0k 1.0M 10.0M 100.0M 1.0G
6/10
f/Hz
5. APPLICATION EXAMPLES
Figure 14: USB2.0 port application diagram using USBLC6-4SC6
USBLC6-4SC6
DEVICEUPSTREAM
TRANSCEIVER
V
BUS
R
X LS/FS
R
X HS
T
X HS
R
X LS/FS -
R
X HS -
T
X HS -
GND GND
T
X LS/FS
T
X LS/FS -
DEVICEUPSTREAM
TRANSCEIVER
V
BUS
R
X LS/FS
R
X HS
T
X HS
R
X LS/FS -
R
X HS -
T
X HS -
GND
T
X LS/FS
T
X LS/FS -
+ 3.3V
R
PU
SW
2
SW
1
+ R
+ R
+ T
USB
connector
V
BUS
D+
+ 5V
D-
R
S
+ T
R
S
USBLC6-2SC6
GND
R
PD
+ 3.3V
R
PU
SW
2
SW
1
+
+
+
USB
connector
V
BUS
D+
D-
R
S
+
R
S
USBLC6-2P6
GND
USBLC6-4SC6
R
PD
Protecting
Bus Switch
R
R
R
PD
R
R
R
PD
DOWNSTREAM
TRANSCEIVER
V
BUS
X LS/FS
+
X HS
+
X HS
R
X LS/FS -
R
X HS -
T
X HS -
S
X LS/FS
S
T
X LS/FS -
R
X LS/FS
R
+
X HS
T
+
X HS
R
X LS/FS -
R
X HS -
T
X HS -
GND
S
T
X LS/FS
S
T
X LS/FS -
HUB-
+
+
+
+
Mode
SW
SW
1
2
ClosedOpenLow Speed LS
OpenClosedFull Speed FS
OpenClosed then openHigh Speed HS
Figure 15: T1/E1/Ethernet protection
Tx
SMP75-8
100nF
Rx
SMP75-8
+V
CC
USBLC6-4SC6
DATA
TRANSCEIVER
7/10
USBLC6-4SC6
6. PSPICE MODEL
Figure 16 shows the PSPICE model of one USBLC6-4SC6 cell. In this model, the diodes are defined by
the PSPICE parameters given in figure 17.
Figure 16: PSPICE model
Lpinsot 23
100mLbondsot 23
MODEL = Dhigh
Lpinsot 23
io1
Lpinsot 23
io2
Lpinsot 23
io3
Lpinsot 23
io4
Lbondsot23 100m
Lbondsot23 100m
Lbondsot23 100m
Lbondsot23 100 m
MODEL = Dlow MODEL = Dlow
MODEL = Dhigh
MODEL = Dhigh MODEL = Dhigh
MODEL = Dlow MODEL = Dlow
100mLbondsot23
Lbondsot23
100m
MODEL = Dzener
Lpi nsot 23
Vcc
RvccLvc c
Rg n dLgnd
Note: This simulation model is available only for an ambient temperature of 27°C.
Figure 17: PSPICE parameters Figure 18: USBLC6-4SC6 PCB layout
considerations
8/10
DzenerDhighDlow
7.35050BV
20p2.4p2.4pCJ0
1m1m1mIBV
2.420.0180.038IKF
3.21p2.27f55.2pIS
100p100p100pISR
1.241.131.62N
0.33330.33330.3333M
0.420.630.38RS
0.60.60.6VJ
0.1u0.1u0.1uTT
0.564nLbondsot23
0.15nLpinsot23
350mRgnd
100pLgnd
350mRvcc
100pLvcc
D+1
D-1
GND
D+2
D-2
1
V
BUS
C = 100nF
BUS
USBLC6-4SC6
Figure 19: SOT23-6L Package Mechanical Data
USBLC6-4SC6
A
E
e
B
e
A2
c
θ
H
A1
L
D
Figure 20: Foot Print Dimensions (in millimeters)
0.60
DIMENSIONS
REF.
Millimeters Inches
Min. Typ. Max. Min. Typ. Max.
A 0.90 1.45 0.035 0.057
A1 0 0.10 0 0.004
A2 0.90 1.30 0.035 0.051
b 0.35 0.50 0.014 0.02
C 0.09 0.20 0.004 0.008
D 2.80 3.05 0.110 0.120
E 1.50 1.75 0.059 0.069
e 0.95 0.037
H 2.60 3.00 0.102 0.118
L 0.10 0.60 0.004 0.024
θ 0° 10° 0° 10°
1.20
3.50 2.30
0.95
1.10
Table 4: Ordering Information
Ordering code Marking Package Weight Base qty Delivery mode
USBLC6-4SC6 UL46 SOT23-6L 16.7 mg 3000 Tape & reel
Table 5: Revision History
Date Revision Description of Changes
10-Dec-2004 1 First issue.
28-Feb-2005 2 Minor layout update. No content change.
9/10
USBLC6-4SC6
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics.
All other names are the property of their respective owners
© 2005 STMicroelectronics - All rights reserved
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10/10
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