ST UC3842 User Manual

APPLICATION NOTE

UC3842 PROVIDES LO W-COST CURREN T-MODE CONT ROL

The fundam ental challeng e of power suppl y design
is to simultaneously realize two conflicting objecti­ves : good electrical performance and low cost. The
UC3842 is an integrated pulse width modulator
(PWM) designed with both these objectives in mind .
This IC provides desi gner s an inexpens ive c ont rol­ler with which they can obtain all the performance
advant age s of cur rent - m ode o per ati on . In ad diti on ,
the UC3 842 is optimiz ed for efficie nt power sequ en­cing of off-line converters and for driving increasin­gly popular POWERMOS.

This application note gives a functional description
of the UC3 842 and sug gests how to incorpor ate the
IC into practical power supplies. A review of current­mode control and its benefits is included and me-

Figure 1 : Two-loo p Cur r ent-mode Cont ro l Sys tem .

thods of avoiding com mon pitfalls dis cussed. The fi­nal sect ion pr es ent s des ig ns of tw o po wer s u p pli es
utilizing UC3842 control.

CURRENT-MODE CONTROL

Figure 1 shows the two-loop current-mode control
system in a typical buck regulator application. A
clock s ignal initia tes power pu lses at a fi xed freque n­cy. The termination of each pulse occurs when an
analog of the inductor current reaches a threshold
establish e d by the error si g nal . I n t his way the er r or
signal actually controls peak inductor current. This
contrasts with conventional schemes in which the
error signal directly controls pulse width without re­gard to induc tor current.

AN246/1188

1/16

APPLICATION NOTE

Several performance advantages result from the
use of current-mode control. First, an input voltage
feed-forward characteristic is achieved ; i.e., the
control circ uit instantaneously corr ects for input volt­age vari ations withou t using up any o f the erro r am­plifier’s dynami c range. Ther ef or e, line re gu lation i s
excel lent and the error amp lifier can be dedic ated to
correc ting for load v ariat io ns excl us ively .

For converters in which inductor current is conti­nuous, cont r olli ng peak curre nt is nea rly equ iv alen t
to controlling average current. Therefore, when
such converters employ current-mode control, the
inductor c an be tr eat e d as an e rr or -v o l tage- control­led-current-source for the purposes of small-signal
analysis . This is illu strated by fi gure 2. The t wo-pole
control-to-outp ut frequency respons e of these co n­verters is reduc ed to a sing le pole (filter capa citor i n
parallel wit h l o ad) res p o ns e.

One resul t is th a t the e rror amplif ie r compen sati on
can be designed to yield a stable closed-loop co n­verter response with greater gain-bandwidth than
would be possible with pulse-width control, giving
the supply improved s mall-signal dynami c response
to changing loads. A second result is that the error
amplifi er compensation c ircuit becomes s impler and
better behaved, as illustrated in figure 3. Capacitor
C

and resistor Riz in figure 3a add a low frequency

i

zero which cancels one of the two control-to-output
poles of no n-curr ent-m ode c onvert ers. For lar ge-si-

gnal load changes, in which converter response is
limited by inductor slew rate, the error amplifier will
saturate while the inductor is catching up with the
load. Dur ing this ti me, C

will charge to an a bnormal

i

level. W hen the inductor current reache s its required
level, the voltage on C
in supply output vol-tage. The recovery time is R

causes a corresponding err or

i

iz Ci

which may be milleseconds. However, the compen­sation netw ork of figur e 3 b can b e us ed where cur­rent-mode control has elimi nated the induc tor pole.
Large-signal dynamic response is then greatly im­prove d due to the a b senc e of C

.

i

Figure 2 : Inductor Looks Like a C urr en t Sou rce to

Small Signals.

,

Figure 3 : Required Error Am plif ier C ompen sa tion for Continuou s Induc tor Curr ent De si gns using (a) Duty -

cycle C ont ro l and (b ) Cur re nt-m o de C ont ro l.

(a)

(b)

2/16

Figure 4 : UC3842 Block Diagram.

APPLICATION NOTE

Current limiting is simplified with current-mode con­trol. Puls e-by-p ulse limi ting is, of course, in herent i n
the control schem e. Furtherm o re, a n upper li m it on
the peak curr ent can b e es tablished by si mply clam­ping the error voltage. Accurate current limiting al­lows optimization of magnetic and power
semiconductor elements while ensuring reliable
supply oper ati o n.

Finally, current-mode controlled power stages can
be operated in parallel with equal current sharing.
This opens the p ossib ility o f a m odul ar a ppro ac h to
power suppl y d es ign.

FUNCTIONAL DESCRIPTION

A block diag ram of th e UC3842 appear s in fi gure 4.
This IC will op erate from a low impedanc e DC sour­ce of 10 V to 30 V. Operation between 10 V and 16
V requires a start-up bootstr ap to a volt age gre ater
than 16 V in order to overcome the undervoltage loc­kout. V

is interna lly clamped to 34 V for operation

CC

from higher voltage current-limited sources

≤ 30 mA).

(I

CC

UNDER-VOLTAGE LOCKOUT (UVLO)
This c ircuit insures that V

is adequate to m ake the

CC

UC3842 fully ope rational before enabling the out put

stage. Figure 5a shows that the UVLO turn-on and
turn-off threshold s are fixed internally at 16 V and 10
V respec tively. The 6 V hysteresis prevents V

CC

oscillations during power sequencing. Figure 5b
shows supp ly current requirem ents. Start-up curre nt
is less than 1 mA for efficien t bootstrapp ing from the
rectified input of an off-line converter, as illustrated
by figure 6. During normal circuit operation, V
developed from auxiliar y winding W
C

. At star t-up, however , CIN must be charged to 16

IN

V through R

. With a start-up current of 1 mA, R

IN

with D1 and

AUX

CC

is

can be as large as 100 k Ω and sti ll charg e CIN when
V

= 90 V RMS (low line). Po wer dissip ation in R

AC

would then be less than 350 mW even under high
line (V

= 130 V RMS) conditions.

AC

During UVLO, the U C3842 o utput driver is bias ed to
a high impeda nce state. H owever, leakage currents
(up to 10 µA), if not shunted to ground, could pull
high the gate of a POWERM OS. A 100 kΩ shunt, as
showi ng in fi gure 6, will h old th e gate v oltag e be low
1V.

IN

IN

3/16

APPLICATION NOTE

Figure 5 : (a) Under-vol tage Lo cko u t and (b) Su pply Curr ent Requir eme nts.

(a) (b)

Figure 6 : Providing Power to the UC3842.

OSCILLATOR
The UC3842 oscillator is program me d as shown in

figure 7a. Oscillator timing capacitor C
from V

(5 V) through RT, and discharged by an

REF

is charged

T

internal c urrent source. Charge a nd discharge time s
are given by :

t

≈ 0.55 RT C

c

4/16

T

≈ RT CT ln ( )

t

d

frequency, then, is : f =

0.0063 RT – 2.7

0.0063 R

– 4.0

T

1

t

+ t

c

d

For RT > 5 kΩ, td is small compared to tc, and :
f ≈≈

11.8

0.55 R

T CT

RT C

T

APPLICATION NOTE

During the discharge ti me, the internal cloc k signal
blan ks the output to the low stat e. Therefor e, t
maximum duty cycle (D

t

D

MAX

c

== 1 –

t

+ t

c

d

MAX

t

d

τ

) to :

limits

d

where τ = 1/f = switching period.
The timing capacitor discharge current is not tightly

controlled, so t

may vary somewhat over temp era-

d

ture and fro m unit t o unit. T herefor e, when v ery pre ­cise duty cycle limiting is required, the circuit of fig­ure 7b is reco m m end ed.

One or more UC3842 osc illators c an be sy nc hroni ­zed to an ex ternal clock as s hown in figur e 8. Nois e
immunity is enhanced if the free-running oscillator
frequency (f = 1/(t

20 % less than the clock frequency.

~

+ td)) is programmed to be

c

Figu re 7 : (a) Oscilla tor Timing C onne cti ons and (b) Cir c uit f or Li m iting Dut y Cy cl e.

(a) (b)

Figure 8 : Synchronizatio n to an E xte rn al Cl oc k.

ERROR AMPLIFIER
The error amplifier (E/A) configuration is shown in

figure 9. The non-inverting input is not brought out

t

D

MAX

= 0.693 (RA + RB) C

t

H

= 0.693 RB C

t

L

c

=

(t

+ tL)

H

to a pin, but is internally biased to 2.5 V ± 2 %. The
E/A output is availab le at pin 1 for externa l compen­sation, allowing the user to control the converter’s
closed-lo op freque nc y respon se.

Figure 10a s ho w s an E /A c o m pe ns at io n ci rcu i t su i­table for stabilizing any current-mode controlled to­pology except for flyback and boost converters
operating with continuous inductor current. The fe­edback co mpon ent s add a pole to th e l oop transfe r
function at f

= 1/2 πRf Cf. Rf and Cf are chosen so

p

that this pole canc els the zero of t he out put fil ter c a­pacito r ESR in the power circu it. R

and Rf fix the low-

i

frequency gain. They are chosen to pr ovide as much
gain as po ssi ble whil e s til l al lowi ng th e p ole for m ed
by the output filter capacitor and load to roll off the
loop gain to unity (0dB) at f ≈ f

switching

/4. This techni­que insures converter stability while providing good
dynamic response.

Continuous-i nductor-curr ent boost and flyback con­verters each have a right-half-plane zero in their
transfer funct io n. An a ddi ti ona l comp ens at io n pole
is needed to roll off loop gain at a frequency less than
that of the RHP zero. R

and Cp in the circuit of figure

p

10b provide t his pol e.

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