ST TSA1204 User Manual

Dual channel 12-bit 20Msps 120mW A/D converter

Features

■ 0.5 Msps to 20 Msps sampling frequency

■ Adaptive power consumption: 120 mW @

20 Msps, 95 mW@10 Msps

■ Single supply voltage: 2.5 V

■ Independent supply for CMOS output stage

with 2.5 V/3.3 V capability

■ ENOB=11.2 @ Nyquist

■ SFDR= -81.5 dBc @ Nyquist

■ 1GHz analog bandwidth track-and-hold

■ Common clocking between channels

■ Dual simultaneous sample and hold inputs

■ Multiplexed outputs

■ Built-in reference voltage with external bias

capability.

Description

index
corner

AGND

INI

AGND

INIB

AGND

IPOL

AVCCB

AGND

INQ

AGND
INBQ
AGND

7x7mm TQFP48

REFPI

REFMI

INCMI

AVCC

48 44 43 42 41 40 39 38

46 45

47

1
2

3
4
5
6

7
8

9
10
11
12

13 14 15 16 17 18 19 20 21 22

REFPQ

AGND

INCMQ

REFMQ

VCCBI

AVCC

CLKD

OEB

TSA1204

DGND

AVCC

DVCC

TSA1204

GNDBE

D0(LSB)

VCCBE

VCCBI

D1

37

36

35
34
33

32

31

30

29

28
27
26
25

23 24

SELECT

CLK

DGND

DVCC

GNDBI

D2
D3
D4

D5
D6
D7
D8
D9

D10
D11(MSB)
VCCBE
GNDBE

The TSA1204 is a new generation of high speed,
dual-channel analog-to-digital converters
implemented in a mainstream 0.25 µm CMO S
technology yielding high performance and very
low power consumption.

The inputs of the ADC must be differentially
driven.

The TSA1204 is specifically designed for
applications requiring very low noise floor, high
SFDR and good insulation between channels. It is
based on a pipeline structure and digital error

The TSA1204 is available in extended (-40°C to
+85° C) temperature range, in a small 48-pin
TQFP package.

correction to provide excellent static linearity and
over 11.2 effective bits at F
F

=10 MHz.

in

For each channel, an integrated v oltage ref erence
simplifies the design and minimizes external
components. It is ne vertheless possible t o use the
circuit with external references.

The ADC outputs are multiplexed in a common

=20 Msps, and

S

Applications

■ Medical imaging and ultrasound

■ 3G base station

■ I/Q signal processing applications

■ High speed data acquisition system

■ Portable instrumentation

bus with a small number of pins. A tri-state
capability is available for the outputs, allowing
chip selection.

December 2006 Rev 4 1/31

www.st.com

31

Contents TSA1204

Contents

1 Schematic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2 Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

3 Dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

4 Timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

5 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

6 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

7 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

8 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

8.1 Additional functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

8.1.1 Output enable mode (OEB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

8.1.2 Select mode (SELECT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

8.2 References and common mode connection . . . . . . . . . . . . . . . . . . . . . . . 16

8.2.1 Internal reference and common mode . . . . . . . . . . . . . . . . . . . . . . . . . . 16

8.2.2 External reference and common mode . . . . . . . . . . . . . . . . . . . . . . . . . 16

8.3 Driving the differential analog inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

8.4 Clock input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

8.5 Power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

8.6 Layout precautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

8.7 EVAL1204/BA evaluation board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

8.7.1 Evaluation board operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 22

8.7.2 Consumption adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

8.7.3 Single and differential inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

8.7.4 Mode select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

9 Practical application examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

9.1 Digital interface applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

9.2 Medical imaging application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

2/31

TSA1204 Contents

10 Definitions of specified parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Static parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Dynamic parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

11 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

12 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

13 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

3/31

Schematic diagram TSA1204

1 Schematic diagram

Figure 1. TSA1204 block diagram

+2.5V/3.3V

VINI

VINBI

VINCMI

common mode

VREFPI

VREFMI

IPOL

Polar.

VREFPQ

VREFMQ

VINCMQ

common mode

VINQ

VINBQ

Figure 2. Timing diagram

AD 12
I channel

REF I

REF Q

AD 12
Q channel

CLK

Timing

12

12

GND

SELECT

M
U

X

12

OEB

Buffers

GNDBE

VCCBE

12

D0
TO
D11

Simultaneous sampling
on I/Q channels

I

Q

CLK

SELECT

OEB

DATA
OUTPUT

sample N-9
I channel

N-1

N

sample N-8
I channel

sample N-7
Q channel

N+1

N+2

sample N-6
Q channel

N+3

Tpd I + Tod

N+4

N+5

N+6

N+7

N+8

CLOCK AND SELECT CONNECTED TOGETHER

sample N
Q channel

sample N+1
I channel

sample N+2
I channel

N+9

Tod

sample N+1
Q channel

N+10

sample N+2
Q channel

sample N+3
I channel

N+11

N+12

N+13

4/31

TSA1204 Pin descriptions

2 Pin descriptions

Table 1. Pin descriptions (TQFP48 package)

Pin Name Description Observation Pin Name Description Observation

1 AGND Analog ground 0 V 25 GNDBE Digital buffer ground 0 V

2 INI I channel analog input 26 VCCBE

3 AGND Analog ground 0 V 27 D11(MSB)

4INBI

5 AGND Analog ground 0 V 29 D9 Digital output

6IPOL

7 AVCC Analog power supply 2.5 V 31 D7 Digital output

8 AGND Analog ground 0V 32 D6 Digital output

9INQ

10 AGND Analog ground 0 V 34 D4 Digital output

11 INBQ

12 AGND Analog ground 0 V 36 D2 Digital output

13 REFPQ

14 REFMQ

15 INCMQ

16 AGND Analog ground 0V 40 GNDBE Digital buffer ground 0 V

17 AVCC Analog power supply 2.5 V 41 VCCBI

18 DVCC Digital power supply 2.5 V 42 CLKD Data clock input

19 DGND Digital ground 0 V 43 OEB Output Enable input

20 CLK Clock input

21 SELECT Channel selection

22 DGND Digital ground 0V 46 INCMI

23 DVCC Digital power supply 2.5 V 47 REFMI

24 GNDBI Digital buffer ground 0 V 48 REFPI

I channel inverted
analog input

Analog bias current
input

Q channel analog
input

Q channel inverted
analog input

Q channel top
reference voltage

Q channel bottom
reference voltage

Q channel input
common mode

0 V 38 D0(LSB)

2.5 V CMOS
input

2.5 V CMOS
input

28 D10 Digital output

30 D8 Digital output

33 D5 Digital output

35 D3 Digital output

37 D1 Digital output

39 VCCBE

44 AVCC Analog power supply 2.5 V

45 AVCC Analog power supply 2.5 V

Digital Buffer power
supply

Most Significant Bit
output

Least Significant Bit
output

Digital Buffer power
supply

Digital Buffer power
supply

I channel input
common mode

I channel bottom
reference voltage

I channel top
reference voltage

2.5 V/3.3 V

CMOS output

(2.5 V/3.3 V)

CMOS output

(2.5 V/3.3 V)

CMOS output

(2.5 V/3.3 V)

CMOS output

(2.5 V/3.3 V)

CMOS output

(2.5 V/3.3 V)

CMOS output

(2.5 V/3.3 V)

CMOS output

(2.5 V/3.3 V)

CMOS output

(2.5 V/3.3 V)

CMOS output

(2.5 V/3.3 V)

CMOS output

(2.5 V/3.3 V)

CMOS output

(2.5 V/3.3 V)

CMOS output

(2.5 V/3.3 V)

2.5 V/3.3 V - See
Application Note

2.5 V

Idle at high level

2.5 V or 3.3 V

2.5 V/3.3 V CMOS
input

0V

5/31

Dynamic characteristics TSA1204

3 Dynamic characteristics

Dynamic characteristics are measured at AVCC = DVCC = V
F

=10.5 MHz, Vin@ -1 dBFS, V

in

REFP

=1.0 V , V

specified).

Table 2. Dynamic characteristics

Symbol Parameter Test conditions Min Typ Max Unit

SFDR Spurious free dynamic range -81.5 -71.0 dBc

SNR Signal to noise ratio 66.9 68.5 dB
THD Total harmonics distortion -80 -70 dBc

SINAD Signal to noise and distortion ratio 64.8 68 dB

ENOB Effective number of bits 10.6 11.2 bits

4 Timing characteristics

Timing characteristics are measured at AVCC = DVCC = V
F

=10.5 MHz, Vin@ -1 dBFS, V

in

specified).

Table 3. Timing characteristics

REFP

=1.0 V , V

REFM

REFM

=0 V and T

CCB

CCB

=0 V and T

= 2.5 V, FS= 20 Msps,

= 25° C (unless otherwise

amb

= 2.5 V, FS= 20 Msps,

= 25° C (unless otherwise

amb

Symbol Parameter Test conditions Min Typ Max Unit

F

Sampling frequency 0.5 20 MHz

S

DC Clock duty cycle 45 50 55 %
TC1 Clock pulse width (high) 22.5 25 ns
TC2 Clock pulse width (low) 22.5 25 ns

T

T

pd

T

pd

T

T

Data output delay (clock edge to data

od

valid)

I Data pipeline delay for channel I 7

Q Data pipeline delay for channel Q 7.5

Falling edge of OEB to digital output

on

valid data
Rising edge of OEB to digital output

off

tri-state

10 pF load

capacitance

9ns

cycle

s

cycle

s

1ns

1ns

6/31

TSA1204 Absolute maximum ratings

5 Absolute maximum ratings

Table 4. Absolute maximum ratings

Symbol Parameter Values Unit

(1)

(1)

(2)

(1)
(1)

(3)

0 to 3.3 V
0 to 3.3 V
0 to 3.6 V
0 to 3.3 V

2

1.5

kV

A

AV

CC

DV

CC

V

CCBE

V

CCBI

ID

out

T

stg

ESD

Latch-up Class

1. All voltage values, except differential voltage, are with respect to network ground terminal. The magnitude
of input and output voltages must not exceed -0.3 V or VCC.

2. Electrostatic discharge pulse (ESD pulse) simulating a human body discharge of 100 pF through 1.5 kΩ.

3. Discharge to ground of a device that has been previously charged.

4. ST Microelectronics corporate procedure number 0018695.

Analog supply voltage
Digital supply voltage
Digital buffer supply voltage
Digital buffer supply voltage
Digital output current -100 to 100 mA
Storage temperature +150 °C
HBM: human body model

CDM: charged device model

(4)

6 Operating conditions

Table 5. Operating conditions

Symbol Parameter Min Typ Max Unit

AV

CC

DV

CC

V

CCBE

V

CCBI

V

REFP

V

REFP

V

REFM

V

REFM

V

INCM

V

INCM

1. Condition V

Analog supply voltage 2.25 2.5 2.7 V
Digital supply voltage 2.25 2.5 2.7 V
External digital buffer supply voltage 1.8 2.5 3.5 V
Internal digital buffer supply voltage 2.25 2.5 2.7 V

I

Forced top voltage reference

Q

I

Forced bottom reference voltage

Q

I

Forced input common mode voltage 0.2 1 V

Q

REFP-VREFM

>0.3V

(1)

(1)

0.96 1.4 V

00.4V

7/31

Electrical characteristics TSA1204

7 Electrical characteristics

Electrical characteristics are measured at AVCC = DVCC = V
F

=2 MHz, Vin@ -1 dBFS, V

in

REFP

=1.0 V, V

REFM

=0 V, and T

= 2.5 V, FS= 20 Msps,

CCB

= 25° C (unless otherwise

amb

specified).

Table 6. Analog inputs

Symbol Parameter Test conditions Min Typ Max Unit

V

IN-VINB

R

Full scale reference
voltage

C

Input capacitance 7.0 pF

in

Equivalent input resistor 3 KΩ

eq

BW Analog input bandwidth V

ERB

Table 7. Digital inputs and outputs

Effective resolution
bandwidth

Symbol Parameter Test conditions Min Typ Max Unit

Clock and select inputs

V
V

Logic "0" voltage 0 0.8 V

IL

Logic "1" voltage 2.0 2.5 V

IH

OEB input

Differential inputs mandatory 1.1 2.0 2.8 Vpp

@full scale, FS=20 Msps 1000 MHz

in

70 MHz

V

V

Logic "0" voltage 0

IL

Logic "1" voltage

IH

0.75 x

V

CCBE

V

CCBE

0.25 x

V

CCBE

Digital outputs

V

V

I

C

Table 8. Reference voltage

Logic "0" voltage IOL=10 µA 0

OL

Logic "1" voltage IOH=10 µA

OH

High impedance leakage

OZ

current
Output load capacitance 15 pF

L

OEB set to V

0.9 x

VCCBE

IH

-1.7 1.7 µA

VCCBE V

0.1 x

VCCBE

Symbol Parameter Test conditions Min Typ Max Unit

V

I

Top internal reference
voltage

Q

I

Input common mode
voltage

Q

0.807 0.89 0.963 V

0.40 0.46 0.52 V

V

V

V

REFP

REFP

INCM

INCM

V

V

V

8/31

TSA1204 Electrical characteristics

Table 9. Power consumption

Symbol Parameter Min Typ Max Unit

I

CCA

I

CCD

I

CCBE

I

CCBI

P

R

thja

Table 10. Accuracy

Analog supply current 40 49.5 mA
Digital supply current 2 3 mA
Digital buffer supply current (10 pF load) 6.2 9 mA
Digital buffer supply current 73 221 µA
Power consumption in normal operation

d

mode

120 155 mW

Thermal resistance (TQFP48) 80 °C/W

Symbol Parameter Min Typ Max Unit

OE Offset error -1.8 -0.5 1.8 LSB
GE Gain error -0.1 0 0.1 %

DNL Differential non linearity -0.93 ±0.4 +0.93 LSB

INL Integral non linearity -1.8 ±0.8 +1.8 LSB

Monotonicity and no missing codes Guaranteed

Table 11. Matching between channels

Symbol Parameter Min Typ Max Unit

GM Gain match 0.033 0.1 %
OM Offset match 0.4 2.5 LSB

PHM Phase match 1 dg

XTLK Crosstalk rejection 87 dB

9/31

Electrical characteristics TSA1204

Figure 3. Static parameter: integral non linearity

FS=20 MSPS; I

0.8

0.6

0.4

0.2
0

-0.2

INL (LSBs)

-0.4

-0.6

-0.8

=40 mA; Fin=2 MH

CCA

0 500 1000 1500 2000 2500 3000 3500 4000

(a)

Output Code

Figure 4. Static parameter: differential non linearity

FS=20 MSPS; I

0.4

0.3

0.2

0.1
0

-0.1

DNL (LSBs)

-0.2

-0.3

-0.4

=40 mA; Fin=2 MHz

CCA

0 500 1000 1500 2000 2500 3000 3500 4000

Output Code

(a)

a. For parameter definitions, see Section 10: Definitions of specified parameters on page 25.

10/31