ST TSA1204 User Manual

Dual channel 12-bit 20Msps 120mW A/D converter

Features

■ 0.5 Msps to 20 Msps sampling frequency

■ Adaptive power consumption: 120 mW @

20 Msps, 95 mW@10 Msps

■ Single supply voltage: 2.5 V

■ Independent supply for CMOS output stage

with 2.5 V/3.3 V capability

■ ENOB=11.2 @ Nyquist

■ SFDR= -81.5 dBc @ Nyquist

■ 1GHz analog bandwidth track-and-hold

■ Common clocking between channels

■ Dual simultaneous sample and hold inputs

■ Multiplexed outputs

■ Built-in reference voltage with external bias

capability.

Description

index
corner

AGND

INI

AGND

INIB

AGND

IPOL

AVCCB

AGND

INQ

AGND
INBQ
AGND

7x7mm TQFP48

REFPI

REFMI

INCMI

AVCC

48 44 43 42 41 40 39 38

46 45

47

1
2

3
4
5
6

7
8

9
10
11
12

13 14 15 16 17 18 19 20 21 22

REFPQ

AGND

INCMQ

REFMQ

VCCBI

AVCC

CLKD

OEB

TSA1204

DGND

AVCC

DVCC

TSA1204

GNDBE

D0(LSB)

VCCBE

VCCBI

D1

37

36

35
34
33

32

31

30

29

28
27
26
25

23 24

SELECT

CLK

DGND

DVCC

GNDBI

D2
D3
D4

D5
D6
D7
D8
D9

D10
D11(MSB)
VCCBE
GNDBE

The TSA1204 is a new generation of high speed,
dual-channel analog-to-digital converters
implemented in a mainstream 0.25 µm CMO S
technology yielding high performance and very
low power consumption.

The inputs of the ADC must be differentially
driven.

The TSA1204 is specifically designed for
applications requiring very low noise floor, high
SFDR and good insulation between channels. It is
based on a pipeline structure and digital error

The TSA1204 is available in extended (-40°C to
+85° C) temperature range, in a small 48-pin
TQFP package.

correction to provide excellent static linearity and
over 11.2 effective bits at F
F

=10 MHz.

in

For each channel, an integrated v oltage ref erence
simplifies the design and minimizes external
components. It is ne vertheless possible t o use the
circuit with external references.

The ADC outputs are multiplexed in a common

=20 Msps, and

S

Applications

■ Medical imaging and ultrasound

■ 3G base station

■ I/Q signal processing applications

■ High speed data acquisition system

■ Portable instrumentation

bus with a small number of pins. A tri-state
capability is available for the outputs, allowing
chip selection.

December 2006 Rev 4 1/31

www.st.com

31

Contents TSA1204

Contents

1 Schematic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2 Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

3 Dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

4 Timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

5 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

6 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

7 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

8 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

8.1 Additional functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

8.1.1 Output enable mode (OEB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

8.1.2 Select mode (SELECT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

8.2 References and common mode connection . . . . . . . . . . . . . . . . . . . . . . . 16

8.2.1 Internal reference and common mode . . . . . . . . . . . . . . . . . . . . . . . . . . 16

8.2.2 External reference and common mode . . . . . . . . . . . . . . . . . . . . . . . . . 16

8.3 Driving the differential analog inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

8.4 Clock input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

8.5 Power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

8.6 Layout precautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

8.7 EVAL1204/BA evaluation board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

8.7.1 Evaluation board operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 22

8.7.2 Consumption adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

8.7.3 Single and differential inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

8.7.4 Mode select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

9 Practical application examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

9.1 Digital interface applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

9.2 Medical imaging application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

2/31

TSA1204 Contents

10 Definitions of specified parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Static parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Dynamic parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

11 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

12 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

13 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

3/31

Schematic diagram TSA1204

1 Schematic diagram

Figure 1. TSA1204 block diagram

+2.5V/3.3V

VINI

VINBI

VINCMI

common mode

VREFPI

VREFMI

IPOL

Polar.

VREFPQ

VREFMQ

VINCMQ

common mode

VINQ

VINBQ

Figure 2. Timing diagram

AD 12
I channel

REF I

REF Q

AD 12
Q channel

CLK

Timing

12

12

GND

SELECT

M
U

X

12

OEB

Buffers

GNDBE

VCCBE

12

D0
TO
D11

Simultaneous sampling
on I/Q channels

I

Q

CLK

SELECT

OEB

DATA
OUTPUT

sample N-9
I channel

N-1

N

sample N-8
I channel

sample N-7
Q channel

N+1

N+2

sample N-6
Q channel

N+3

Tpd I + Tod

N+4

N+5

N+6

N+7

N+8

CLOCK AND SELECT CONNECTED TOGETHER

sample N
Q channel

sample N+1
I channel

sample N+2
I channel

N+9

Tod

sample N+1
Q channel

N+10

sample N+2
Q channel

sample N+3
I channel

N+11

N+12

N+13

4/31

TSA1204 Pin descriptions

2 Pin descriptions

Table 1. Pin descriptions (TQFP48 package)

Pin Name Description Observation Pin Name Description Observation

1 AGND Analog ground 0 V 25 GNDBE Digital buffer ground 0 V

2 INI I channel analog input 26 VCCBE

3 AGND Analog ground 0 V 27 D11(MSB)

4INBI

5 AGND Analog ground 0 V 29 D9 Digital output

6IPOL

7 AVCC Analog power supply 2.5 V 31 D7 Digital output

8 AGND Analog ground 0V 32 D6 Digital output

9INQ

10 AGND Analog ground 0 V 34 D4 Digital output

11 INBQ

12 AGND Analog ground 0 V 36 D2 Digital output

13 REFPQ

14 REFMQ

15 INCMQ

16 AGND Analog ground 0V 40 GNDBE Digital buffer ground 0 V

17 AVCC Analog power supply 2.5 V 41 VCCBI

18 DVCC Digital power supply 2.5 V 42 CLKD Data clock input

19 DGND Digital ground 0 V 43 OEB Output Enable input

20 CLK Clock input

21 SELECT Channel selection

22 DGND Digital ground 0V 46 INCMI

23 DVCC Digital power supply 2.5 V 47 REFMI

24 GNDBI Digital buffer ground 0 V 48 REFPI

I channel inverted
analog input

Analog bias current
input

Q channel analog
input

Q channel inverted
analog input

Q channel top
reference voltage

Q channel bottom
reference voltage

Q channel input
common mode

0 V 38 D0(LSB)

2.5 V CMOS
input

2.5 V CMOS
input

28 D10 Digital output

30 D8 Digital output

33 D5 Digital output

35 D3 Digital output

37 D1 Digital output

39 VCCBE

44 AVCC Analog power supply 2.5 V

45 AVCC Analog power supply 2.5 V

Digital Buffer power
supply

Most Significant Bit
output

Least Significant Bit
output

Digital Buffer power
supply

Digital Buffer power
supply

I channel input
common mode

I channel bottom
reference voltage

I channel top
reference voltage

2.5 V/3.3 V

CMOS output

(2.5 V/3.3 V)

CMOS output

(2.5 V/3.3 V)

CMOS output

(2.5 V/3.3 V)

CMOS output

(2.5 V/3.3 V)

CMOS output

(2.5 V/3.3 V)

CMOS output

(2.5 V/3.3 V)

CMOS output

(2.5 V/3.3 V)

CMOS output

(2.5 V/3.3 V)

CMOS output

(2.5 V/3.3 V)

CMOS output

(2.5 V/3.3 V)

CMOS output

(2.5 V/3.3 V)

CMOS output

(2.5 V/3.3 V)

2.5 V/3.3 V - See
Application Note

2.5 V

Idle at high level

2.5 V or 3.3 V

2.5 V/3.3 V CMOS
input

0V

5/31

Dynamic characteristics TSA1204

3 Dynamic characteristics

Dynamic characteristics are measured at AVCC = DVCC = V
F

=10.5 MHz, Vin@ -1 dBFS, V

in

REFP

=1.0 V , V

specified).

Table 2. Dynamic characteristics

Symbol Parameter Test conditions Min Typ Max Unit

SFDR Spurious free dynamic range -81.5 -71.0 dBc

SNR Signal to noise ratio 66.9 68.5 dB
THD Total harmonics distortion -80 -70 dBc

SINAD Signal to noise and distortion ratio 64.8 68 dB

ENOB Effective number of bits 10.6 11.2 bits

4 Timing characteristics

Timing characteristics are measured at AVCC = DVCC = V
F

=10.5 MHz, Vin@ -1 dBFS, V

in

specified).

Table 3. Timing characteristics

REFP

=1.0 V , V

REFM

REFM

=0 V and T

CCB

CCB

=0 V and T

= 2.5 V, FS= 20 Msps,

= 25° C (unless otherwise

amb

= 2.5 V, FS= 20 Msps,

= 25° C (unless otherwise

amb

Symbol Parameter Test conditions Min Typ Max Unit

F

Sampling frequency 0.5 20 MHz

S

DC Clock duty cycle 45 50 55 %
TC1 Clock pulse width (high) 22.5 25 ns
TC2 Clock pulse width (low) 22.5 25 ns

T

T

pd

T

pd

T

T

Data output delay (clock edge to data

od

valid)

I Data pipeline delay for channel I 7

Q Data pipeline delay for channel Q 7.5

Falling edge of OEB to digital output

on

valid data
Rising edge of OEB to digital output

off

tri-state

10 pF load

capacitance

9ns

cycle

s

cycle

s

1ns

1ns

6/31

TSA1204 Absolute maximum ratings

5 Absolute maximum ratings

Table 4. Absolute maximum ratings

Symbol Parameter Values Unit

(1)

(1)

(2)

(1)
(1)

(3)

0 to 3.3 V
0 to 3.3 V
0 to 3.6 V
0 to 3.3 V

2

1.5

kV

A

AV

CC

DV

CC

V

CCBE

V

CCBI

ID

out

T

stg

ESD

Latch-up Class

1. All voltage values, except differential voltage, are with respect to network ground terminal. The magnitude
of input and output voltages must not exceed -0.3 V or VCC.

2. Electrostatic discharge pulse (ESD pulse) simulating a human body discharge of 100 pF through 1.5 kΩ.

3. Discharge to ground of a device that has been previously charged.

4. ST Microelectronics corporate procedure number 0018695.

Analog supply voltage
Digital supply voltage
Digital buffer supply voltage
Digital buffer supply voltage
Digital output current -100 to 100 mA
Storage temperature +150 °C
HBM: human body model

CDM: charged device model

(4)

6 Operating conditions

Table 5. Operating conditions

Symbol Parameter Min Typ Max Unit

AV

CC

DV

CC

V

CCBE

V

CCBI

V

REFP

V

REFP

V

REFM

V

REFM

V

INCM

V

INCM

1. Condition V

Analog supply voltage 2.25 2.5 2.7 V
Digital supply voltage 2.25 2.5 2.7 V
External digital buffer supply voltage 1.8 2.5 3.5 V
Internal digital buffer supply voltage 2.25 2.5 2.7 V

I

Forced top voltage reference

Q

I

Forced bottom reference voltage

Q

I

Forced input common mode voltage 0.2 1 V

Q

REFP-VREFM

>0.3V

(1)

(1)

0.96 1.4 V

00.4V

7/31

Electrical characteristics TSA1204

7 Electrical characteristics

Electrical characteristics are measured at AVCC = DVCC = V
F

=2 MHz, Vin@ -1 dBFS, V

in

REFP

=1.0 V, V

REFM

=0 V, and T

= 2.5 V, FS= 20 Msps,

CCB

= 25° C (unless otherwise

amb

specified).

Table 6. Analog inputs

Symbol Parameter Test conditions Min Typ Max Unit

V

IN-VINB

R

Full scale reference
voltage

C

Input capacitance 7.0 pF

in

Equivalent input resistor 3 KΩ

eq

BW Analog input bandwidth V

ERB

Table 7. Digital inputs and outputs

Effective resolution
bandwidth

Symbol Parameter Test conditions Min Typ Max Unit

Clock and select inputs

V
V

Logic "0" voltage 0 0.8 V

IL

Logic "1" voltage 2.0 2.5 V

IH

OEB input

Differential inputs mandatory 1.1 2.0 2.8 Vpp

@full scale, FS=20 Msps 1000 MHz

in

70 MHz

V

V

Logic "0" voltage 0

IL

Logic "1" voltage

IH

0.75 x

V

CCBE

V

CCBE

0.25 x

V

CCBE

Digital outputs

V

V

I

C

Table 8. Reference voltage

Logic "0" voltage IOL=10 µA 0

OL

Logic "1" voltage IOH=10 µA

OH

High impedance leakage

OZ

current
Output load capacitance 15 pF

L

OEB set to V

0.9 x

VCCBE

IH

-1.7 1.7 µA

VCCBE V

0.1 x

VCCBE

Symbol Parameter Test conditions Min Typ Max Unit

V

I

Top internal reference
voltage

Q

I

Input common mode
voltage

Q

0.807 0.89 0.963 V

0.40 0.46 0.52 V

V

V

V

REFP

REFP

INCM

INCM

V

V

V

8/31

TSA1204 Electrical characteristics

Table 9. Power consumption

Symbol Parameter Min Typ Max Unit

I

CCA

I

CCD

I

CCBE

I

CCBI

P

R

thja

Table 10. Accuracy

Analog supply current 40 49.5 mA
Digital supply current 2 3 mA
Digital buffer supply current (10 pF load) 6.2 9 mA
Digital buffer supply current 73 221 µA
Power consumption in normal operation

d

mode

120 155 mW

Thermal resistance (TQFP48) 80 °C/W

Symbol Parameter Min Typ Max Unit

OE Offset error -1.8 -0.5 1.8 LSB
GE Gain error -0.1 0 0.1 %

DNL Differential non linearity -0.93 ±0.4 +0.93 LSB

INL Integral non linearity -1.8 ±0.8 +1.8 LSB

Monotonicity and no missing codes Guaranteed

Table 11. Matching between channels

Symbol Parameter Min Typ Max Unit

GM Gain match 0.033 0.1 %
OM Offset match 0.4 2.5 LSB

PHM Phase match 1 dg

XTLK Crosstalk rejection 87 dB

9/31

Electrical characteristics TSA1204

Figure 3. Static parameter: integral non linearity

FS=20 MSPS; I

0.8

0.6

0.4

0.2
0

-0.2

INL (LSBs)

-0.4

-0.6

-0.8

=40 mA; Fin=2 MH

CCA

0 500 1000 1500 2000 2500 3000 3500 4000

(a)

Output Code

Figure 4. Static parameter: differential non linearity

FS=20 MSPS; I

0.4

0.3

0.2

0.1
0

-0.1

DNL (LSBs)

-0.2

-0.3

-0.4

=40 mA; Fin=2 MHz

CCA

0 500 1000 1500 2000 2500 3000 3500 4000

Output Code

(a)

a. For parameter definitions, see Section 10: Definitions of specified parameters on page 25.

10/31

TSA1204 Electrical characteristics

Q

Q

Q

Figure 5. Linearity vs. F

Fin=5MHz; R

100

90

ENOB I

80

70

60

50

Dynamic parameters (dB)

40

SNR

10 15 20 25

pol

ENOB

SINAD

SNR_I

Fs (MHz)

Figure 7. Linearity vs. F

FS=20Msps; I

100

90

80

SNR_Q

70

60

SNR_I

50

40

Dynamic parameters (dB)

30

0 1020304050

ENOB_Q

SINAD_Q

SINAD_I

Fin (MHz)

S

adjustment

SINAD_I

in

=40mA

CCA

ENOB_I

12

11

10

9

8

7

6

5

12

11

10

9

8

7

6

5

Figure 6. Distortion vs. F

Fin=5MHz; R

-20

-30

-40

-50
SFDR_I

-60

-70

ENOB (bits)

-80

-90

-100

-110

Dynamic parameters (dBc)

-120
10 15 20 25

Figure 8. Distortion vs. F

FS=20Msps; I

-30

-40

-50

THD_Q

-60

-70

-80

ENOB (bits)

-90

-100

-110

Dynamic parameters (dBc)

-120
0 1020304050

SFDR_Q

SFDR_I

S

adjustment

pol

Fs (MHz)

in

=40mA

CCA

Fin (MHz)

THD_I

THD_Q

SFDR_QTHD_I

Figure 9. Linearity vs. Temperature

F

=20Msps; I

S

100

90

80

70

60

50

Dynamic parameters (dB)

40

ENOB_I

ENOB_Q

SNR_I

SNR_Q

-40 10 60

Temperature (°C)

=40mA; Fin=2MHz

CCA

SINAD_I

SINAD_Q

12

11.5
11

10.5
10

9.5
9

8.5
8

7.5
7

Figure 10. Distortion vs. Temperature

FS=20Msps; I

120
110
100

90
80

ENOB (bits)

11/31

70

SFDR_I

60
50

Dynamic parameters (dBc)

40

-40 10 60

THD_I

Temperature (°C)

=40mA; Fin=2MHz

CCA

THD_QSFDR_Q

Electrical characteristics TSA1204

Figure 11. Linearity vs. AV

FS=20Msps; I

100

95
90
85
80
75
70
65
60
55

Dynamic parameters (dB)

50

2.25 2.35 2.45 2.55 2.65

ENOB_Q

SNR_Q

SINAD_I

CCA

ENOB_I

SINAD_Q

AVCC (V)

Figure 13. Linearity vs. DV

FS=20Msps; I

100

90

80

70

60

50

Dynamic parameters (dB)

40

2.25 2.35 2.45 2.55 2.65

ENOB_Q

SNR_Q

SINAD_I

CCA

ENOB_I

SINAD_Q

DVCC (V)

CC

=40mA; Fin=5MHz

12

11

10

9

8

SNR_I

7

6

CC

=40mA; Fin=5MHz

12

11

SNR_I

10

9

8

7

6

Figure 12. Distortion vs. AV

FS=20Msps; I

-30

-40

-50

-60

-70

-80

ENOB (bits)

-90

-100

-110

Dynamic Parameters (dBc)

-120

2.25 2.35 2.45 2.55 2.65

Figure 14. Distortion vs. DV

FS=20Msps; I

-40

-50

-60

-70

-80

-90

ENOB (bits)

Dynamic Parameters (dBc)

THD_Q

-100

-110

-120

2.25 2.35 2.45 2.55 2.65

THD_Q

CCA

THD_I

AVCC (V)

CCA

THD_I

DVCC (V)

CC

=40mA; Fin=5MHz

SFDR_I

SFDR_Q

CC

=40mA; Fin=5MHz

SFDR_I

SFDR_Q

Figure 15. Linearity vs. V

CCBI

FS=20Msps; I

90
85
80
75
70
65
60
55

Dynamic parameters (dB)

50

2.25 2.35 2.45 2.55 2.65

ENOB_I

ENOB_Q

SNR_I

SINAD_I

=40mA; Fin=5MHz

CCA

SNR_Q

SINAD_Q

12

11.5
11

10.5
10

9.5
9

8.5
8

ENOB (bits)

VCCBI (V )

12/31

Figure 16. Distortion vs. V

FS=20Msps; I

-40

-50

-60

-70

-80

-90

-100

-110

Dynamic Parameters (dBc)

-120

THD_Q

2.25 2.35 2.45 2.55 2.65

CCA

THD_I

VCCBI (V)

CCBI

=40mA; Fin=5MHz

SFDR_I

SFDR_Q

TSA1204 Electrical characteristics

Figure 17. Linearity vs. V

FS=20Msps; I

90
85
80
75
70
65
60
55

Dynamic parameters (dB)

50

2.25 2.75 3.25

SNR_I

CCA

ENOB_I

ENOB_Q

SINAD_I

SNR_Q

CCBE

=40mA; Fin=5MHz

SINAD_Q

VCCBE (V)

Figure 19. Linearity vs. duty cycle

F

=20Msps; I

S

100

90

80

70

60

50

Dynamic parameters (dB)

40

45 47 49 51 53 55

Positive Duty Cycle (%)

=40mA; Fin=5MHz

CCA

ENOB_I

ENOB_Q

SNR_I SINAD_I

SINAD_Q

SNR_Q

12

11.5
11

10.5
10

9.5
9

8.5
8

7.5
7

12

11.5
11

10.5
10

9.5
9

8.5
8

7.5
7

Figure 18. Distortion vs. V

FS=20Msps; I

-40

-50

-60

-70

-80

ENOB (bits)

-90

-100

-110

Dynamic Parameters (dBc)

-120

THD_Q

2.25 2.75 3.25

VCCBE (V)

Figure 20. Distortion vs. duty cycle

FS=20Msps; I

-40

-50

ENOB (bits)

-60

-70

-80

-90

-100

-110

Dynamic parameters (dBc)

-120

SFDR_Q

SFDR_I

45 47 49 51 53 55

THD_Q

THD_I

Posit ive Duty Cycle (%)

CCBE

=40mA; Fin=5MHz

CCA

SFDR_Q

SFDR_I

=40mA; Fin=5MHz

CCA

THD_I

13/31

Electrical characteristics TSA1204

Figure 21. Single-tone 8K FFT at 20Msps - Channel I

F

=5MHz; I

in

=40mA, Vin@-1dBFS

CCA

0

-20

-40

-60

-80

-100

-120

Power spectrum (dB)

-140
1234 6789105

Frequency (MHz)

Figure 22. Dual-tone 8K FFT at 20Msps - Channel I

F

=9.7MHz; F

in1

in2

0

-20

-40

-60

-80

-100

-120

Power spectrum (dB)

-140

=10.7MHz; I

1234 6789105

=40mA, V

CCA

@-7dBFS; V

in1

Frequency (MHz)

@-7dBFS; IMD=-76dBc

in2

14/31

TSA1204 Application information

8 Application information

The TSA1204 is a dual-channel, 12-bit resolution analog-to-digital converter based on a
pipeline structure and the latest deep submicron CMOS process to achieve the best
performance in terms of linearity and power consumption.

Each channel achieves 12-bit resolution through the pipeline structure which consists of 12
internal conversion stages in which the analog signal is fed and sequentially converted into
digital data. A latency time of 7 clock periods is necessary to obtain the digitiz ed data on the
output bus.

The input signals are simultaneously sampled, for both channels, on the rising edge of the
clock. The output data is delivered on the rising edge of the clock for channel I and on the
falling edge of the clock f or channel Q, as shown in Figure 2: Timing diagram on page 4. The
digital data produced at the diff erent st ages must be t ime dela y ed accordidng t o the order of
conversion. Fianlly, a digital data correction completes the processing and ensures the
validity of the ending codes on the output bus.

The structure is specifically designed to accept differential signals only.

8.1 Additional functions

To simplify the application board as much as possible, the following operating modes are
provided:

● Output enable mode (OEB)

● Select mode (SELECT)

8.1.1 Output enable mode (OEB)

When set to low level (VIL), all digital outputs remain active and are in low impedance state.
When set to high level (V
converter goes on sampling. When OEB is set to a low lev el again, the data arrives on the
output with a very short T

Figure 2: Timing diagram on page 4 summarizes this functionality.

If you do not want to use OEB mode, the OEB pin should be grounded through a low value
resistor.

), all digital output buffers are in high impedance state while the

IH

delay. This mechanism allows the chip select of the device.

on

8.1.2 Select mode (SELECT)

The digital data output from each of the ADC cores is multiplexed to share the same output
bus. This pre vents an incr ease in the number of pins and allo ws to use the same package as
for a single-channel ADC lik e the TSA1201.

The information channel is selected with the "SELECT" pin. When set to high level (V
channel I data is present on the D0-D11 output bus. When set to low level (V
data is delivered on D0-D11.

), channel Q

IL

IH

),

By connecting SELECT to CLK, channel I and channel Q are simulta neously present on D0­D11, channel I on the rising edge of the clock and channel Q on the falling edge of the clock.
(Refer to Figure 2: Timing diagram on page 4).

15/31

Application information TSA1204

8.2 References and common mode connection

VREFM must always be connected externally.

8.2.1 Internal reference and common mode

In the default configu ration, the ADC operates with its own reference and common mode
voltages generated by its internal bandgap. It is recommend ed to d ecouple t he VREFP and
INCM pins in order to minimize low and high frequency noise (see Figure 23).

Figure 23. Internal reference and common mode setting

1.03V

VIN

TSA1204

VINB

VREFP

VREFM

INCM

330pF

0.57V

330pF

10nF

10nF

4.7μF

8.2.2 External reference and common mode

Each of the voltages V
application needs (refer t o Table 5: Operating conditions on page 7 for min/max values). It is
possible to use an external reference voltage device for specific applications requiring even
better linearity, accuracy or enhanced temperature behavior.

The V

REFP

and V

REFM

that has a full scale amplitude of 2*(V
The INCM voltage is half the value of V
The best linearity and distortion performance is achieved with a dynamic ran ge abo v e 2 V

and by increasing the V
To obta in the h i ghest pe rformance from the TSA1204 device, we recommend implement ing

the configuration shown in Figure 24 with the STMicroelectronics TS821or TS4041-1.2 Vref.

REFM

, V

and INCM can be fixed externally to better fit to the

REFP

voltages set the analog dynamic r ange at the input of the converter

REFP-VREFM

REFP-VREFM

voltage instead of lowering the V

REFM

4.7μF

).

.

pp

REFP

one.

Figure 24. External reference setting

1kΩ

VREFP

VCCA

VIN

TSA1204

VINB

16/31

VREFM

TS821

TS4041

330pF

external
reference

10nF

4.7μF

TSA1204 Application information

8.3 Driving the differential analog inputs

The TSA1204 is designed to deliver optimum performance when driven on differential
inputs. An RF transformer is an efficient way of achieving this high performance.

Figure 25 describes the schematics . The input signal is f ed to the primary of the transf ormer,

while the secondary drives both ADC inputs. The common mo de v oltage of the ADC (INCM)
is connected to the center-tap of the secondary of the transformer in order to bias the input
signal around this common voltage , internally set to 0.46 V . It determines the DC component
of the analog signal. Being a high impedance input, it acts as an I/O and can be externally
driven to adjust this DC component. The INCM is decoupled to maintain a low noise lev el on
this node. Our evaluation board is mounted with a 1:1 ADT1-1WT transformer from
Minicircuits. You might also use a higher impedance ratio (1:2 or 1:4) to reduce the driving
requirement on the analog signal source.

Each analog input can drive a 1.4 V
amplitude is 2.8 V

pp

.

amplitude input signal, so the resulting differential

pp

Figure 25. Differential input configuration with transformer

Analog source

ADT1-1

1:1

VIN

TSA1204

50Ω

Figure 26. AC-coupled differential input

50Ω

common

mode

50Ω

10nF

33pF

10nF

33pF

330pF 470nF10nF

100kΩ

100kΩ

VINB

INCM

channels

I or Q

INCM

VIN

TSA1204

VINB

Figure 26 represents the biasing of a differential input signal in A C- coupl ed differential input

configuration. Both inputs V

and V

IN

are centered around the common mo de volt age, that

INB

can be let internal or fixed externally.

17/31

Application information TSA1204

Figure 27. DC-coupled 2 Vpp differential analog input

Figure 27 shows a DC-coupled configuration with forced VREFP and INCM to the 1 V DC

analog input while VREFM is connected to ground; the differential amplitude obtained is
2V

.

pp

8.4 Clock input

The quality of your TSA1204 converter is very dependent on your clock input accur acy, in
terms of aperture jitter; the use of a low jitter crystal controlled oscillator is recommended.

Further points to consider in your implementation are:

● The duty cycle must be between 45% and 55%.

● The clock pow er supplies must be independent from the ADC output supplies to avoid

digital noise modulation on the output.

● When powered-on, the circuit needs se v eral cloc k periods to reach its normal operating

conditions. Theref ore, it is recommended to keep the circuit clocked to avoid random
states before applying the supply voltages.

analog

DC

analog

DC

VREFP-VREFM = 1 V

AC+DC

330pF

VIN

VINB

10nF

VREFP

TSA1204

VREFM

INCM

4.7μF

8.5 Power consumption optimization

The internal architecture of the TSA1204 makes it possible to optimize power consumption
according to the sampling frequency of the applica tion. For this purpose, an external resistor
is placed between I
optimized over the full sampling range (0.5 Msps up to 20 Msps).

The TSA1204 combines the highest performance and the lowest consumption at 20 Msps
when R

is equal to 54 kΩ. This value is nev ertheless dependent on the application and the

pol

environment.
In the lower sampling frequency range, this value of resistor may be adjusted in order to

decrease the analog current without any degradation of the dynamic performance.

Table 12 gives some values to illustrate this.

18/31

and the analog ground pins. Therefore, the total dissipation can be

POL

TSA1204 Application information

Table 12. Total power consumption optimization depending on R

pol

value

FS (Msps) 10 20

(kΩ) 120 54

R

pol

Optimized power (mW) 95 120

8.6 Layout precautions

To use the ADC circuits most ef ficiently at high frequencies, some preca utions have to be
taken for power supplies:

● First of all, the implementation of 4 proper separate supplies and ground planes

(analog, digital, internal and external buffer ones) on the PCB is recommended f or hig h
speed circuit applications to provide lo w inductance and lo w resistance common return.

The separation of the analog si gna l from t he digi tal out put p art is mandatory to prevent
noise from coupling onto the input signal. The best compromise is to connect AGND,
DGND , GNDBI in a common point whereas GNDBE must be isolated. Similarly, the
AVCC, DVCC and VCCBI power supplies must be separate from the VCCBE power
supply.

● Power supply bypass capacitors must be placed as close as possible to the IC pins in

order to improve high frequency bypassing and reduce harmonic distortion.

● All inputs and outputs must be properly terminated with output termination resistors;

then the amplifier load is resistive only and the stability of the amplifier is improved. All
leads must be wide and as short as possible especially for the analog input in order to
decrease parasitic capacitance and inductance.

● To keep the capacitive loading as low as possible at digital outputs, short lead lengths

of routing are essential to minimize currents when the outpu t changes . To minimize this
output capacitance, use buffers or latches close to the output pins.

● Choose component sizes as small as possible (SMD).

8.7 EVAL1204/BA evaluation board

The EVAL1204/BA is a 4-layer board with high decoupling and grounding level. The
schematic of the evaluation board is shown in Figure 30 and its top overlay view in

Figure 29. The board has been characterized with a fully devoted ADC test bench as shown

in Figure 28.

Figure 28. Analog-to-digital converter characterization bench

HP8644

Sine Wave

Generator

Vin

HP8133

HP8644

ADC

evaluation

board

Pulse

Generator

Sine Wave
Generator

19/31

Clk

Data

Clk

Logic

Analyzer

PC

Application information TSA1204

Note: The analog signal must be filtered to be very pure. The dataready signal is the acquisition

clock of the logic analyzer. The ADC digital outputs are latched by the octal buffers
74LCX573. All characterization measurements are made with SFSR=1 dB for static
parameters.

Figure 29. Evaluation board printed circuit

Table 13. Printed circuit board - list of components

Name Footprint Name Footprint Name Footprint Name Part Footprint

RSQ6
RSQ7
RSQ8
RSI6
RSI7
RSI8
R3
R5
RQ19
RI1
RQ1
RI19
RSI9
RSQ5
RSQ9
RSI5
R24
R23
R21
R22
R2
R12
R11
Raj1

C23
C41
C29

Part
Type

0

805 CD2 10nF 603 C26 330pF 603 CQ6 NC 805

0

805 C40 10nF 603 C20 330pF 603 CI6 NC 805

0

805 C39 10nF 603 C33 330pF 603 U2 74LCX573 TSSOP20

0

805 CQ12 10nF 603 C25 330pF 603 U3 74LCX573 TSSOP20

0

805 CQ9 10nF 603 CI1 33pF 603 U1 STG719 SOT23-6

0

805 C52 10nF 603 CQ1 33pF 603 JA ANALOGIC connector

47

603 C18 10nF 603 C34 47µF RB.1 J17 BUFPOW connector

47

603 C21 10nF 603 C42 47µF RB.1 J25 CKDATA SMA

47

603 C4 10nF 603 C35 47µF RB.1 J4 CLK SMA

47

603 C15 10nF 603 C44 47µF RB.1 J27 CON2 SIP2

47

603 C27 10nF 603 C36 47µF RB.1 J26 CON2 SIP2

47

603 C11 10nF 603 C32 47µF RB.1 JD DIGITAL connector

0NC

805 CI9 10nF 603 C37 470nF 805 JI1 InI SMA

0NC

805 CI12 10nF 603 CQ10 470nF 805 JI1B InIB SMA

0NC

805 CI31 10nF 603 C28 470nF 805 JQ1 InQ SMA

0NC

805 CQ31 10nF 603 CI10 470nF 805 JQ1B InQB SMA

0NC

805 CQ30 330pF 603 CQ32 470nF 805 SW1 SWITCH connector

0NC

805 CI11 330pF 603 CQ13 470nF 805 S5 SW-SPST connector

0NC

805 C51 330pF 603 CI32 470nF 805 S4 SW-SPST connector

0NC

805 C2 330pF 603 C13 470nF 805 TI2 T2-AT1-1WT ADT

1K

603 C17 330pF 603 C53 470nF 805 TQ2 T2-AT1-1WT ADT

47K

603 CD3 330pF 603 C16 470nF 805 JI2 VREFI connector

47K

603 C10 330pF 603 C3 470nF 805 JQ2 VREFQ connector

200K

VR5
trimmer

10µF

1210 CI8 330pF 603 C38 470nF 805

10µF

1210 C14 330pF 603 CD1 470nF 805 NC: non soldered

10µF

1210 CI30 330pF 603 C19 470nF 805

Part
Type

CQ8 330pF 603 C22 470nF 805 J6 32Pin
CQ11 330pF 603 CI13 470nF 805

Part
Type

Type

IDC-32
connector

20/31

TSA1204 Application information

1

1

2

2

3

3

M

G
V

Figure 30. TSA1204 evaluation board schematic

D0 GND

D1 GND

D2 GND

D3 GND

D4 GND

D5 GND

D6 GND

D7 GND

D8 GND

D9 GND

D10 GND

D11 GND

CLK GND

J6

123456789

RS5 RS6 RS7 RS8 RS9

C C C

C C

C C

single input

differential input

Open Normal mode

Short High Impedance output mode

Switch S5

Open Normal mode

Short Test mode

VCCB3

VccB
GndB
VccB

VCCB2 Switch S4 OEB Mode

GndB
VccB
GndB

VCCB1

J17

BUFPOW

J25

CKDATA

R5

50

VCCB2

D

Vcc

47K

VCCB2
C28

470nF

47µF

GNDS1

STG719

C43 10µF+C44

VCCB1

AVCC

C16 470nF

0NM

0NM

0NM

0NM

RSI5

1

2

J26

CON2

S2

R12

47K

IN

U1

S5

SW-SPST

VCCB2
VCCB1

S4

SW-SPST

R11

INCM
REF
REFP

JI2

VREFI

R24

R23

R22

NM: non soudé analog input with transfo rmer (default)

R21

1011121314151617181920212223242526272829303132

D1D2D3D4D5

DO

VCCB3

20

47µF

+

C34

C27

C53 470nF

C15 10nF

RSI7

0 NC

TI2

1

RSI6

C37 470nF

10nF

C52 10nF

C14 330pF

C39 10nF

C25

0

0

RI1

50

Q019Q118Q217Q316Q415Q514Q613Q7

VCC

C26 330pF

OEB1D02D13D24D35D46D57D68D79GND

330pF

C51 330pF

CI11

330pF

CI12

10nF

CI13

470nF

CI30

330pF

CI31

10nF

CI32

470nF

CI8

330pF

CI9

10nF

CI10

470nF

RSI80RSI9

4326

T2-AT1-1WT

JI1B

InIB

D6

12

11

LE

U2

10

36

D1

37

D0(LSB)

38

VCCBE

39

GNDBE

40

VCCBI

41

VCCBI

CLKD

42

OEB

43

AVCC

44

AVCC

45

INCMI

46

REFMI

47

REFPI

48

AGND1INI2AGND3INBI4AGND5IPOL6AVCC7AGND8INQ9AGND10INBQ11AGND

CI6

NM

CI1

33pF

0 NC

RI19

50

D7D8D9

20

Q019Q118Q217Q316Q415Q514Q613Q7

VCC

74LCX573

OEB1D02D13D24D35D46D57D68D79GND

27

28

D929D830D731D632D533D434D335D2

D10

D11(MSB)

8-14bits ADCJ9ADC DUAL12B

R2

1K

Raj1

47K

C2

330pF

C4

10nF

C3

470nF

C41

10µF

C42

47µF

+

AVCC

JA

VCC

GND

D10

U3

26

VCCBE

ANALOGIC

25

12

GNDBE

D11

GNDBI
DVCC
DGND
SELECT
CLK
DGND
DVCC
AVCC
AGND
INCMQ
REFMQ
REFPQ

RSQ5

CLK

12

11

LE

10

10µF

+

C29

24
23
22
21
20
19
18
17
16
15
14
13

CQ6

NM

CQ1

33pF

RSQ70RSQ8

0 NC

TQ2
1

0

RSQ6

C33 330pF

C40 10nF

C38 470nF

74LCX573

VCCB2

47µF

C17 330pF

DVcc

4326

RQ1

50

+

C18 10nF

C19 470nF

C35

DVCC

SW1

CD3 330pF

CD2 10nF

CD1 470nF

CQ11

330pF

CQ12

10nF

CQ13

470nF

CQ30

330pF

CQ31

10nF

CQ32

470nF

CQ8

330pF

CQ9

10nF

CQ10

470nF

0

RSQ9

T2-AT1-1WT

JQ1B

InQB

C10 330pF

C20 330pF

0 NC

RQ19

50

R3

50

C5

J4

CLK

100nF

1

2

J27

CON2

C11 10nF

C13 470nF

AVCC

DVCC

C21 10nF

C22 470nF

C23 10µF+C36

JQ2

C31 10µF+C32

47µF

INCM
REFM

REFP

VREFQ

JD

DIGITAL

ND
CC

47µF

21/31

Application information TSA1204

8.7.1 Evaluation board operating conditions

Table 14 below shows the connections to the board for the power supplies and other pins.

Table 14. Board connections for power supplies and other pins

Board marking Connection Internal voltage (V) External voltage (V)

AV AVCC 2.5
AG AGND 0
RPI REFPI 0.89 <1.4

RMI REFMI <0.4

CMI INCMI 0.46 <1
RPQ REFPQ 0.89 <1.4
RMQ REFMQ <0.4
CMQ INCMQ 0.46 <1

DV DVCC 2.5

DG DGND 0
GB1 GNDBI 0
VB1 VCCBI 2.5
GB2 GNDBE 0
VB2 VCCBE 1.8/2.5/3.3
GB3 GNDB3 0
VB3 VCCB3 2.5

Caution: Do not use the VB3 power supply (5 V) dedicated to the 74LCX573 external buffer s to

supply the VB2 of the TSA1203 which cannot exceed 3.3 V.

8.7.2 Consumption adjustment

Before beginnning characterization tests, make su re to a dju st t he R
I

, value according to y our sampling frequency.

pol

(Raj1), and theref or e

pol

8.7.3 Single and differentia l inputs

The test board can be driven on a single analog input, or on dif f erent ial inputs . With a single
analog input, you must use the ADT1-1WT transformer to genera te a differential signal. In
this configuration, the resistors RSI6, RSI7, RSI8 for channel I (respectively RSQ6, RSQ7,
RSQ8 for channel Q) are connected as short-circuits whereas RSI5, RSI9 (respectively
RSQ5, RSQ9 for channel Q) are open circuits.

Alternatively, you can use the JI1 and JI1B differential inputs. In this case, the resistances
RSI5, RSI9 for channel I (respectively RSQ5, RSQ9 for channel Q) are connected as short­circuits whereas RSI6, RSI7, RSI8 (respectively RSQ6, RSQ7, RSQ8 for channel Q) are
open circuits.

22/31

TSA1204 Application information

8.7.4 Mode select

In order to select the channel you want to evaluate, you m ust set a jumper on the board in
the relevant position for the SELECT pin (see Figure 31).

The channels selected depend on the position of the jumper:

● With the jumper connected to the upper conn ecto rs, channel I at the output is selecte d.

● With the jumper connected horizontally, channel Q at the output is selected.

● With the jumper connected to the lower connectors, both channels are selected,

relative to the clock edge.

Figure 31. Mode selection

SELECT

DVCCDGNDCLK

SELECT

I channel

Q channel

I/Q channels

23/31

Practical application examples TSA1204

9 Practical application examples

9.1 Digital interface applications

The wide external buffer power supply range of the TSA1204 makes it a perfect choice for
plugging into 2.5 V or 3.3 V low voltage DSPs or digital interfaces.

9.2 Medical imaging application

Driven by the demand of the applications requiring nowadays either portability or ahigh
degree of parallelism (or both), this produ ct satisfies the requirements of medical imaging
and telecom infrastructures.

The typical system diagram in Figure 32 shows how a narrow input b eam of acoustic energ y
is sent into a living body via the transducer and how the energy reflected back is analyzed.

Figure 32. Medical imaging application

HV TX amps

TX beam

former

Mux and

T/R

switches

TGC amplifier

The transducer is a piezoelectric ceramic such as zirconium titanate. The whole array can
reach up to 512 channels. The TX beam f ormer , amplified by the HV TX amps , delivers up t o
100 V amplitude excitation pulses with phase an d amplitude shifts . Th e mux and T/R switch
is a two-way input signal transmitter/output receiver.

To compensate for skin and tissues attenuation effects, the time gain compensation (TGC)
amplifier is an exponential amplifier that enables the amplification of low voltage signals to
the ADC input range. Differential output structure with low noise and very high linearity are
mandatory factors.

These applications need high speed, low power and high performance ADCs. 10-12 bit
resolution is necessary to lower the quantification noise. As multiple channels are used, a
dual converter is a must for room saving issues.

The input signal is in the range of 2 to 20 MHz (mainly 2 to 7 MHz) and the application uses
mostly a 4 over-sampling ratio for spurious free dynamic range ( SFDR) optimization.

ADC

RX beam

former

Processing
and display

The next RX beam f ormer and processing b loc ks e nable t he analysis of th e output channe ls
versus the input beam.

24/31

TSA1204 Definitions of specified parameters

10 Definitions of specified parameters

Static parameters

Static measurements are performed using the histograms method on a 2 MHz input signal,
sampled at 50 Msps, which is high enough t o fully characteriz e the test freq uency response .
The input level is +1 dBFS to saturate the signal.

Differential non linearity (DNL)

The average deviation of any output code width from the ideal code width of 1 LSB.

Integral non linearity (INL)

An ideal converter exhibits a transfer function which is a straight line from the starting code
to the ending code. The INL is the deviation from this ideal line for each transition.

Dynamic parameters

Dynamic measurements are performed by spectral analysis, applied to an input sine wave
of various frequencies sampled at 40 Msps.

The input lev el is -1dBFS to measure the linear beha vior of the con v erter. All th e parameters
are given without correction for the full scale amplitude performance except the calculated
ENOB parameter.

Spurious free dynamic range (SFDR)

The ratio between the power of the worst spurious signal (not always an harmonic) and the
amplitude of fundamental tone (signal power) over the fu ll Nyquist band. It is expressed in
dBc.

Total harmonic distortion (THD)

The ratio of the rms sum of the first fiv e harmonic distortion components to the rms value of
the fundamental line. It is expressed in dB.

Signal to noise ratio (SNR)

The ratio of the rms value of the fundamental componen t to the rms sum of all other spectr al
components in the Nyquist band (f
harmonics. SNR is reported in dB.

/2) excluding DC, fundamental and the first five

s

Signal to noise and distortion ratio (SINAD)

Similar ratio as for SNR b ut including the harmonic distortion components in the noise figure
(not DC signal). It is expressed in dB.

The effective number of bits (ENOB) is easily deduced from the SINAD, using the formula:
SINAD= 6.02 × ENOB + 1.76 dB.
When the applied signal is not full scale (FS), but has an A

expression becomes:

amplitude, the SINAD

0

SINAD

2Ao

=SINAD

Full Scale

+ 20 log (2A0/FS)

25/31

Definitions of specified parameters TSA1204

SINAD
The ENOB is expressed in bits.

=6.02 × ENOB + 1.76 dB + 20 log (2A0/FS)

2Ao

Analog input bandwidth

The maximum analog input frequency at which the spectral response of a full power signal
is reduced by 3 dB. Higher values can be achieved with smaller input levels.

Effective resolution bandwidth (ERB)

The band of input signal frequencies that the ADC is intended to convert without loosing
linearity i.e. the maximum analog input frequency at which the SINAD is d ecreased by 3 dB
or the ENOB by 1/2 bit.

Pipeline delay

Delay between the initial sample of the analog input and the av ailability of the corresponding
digital data output, on the output bus. Also called data latency. It is expressed as a number
of clock cycles.

26/31

TSA1204 Package mechanical data

11 Package mechanical data

In order to meet environmental requirements, STMicroelectronics offers these devices in
ECOPACK
category of second level interconnect is marke d on the pa ckage and on the inner box label,
in compliance with JEDEC Standard JESD97. The maximum ratings related t o soldering
conditions are also marked on the inner box label. ECOPACK is an STMicroelectronics
trademark. ECOPACK specifications are available at: www.st.com

®

packages. These packages have a Lead-free second level interconnect. The

.

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Package mechanical data TSA1204

Figure 33. Package mechanical data (48-pin plastic package)

A

A2

48 37

1

e

0,10 mm
.004 inch

36

SEATING PLANE

A1

E

E3

E1

12

13 24

D3
D1

D

25

L1

L

K

0,25 mm
.010 inch
GAGE PLANE

B

c

Millimeters Inches

Ref.

Min. Typ. Max. Min. Typ. Max.

A 1.60 0.063
A1 0.05 0.15 0.002 0.006
A2 1.35 1.40 1.45 0.053 0.055 0.057

B 0.17 0.22 0.27 0.007 0.009 0.011

C 0.09 0.20 0.004 0.008

D9.00 0.354
D1 7.00 0.276
D3 5.50 0.216

e 0.50 0.0197

E9.00 0.354
E1 7.00 0.276
E3 5.50 0.216

L 0.45 0.60 0.75 0.018 0.024 0.030

L1 1.00 0.039

K

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0° (min.), 7° (max.)

TSA1204 Ordering information

12 Ordering information

Table 15. Order codes

Part number

TSA1204IFT-E -40° C to +85° C TQFP48 Tape & reel SA1204I
EVAL1204/BA Evaluation board

Temperature

range

Package Packing Marking

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Revision history TSA1204

13 Revision history

Table 16. Document revision history

Date Revision Changes

1-Apr-2004 1 Initial release.

2-May-2005 2

26-Sep-2006 3

12-Dec-2006 4 Renamed pin 42 to CLKD.

Datasheet modified from Not for new Design to full production further
to new business demand.

Editorial updates. Reorganized document structure. No technical
changes.

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TSA1204

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