ST TSA1002 User Manual

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TSA1002

10-BIT, 50MSPS, 50mW A/D CONVERTER

■ 10-bit A/D converter in deep submicron

CMOS technology

■ Single supply voltage: 2.5V

■ Input range: 2Vpp differential

■ 50Msps sampling frequency

■ Ultra low power consumption: 50mW @

50Msps

■ ENOB=9.4 @ Fs=50Msps, Fin=15MHz

■ SFDR typically up to 72dB @ Fs=50Msps,

Fin=5MHz

■ Built-in reference voltage with external bias

capability

■ STMicroelectronics 8, 10, 12 and 14-bits ADC

pinout compatibility

DESCRIPTION

The TSA1002 is a 10-bit, 50Msps sampling
frequency Analog to Digital converter using a
CMOS technology combining high performances
and very low power consumption.
The TSA1002 is based on a pipeline structure and
digital error correction to provide excellent static
linearity and guarantee 9.4 effective bits at
Fs=50Msps, and Fin=15MHz .
A voltage reference is int egrated in the circuit to
simplify the design and minimize external
components. It is nevertheless possible to use the
circuit with an external reference.
Especially designed for high speed, low power
applications, the TSA1002 only dissipates 50m W
at 50Msps. A tri-state capability, available on the
output buffers, enables to address several slave
ADCs by a unique master.
The output data can be coded into two d ifferent
formats. A Data Ready signal is raised as the data
is valid on the output and can be used for
synchronization purposes.
The TSA1002 is available in commercial (0 to

+70°C) and extended (-40 t o +85°C) temperat ure
range, in a small 48 pins TQFP package.

ORDER CODE

Part Number

TSA1002CF 0°C to +70°C TQFP48 Tray SA1002C
TSA1002CFT 0°C to +70°C TQFP48 Tape & Reel SA1002C
TSA1002IF -40°C to +85°C TQFP48 Tray SA1002I
TSA1002IFT -40°C to +85°C TQFP48 Tape & Reel SA1002I
EVAL1002/AA Evaluation board

Temperature

Range

Package Conditioning Marking

PIN CONNECTIONS (top view)

AGND

index

corner

IPOL

VREFP

VREFM

AGND

VIN

AGND

VINB
AGND
INCM

AGND
AVCC
AVCC

AVCC

AVCC

DFSB

4748 44 43 42 41 40 39 38

46 45

1
2

3
4

5
6

7
8

9
10
11
12

13 14 15 16 17 18 19 20 21 22

DVCC

DVCC

TSA1002

CLK

DGND

DGND

OEB

NC

NC

DGND

VCCB

GNDB

VCCB

NC

DR

37

NC

36

NC

35

NC

34

D0 (LSB)

33
32

D1

31

D2

30

D3
D4

29

D5

28

D6

27
26

D7

25

D8

23 24

GNDB

GNDB

VCCBNCOR

D9 (MSB)

PACKAGE

7 × 7 mm TQFP48

APPLICATIONS

■ Medical imaging and ultrasound

■ Portable instrumentation

■ Cable Modem Receivers

■ High resolution fax and scanners

■ High speed DSP interface

October 2000

1/19

TSA1002

ABSOLUTE MAXIMUM RATINGS

Symbol Parameter Values Unit

AVCC
DVCC
VCCB

Analog Supply voltage
Digital Supply voltage
Digital buffer Supply voltage

IDout Digital output current -100 to 100 mA

Tstg Storage temperature +150 °C

Electrical Static Discharge

ESD

- HBM

- CDM-JEDEC Standard

1) All voltages values, e xcept differential voltage, are with respect to network g round terminal. The m agnitude of i nput and output volt ages
must neve r exceed -0.3V or VCC+0V

OPERATING CONDITIONS

Symbol Parameter Test conditions Min Typ Max Unit

AVCC Analog Supply voltage 2.25 2.5 2.7 V
DVCC Digital Supply voltage 2.25 2.5 2.7 V
VCCB Digital buffer Supply voltage 2.25 2.5 2.7 V

VREFP Forced top reference voltage 1.16 - AVCC V

VREFM Forced bottom reference voltage 0 0 0.5

1)

1)

1)

0 to 3.3 V
0 to 3.3 V
0 to 3.3 V

2

KV

1.5

BLOCK DIAGRAM

VIN

INCM

VINB

CLK

+2.5V

Timing

GND

stage
1 2

stage

stage
n

Sequencer-ph as e shifting

Digital data correction

Referen ce

Buffers

VREFP

circuit

GNDA

IPOL

VREFM

DFSB
OEB

DR
DO

TO

D9

OR

2/19

PIN CONNECTIONS (top view)

index

corner

1

IPOL

2

VREFP

AGND

VIN

AGND

VINB
AGND
INCM

AGND
AVCC

3
4

5
6

7
8

9
10
11
12

VREFM

AGND

AVCC

AVCC

DFSB

OEB

4748 44 43 42 41 40 39 38

46 45

VCCB

NC

GNDB

NC

TSA1002

13 14 15 16 17 18 19 20 21 22

DVCC

CLK

DGND

DVCC

DGND

DGND

GNDB

GNDB

VCCB

23 24

VCCBNCOR

DR

NC

37

D9 (MSB)

36
35

34
33
32
31
30
29
28
27

26
25

TSA1002

NC
NC
NC

D0 (LSB)
D1
D2
D3

D4
D5
D6

D7
D8AVCC

PIN DESCRIPTION

Pin No Name Description Observation Pin No Name Description Observation

1 IPOL Analog bias current input 25 D8 Digital ou tput CMOS output (2.5V)
2 VREFP Top voltage reference 1V 26 D7 Digita l output CMOS output (2.5V)
3 VREFM Bottom voltage reference 0V 27 D6 Digital output CMOS output (2.5V)
4 AGND Analog ground 0V 28 D5 Digital output CMOS output (2.5V)
5 VIN Analog input 1Vpp 29 D4 Digital output CMOS output (2.5V)
6 AGND Analog ground 0V 30 D3 Digital output CMOS output (2.5V)
7 VINB Inverted analog input 1Vpp 31 D2 Digital output CMOS output (2.5V)
8 AGND Analog ground 0V 32 D1 Digital output CMOS output (2.5V)

9 INCM Input common mode 0.5V 33 D0(LSB) Least Significant Bit output CMOS output (2.5V)
10 AGND Analog ground 0V 34 NC Non connected
1 1 AVCC Analog p ow er supply 2.5V 35 NC Non c onnected
12 AVCC Analog power supply 2.5V 36 NC Non connected
13 DVCC Digital power s upply 2.5V 37 NC Non connected
14 DVCC Digital power supply 2.5V 38 DR Data Ready output CMOS out put (2.5V)
15 DGND Digital ground 0V 39 VCCB Digital Buffer power supply 2.5V
16 CLK Clock input 2.5V compatible CMOS input 40 GNDB Digital Buffer ground 0V
17 DGND Digital ground 0V 41 VCCB Digital Buffer power supply 2.5V
18 NC Non connected 42 NC Non connected
19 DGN D Digita l ground 0V 43 NC Non connected
20 GND B Digital buffer ground 0V 44 OEB Output Enable i nput 2.5V compatible CMOS input
21 GNDB Digital buffer gro und 0V 45 DFSB Data Format Se lect input 2.5V compa tible CMOS inpu t
22 VCCB Digital buffer power supply 2.5V 46 AVCC Analog power supply 2.5V
23 OR Out Of Range output CMOS output (2.5V) 47 AVCC Analog power supply 2.5V
24 D9(MSB) Most Significant Bit output CMOS output (2.5V) 48 AGND Analog ground 0V

3/19

TSA1002

ELECTRICAL CHARACTERISTICS

AVCC = DVCC = VCCB = 2.5V, Fs= 40Msps,Fin= 1MHz, Vin@ -1.0dBFS, VREFM= 0V

Tamb = 25°C (unless otherwise specified)

TIMING CHARACTERISTICS

Symbol Parameter Test conditions Min Typ Max Unit

FS Sampling Frequency 0.5 50 Msps

DC Clock Duty Cycle 45 50 55 %
TC1 Clock pulse width (high) 9 10 ns
TC2 Clock pulse width (low) 9 10 ns

Tod

Data Output Delay (Fall of Clock
to Data Valid)

Tpd Data Pipeline delay 6.5 cycles

Ton

Toff

Falling edge of OEB to digital
output valid data

Rising edge of OEB to digital
output tri-state

10pF load capacitance

5ns

1ns

1ns

TIMING DIAGRAM

N-1

CLK

OEB

Tod

DATA

OUT

DR

N-8

N+4

N+3

N+2

N-7

N+1

N-6

N-5

6.5 clk cycles

N-4

N-3

N

Toff

N+5

N-2

N+6

N+7

N+8

Ton

N

N+1

HZ state

4/19

TSA1002

CONDITIONS

AVCC = DVCC = VCCB = 2.5V, Fs= 40Msps,Fin= 1MHz, Vin@ -1.0dBFS, VREFM= 0V

Tamb = 25°C (unless otherwise specified)

ANALOG INPUTS

Symbol Parameter Test conditions Min Typ Max Unit

VIN-VINB Full scale refere nce voltag e 2.0 Vpp

Cin Input capacitance 7.0 pF

BW Analog Input Bandwidth Vin@ Full scale, FS=50Msps 100 MHz

ERB

1) See parameters definiti on for more in formation

Effective Resolution Bandwidth

REFERENCE VOLTAGE

Symbol Parameter Test conditions Min Typ Max Unit

1)

60 MHz

VREFP Top internal reference voltage

Tmin= -40°C to Tmax= 85°C

1)

0.88 1.16 V

1.20 1.27 1.35 V

0.91 1.03 1.14 V

Vpol Analog bias voltage

Tmin= -40°C to Tmax= 85°C

1)

1.18 1.36 V

Ipol Analog bias current Normal operating mode 50 70 100 µA
Ipol Analog bias current Shutdown mode 0 µA

0.47 0.57 0.68 V

VINCM Input common mode voltage

Tmin= -40°C to Tmax= 85°C

1) No t f ul l y tested over the temperat ure range. Gua ranted by sam pl i ng.

1)

0.46 0.66 V

5/19

TSA1002

CONDITIONS

AVCC = DVCC = VCCB = 2.5V, Fs= 40Msps,Fin= 1MHz, Vin@ -1.0dBFS, VREFP=1V, VREFM= 0V

Tamb = 25°C (unless otherwise specified)

POWER CONSUMPTION

Symbol Parameter Test conditions Min Typ Max Unit

1)

ICCA Analog Supply current

Tmin= -40°C to Tmax= 85°C

1)

ICCD Digital Supply Current

Tmin= -40°C to Tmax= 85°C

1)

ICCB Digital Buffer Supply Current

Tmin= -40°C to Tmax= 85°C

ICCBZ

PdZ

Rthja

1) Rp ol = 18KΩ. Equivalent load: Rload= 470Ω and Cload= 6pF

2) No t f ul l y t ested over the temperature range. Gua ranted by sam pling.

Digital Buffer Supply Current in
High Impedance Mode

Power consumption in normal

Pd

operation mode
Power consumption in High

Impedance mode
Junction-ambient thermal resis-

tor (TQFP48)

1)

1)

Tmin= -40°C to Tmax= 85°C

1)

2)

2)

2)

2)

15.6 18 mA

21 mA

1.3 2 mA
2mA

2.5 5 mA
5mA

40 100 µA
48 60 mW

62 mW

43 48 mW

80 °C/W

DIGITAL INPUTS AND OUTPUTS

Symbol Parameter Test conditions Min Typ Max Unit

Digital inputs

VIL Logic "0" voltage 0.8 V

VIH Logic "1" voltage 2.0 V

Digital Outputs

VOL Logic "0" voltage Iol=10µA 0.4 V

VOH Logic "1" voltage Ioh=-10µA 2.4 V

IOZ High Impedance leakage current OEB set to VIH -1.5 1.5 µA

C

Output Load Capacitance 15 pF

L

ACCURACY

Symbol Parameter Test conditions Min Typ Max Unit

OE Offset Error

DNL Differential Non Linearity

INL Integral Non Linearity

Monotonicity and no missing

-

codes

6/19

Fin= 2MHz , VIN@+1dBF S

Fin= 2MHz , VIN@+1dBF S
Fin= 2MHz , VIN@+1dBF S

-5 ±0.2 +5 %

-0.7 ±0.2 +0.7 LSB

-0.8 ±0.3 +0.8 LSB

Guaranted

TSA1002

CONDITIONS

AVCC = DVCC = 2.5V, Fs= 40Msps Vin@ -1.0dBFS, VREFP=1V, VREFM= 0V

Tamb = 25°C (unless otherwise specified)

DYNAMIC CHARACTERISTICS

Symbol Parameter Test conditions Min Typ Max Unit

Fin= 5MHz
Fin= 10MHz

1)

Fin= 24MHz

SFDR Spurious Free Dynamic Range

Fin= 5MHz
Fin= 10MHz

2)

Fin= 24MHz
Fin= 5MHz

Fin= 10MHz

1)

Fin= 24MHz

SNR Signal to Noise Ratio

Fin= 5MHz
Fin= 10MHz

2)

Fin= 24MHz
Fin= 5MHz

Fin= 10MHz

1)

Fin= 24MHz

THD Total Harmonic Distortion

Fin= 5MHz
Fin= 10MHz

2)

Fin= 24MHz
Fin= 5MHz

1)

2)

SINAD

Signal to Noise and Distortion­Ratio

Fin= 10MHz
Fin= 24MHz

Fin= 5MHz
Fin= 10MHz

Fin= 24MHz
Fin= 5MHz

Fin= 10MHz

1)

Fin= 24MHz

ENOB Effective Number of Bits

Fin= 5MHz
Fin= 10MHz

2)

Fin= 24MHz

1) Rp ol = 18KΩ. Equiv alent load: Rloa d= 470Ω and Cload= 6pF

Tmin= -40°C to Tmax= 85°C. Not fully tes t ed over the tem perature ra nge. Guarant ed by samplin g.

2)

65.5

68.5

63.4
60

60
60

58.5

58.3

57.4
48

48
48

63.5

67.4

62.5
57

55
57

58.5

58.2

57.0
48

48
48

9.6

9.5

9.3

7.9

7.9

7.9

79.2
77
69

59.5

59.4

59.0

77.8
76

68.1

59.4

59.3

58.5

9.76

9.71

9.60

dBc

dBc

dB

dB

dB

dB

dB

dB

bits

bits

7/19

TSA1002

DEFINITIONS OF SPECIFIED PARAMETERS

STATIC PARAMETERS

Static measurements are performed through
method of histograms on a 2MHz input signal,
sampled at 40Msps, which is high eno ugh to fully
characterize the test frequency response. The
input level is +1dBFS to saturate the signal.

Differential Non Linearity (DNL)

The average devia tion of any outp ut code width
from the ideal code width of 1LSB.

Integral Non linearity (INL)

An ideal converter presents a transfer function as
being the straight line from the starting code to the
ending code. The INL is the deviation for each
transition from this ideal curve.

DYNAMIC PARAMETERS

Dynamic measurements are performed by
spectral analysis, appli ed to an in put sinewave of
various frequencies and sampled at 40Msps.

Spurious Free Dynamic Range (SFDR)

The ratio between the am plitude of fundamental
tone (signal power) and the power of the worst
spurious signal (not always an harmonic) over the
full Nyquist band. It is expressed in dBc.

Total Harmonic Distortion (THD)

The ratio of the rms sum of the first five harmonic
distortion components to the rms value of the
fundamental line. It is expressed in dB.

Signal to Noise Ratio (SNR)

The ratio of the rms value of the fundamental
component to the rms sum of all other spectral
components in the N yquist band (f

/2) excluding

s

DC, fundamental and the first five harmonics.
SNR is reported in dB.

Signal to Noise and Distorsion Ratio (SINAD)

Similar ratio as for SNR but including the harmonic
distortion components in the noise figure (not DC
signal). It is expressed in dB.
From the SINAD, the Effective Number of Bits
(ENOB) can easily be deduced using the formula:
SINAD= 6.02 × ENOB + 1.76 dB.
When the applied signal is not Full Scale (FS), but
has an A

amplitude, the SINAD expression

0

becomes:
SINAD= 6.02 × ENOB + 1.76 dB + 20 log (2A

/FS)

0

The ENOB is expressed in bits.

Anal og Input Bandwidt h

The maximum analog input frequency at which the
spectral response of a full power signal is reduced
by 3dB. Higher values can be achieved with
smaller in put levels.

Effective Resolution Bandwidth (ERB)

The band of input signal frequencies that the ADC
is intended to convert without l oosing linearity i.e.
the maximum analog input frequency at which the
SINAD is decreased by 3dB or the ENOB by 1/2
bit.

Pipeline dela y

Delay between time when the analog input is
initially sampled and time when the corresponding
digital data output is valid on the output bus. Also
called data latency. It is expressed as a number of
clock cycles.

8/19

EQUIVALENT CIRCUITS

TSA1002

Figure 1 : Analog Input Circuit

AVCC=2.5V

VIN

(or V IN B )

PAD
CAPACITANCE

7 pF

AGND=0V

Figure 2 : Input clock circuit

DVCC=2.5V

CLK

Req # 33 kΩ

(if Fs=50 MHz)

comm on m ode

Figure 3 : Input buffers

VCC buf=2.5V

Ω278.5 Ω208.2Ω355.5

DFS

7 pF

PAD
CAPACITANCE

GND buff=0V

Figure 4 : Tri-state output buffers

VCC buf=2.5V

OE

PAD
CAPACITANCE

7 pF

DGND=0V

DATA

GN D bu ff=0V

GND buff =0V

VCC b u f =2 .5V

OUT

2 mA
OUTPUT
BUFFER

PAD CAPAC ITANCE
7pF

9/19

TSA1002

Static parameter: Integral Non Linearity
Fs=50MSPS; Fin=1MHz; Icc=20mA; N=131072pts

0.8

0.6

0.4

0.2
0

-0.2

INL (LSBs)

-0.4

-0.6

-0.8

0 200 40 0 600 800 10 00

O utput Code

Static parameter: Differential Non Linearity
Fs=50MSPS; Fin=1MHz; Icc=20mA; N=131072pts

0.5

0.4

0.3

0.2

0.1
0

-0 .1

DNL (LSBs)

-0 .2

-0 .3

-0 .4

-0 .5
0 200 400 600 800 1000

Linearity vs. AVcc
Fs=50MSPS; Icca=20mA; Fin=1MHz

60

59.5
59

58.5
58

57.5
57

56.5
56

55.5

Dynamic parameters (dB)

55

2.25 2.35 2.45 2.55 2.65

SNR

SINAD

ENOB

AVCC (V)

Output Code

10

9.9

9.8

9.7

9.6

ENOB (bits)

9.5

9.4

9.3

Distortion vs. AVcc
Fs=50MSPS; Icca=20mA; Fin=1MHz

-69

-71

-73

-75

-77

-79

-81

-83

Dynamic Parameters (dB)

-85

2.25 2.35 2.45 2.55 2.65

SFDR

THD

AVCC (V)

10/19

TSA1002

Linearity vs. DVcc
Fs=50MSPS; Icca=20mA; Fin=1MHz

59.1

59.05

59

58.95

58.9

58.85

SNR

ENOB

SINAD

Dynamic parameters (dB)

58.8

2.25 2.35 2.45 2.55 2.65

DVCC (V)

Linearity vs. VccB
Fs=50MSPS; Icca=20mA; Fin=1MHz

59.5

59

58.5

58

57.5

Dynamic parameters (dB)

57

2.25 2.35 2.45 2.55 2.65

SNR

SINAD

ENOB

VCCB (V)

9.6

9.595

9.59

9.585

9.58

9.575

9.57

10

9.9

9.8

9.7

9.6

9.5

9.4

Distortion vs. DVcc
Fs=50MSPS; Icca=20mA; Fin=1MHz

-65

-67

-69

-71

-73

-75

ENOB (bits)

-77

-79

-81

-83

Dynamic parameters (dB)

-85

2.25 2.35 2.45 2.55 2.65

SFDR

THD

DVCC (V)

Distortion vs. VccB
Fs=50MSPS; Icca=20mA; Fin=1MHz

-72

-73

-74

-75

-76

ENOB (bits)

-77

-78

-79

Dynamic Parameters (dB)

-80

2.25 2.35 2.45 2.55 2.65

THD

SFDR

VCCB (V)

Linearity vs. Fs
Icca=20mA; Fin=5MHz

66

61

56

51

Dynamic parameters (dB)

46

25 35 45 55 65 75

ENOB

SNR

SINAD

Fs (MHz)

10

9.5

9

8.5

8

7.5

Distortion vs. Fs
Icca=20mA; Fin=5MHz

-50

-55

-60

-65

-70

ENOB (bits)

-75

-80

-85

Dynamic parameters (dB)

-90
25 35 45 55 65 75

THD

SFDR

Fs (MHz)

11/19

TSA1002

Linearity vs. Fs

Icca=20mA; Fin=15 MHz

66

61

56

51

Dynamic parameters (dB)

46

25 35 45 55 65 75

ENOB

SNR

SINAD

Fs (MHz)

Linearity vs. Fin
Fs=50MSPS; Icca=20mA

64

62

60

58

56

Dynamic parameters (dB)

54

0 204060

Fin (MH z)

SNR

SINAD

ENOB

9.6

9.1

8.6

8.1

7.6

10

9.5

9

8.5

8

7.5

Distortion vs. Fs
Icca=20mA; Fin=15 MHz

-50

-55

-60

-65

-70

ENOB (bits)

-75

-80

-85

Dynamic parameters (dB)

-90
25 35 45 55 65 75

THD

SFDR

Fs (MHz)

Distortion vs. Fin
Fs=50MSPS; Icca= 2 0mA

-50

-55

-60

-65

-70

ENOB (bits)

-75

-80

Dynamic parameters (dB)

-85

0 204060

THD

SFDR

Fin (MHz)

Linearity vs.Temperatur e

Fs=50MSPS; Icca=20mA; Fin=5MHz

12/19

64
62
60
58
56
54
52

Dynamic Parameters (dB)

50

-50 0 50 100

ENOB

SNR

SINAD

Temperature (°C)

10

9.8

9.6

9.4

9.2
9

8.8

8.6

8.4

8.2
8

Distortion vs. Temperature
Fs=50MSPS; Icca=20mA; Fin=5MHz;

80

75

70

65

60

Dynamic Parameters (dB)

55

-50 0 50 100

SFDR

THD

Temperature (°C)

TSA1002 APPLICATION NOTE

DETAILED INFORMATION

The TSA1002 is a High Speed analog to digital
converter based on a pipeline architecture and the
latest deep submicron CMOS process to achieve
the best performances in terms of linearity and
power consumption.

The pipeline structure consists of 9 internal
conversion stages in which the analog signal is
fed and sequencially converted into digital data.

Each 8 first stages consists of an Analog to Digital
converter, a Digital to Analog converter, a Sample
and Hold and a gain of 2 amplifier. A 1.5bit
conversion resolution is achieved in each stage.
The latest stage simply is a comparator. Each
resulting LSB-MSB c ouple is then time shifted to
recover from the conversion delay. Digital data
correction completes the processing by
recovering from the redundancy of the (LSB-MSB)

couple for each stage. The corrected data are
outputed through the digital buffers.
Signal input is sampled on the rising edge of the
clock while digital outputs are delivered on the
falling edge of the Data Ready signal.
The advantages of such a convert er reside in the
combination of pipeline architec ture and the most
advanced technologies. The highest dynamic
performances are achieved while consumption
remains at the lowest level.
Some functionalities hav e been added i n order to
simplify as much as possible the application
board. These operational m odes are described in
the following table.
The TSA1002 is pin to pin compatible with the
8bits/40Msps TSA0801, the 10bits/25Msps
TSA1001 and t he 12bits/50Msps TSA1201. T his
ensures a conformity within the product family and
above all, an easy upgrade of the application.

OPERATIONAL MODES DESCRIPTION

Inputs Output s

Analog input differential level DFSB OEB OR DR Most Significant Bit (MSB)

(VIN-VINB) > RANGE H L H CLK D9

-RANGE > (VIN-VINB) H L H CLK D9

RANGE> (VIN-VINB) >-RANGE H L L CLK D9

(VIN-VINB) > RANGE L L H CLK Complemented D9

-RANGE > (VIN-VINB) L L H CLK Complemented D9

RANGE> (VIN-VINB) >-RANGE L L L CLK Complemented D9

XXHHZHZHZ

Data Format Select (DFSB)

When set to low level (VIL), the digital input DFSB

provides a tw o’s complement d igital output MSB.
This can be of interest when performing some
further signal processing.
When set to high level (VIH), DFSB provides a
standard binary output coding.

Output Enable (OEB)

When set to low level (VIL), all digital outputs
remain active and are in low impedance state.
When set to high level (VIH), all digital outputs
buffers are in high impedance state. This results in

13/19

lower consumption while the converter goes on
sampling.

When OEB is set to low level again, , the data is
then valid on the output with a very short Ton
delay.

The timing diagram summarizes this operating
cycle.

Out of Range (OR)

This function is im plemented on the output stage
in order to set up an "Out of Range" flag whenever
the digital data is over the full scale range.

TSA1002

Typically, there is a detection of all the dat a bei ng

at ’0’ or all the data being at ’1’. This ends up with
an output signal OR which is in low level state
(VOL) when the data stay within the range, or in
high level state (VOH) when the data are out of the
range.

Data Ready (DR)

The Data Ready output is an image of the clock
being synchronized on the output data (D0 to D9).
This is a very helpful signal that simplifies the
synchronization of the measurement equipment or
the cont ro llin g DSP.

As digital output, DR goes in high impedance state
when OEB is as serted to High level as described
in the timing diagram.

DRIVING THE ANALOG INPUT

Differentia l inp u t s

The TSA1002 has been designed to obtain
optimum performances when being differentially
driven. An RF transformer is a good way to
achieve such performances.

Figure 5 describes the schematics. The input
signal is fed to the primary of the transformer,
while the secondary drives both ADC inputs. The
common mode voltage of the ADC (INCM) is
connected to the center-tap of the second ary of
the transformer in order to bias the input signal
around this common voltage, internally set to

0.56V. The INCM is decoupled to maintain a low
noise level on this node. Our evaluation b oard is
mounted with a 1:1 ADT1-1 transformer from
Minicircuits. You might also use a higher
impedance ratio (1:2 or 1:4) to reduce the driving
requirement on the analog signal source.

Each analog input can drive a 1Vpp amplitude
input signal, so the resultant differential amplitude
is 2Vpp.

Figure 5 : Differential input configuration

Single-ended input configuration

Some applications may require a single-ended
input which is easily achieved with the
configuration reported on Figure 6.
In this case, it is recommended to use an
AC-coupled analog input and connect the other
analog input to the common mode voltage of the
circuit (INCM) so as to properly bi as the ADC. The
INCM may remain at the same internal level
(0.56V) thus driving only a 1Vpp i nput amplitude,
or it must be increased to 0.9V to drive a 2Vpp
input amplitude. You wi ll get higher pe rform ances
using a 2Vpp signal.

Figure 6 : Single-ended input configuration

Signal so urce

50Ω

100nF

330pF

VIN

TSA1002

VINB

INCM

10nF

470nF

0.9V

Dynamic characteristics, while not being as
remarkable as for differential configuration, are
still of very goo d quality. Measurements done at
50Msps, 2MHz input frequency, -1dBFS input
level sum up these performances. An SFDR of

-64.5dBc, a SNR of 57.8dB and an ENOB Full
Scale of 9.3bits are achieved.

REFERENCE CONNECTION
Inte rnal ref erence

In the standard configuration, the ADC is bi ased
with the internal reference voltage. VREFM pin is
connected to Analog Ground while VREFP is
internally set to a voltage of 1.03V. It is
recommended to d ecouple the V R EF P i n order to
minimize low and high frequency noise. Refer to
Figure 7 for the schematics.

Analog source

14/19

50Ω

ADT1-1

1:1

330pF

100pF

10nF

VIN

TSA1002

VINB

INCM

470nF

Figure 7 : Internal reference setting

VIN

1.03V
VREFP

330pF

TSA1002

VINB

VREFM

10nF

470nF

TSA1002

Exte rnal ref eren ce

It is possible to use an external reference vo ltage
instead of the internal one for specific applications
requiring even better linearity or enhanced
temperature behaviour. In this case, the amplitude
of the external voltage mu st be at least equal to
the internal one (1.03V). Using the
STMicroelectronics Vref TS821 leads to optim um
performances when configured as shown on
Figure 8.

Figure 8 : External reference setting

1k

Ω

10nF

470nF

VCCA

VIN

TSA1002

VINB

VREFP

VREFM

330pF

TS821

external
reference

At 15Msps sampling frequency, 1MHz input
frequency and -1dBFS amplitude signal,
performances can be improved of up to 2dBc on
SFDR and 0.3dB on SINAD. At 50Msps sam pling
frequency, 1MHz input frequency and -1dBFS
amplitude signal, performanc es can be improved
of up to 1dBc on SFDR and 0.6dB on SINAD.
This can be very helpful for example for
multichannel application to kee p a good matching
among the sampling frequency range.

Clock input

The quality of your converter is very dependant on
your clock input accuracy, in terms of aperture
jitter; the use of low jitter crystal controlled
oscillator is recommended.
The duty cycle must be between 45% and 55%.
The clock power supplies must be separated from
the ADC output ones to avoid digital noise
modulation at the output.
It is recommended to always keep the circuit
clocked, even at the lowest specified sampling
frequency of 0.5Msps, bef ore applying the supply
voltages.

Power co nsumption

The internal architecture of the TSA1 002 enables
to optimize the power consumption according to
the sampling frequency of the application. For this
purpose, a resistor is placed between I POL and
the analog Ground pins.

The TSA1002 wi ll combine highest pe rformances
and lowest consumption at 50Msps when Rpol is
in the range of 12kΩ to 20kΩ.

At lower sampling frequency, this value of resistor
may be changed and the consumption will
decrease as wel l.

The figure 9 sums up the relevant data.
Figure 9 : Analog Current consumption vs. Fs

According value of Rpol polarization resistance

60

50

40

30

Icca (mA)

20

10

0

25 35 45 55 65 75

RPOL

ICCA

Fs (MHz)

20
18
16
14
12
10
8

Rpol (kOhms)

6
4
2
0

Layout precautions

To use the ADC circuits in the best manner at high
frequencies, some precautions have to be taken
for power supplies:

- First of all, the implementation of 4 separate
proper supplies and ground planes (analog,
digital, internal and external buffer ones) on the
PCB is mandatory for high speed circuit
applications to provide low inductance and low
resistance common return.

The separation of the analog signal from the
digital part is essential to prevent noise from
coupling onto the input signal.

- Power supply bypass capacitors must be placed
as close as possible to the IC pins in order to
improve high frequency bypassing and reduce
harmonic distortion.

- Proper termination of all inputs and outputs must
be incorporated with output termination resistors;
then the amplifier load wi ll be only resistive and
the stability of the amplifier will be improved. All
leads must be wide and as short as possible
especially for the analog input in order to decrease
parasitic capacitance and inductance.

- To keep the capacitive loading as low as
possible at digital outputs, short lead lengths of
routing are essential to minimize currents when
the output changes. To minimize this output

15/19

TSA1002

capacitance, buffers or latches close to the output
pins will relax this constraint.

- Choose component sizes as small as possible
(SMD).

EVAL1002 evaluation board

The characterization of the board has been made
with a fully ADC devoted test bench as shown on
Figure 10. The analog signal must be filtered t o be
very pure.

The dataready signal is the acquisition clock of the
logic analyzer.

The ADC digital outputs are latched by the octal
buffers 74LCX573.

All characterization measurements have been
made with:

SFSR=+0.2dB for static parameters.­SFSR=-0.5dB for dynamic parameters.

Figure 10 : Analog to Digital Converter characterization bench

Power

HP8644B

Sine wave
Generator

Vin

HP8133A

ADC

evaluation

board

ck

Pulse

Generator

data

dataready

Logic

Analyzer

TLA704

HP8644B

Sine Wave
Generator

16/19

Figure 11 : TSA1002 Evaluation board schematic

TSA1002

J6

123456789

DR

2

VCCB2

1

J17

VDDBU FF3V

+

C34

47µ

C37

2
1

J13

2
1

J11

2
1

J10

OEB

2
1

J9

DFSB

R10

47K

R11

47K

VCCB1
C28

AVCC

R12

47K

R13

47K

C16

470nF

470nF

470nF

C26

10nF

C39

R19
R18

R17

R16

R15

R14

C25

10nF

C27

C14

C15

10nF

Raj1

47K

R2

1K

1011121314151617181920212223242526272829303132

D1D2D3D4D5

DO

20

Q019Q118Q217Q316Q415Q514Q613Q7

VCC

330pF

OEB1D02D13D24D35D46D57D68D79GND

47K
47K

47K

47K

47K

47K

37
38

330pF

39
40
41
42
43
44
45
46
47
48

330pF

12

U2

36

D0

DR

NC
NC

OEB

DFSB

AVCC
AVCC
AGND

Ipol1Vre fP2Vre fM3AGND4Vin5AGND6VINB7AGND8INCM9AGND10AVCC11AVCC

C11

330pF

C12

10nF

C13

470nF

C30

330pF

10nF

C31

C32

470nF

D6

11

LE

74LCX573

10

2.5VCCBUFF

GNDBUFF

2.5VCCBUFF

8-14bits ADC

D7D8D9

D10

20

Q019Q118Q217Q316Q415Q514Q613Q7

VCC

U3

OEB1D02D13D24D35D46D57D68D79GND

27

D928D829D730D631D532D433D334D235D1

D1225D1126D10

D13
OR

2.5VCCBUFF
GNDBUFF
GNDBUFF
DGND
NC
DGND
CLK
DGND

TSA1002

DVCC
DVCC

12

C2

330pF

C4

10nF

C3

470nF

D11

12

24
23
22
21
20
19
18
17
16
15
14
13

32PIN

OR

D12

D13

11

LE

C38

74LCX573

10

+

C29

43

2
6

470nF

C33

10nF

330pF

C40

VCCB1

1
2

+

J18

C17

330pF

C18

10nF

C19

470nF

10µF

T1

T2-AT1-1WT

1

C20

330pF

C21

C24

R3

50

10nF

C22

470nF

C23

VccB1

10µ

C35

47µ

J4

CLJ/SMB

1
2

J16

CON2

C36

47µ

+

1

10µ

2

J15

DVCC

AVCC

C5

330pF

C8

330pF

C1

100pF

4326

T2

R1

50

1

1

2

1

J2

2

Vre fP

J5

Vre fM

J1

Vin

C6

10nF

C9

10nF

C7

470nF

C10

470nF

T2-AT1-1WT

1

2

1

J7

Regl com mode

J8

C41

10µF

C42

47µF

+

1

2

2

Mes c om Mod e

1

2

1

2

1

2

1

J12

AVCC

J19

AGND

J20

DGND

J21

2

GndB2

J22

GndB1

17/19

TSA1002

Regl com mode

74LCX 573

74LCX 573

Figure 12 : Printed circuit of evaluation board.

Print ed circui t board - List of components

Part Design Foo tprint P art Design Fo o tprint P art D esign Footprint P art Design F oo tprint

ator

Type
10 uF C 2 4 12 10
10 uF C 2 3 12 10
10 uF C 4 1 12 10
10 uF C 2 9 12 10
100pF C1 603
10 nF C 12 6 0 3
10 nF C 3 9 6 03
10 nF C 15 6 0 3
10 nF C 4 0 6 03
10 nF C 2 7 6 03
10 nF C 4 6 0 3
10 nF C 2 1 6 03
10 nF C 3 1 6 03
10 nF C 6 6 0 3
10 nF C 9 6 0 3
10 nF C 18 6 0 3
1K

R2 603

Ω

32P IN J6 IDC32
330pF C 25 603

330pF C 26 603

18/19

ator

Type
330pF C33 603 470nF C7 805 A VCC J12 FICHE2M M
330pF C20 603 470nF C16 805 CLJ/SM B J4 SM B/H
330pF C8 603 470nF C19 805 AGND J19 FICHE2MM
330pF C2 603 470nF C3 805 DFSB J9 FICHE2MM
330pF C5 603
330pF C11 603
330pF C30 603
330pF C17 603
330pF C14 603
47uF C36 C A P
47uF C34 C A P
47uF C35 C A P
47uF C42 C A P
470nF C22 805
470nF C32 805
470nF C37 805
470nF C38 805
470nF C13 805
470nF C28 805
470nF C10 805 C O N 2 J16 SIP2

Type

47K
47K
47K
47K
47K
47K
47K
47K
47K
47K
47K
50
50

ator

Ω R12 603 DGND J20 FICHE2MM
Ω

R14 603 DVCC J15 FICHE2M M

Ω R11 603 GndB1 J22 FICHE2MM
Ω

Raj1 VR5 GndB2 J21 FICHE2MM

Ω R 10 603 M es co m m ode J8 F IC H E2M M
Ω

R19 603 OEB J10 FICHE2MM

Ω R13 603
Ω

R15 603 T2-A T1-1WT T2 ADT

Ω

R16 603 T2-A T1-1WT T1 ADT

Ω

R17 603 VccB1 J18 FICHE2M M

Ω

R18 603 VDDBUFF3V J17 FICHE2M M

Ω

R3 603 Vin J1 SM B/H

Ω

R1 603 VrefM J5 FICHE2M M
U3 T S SO P 20 VrefP J2 F ICH E 2M M
U2 TS S OP 20 T SA 1002 U1 T Q F P 48

Type

ator

J7 F ICH E 2M M

PACKAGE MECHANICAL DATA
48 PINS - PLASTIC PACKAGE

48 37

1

e

36

E3

E1

TSA1002

A

A2

A1

0,10 mm
.004 inch

SEATING PLANE

B

E

12

13 24

D3

25

c

D1

D

L1

L

0,25 mm
.010 inch

K

Millimeters Inches

Dim.

Min. Typ. Max. Min. Typ. Max.

A 1.60 0.063
A1 0.05 0.15 0.002 0.006
A2 1.35 1.40 1.45 0.053 0.055 0.057

B 0.17 0.22 0.27 0.007 0.009 0.011

C 0.09 0.20 0.004 0.008

D 9.00 0.354
D1 7.00 0.276
D3 5.50 0.216

e 0.50 0.0197

E 9.00 0.354
E1 7.00 0.276
E3 5.50 0.216

L 0.45 0.60 0.75 0.018 0.024 0.030

L1 1.00 0.039

K 0° (min.), 7° (max.)

Information furnished is bel ieved to be accurate and reliable. However, STMicroe lectronics assumes no responsibility for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from
its use. No li cense is granted by imp lica tion or otherwise under any patent or patent rig hts of STMicroelectronics. Specificat ions
mentioned in this publication ar e subject to change without notice. This publication supersedes and replaces all information
previously supplied. S TMicroelectronics products are not authorized for use as critica l components in life suppo rt devices or
systems without express written approval of STMicroelectronics.

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19/19