ST TSA1002 User Manual

查询TSA1002供应商

TSA1002

10-BIT, 50MSPS, 50mW A/D CONVERTER

■ 10-bit A/D converter in deep submicron

CMOS technology

■ Single supply voltage: 2.5V

■ Input range: 2Vpp differential

■ 50Msps sampling frequency

■ Ultra low power consumption: 50mW @

50Msps

■ ENOB=9.4 @ Fs=50Msps, Fin=15MHz

■ SFDR typically up to 72dB @ Fs=50Msps,

Fin=5MHz

■ Built-in reference voltage with external bias

capability

■ STMicroelectronics 8, 10, 12 and 14-bits ADC

pinout compatibility

DESCRIPTION

The TSA1002 is a 10-bit, 50Msps sampling frequency Analog to Digital converter using a CMOS technology combining high performances and very low power consumption. The TSA1002 is based on a pipeline structure and digital error correction to provide excellent static linearity and guarantee 9.4 effective bits at Fs=50Msps, and Fin=15MHz . A voltage reference is int egrated in the circuit to simplify the design and minimize external components. It is nevertheless possible to use the circuit with an external reference. Especially designed for high speed, low power applications, the TSA1002 only dissipates 50m W at 50Msps. A tri-state capability, available on the output buffers, enables to address several slave ADCs by a unique master. The output data can be coded into two d ifferent formats. A Data Ready signal is raised as the data is valid on the output and can be used for synchronization purposes. The TSA1002 is available in commercial (0 to

+70°C) and extended (-40 t o +85°C) temperat ure range, in a small 48 pins TQFP package.

ORDER CODE

Part Number

TSA1002CF 0°C to +70°C TQFP48 Tray SA1002C TSA1002CFT 0°C to +70°C TQFP48 Tape & Reel SA1002C TSA1002IF -40°C to +85°C TQFP48 Tray SA1002I TSA1002IFT -40°C to +85°C TQFP48 Tape & Reel SA1002I EVAL1002/AA Evaluation board

Temperature

Range

Package Conditioning Marking

PIN CONNECTIONS (top view)

AGND

index

corner

IPOL

VREFP

VREFM

AGND

VIN

AGND

VINB AGND INCM

AGND AVCC AVCC

AVCC

DFSB

4748 44 43 42 41 40 39 38

46 45

1 2

3 4

5 6

7 8

9 10 11 12

13 14 15 16 17 18 19 20 21 22

DVCC

TSA1002

CLK

DGND

OEB

DGND

VCCB

GNDB

VCCB

D0 (LSB)

33 32

D3 D4

27 26

23 24

GNDB

VCCBNCOR

D9 (MSB)

PACKAGE

7 × 7 mm TQFP48

APPLICATIONS

■ Medical imaging and ultrasound

■ Portable instrumentation

■ Cable Modem Receivers

■ High resolution fax and scanners

■ High speed DSP interface

October 2000

1/19

TSA1002

ABSOLUTE MAXIMUM RATINGS

Symbol Parameter Values Unit

AVCC DVCC VCCB

Analog Supply voltage Digital Supply voltage Digital buffer Supply voltage

IDout Digital output current -100 to 100 mA

Tstg Storage temperature +150 °C

Electrical Static Discharge

ESD

- HBM

- CDM-JEDEC Standard

1) All voltages values, e xcept differential voltage, are with respect to network g round terminal. The m agnitude of i nput and output volt ages must neve r exceed -0.3V or VCC+0V

OPERATING CONDITIONS

Symbol Parameter Test conditions Min Typ Max Unit

AVCC Analog Supply voltage 2.25 2.5 2.7 V DVCC Digital Supply voltage 2.25 2.5 2.7 V VCCB Digital buffer Supply voltage 2.25 2.5 2.7 V

VREFP Forced top reference voltage 1.16 - AVCC V

VREFM Forced bottom reference voltage 0 0 0.5

0 to 3.3 V 0 to 3.3 V 0 to 3.3 V

1.5

BLOCK DIAGRAM

VIN

INCM

VINB

CLK

+2.5V

Timing

GND

stage 1 2

stage

stage n

Sequencer-ph as e shifting

Digital data correction

Referen ce

Buffers

VREFP

circuit

GNDA

IPOL

VREFM

DFSB OEB

DR DO

2/19

PIN CONNECTIONS (top view)

index

corner

IPOL

VREFP

AGND

VIN

AGND

VINB AGND INCM

AGND AVCC

3 4

5 6

7 8

9 10 11 12

VREFM

AGND

AVCC

DFSB

OEB

4748 44 43 42 41 40 39 38

46 45

VCCB

GNDB

TSA1002

13 14 15 16 17 18 19 20 21 22

DVCC

CLK

DGND

DVCC

DGND

GNDB

VCCB

23 24

VCCBNCOR

D9 (MSB)

36 35

34 33 32 31 30 29 28 27

26 25

TSA1002

NC NC NC

D0 (LSB) D1 D2 D3

D4 D5 D6

D7 D8AVCC

PIN DESCRIPTION

Pin No Name Description Observation Pin No Name Description Observation

1 IPOL Analog bias current input 25 D8 Digital ou tput CMOS output (2.5V) 2 VREFP Top voltage reference 1V 26 D7 Digita l output CMOS output (2.5V) 3 VREFM Bottom voltage reference 0V 27 D6 Digital output CMOS output (2.5V) 4 AGND Analog ground 0V 28 D5 Digital output CMOS output (2.5V) 5 VIN Analog input 1Vpp 29 D4 Digital output CMOS output (2.5V) 6 AGND Analog ground 0V 30 D3 Digital output CMOS output (2.5V) 7 VINB Inverted analog input 1Vpp 31 D2 Digital output CMOS output (2.5V) 8 AGND Analog ground 0V 32 D1 Digital output CMOS output (2.5V)

9 INCM Input common mode 0.5V 33 D0(LSB) Least Significant Bit output CMOS output (2.5V) 10 AGND Analog ground 0V 34 NC Non connected 1 1 AVCC Analog p ow er supply 2.5V 35 NC Non c onnected 12 AVCC Analog power supply 2.5V 36 NC Non connected 13 DVCC Digital power s upply 2.5V 37 NC Non connected 14 DVCC Digital power supply 2.5V 38 DR Data Ready output CMOS out put (2.5V) 15 DGND Digital ground 0V 39 VCCB Digital Buffer power supply 2.5V 16 CLK Clock input 2.5V compatible CMOS input 40 GNDB Digital Buffer ground 0V 17 DGND Digital ground 0V 41 VCCB Digital Buffer power supply 2.5V 18 NC Non connected 42 NC Non connected 19 DGN D Digita l ground 0V 43 NC Non connected 20 GND B Digital buffer ground 0V 44 OEB Output Enable i nput 2.5V compatible CMOS input 21 GNDB Digital buffer gro und 0V 45 DFSB Data Format Se lect input 2.5V compa tible CMOS inpu t 22 VCCB Digital buffer power supply 2.5V 46 AVCC Analog power supply 2.5V 23 OR Out Of Range output CMOS output (2.5V) 47 AVCC Analog power supply 2.5V 24 D9(MSB) Most Significant Bit output CMOS output (2.5V) 48 AGND Analog ground 0V

3/19

TSA1002

ELECTRICAL CHARACTERISTICS

AVCC = DVCC = VCCB = 2.5V, Fs= 40Msps,Fin= 1MHz, Vin@ -1.0dBFS, VREFM= 0V

Tamb = 25°C (unless otherwise specified)

TIMING CHARACTERISTICS

Symbol Parameter Test conditions Min Typ Max Unit

FS Sampling Frequency 0.5 50 Msps

DC Clock Duty Cycle 45 50 55 % TC1 Clock pulse width (high) 9 10 ns TC2 Clock pulse width (low) 9 10 ns

Tod

Data Output Delay (Fall of Clock to Data Valid)

Tpd Data Pipeline delay 6.5 cycles

Ton

Toff

Falling edge of OEB to digital output valid data

Rising edge of OEB to digital output tri-state

10pF load capacitance

5ns

1ns

TIMING DIAGRAM

N-1

CLK

OEB

Tod

DATA

OUT

N-8

N+4

N+3

N+2

N-7

N+1

N-6

N-5

6.5 clk cycles

N-4

N-3

Toff

N+5

N-2

N+6

N+7

N+8

Ton

N+1

HZ state

4/19

TSA1002

CONDITIONS

AVCC = DVCC = VCCB = 2.5V, Fs= 40Msps,Fin= 1MHz, Vin@ -1.0dBFS, VREFM= 0V

Tamb = 25°C (unless otherwise specified)

ANALOG INPUTS

Symbol Parameter Test conditions Min Typ Max Unit

VIN-VINB Full scale refere nce voltag e 2.0 Vpp

Cin Input capacitance 7.0 pF

BW Analog Input Bandwidth Vin@ Full scale, FS=50Msps 100 MHz

ERB

1) See parameters definiti on for more in formation

Effective Resolution Bandwidth

REFERENCE VOLTAGE

Symbol Parameter Test conditions Min Typ Max Unit

60 MHz

VREFP Top internal reference voltage

Tmin= -40°C to Tmax= 85°C

0.88 1.16 V

1.20 1.27 1.35 V

0.91 1.03 1.14 V

Vpol Analog bias voltage

Tmin= -40°C to Tmax= 85°C

1.18 1.36 V

Ipol Analog bias current Normal operating mode 50 70 100 µA Ipol Analog bias current Shutdown mode 0 µA

0.47 0.57 0.68 V

VINCM Input common mode voltage

Tmin= -40°C to Tmax= 85°C

1) No t f ul l y tested over the temperat ure range. Gua ranted by sam pl i ng.

0.46 0.66 V

5/19

TSA1002

CONDITIONS

AVCC = DVCC = VCCB = 2.5V, Fs= 40Msps,Fin= 1MHz, Vin@ -1.0dBFS, VREFP=1V, VREFM= 0V

Tamb = 25°C (unless otherwise specified)

POWER CONSUMPTION

Symbol Parameter Test conditions Min Typ Max Unit

ICCA Analog Supply current

Tmin= -40°C to Tmax= 85°C

ICCD Digital Supply Current

Tmin= -40°C to Tmax= 85°C

ICCB Digital Buffer Supply Current

Tmin= -40°C to Tmax= 85°C

ICCBZ

PdZ

Rthja

1) Rp ol = 18KΩ. Equivalent load: Rload= 470Ω and Cload= 6pF

2) No t f ul l y t ested over the temperature range. Gua ranted by sam pling.

Digital Buffer Supply Current in High Impedance Mode

Power consumption in normal

operation mode Power consumption in High

Impedance mode Junction-ambient thermal resis-

tor (TQFP48)

Tmin= -40°C to Tmax= 85°C

15.6 18 mA

21 mA

1.3 2 mA 2mA

2.5 5 mA 5mA

40 100 µA 48 60 mW

62 mW

43 48 mW

80 °C/W

DIGITAL INPUTS AND OUTPUTS

Symbol Parameter Test conditions Min Typ Max Unit

Digital inputs

VIL Logic "0" voltage 0.8 V

VIH Logic "1" voltage 2.0 V

Digital Outputs

VOL Logic "0" voltage Iol=10µA 0.4 V

VOH Logic "1" voltage Ioh=-10µA 2.4 V

IOZ High Impedance leakage current OEB set to VIH -1.5 1.5 µA

Output Load Capacitance 15 pF

ACCURACY

Symbol Parameter Test conditions Min Typ Max Unit

OE Offset Error

DNL Differential Non Linearity

INL Integral Non Linearity

Monotonicity and no missing

codes

6/19

Fin= 2MHz , VIN@+1dBF S

Fin= 2MHz , VIN@+1dBF S Fin= 2MHz , VIN@+1dBF S

-5 ±0.2 +5 %

-0.7 ±0.2 +0.7 LSB

-0.8 ±0.3 +0.8 LSB

Guaranted

+ 13 hidden pages