The TS982 is a dual operational amplifier able to
drive 200 mA down to voltages as low as 2.7 V.
The SO-8 exposed-pad package allows high
current output at high ambient temperatures
making it a reliable solution for automotive and
industrial applications.
DW
SO-8 exposed-pad
(Plastic micropackage)
Pin connections (top view)
Output1
Output1
1
1
2
Inverting Input1Output2
Inverting Input1Output2
Non Inverting Input1
Non Inverting Input1
This pad can be connected to a (-Vcc) copper area on the PCB
This pad can be connected to a (-Vcc) copper area on the PCB
2
-
-
+
+
3
3
VCC -
VCC -
4
4
Cross Section View Showing Exposed-Pad
Cross Section View Showing Exposed-Pad
VCC +
VCC +
8
8
7
7
Inverting Input2
Inverting Input2
6
6
-
-
+
+
Non Inverting Input2
Non Inverting Input2
5
5
The TS982 is stable with a unity gain.
June 2008 Rev 61/20
www.st.com
20
ContentsTS982
Contents
1Absolute maximum ratings and operating conditions . . . . . . . . . . . . . 3
TS982Absolute maximum ratings and operating conditions
1 Absolute maximum ratings and operating conditions
Table 1.Absolute maximum ratings (AMR)
SymbolParameterValueUnit
V
T
T
R
R
CC
V
oper
stg
T
thja
thjc
in
j
Supply voltage
Input voltage -0.3 V to V
Operating free-air temperature range-40 to + 125°C
Storage temperature-65 to +150°C
Maximum junction temperature150°C
Thermal resistance junction to ambient
Thermal resistance junction to case10°C/W
Human body model (HBM)l
ESD
Charged device model (CDM)
Machine model (MM)
Latch-upLatch-up immunity (all pins)200mA
Lead temperature (soldering, 10sec)250°C
Output short-circuit durationsee note
1. All voltage values are measured with respect to the ground pin.
2. With two sides, two-plane PCB following the EIA/JEDEC JESD51-7 standard.
3. Human body model: A 100 pF capacitor is charged to the specified voltage, then discharged through a
1.5 kΩ resistor between two pins of the device. This is done for all couples of connected pin combinations
while the other pins are floating.
4. Charged device model: all pins and the package are charged together to the specified voltage and then
discharged directly to the ground through only one pin. This is done for all pins.
5. Machine model: A 200pF capacitor is charged to the specified voltage, then discharged directly between
two pins of the device with no external series resistor (internal resistor < 5 Ω). This is done for all couples of
connected pin combinations while the other pins are floating.
6. Short-circuits can cause excessive heating. Destructive dissipation can result from a short-circuit on one or
two amplifiers simultaneously.
Table 2.Operating conditions
(1)
(5)
(3)
(4)
(2)
6V
+0.3 V V
CC
45°C/W
2kV
1.5kV
200V
(6)
SymbolParameterValueUnit
V
CC
V
icm
Supply voltage2.5 to 5.5V
Common mode input voltage rangeGND to V
CC
V
Load capacitor
C
L
R
< 100 Ω
L
> 100 Ω
R
L
400
100
pF
3/20
Electrical characteristicsTS982
2 Electrical characteristics
Table 3.Electrical characteristics for V
(unless otherwise specified)
SymbolParameterMin.Typ.Max.Unit
= +5 V, V
CC+
= 0 V, and T
CC-
amb
= 25° C
V
ΔV
I
CC
I
I
Supply current - No input signal, no load
< Top < T
T
min
Input offset voltage (V
IO
IO
< Top < T
T
min
Input offset voltage drift2µV/°C
Input bias current - V
IB
T
min
< Top < T
max
max
max
icm
= VCC/2
icm
= VCC/2)
Input offset current
IO
V
icm
= VCC/2
5.57.2
7.2
15
7
200500
500
10nA
mA
mV
nA
High level output voltage
RL = 16Ω
R
V
OH
= 16Ω, T
L
I
= 200mA
out
VCC= 4.75V, T = 125° C, I
< Top < T
min
max
= 25mA4.3V
out
4.2
4
4.4
4
V
Low level output voltage
0.5510.65
0.95
95dB
V
V
OL
A
VD
GBP
RL = 16Ω
R
= 16Ω, T
L
I
= 200mA
out
V
= 4.75V, T = 125°C, I
CC
< Top < T
min
Large signal voltage gain
= 16Ω
R
L
Gain bandwidth product
R
= 32Ω
L
max
= 25mA0.45V
out
1.352.2MHz
CMRCommon mode rejection ratio80dB
SVRSupply voltage rejection ratio95dB
SR
Φ
G
e
Crosstalk
Slew rate, unity gain inverting
= 16Ω
R
L
Phase margin at unit gain
m
= 16Ω, CL = 400pF
R
L
Gain margin
m
= 16Ω, CL = 400pF
R
L
Equivalent input noise voltage
n
F = 1kHz
Channel separation
= 16Ω, F = 1kHz
R
L
4/20
0.450.7V/µs
56degrees
18dB
nV
17
----------- Hz
100dB
TS982Electrical characteristics
Table 4.Electrical characteristics for V
(unless otherwise specified)
Symbol
Table 5.Parameter
(1)
CC+
= +3.3 V, V
= 0 V, and T
CC-
amb
= 25° C
Min.Typ.Max.Unit
ΔV
I
V
CC
I
I
Supply current - No input signal, no load
T
< Top < T
min
Input offset voltage (V
IO
T
< Top < T
min
Input offset voltage drift2µV/°C
IO
Input bias current - V
IB
T
min
< Top < T
max
max
max
= VCC/2)
icm
= VCC/2
icm
Input offset current
IO
V
icm
= VCC/2
5.37.2
7.2
15
7
200500
500
10nA
mA
mV
nA
High level output voltage
= 16Ω
R
V
OH
L
R
= 16Ω, T
L
I
= 200 mA
out
< Top < T
min
max
2.68
2.64
2.85
2.3
V
Low level output voltage
V
OL
A
VD
GBP
= 16Ω
R
L
R
= 16Ω, T
L
I
= 200mA
out
< Top < T
min
Large signal voltage gain
RL = 16Ω
Gain bandwidth product
R
= 32Ω
L
0.45
max
92dB
1.22MHz
0.52
0.65
V
1
CMRCommon mode rejection ratio75dB
SVRSupply voltage rejection ratio95dB
SR
Φ
G
e
Crosstalk
1. All electrical values are guaranteed by correlation with measurements at 2.7 V and 5 V.
Slew rate, unity gain inverting
= 16Ω
R
L
Phase margin at unit gain
m
= 16Ω, CL = 400pF
R
L
Gain margin
m
= 16Ω, CL = 400pF
R
L
Equivalent input noise voltage
n
F = 1kHz
Channel separation
= 16Ω, F = 1kHz
R
L
0.450.7V/µs
57degrees
16dB
17
100dB
5/20
nV
----------- Hz
Electrical characteristicsTS982
Table 6.Electrical characteristics for VCC = +2.7 V, V
= 0 V, and T
CC-
amb
= 25° C
(unless otherwise specified)
SymbolParameterMin.Typ.Max.Unit
I
V
ΔV
CC
I
IB
I
IO
Supply current - No input signal, no load
T
< Top < T
min
Input offset voltage (V
IO
T
< Top < T
min
Input offset voltage drift2µV/°C
IO
Input bias current - V
< Top < T
T
min
ma
max
max
= VCC/2)
icm
= VCC/2
icm
Input offset current
= VCC/2
V
icm
5.36.4
6.4
15
7
200500
500
10nA
mA
mV
nA
High level output voltage
= 16Ω
R
V
OH
L
R
= 16Ω, T
L
I
= 20 mA
out
< Top < T
min
max
2.3
2.25
2.85
2.3
V
Low level output voltage
V
OL
A
VD
GBP
= 16Ω
R
L
R
= 16Ω, T
L
I
= 200mA
out
< Top < T
min
Large signal voltage gain
RL = 16Ω
Gain bandwidth product
R
= 32Ω
L
max
1.22MHz
0.4510.37
0.42
92dB
V
CMRCom mo n mo de r ejection ratio75dB
SVRSupply voltage rejection ratio95dB
SR
Φ
G
e
Crosstalk
Slew rate, unity gain inverting
= 16Ω
R
L
Phase margin at unit gain
m
= 16Ω, CL = 400pF
R
L
Gain margin
m
= 16 Ω, CL = 400pF
R
L
Equivalent input noise voltage
n
F = 1kHz
Channel separation
RL = 16Ω, F = 1kHz
6/20
0.450.7V/µs
57degrees
16dB
nV
17
----------- Hz
100dB
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