ST TS4621E User Manual

TS4621E

High-performance class-G stereo headphone amplifier

with I

2

C volume control

Features

■ Power supply range: 2.3 V to 4.8 V

■ 0.6 mA/channel quiescent current

■ 2.1 mA current consumption with

100 µW/channel (10 dB crest factor)

■ 0.006% typical THD+N at 1 kHz

■ 100 dB typical PSRR at 217 Hz

■ 100 dB of SNR A-weighted at G = 0 dB

■ Zero pop and click

2

■ I

C interface for volume control

■ Digital volume control range from -60 dB to

+4 dB

■ Independent right and left channel shutdown

control

■ Integrated high-efficiency buck converter

■ Low software standby current: 5 µA max

■ Output-coupling capacitors removed

■ Thermal shutdown and short-circuit protection

■ Flip-chip package: 1.65 mm x 1.65 mm,

400 µm pitch, 16 bumps

Applications

■ Cellular phones, smart phones

■ Mobile internet devices

■ PMP/MP3 players

Description

The TS4621E is a class-G stereo headphone
driver dedicated to high audio performance, high
power efficiency and space-constrained
applications.

It is based on the core technology of a low power
dissipation amplifier combined with a high­efficiency buck converter for supplying this
amplifier.

TS4621EIJT - flip-chip

Pinout (top view)

SCL

SCL

SDA

PVSS

PVSS

C1

C1

AVDD

AVDD

SDA

C2

C2

AGND

AGND

SW

SW

D

D

C

C

B

B

A

A

INR-

INR-

VOUTR

VOUTR

INR+

INR+

CMS

CMS

HPVDD

INL+

HPVDD

INL+

VOUTL

VOUTL

INL-

INL-

4321

4321

Balls are underneath

When powered by a battery, the buck converter
generates the appropriate voltage to the amplifier
depending on the amplitude of the audio signal to
supply the headsets. It achieves a total 2.1 mA
current consumption at 100 µW output power
(10 dB crest factor).

THD+N is 0.02% maximum at 1 kHz and PSRR is
100 dB at 217 Hz, which ensures a high audio
quality of the device in a wide range of
environments.

The traditionally bulky output coupling capacitors
can be removed.

A dedicated common-mode sense pin removes
parasitic ground noise.

The TS4621E is designed to be used with an
output serial resistor. It ensures unconditional
stability over a wide range of capacitive loads.

The TS4621E is packaged in a tiny 16-bump
flip-chip package with a pitch of 400 µm.

September 2011 Doc ID 022201 Rev 1 1/32

www.st.com

32

Contents TS4621E

Contents

1 Absolute maximum ratings and operating conditions . . . . . . . . . . . . . 3

2 Typical application schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

4 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

4.1 I2C bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

4.1.1 I²C bus operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

4.1.2 Control register CR2 - address 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4.1.3 Control register CR1 - address 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4.2 Wake-up and standby time definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

4.3 Common mode sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

5 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

6 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

7 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

2/32 Doc ID 022201 Rev 1

TS4621E Absolute maximum ratings and operating conditions

1 Absolute maximum ratings and operating conditions

Table 1. Absolute maximum ratings

Symbol Parameter Value Unit

V

V

in+,Vin-

T

R

P

ESD

CC

stg

T

thja

Supply voltage

Input voltage referred to ground +/- 1.2 V

Storage temperature -65 to +150 °C

Maximum junction temperature

j

Thermal resistance junction to ambient

Power dissipation Internally limited

d

Human body model (HBM)

All pins
VOUTR, VOUTL vs. AGND

Machine model (MM), min. value

Charge device model (CDM)

All pins
VOUTR, VOUTL

IEC61000-4-2 level 4, contact
IEC61000-4-2 level 4, air discharge

(1)

during 1ms.

(5)

(7)

(2)

(6)

(7)

(3)

5.5 V

150 °C

200 °C/W

(4)

2
4

100 V

500
750

+/- 8

+/- 15

kV

V

kV

Latch-up Latch-up immunity 200 mA

Lead temperature (soldering, 10 sec) 260 °C

1. All voltage values are measured with respect to the ground pin.

2. Thermal shutdown is activated when maximum junction temperature is reached.

3. The device is protected from over-temperature by a thermal shutdown mechanism, active at 150° C.

4. Exceeding the power derating curves for long periods may provoke abnormal operation.

5. Human body model: a 100 pF capacitor is charged to the specified voltage, then discharged through a

1.5 kΩ resistor between two pins of the device. This is done for all couples of connected pin combinations
while the other pins are floating.

6. Machine model: a 200 pF capacitor is charged to the specified voltage, then discharged directly between
two pins of the device with no external series resistor (internal resistor < 5 Ω). This is done for all couples of
connected pin combinations while the other pins are floating.

7. The measurement is performed on an evaluation board, with ESD protection EMIF02-AV01F3.

Doc ID 022201 Rev 1 3/32

Absolute maximum ratings and operating conditions TS4621E

Table 2. Operating conditions

Symbol Parameter Value Unit

V

CC

Supply voltage 2.3 to 4.8 V

Buck DC output voltages

HPVDD

High rail voltage
Low rail voltage

1.9

1.2

SDA, SCL Input voltage range GND to V

T

R

R

C

oper

thja

L

L

Load resistor ≥ 16 Ω

Load capacitor
Serial resistor of 12 Ω minimum, R

≥ 16 Ω 0.8 to 100

L

Operating free air temperature range -40 to +85 °C

Flip-chip thermal resistance junction to ambient 90 °C/W

V

cc

V

nF

4/32 Doc ID 022201 Rev 1

TS4621E Typical application schematics

2 Typical application schematics

Figure 1. Typical application schematics for the TS4621E

Negative left in put

Positive left input

Negative rig ht input

Positive right input

I²C bus

Cin

2.2 uF

Cin

2.2 uF

Cin

2.2 uF

Cin

2.2 uF

InL+

InR-

SDA

SCL

InL-

InR+

I2C

Cs

2.2 uF

PVss

Css

2.2 uF

-

+

+

-

Negative

supply

AVdd

Vbat

detector

Positive

supply

Level

detector

Level

C12

2.2 uF

Sw

3.3 uH

HpVdd

VoutL

CMS

VoutR

AGndC1 C2

L1

Ct
10 uF

Rout

12 ohms min.

Rout

12 ohms min.

Cout

0.8 nF min.

3

J1

2

1

Cout

0.8 nF min.

Table 3. TS4621E pin description

Pin number Pin name Pin definition

A1 SW Switching node of the buck converter

A2 AVDD Analog supply voltage, connect to battery

A3 VOUTL Output signal for left audio channel

A4 INL- Negative input signal for left audio channel

B1 AGND Device ground

B2 C1 Flying capacitor terminal for internal negative supply generator

B3 HPVDD Buck converter output, power supply for amplifier

B4 INL+ Positive input signal for left audio channel

C1 C2 Flying capacitor terminal for internal negative supply generator

C2 PVSS Negative supply generator output

C3 CMS

Common mode sense, to be connected as close as possible to the
ground of headphone/line out plug

C4 INR+ Positive input signal for right audio channel

D1 SDA I²C data signal, up to V

D2 SCL I²C clock signal, up to V

tolerant input

CC

tolerant input

CC

D3 VOUTR Output signal for right audio channel

D4 INR- Negative input signal for right audio channel

AM06119

Doc ID 022201 Rev 1 5/32

Typical application schematics TS4621E

Table 4. TS4621E component description

Component Value Description

Cs 2.2 µF

C12 2.2 µF

C

SS

C

in

C

out

R

out

2.2 µF

Cin

------------------------=

2π ZinFc

0.8 to 100 nF

12 Ω min.

L1 3.3 µH

Decoupling capacitors for V

. A 2.2 µF capacitor is sufficient for proper

CC

decoupling of the TS4621E. An X5R dielectric and 10 V rating voltage is
recommended to minimize ΔC/ΔV when V

CC

=4.8V.

Must be placed as close as possible to the TS4621E to minimize parasitic
inductance and resistance.

Capacitor for internal negative power supply operation. An X5R dielectric and

6.3 V rating voltage is recommended to minimize ΔC/ΔV when
HPVDD = 1.9 V.

Must be placed as close as possible to the TS4621E to minimize parasitic
inductance and resistance.

Filtering capacitor for internal negative power supply. An X5R dielectric and

6.3 V rating voltage is recommended to minimize ΔC/ΔV when
HPVDD = 1.9 V.

1

Input coupling capacitor that forms with Zin/2 a first-order high-pass filter with
a -3 dB cutoff frequency FC. For example, at maximum gain G = 4 dB,
Zin = 12.5 kΩ, C

= 2.2 µF, therefore FC = 6 Hz.

in

Output capacitor of 0.8 nF minimum to 100 nF maximum. This capacitor is
mandatory for operation of the TS4621E.

Output resistor in-series with the TS4621E output. This 12 Ω minimum resistor
is mandatory for operation of the TS4621E.

Inductor for the buck convertor.
References of inductors:

FDK: MIPSZ2012D3R3 (DC resistance = 0.19 Ω, rated current = 0.8 A)
Murata: LQM2MPN3R3G0 (DC resistance = 0.12 Ω, rated current = 1.2 A)

Tank capacitor for internal buck convertor. An X5R dielectric and 6.3 V rating

C

t

10 µF

voltage is recommended to minimize ΔC/ΔV when HPVDD = 1.9 V.
ESR of the C

capacitor must be as low as possible to obtain the best buck

t

efficiency.

6/32 Doc ID 022201 Rev 1

TS4621E Electrical characteristics

3 Electrical characteristics

Table 5. Electrical characteristics of the I²C interface

for V

= +3.6 V, AGND = 0 V, T

CC

= 25°C (unless otherwise specified)

amb

Symbol Parameter Min. Typ. Max. Unit

V

V

V

Table 6. Electrical characteristics of the amplifier

Low level input voltage on SDA, SCL pins 0.6 V

IL

High level input voltage on SDA, SCL pins 1.2 V

IH

Low level output voltage, SDA pin, I

OL

Input current on SDA, SCL 10 µA

I

in

for V

= +3.6 V, AGND = 0 V, RL= 32 Ω + 15 Ω, T

CC

= 3mA 0.4 V

sink

V

SDA SCL,

------------------------------ -- -

600k Ω

= 25° C

amb

(unless otherwise specified)

Symbol Parameter Min. Typ. Max. Unit

I

I

STBY

V

V

V

Quiescent supply current, no input signal, both channels

CC

enabled

Supply current, with input modulation, both channels enabled,
HPVDD = 1.2 V, output power per channel, F=1kHz

Pout = 100 µW at 3 dB crest factor

I

s

Pout = 500 µW at 3 dB crest factor
Pout = 1mW at 3dB crest factor
Pout = 100 µW at 10 dB crest factor
Pout = 500 µW at 10 dB crest factor
Pout = 1 mW at 10 dB crest factor

Standby current, no input signal, I²C CR1 = 01h

= 0 V, V

V

SDA

Input differential voltage range

in

SCL

= 0 V

(1)

Output offset voltage

oo

No input signal

Maximum output voltage, in-phase signals

= 16 Ω, THD+N = 1% max, f = 1 kHz

R

L

= 47 Ω, THD+N = 1% max, f = 1 kHz

out

R

L

RL = 10 kΩ, Rs = 15 Ω, CL = 1 nF, THD+N = 1% max,
f = 1 kHz

1.2 1.5 mA

2.3

3.7

4.7

3.5
5

6.5

2.1

3.1

3.9

0.6 5 µA

1V

-500 +500 µV

0.6

1.0

1.0

0.8

1.1

1.3

mA

V

rms

rms

THD+N

PSRR

Total harmonic distortion + noise, G = 0 dB

= 700 mVrms, F = 1 kHz

V

out

= 700 mVrms, 20 Hz < F < 20 kHz

V

out

(1)

, V

Power supply rejection ratio

= 200 mVpp, grounded

ripple

inputs

F = 217 Hz, G = 0 dB, R
F = 10 kHz, G = 0 dB, R

≥16 Ω

L

≥16 Ω

L

Doc ID 022201 Rev 1 7/32

0.006

0.05

90 100

70

0.02 %

dB

Electrical characteristics TS4621E

Table 6. Electrical characteristics of the amplifier

for V

= +3.6 V, AGND = 0 V, RL= 32 Ω + 15 Ω, T

CC

amb

= 25° C

(unless otherwise specified) (continued)

Symbol Parameter Min. Typ. Max. Unit

Common mode rejection ratio

CMRR

F = 1 kHz, G = 0 dB, V
F = 20 Hz to 20 kHz, G = 0 dB, Vic = 200 mV

= 200 mV

ic

pp

65

pp

45

Channel separation

Crosstalk

SNR

ONoise

= 32 Ω + 15 Ω , G = 0 dB, F = 1 kHz, Po = 10 mW

R

L

= 10 kΩ, G = 0 dB, F = 1 kHz, V

R

L

Signal-to-noise ratio, A-weighted, V
F = 1 kHz

(1)

out

out

= 1 V

=1 Vrms

G = +4 dB
G = +0 dB

Output noise voltage, A-weighted

(1)

G = +4 dB

, THD+N < 1%,

rms

60
80

99

100

100
110

9119µVrms

G = +0 dB

G Gain range with gain (dB) = 20 x log[(V

Mute InL/R+ - InL/R- = 1 V

rms

L/R)/(InL/R+ - InL/R-)] -60 +4 dB

out

- Gain step size error -0.5 +0.5

-80 dB

dB

dB

dB

step-

size

- Gain error (G = +4 dB) -0.45 +0.42 dB

Z

Differential input impedance 25 34 kΩ

in

Input impedance during wake-up phase (referred to ground) 2 kΩ

Output impedance when CR1 = 00h (negative supply is ON and
amplifier output stages are OFF)

Z

out

F < 40 kHz
F = 6 MHz
F = 36 MHz

t

t

stby

t

t

1. Guaranteed by design and parameter correlation.

2. Refer to the application information in Section 4.3 on page 27.

Wake-up time

wu

Standby time 100 µs

Attack time. Setup time between low rail buck voltage and high

atk

rail buck voltage

Decay time 50 ms

dcy

(2)

(1)

10

500

75

12 16 ms

100 µs

kΩ

Ω
Ω

8/32 Doc ID 022201 Rev 1

TS4621E Electrical characteristics

Table 7. Timing characteristics of the I²C interface for I²C interface signals over

recommended operating conditions (unless otherwise specified)

Symbol Parameter Min. Typ. Max. Unit

f

SCL

t

d(H)

t

d(L)

t

t

t

t

t

Frequency, SCL 400 kHz

Pulse duration, SCL high 0.6 µs

Pulse duration, SCL low 1.3 µs

Setup time, SDA to SCL 100 ns

st1

Hold time, SCL to SDA 0 ns

h1

Bus free time between stop and start condition 1.3 µs

t

f

Setup time, SCL to start condition 0.6 µs

st2

Hold time, start condition to SCL 0.6 µs

h2

Setup time, SCL to stop condition 0.6 µs

st3

Figure 2. SCL and SDA timing diagram

t

d(H)

t

SCL

SDA

d(L)

t

st1

t

h1

Figure 3. Start and stop condition timing diagram

SCL

t

t

st2

h2

SDA

Start condition Stop condition

AM06113

t

f

t

st3

AM06114

Doc ID 022201 Rev 1 9/32

Electrical characteristics TS4621E

No load; No input Signal
SDA=SCL = 0V
Ta = 25°C

2.3 2.7 3.1 3.5 3.9 4.3 4.7

0

20

40

60

80

THD+N=10% (180°)

THD+N=10% (0°)

THD+N=1% (0°)

RL = 32Ω, F = 1kHz
BW < 30kHz, Tamb = 25°C

THD+N=1% (180°)

Output power (mW)

Power Supply Voltage Vcc (V)

Figure 4. Current consumption vs. power

(mA)

CC

Quiscent Supply Current I

supply voltage

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0.0

2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8

Power Supply Voltage Vcc (V)

No load; No input Signal
Both channels enabled
Ta = 25°C

Figure 5. Standby current consumption vs.

power supply voltage

Figure 6. Maximum output power vs. load Figure 7. Maximum output power vs. load

80

70

60

50

40

30

20

Output power (mW)

10

0

10 100 1k

VCC=4.8V

VCC=3.6V

VCC=2.3V

RL Load resistance ( )

Inputs = 0°, F = 1kHz
THD+N = 1%
Tamb = 25°C

80

70

60

50

40

30

20

Output power (mW)

10

0

10 100 1k

VCC=4.8V

VCC=3.6V

VCC=2.3V

RL Load resistance ( )

Inputs = 180°, F = 1kHz
THD+N = 1%
Tamb = 25°C

Figure 8. Maximum output power vs. power

supply voltage

RL = 16Ω, F = 1kHz

120

BW < 30kHz, Tamb = 25°C

100

80

60

40

Output power (mW)

20

0

2.3 2.7 3.1 3.5 3.9 4.3 4.7

10/32 Doc ID 022201 Rev 1

THD+N=10% (0°)

THD+N=1% (180°)

Power Supply Voltage Vcc (V)

Figure 9. Maximum output power vs. power

supply voltage

THD+N=10% (180°)

THD+N=1% (0°)