ST TMPE2401 User Manual
STMPE2401
24-bit Enhanced port expander with Keypad and PWM controller
Xpander logic
Features
■ 24 GPIOs
■ Operating voltage 1.8V
■ Hardware key pad controller (8*12 matrix ma x)
■ 3 PWM (8 bit) output for LED brightness control
and blinking
■ Interrupt output (open drain) pin
■ Configurable hotkey feature on each GPIO
■ Ul tr a-l ow St an db y- mo de cu rr ent
■ Package TFBGA - 36 pins 3.6x3.6mm, pitch
0.5mm
Description
The STMPE2401 is a GPIO (General Purpose
Input / output) port expander able to interface a
Main Digital ASIC via the two-line bidirectional
bus (I2C); separate GPIO Expander IC is often
used in Mobile-Multimedia platforms to solve the
problems of the limited amounts of GPIOs usually
available on the Digital Engine.
TFBGA
The STMPE2401 offers great flexibility as each
I/Os is configurable as input, output or specific
functions; it's able to scan a keyboard, also
provides PWM outputs for brightness control in
backlight, rotator decoder interface and GPIO.
This device has been designed very low
quiescent current, and is including a wake up
feature for each I/O, to optimize the power
consumption of the IC.
Potential application of the STMPE2401 includes
portable media player, game console, mobile
phone, smart phone
Figure 1. Device summary
Part number Package Packaging
STMPE2401TBR TFBGA36 Tape and reel
May 2007 Rev 2 1/55
www.st.com
55
Contents STMPE2401
Contents
1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.1 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.2 Pin assignment and TFBGA ball location . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.3 GPIO Pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.4 Pin mapping to TFBGA ( bottom view, balls up) . . . . . . . . . . . . . . . . . . . . . 9
3 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1 Absolute maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.1 DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.2 I/O DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.3 DC input specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.4 DC output specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.5 AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5 Register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
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STMPE2401 Contents
6 I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.1 Start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.2 Stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.3 Acknowledge bit (ACK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.4 Data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6.5 Slave device address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6.6 Memory addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6.7 Operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
7 System controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
7.1 Identification register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
7.2 System control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7.3 States of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
8 Clocking system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
8.1 Programming sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
9 Interrupt system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
9.1 Register map of interrupt system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
9.2 Interrupt control register (ICR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
9.3 Interrupt enable mask register (IER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
9.4 Interrupt status register (ISR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
9.5 Interrupt enable GPIO mask register (IEGPIOR) . . . . . . . . . . . . . . . . . . . 25
9.6 Interrupt status GPIO register (ISGPIOR) . . . . . . . . . . . . . . . . . . . . . . . . 26
9.7 Programming sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
10 GPIO controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
10.1 GPIO control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
10.2 GPIO alternate function register (GPAFR) . . . . . . . . . . . . . . . . . . . . . . . . 30
10.3 Hot key feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
10.3.1 Programming sequence for hot key . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
10.3.2 Minimum pulse width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
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Contents STMPE2401
11 PWM controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
11.1 Registers in the PWM controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
11.2 PWM control and status register (PWMCS) . . . . . . . . . . . . . . . . . . . . . . . 35
11.3 PWM instruction channel x (PWMICx) . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
12 PWM commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
13 Keypad controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
13.1 Registers in keypad controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
13.2 KPC_col register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
13.3 KPC_row_msb register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
13.4 KPC_row_lsb register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
13.5 KPC_ctrl_msb register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
13.6 KPC_ctrl_lsb register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
13.7 Data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
13.7.1 Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
13.7.2 Using the keypad controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
14 Rotator controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
14.1 Rotator_Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
14.2 Rotator_Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
15 Miscellaneous features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
15.1 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
15.2 Under voltage lockout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
15.3 Clock output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
16 Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
17 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
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STMPE2401 Block diagram
1 Block diagram
Figure 1. Block diagram
5/55
Pin settings STMPE2401
2 Pin settings
2.1 Pin connection
Figure 2. Pin connection
TFBGA
2.2 Pin assignment and TFBGA ball location
Table 1. Pin assignment
Ball Name Type Name and function
C3 GND -
C2 KP_X0 IO GPIO
C1 Reset_N I External reset input, active LOW
B1 KP_X1 IO GPIO
A1 KP_X2 IO GPIO
B2 KP_X3 IO GPIO
A2 KP_X4 IO GPIO
B3 KP_X5 IO GPIO
A3 KP_X6 IO GPIO
C4 GND -
A4 VCC1 - 1.8V Input
6/55
STMPE2401 Pin settings
Table 1. Pin assignment
Ball Name Type Name and function
B3 KP_X7 IO GPIO
A5 KP_Y5 IO GPIO
A6 KP_Y4 IO GPIO
B5 KP_Y3 IO GPIO
B6 KP_Y2 IO GPIO
C5 KP_Y1 IO GPIO
C6 KP_Y0 IO GPIO
D3 GND -
D6 ADDR0 IO GPIO and I2C ADDR 0 (in reset)
D5 KP_Y9 A/IO GPIO
E6 KP_Y10 A/IO GPIO
F6 KP_Y11 A/IO GPIO
E5 PWM3 A/IO GPIO and I2C ADDR 1 (in reset)
F5 PWM2 A/IO GPIO
E4 PWM1 A/IO GPIO
F4 VCC2 - 1.8V Input
D4 GND -
F3 INT O Open drain interrupt output pin
E3 KP_Y8 IO GPIO
F2 KP_Y7 IO GPIO
F1 KP_Y6 IO GPIO
E2 SDATA A I2C DATA
E1 SCLK A I2C Clock
D2 XTALIN A XTAL Oscillator or External 32KHz input
D1 XTALOUT A XTAL Oscillator
7/55
Pin settings STMPE2401
2.3 GPIO Pin functions
Table 2. GPIO Pin functions
Pin N° Name
2 KP_X0 GPIO 0 Keypad input 0
4 KP_X1 GPIO 1 Keypad input 1
5 KP_X2 GPIO 2 Keypad input 2
6 KP_X3 GPIO 3 Keypad input 3
7 KP_X4 GPIO 4 Keypad input 4
8 KP_X5 GPIO 5 Keypad input 5
9 KP_X6 GPIO 6 Keypad input 6
12 KP_X7 GPIO 7 Keypad input 7
13 KP_Y5 GPIO 13 Keypad output 5
14 KP_Y4 GPIO 12 Keypad output 4
15 KP_Y3 GPIO 11 Keypad output 3
16 KP_Y2 GPIO 10 Keypad output 2
Primary
Function
Alternate Function 1 Alternate Function 2 Alternate Function 3
17 KP_Y1 GPIO 9 Keypad output 1
18 KP_Y0 GPIO 8 Keypad output 0
20 ADDR0 GPIO 15
21 KP_Y9 GPIO 18 Keypad output 9 Rotator 0
22 KP_Y10 GPIO 19 Keypad output 10 Rotator 1
23 KP_Y11 GPIO 20 Keypad output 11 Rotator 2
24 PWM3 GPIO 23 Channel 3
25 PWM2 GPIO 22 Channel 2
26 PWM1 GPIO 21 Channel 1
30 KP_Y8 GPIO 17 Keypad output 8 ClkOut
31 KP_Y7 GPIO 16 Keypad output 7
32 KP_Y6 GPIO 14 Keypad output 6
8/55
STMPE2401 Pin settings
2.4 Pin mapping to TFBGA ( bottom view, balls up)
Table 3. Pin mapping to TFBGA
ABCDEF
1 KP-X2 KP-X1 Reset_N XTALOUT SCLK KP-Y6
2 KP-X4 KP-X3 KP-X0 XTALIN SDATA KP-Y7
3 KP-X6 KP-X5 GND GND KP-Y8 INT
4 VCC KP-X7 GND GND PWM-1 VCC
5 KP-Y5 KP-Y3 KP-Y1 KP-Y9 PWM-3 PWM-2
6 KP-Y4 KP-Y2 KP-Y0 ADDR0 KP-Y10 KP-Y11
9/55
Maximum rating STMPE2401
3 Maximum rating
Stressing the device above the rating listed in the “Absolute Maximum Ratings” table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the Operating sections of
this specification is not implied. Exposure to Absolute Maximum Rating conditions for
extended periods may affect device reliability. Refer also to the STMicroelectronics SURE
Program and other relevant quality documents.
3.1 Absolute maximum rating
Table 4. Absolute maximum rating
Symbol Parameter Value Unit
V
CC
V
Input voltage on GPIO pin 2.5 V
IN
V
Input voltage on I2C pin
I2C
VESD (HBM) ESD protection on each GPIO pin 2 KV
Supply voltage 2.5 V
4.5 V
(SDATA,SCLK, INT)
3.2 Thermal data
Table 5. Thermal data
Symbol Parameter Min Typ Max Unit
R
thJA
T
A
T
J
Thermal resistance junction-ambient 100 °C/W
Operating ambient temperature -40 25 85 °C
Operating junction temperature -40 25 125 °C
10/55
STMPE2401 Electrical specification
4 Electrical specification
4.1 DC electrical characteristics
Table 6. DC electrical characteristics
Symbol Parameter Test conditions
VCC1,2 1.8V supply voltage 1.65 1.8 1.95 V
I
HIBERNATE
HIBERNATE mode
current
Min. Typ. Max.
Val ue
Unit
612uA
I
SLEEP
Icc Operating current
I
_INT Open drain output
O
V_INT Voltage level at INT pin 3.6 V
SLEEP mode current 15 50 uA
(FSM working – No
peripheral activity)
current
4.2 I/O DC electrical characteristics
The 1.8V I/O complies to the EIA/JEDEC standard JESD8-7.
Table 7. I/O DC electrical characteristic
Symbol Parameter
Vil
Vih
Vhyst Schmitt trigger hysteresis 0.10 V
Low level input voltage 0.35*Vcc
High level input voltage 0.65*Vcc
0.5 1.0 mA
4mA
Val u e
Min. Typ. Max.
= 0.63
= 1.17
Unit
V
V
4.3 DC input specification
(1.55V < VDD < 1.95V)
Table 8. DC input specification
Symbol Parameter Test conditions
Vol Low level output voltage Iol = 4mA 0.45 V
Voh High level output voltage Ioh = 4mA
Val ue
Min. Typ. Max.
Vcc - 0.45
= 1.35
11/55
Unit
V
Electrical specification STMPE2401
4.4 DC output specification
(1.55V < vdd < 1.95V)
Table 9. DC output specification
Symbol Parameter
Ipu Pull-up current Vi = 0V 15 35 65 µA
Ipd Pull-down current Vi = vdd 14 35 60 µA
Rup Equivalent pull-up resistance Vi = 0V 30 50 103.3 KΩ
Rpd Equivalent pull-down resistance Vi = vdd 32.5 50 110.7 KΩ
Test
conditions
Min. Typ. Max.
Val ue
Unit
Note: Pull-up and Pull-down characteristics
4.5 AC characteristics
Table 10. AC characteristics
Symbol Parameter
Frequency 16 32 kHz
F
O
C
Load capacitance 27 pF
L
Min. Typ. Max.
Val ue
Unit
12/55
STMPE2401 Register map
5 Register map
All registers have the size of 8-bit. Some of the registers are composed of 2-byte to form 16bit registers. For each of the module, their registers are residing within the given address
range.
Table 11. Register map
Address Module registers Description
0x00 – 0x07
0x80 – 0x81
Clock and Power
Manager module
Clock and Power Manager register
range.
Auto-Increment
(during read/write)
Ye s
0x10 – 0x1F Interrupt Controller
module
0x30 – 0x37 PWM Controller Module PWM Controller register range Yes
0x38 – 0x3F PWM Controller register range No
0x60 – 0x67 Keypad Controller
Module
0x68 – 0x6F Keypad Controller register range No
0x70 – 0x77 Rotator Controller
Module
0x82 – 0xBF GPIO Controller Module GPIO Controller register range Yes
Interrupt Controller register range Yes
Keypad Controller register range Yes
Rotator Controller register range Yes
13/55
I2C Interface STMPE2401
6 I2C Interface
The features that are supported by the I2C interface are as below:
2
● I
C Slave device
● SDAT and SCLK operates from 1.8V to 3.3V
● Compliant to Philip I
● Supports Standard (up to 100kbps) and Fast (up to 400kbps) modes.
● 7-bit device addressing mode
● General Call
● Start/Restart/Stop
● Address up to 4 STMPE2401 devices via I
The address is selected by the state of two pins. The state of the pins will be read upon
reset and then the pins can be configured for normal operation. The pins will have a pull-up
or down to set the address. The I2C interface module allows the connected host system to
access the registers in the STMPE2401.
2
C specification version 2.1
2
C
6.1 Start condition
A Start condition is identified by a falling edge of SDATA while SCLK is stable at high state.
A Start condition must precede any data/command transfer. The device continuously
monitors for a Start condition and will not respond to any transaction unless one is
encountered.
6.2 Stop condition
A Stop condition is identified by a rising edge of SDATA while SCLK is stable at high state.
A Stop condition terminates communication between the slave device and bus master. A
read command that is followed by NoAck can be followed by a Stop condition to force the
slave device into idle mode. When the slave device is in idle mode, it is ready to receive the
2
next I
C transaction. A Stop condition at the end of a write command stops the write
operation to registers.
6.3 Acknowledge bit (ACK)
The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter
releases the SDATA after sending eight bits of data. During the ninth bit, the receiver pulls
the SDATA low to acknowledge the receipt of the eight bits of data. The receiver may leave
the SDATA in high state if it would to not acknowledge the receipt of the data.
14/55
STMPE2401 I2C Interface
6.4 Data input
The device samples the data input on SDATA on the rising edge of the SCLK. The SDATA
signal must be stable during the rising edge of SCLK and the SDATA signal must change
only when SCLK is driven low.
6.5 Slave device address
The slave device address is a 7 address, where the least significant 2-bit are programmable.
These 2-bit values will be loaded in once upon reset and after that these 2 pins no longer be
needed with the exception during General Call. Up to 4 STMPE2401 devices can be
connected on a single I
Table 12. Slave device address
ADDR 1 ADDR 0 Address
0 0 0x84
0 1 0x86
1 0 0x88
11 0x8A
2
C bus.
6.6 Memory addressing
For the bus master to communicate to the slave device, the bus master must initiate a Start
condition and followed by the slave device address. Accompanying the slave device
address, there is a Read/Write
operation.
If a match occurs on the slave device address, the corresponding device gives an
acknowledgement on the SDA during the 9
from the bus by not responding to the transaction.
bit (R/W). The bit is set to 1 for Read and 0 for Write
th
bit time. If there is no match, it deselects itself
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I2C Interface STMPE2401
6.7 Operation modes
Table 13. Operating modes
Mode Bytes Programming sequence
START, Device Address, R/W
= 0, Register Address to be read
RESTART, Device Address, R/W
If no STOP is issued, the Data Read can be continuously preformed. If the register
Read ≥1
Write ≥1
address falls within the range that allows address auto-increment, then register
address auto-increments internally after every byte of data being read. For register
address that falls within a non-incremental address range, the address will be kept
static throughout the entire read operations. Refer to the Memory Map table for the
address ranges that are auto and non-increment. An example of such a nonincrement address is FIFO.
START, Device Address, R/W
If no STOP is issued, the Data Write can be continuously performed. If the register
address falls within the range that allows address auto-increment, then register
address auto-increments internally after every byte of data being written in. For
register address that falls within a non-incremental address range, the address will
be kept static throughout the entire write operations. Refer to the Memory Map table
for the address ranges that are auto and non-increment. An example of a nonincrement address is Data Port for initializing the PWM commands.
=0, Register Address to be written, Data Write, STOP
Figure 3. Master/slave operation modes
= 1, Data Read, STOP
16/55
STMPE2401 I2C Interface
Figure 4. I2C timing
Table 14. I2C address
Symbol Parameter Min Typ Max Unit
f
SCL
t
LOW
t
HIGH
t
F
t
HD:STA
t
SU:STA
t
SU:DAT
t
HD:DAT
t
SU:STO
t
BUF
SCL clock frequency 0 400 kHz
Clock low period 1.3 µs
Clock high period 600 ns
SDA and SCL fall time 300 ns
START condition hold time
(After this period the first clock is generated)
START condition setup time
(Only relevant for a repeated start period)
600 ns
600 ns
Data setup time 100 ns
Data hold time 0 µs
STOP condition setup time 600 ns
Time the bust must be free before a new
trasmission can start
1.3 µs
17/55
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