The STEVAL-TDR006V1 is a two stage RF power
amplifier which includes a low pass output filter for
harmonics rejection specifically designed for
portable two-way UHF radio communication.
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
®
packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK is an ST trademark.
10/18 Doc ID 15623 Rev 1
STEVAL-TDR006V1Package mechanical data
6.1 PowerFLAT™ mechanical data
Table 5.PowerFLAT™ mechanical data
mminch
Dim.
Min.Typ.Max.Min.Typ.Max.
A0.901.000.0350.039
A10.020.050.0010.002
A30.240.009
AA0.150.250.350.0060.010.014
b0.430.510.580.0170.0200.023
c0.640.710.790.0250.0280.031
D5.000.197
d0.300.011
E5.000.197
E22.492.572.640.0980.1010.104
e1.270.050
f3.370.132
g0.740.03
h0.210.008
Figure 10. PowerFLAT™ package dimensions
Doc ID 15623 Rev 111/18
Package mechanical dataSTEVAL-TDR006V1
Table 6.PowerFLAT™ tape and reel dimensions
mm.inch
Dim.
Min.TypMax.Min.TypMax.
Ao5.155.255.350.120.130.13
Bo5.155.255.350.120.130.13
Ko1.01.11.20.020.020.02
Figure 11. PowerFLAT™ tape and reel
12/18 Doc ID 15623 Rev 1
STEVAL-TDR006V1Package mechanical data
6.1.1 Mounting indications
Figure 12. Standard SMD mounting
Doc ID 15623 Rev 113/18
Package mechanical dataSTEVAL-TDR006V1
6.2 Thermal pad and via design SOT-89
Thermal vias are required in the PCB layout to effectively conduct heat away from the
package. The via pattern has been designed to address thermal, power dissipation and
electrical requirements of the device.
The via pattern is based on thru-hole vias with 0.203 mm to 0.330 mm finished hole size on
a 0.5 mm to 1.2 mm grid pattern with 0.025 plating on via walls. If micro vias are used in a
design, it is suggested that the quantity of vias be increased by a 4:1 ratio to achieve similar
results.
Figure 13. Pad layout details
14/18 Doc ID 15623 Rev 1
STEVAL-TDR006V1Package mechanical data
6.2.1 Soldering profile
Figure 14 shows the recommeded solder for devices that have Pb-free terminal plating and
where a Pb-free solder is used.
Figure 14. Recommended solder profile
Figure 15 shows the recommeded solder for devices with Pb-free terminal plating used with
leaded solder, or for devices with leaded terminal plating used with a leaded solder.
Figure 15. Recommended solder profile for leaded devices
Doc ID 15623 Rev 115/18
Package mechanical dataSTEVAL-TDR006V1
Figure 16. Reel information
16/18 Doc ID 15623 Rev 1
STEVAL-TDR006V1Revision history
7 Revision history
Table 7.Document revision history
DateRevisionChanges
23-Apr-20091Initial release.
Doc ID 15623 Rev 117/18
STEVAL-TDR006V1
y
y
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