ST TDA7498L User Manual

80 watt + 80 watt dual BTL class-D audio amplifier
Features
80 W + 80 W output power at
THD = 10% with R
70 W + 70 W output power at
THD = 10% with R
Wide-range single-supply operation (14 - 36 V)
High efficiency (η = 90%)
Four selectable, fixed gain settings of
nominally 25.6 dB, 31.6 dB, 35.1 dB and
37.6 dB
Differential inputs minimize common-mode
noise
Standby and mute features
Short-circuit protection
Thermal overload protection
Externally synchronizable
L
L
CC
CC
= 32 V
= 34 V
TDA7498L
PowerSSO-36 with exposed pad up
Description
The TDA7498L is a dual BTL class-D audio amplifier with single power supply designed for home systems and active speaker applications.
It comes in a 36-pin PowerSSO package with exposed pad up (EPU) to facilitate mounting a separate heatsink.

Table 1. Device summary

Order code Temperature range Package Packaging
TDA7498L -40 to 85 °C PowerSSO-36 (EPU) Tube
TDA7498LTR -40 to 85 °C PowerSSO-36 (EPU) Tape and reel
September 2011 Doc ID 16504 Rev 3 1/27
www.st.com
27
Contents TDA7498L

Contents

1 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.1 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.2 Pin list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.4 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3 Characterizations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.1 Test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.2 Characterization curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.2.1 For RL = 6 Ω . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
3.2.2 For R
= 8 Ω . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
L
4 Applications information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.1 Applications circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.2 Mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.3 Gain setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.4 Input resistance and capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.5 Internal and external clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.5.1 Master mode (internal clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.5.2 Slave mode (external clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.6 Output low-pass filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.7 Protection functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.8 Diagnostic output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2/27 Doc ID 16504 Rev 3
TDA7498L List of figures

List of figures

Figure 1. Internal block diagram (showing one channel only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 2. Pin connections (top view, PCB view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 3. Test circuit for characterizations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 4. Test board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 5. Output power (THD = 10%) vs. supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 6. THD vs. output power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 7. THD vs. frequency (1 W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 8. THD vs. frequency (100 mW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 9. Frequency response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 10. FFT performance (0 dBFS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 11. FFT performance (-60 dBFS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 12. Output power (THD = 10%) vs. supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 13. THD vs. output power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 14. THD vs. frequency (1 W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 15. THD vs. frequency (100 mW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 16. Frequency response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 17. FFT performance (0 dB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 18. FFT performance (-60 dB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 19. Applications circuit for 6- or 8-Ω speakers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 20. Standby and mute circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 21. Turn on/off sequence for minimizing speaker “pop” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 22. Input circuit and frequency response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 23. Master and slave connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 24. Typical LC filter for a 8-Ω speaker . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 25. Typical LC filter for a 6-Ω speaker . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 26. Behavior of pin DIAG for various protection conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 27. PowerSSO36 EPU outline drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Doc ID 16504 Rev 3 3/27
List of tables TDA7498L

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. Pin description list. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 3. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 4. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 5. Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 6. Electrical specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 7. Mode settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 8. Gain settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 9. How to set up SYNCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 10. PowerSSO-36 EPU dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 11. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4/27 Doc ID 16504 Rev 3
TDA7498L Device block diagram

1 Device block diagram

Figure 1 shows the block diagram of one of the two identical channels of the TDA7498L.

Figure 1. Internal block diagram (showing one channel only)

Doc ID 16504 Rev 3 5/27
Pin description TDA7498L

2 Pin description

2.1 Pinout

Figure 2. Pin connections (top view, PCB view)

36
35
34
33
32
31
30
29
28
27
26
25
24
VSS
SVCC
VREF
INNB
INPB
GAIN1
GAIN0
SVR
DIAG
SGND
VDDS
SYNCLK
ROSC
SUB_GND
OUTPB
OUTPB
PGNDB
PGNDB
PVCCB
PVCCB
OUTNB
OUTNB
OUTNA
OUTNA
PVCCA
PVCCA
1
2
3
4
5
6
7
8
9
10
11
12
13
23
INNA
22
INPA
21
MUTE
20
STBY
19
VDDPW
6/27 Doc ID 16504 Rev 3
EP, exposed pad Connect to ground
PGNDA
PGNDA
OUTPA
OUTPA
PGND
14
15
16
17
18
TDA7498L Pin description

2.2 Pin list

Table 2. Pin description list

Number Name Type Description
1 SUB_GND PWR Connect to the frame
2,3 OUTPB O Positive PWM for right channel
4,5 PGNDB PWR Power stage ground for right channel
6,7 PVCCB PWR Power supply for right channel
8,9 OUTNB O Negative PWM output for right channel
10,11 OUTNA O Negative PWM output for left channel
12,13 PVCCA PWR Power supply for left channel
14,15 PGNDA PWR Power stage ground for left channel
16,17 OUTPA O Positive PWM output for left channel
18 PGND PWR Power stage ground
19 VDDPW O
3.3-V (nominal) regulator output referred to ground for power stage
20 STBY I Standby mode control
21 MUTE I Mute mode control
22 INPA I Positive differential input of left channel
23 INNA I Negative differential input of left channel
24 ROSC O Master oscillator frequency-setting pin
25 SYNCLK I/O Clock in/out for external oscillator
26 VDDS O
3.3-V (nominal) regulator output referred to ground for signal blocks
27 SGND PWR Signal ground
28 DIAG O Open-drain diagnostic output
29 SVR O Supply voltage rejection
30 GAIN0 I Gain setting input 1
31 GAIN1 I Gain setting input 2
32 INPB I Positive differential input of right channel
33 INNB I Negative differential input of right channel
34 VREF O Half VDDS (nominal) referred to ground
35 SVCC PWR Signal power supply decoupling
36 VSS O 3.3-V (nominal) regulator output referred to power supply
- EP - Exposed pad for heatsink, to be connected to ground
Doc ID 16504 Rev 3 7/27
Electrical specifications TDA7498L

3 Electrical specifications

3.1 Absolute maximum ratings

Table 3. Absolute maximum ratings

Symbol Parameter Value Unit
V
CC_MAX
V
L_MAX
T
j_MAX
T
stg
DC supply voltage for pins PVCCA, PVCCB 44 V
Voltage limits for input pins STBY, MUTE, INNA, INPA, INNB, INPB, GAIN0, GAIN1
Operating junction temperature 0 to 150 °C
Storage temperature -40 to 150 °C
-0.3 to 3.6 V
Warning: Stresses beyond those listed under “Absolute maximum
ratings” make cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “Recommended operating condition” are not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. In the real application, the power supply with the nominal value rated in the recommended operating conditions, may rise beyond the maximum operating condition for a short time when no or very low current is sunk (amplifier in mute state). In this case the reliability of the device is guaranteed, provided that the absolute maximum rating is not exceeded.

3.2 Thermal data

Table 4. Thermal data

Symbol Parameter Min Typ Max Unit
R
th j-case
Thermal resistance, junction to case - 2 3 °C/W

3.3 Recommended operating conditions

Table 5. Recommended operating conditions

Symbol Parameter Min Typ Max Unit
V
CC
T
amb
8/27 Doc ID 16504 Rev 3
Supply voltage for pins PVCCA, PVCCB 14 - 36 V
Ambient operating temperature -20 - 85 °C
TDA7498L Electrical specifications

3.4 Electrical specifications

Unless otherwise stated, the results in Ta bl e 6 below are given for the conditions: V
=32V, RL (load) = 6 Ω, R
CC
Ta mb = 2 5 ° C.

Table 6. Electrical specifications

Symbol Parameter Condition Min Typ Max Unit
= R3 = 39 kΩ, C8 = 100 nF, f = 1 kHz, GV = 25.6 dB and
OSC
I
q
I
qSTBY
Total quiescent current No LC filter, no load - 40 60 mA
Quiescent current in standby - - 1 10 µA
Play mode -100 - 100
V
I
OCP
T
R
V
V
OS
jS
i
OVP
UVP
Output offset voltage
Mute mode -60 - 60
Overcurrent protection threshold RL = 0 Ω 5.0 6.0 - A
Junction temperature at thermal shutdown
- - 150 - °C
Input resistance Differential input 48 60 - kΩ
Overvoltage protection threshold - 42 43 - V
Undervoltage protection threshold
- --8V
High side - 0.2 -
R
dsON
Power transistor on resistance
Low side - 0.2 -
THD = 10% - 80 -
P
o
P
o
P
D
η Efficiency P
THD Total harmonic distortion P
Output power
Output power
Dissipated power
THD = 1% - 65 -
= 8 Ω, THD = 10%,
R
L
VCC= 32V
P
= 80 W + 80 W,
o
THD = 10%
= 80 W + 80W - 90 - %
o
= 1 W - 0.1 - %
o
GAIN0 = L, GAIN1 = L 24.6 25.6 26.6
GAIN0 = L, GAIN1 = H 30.6 31.6 32.6
G
V
Closed-loop gain
GAIN0 = H, GAIN1 = L 34.1 35.1 36.1
GAIN0 = H, GAIN1 = H 36.6 37.6 38.6
ΔG
V
Gain matching - -1 - 1 dB
CT Crosstalk f = 1 kHz, P
A Curve, G
eN Total input noise
f = 22 Hz to 22 kHz - 25 50
mV
Ω
W
-65-W
-16-W
dB
= 1 W 5070- dB
o
= 20 dB - 15 -
V
µV
SVRR Supply voltage rejection ratio
, T
T
r
Rise and fall times - - 50 - ns
f
Doc ID 16504 Rev 3 9/27
fr = 100 Hz, Vr = 0.5 Vpp, C
= 10 µF
SVR
-70-dB
Electrical specifications TDA7498L
Table 6. Electrical specifications (continued)
Symbol Parameter Condition Min Typ Max Unit
f
SW
f
SWR
V
inH
V
inL
Switching frequency Internal oscillator 290 310 330 kHz
Output switching frequency Range
Digital input high (H)
Digital input low (L) - - 0.8
Pin STBY voltage high (H)
V
STBY
Pin STBY voltage low (L) - - 0.5
Pin MUTE voltage high (H)
V
MUTE
A
MUTE
1. fSW = 106 / ((16 * R
2. f
SW
Pin MUTE voltage low (L) - - 0.8
Mute attenuation V
= f
/ 2 with the external oscillator.
SYNCLK
+ 182) * 4) kHz, f
OSC
With internal oscillator
With external oscillator
(1)
(2)
-
-
-
< 0.8 V - 70 - dB
MUTE
= 2 * fSW with R3 = 39 kΩ (see Figure 20.).
SYNCLK
250 - 400
kHz
250 - 400
2.3 - ­V
2.7 - ­V
2.5 - ­V
10/27 Doc ID 16504 Rev 3
TDA7498L Characterization curves

4 Characterization curves

Figure 20 on page 18 shows the test circuit with which the characterization curves, shown in
the next sections, were measured. Figure 3 below shows the PCB layout.

4.1 PCB layout

Figure 3. Test board

To p view
Bottom view
Top copper
Bottom copper
Doc ID 16504 Rev 3 11/27
Characterization curves TDA7498L

4.2 Characterization curves

Unless otherwise stated the measurements were made under the following conditions:
V
= 32 V, f = 1 kHz, GV = 25.6 dB, R
CC
4.2.1 For RL = 6 Ω
Figure 4. Output power vs. supply voltage
= 39 kΩ, C
OSC
= 100 nF, Tamb = 25 °C
OSC
Figure 5. THD vs. output power (1 kHz)
10
5
2
1
0.5
0.2
0.1
%
0.05
0.02
0.01
0.005
0.002
0.001 100m 90200m 500m 1 2 5 10 20 50
W
12/27 Doc ID 16504 Rev 3
TDA7498L Characterization curves
Figure 6. THD vs. output power (100 Hz)
10
5
2
1
0.5
0.2
0.1
%
0.05
0.02
0.01
0.005
0.002
0.001
100m 90200m 500m 1 2 5 10 20 50
W
Figure 7. THD vs. frequency (1 W)
1
0.5
0.2
0.1
%
0.05
0.02
0.01
0.005
20 20k50 100 200 500 1k 2k 5k 10k
Figure 8. THD vs. frequency (100 mW)
1
0.5
0.2
0.1
%
0.05
Hz
0.02
0.01 20 20k50 100 200 500 1k 2k 5k 10k
Hz
Doc ID 16504 Rev 3 13/27
Characterization curves TDA7498L
Figure 9. Frequency response
+3
+2.5
+2
+1.5
+1
+0.5
d B
+0
r
A
-0.5
-1
-1.5
-2
-2.5
-3 20 20k50 100 200 500 1k 2k 5k 10k
Hz
Figure 10. FFT performance (0 dBFS)
+0
-10
-20
-30
-40
-50
-60
d
B
-70
r
-80
A
-90
-100
-110
-120
-130
-140
-150 20 20k50 100 200 500 1k 2k 5k 10k
Hz
Figure 11. FFT performance (-60 dBFS)
+0
-10
-20
-30
-40
-50
-60
d
B
-70
r
-80
A
-90
-100
-110
-120
-130
-140
-150 20 20k50 100 200 500 1k 2k 5k 10k
14/27 Doc ID 16504 Rev 3
Hz
TDA7498L Characterization curves
4.2.2 For RL = 8 Ω
Figure 12. Output power vs. supply voltage
Figure 13. THD vs. output power (1 kHz)
10
5
2
1
0.5
0.2
0.1
%
0.05
0.02
0.01
0.005
0.002
0.001 100m 90200m 500m 1 2 5 10 20 50
W
Doc ID 16504 Rev 3 15/27
Characterization curves TDA7498L
Figure 14. THD vs. output power (100 Hz)
10
5
2
1
0.5
0.2
0.1
%
0.05
0.02
0.01
0.005
0.002
0.001 100m 90200m 500m 1 2 5 10 20 50
W
Figure 15. THD vs. frequency (1 W)
1
0.5
0.2
0.1
%
0.05
0.02
0.01
0.005
20 20k50 100 200 500 1k 2k 5k 10k
Figure 16. THD vs. frequency (100 mW)
1
0.5
0.2
0.1
%
0.05
Hz
0.02
0.01 20 20k50 100 200 500 1k 2k 5k 10k
Hz
16/27 Doc ID 16504 Rev 3
TDA7498L Characterization curves
Figure 17. Frequency response
+3
+2.5
+2
+1.5
+1
+0.5
d B
+0
r
A
-0.5
-1
-1.5
-2
-2.5
-3 20 20k50 100 200 500 1k 2k 5k 10k
Hz
Figure 18. FFT performance (0 dBFS)
+0
-10
-20
-30
-40
-50
-60
d B
-70
r
-80
A
-90
-100
-110
-120
-130
-140
-150 20 20k50 100 200 500 1k 2k 5k 10k
Hz
Figure 19. FFT performance (-60 dBFS)
+0
-10
-20
-30
-40
-50
-60
d B
-70
r
-80
A
-90
-100
-110
-120
-130
-140
-150 20 20k50 100 200 500 1k 2k 5k 10k
Doc ID 16504 Rev 3 17/27
Hz
Applications information TDA7498L

5 Applications information

5.1 Applications circuit

Figure 20. Applications circuit

J1
INPUT
L-
3
L+
4
R-
1
R+
2
3V3
3V3
J4
OUT
C29
2.2uF
SGND
SGND SGND
C8
100nF
FS
FS
S2
S1
SGND
SGND
SGNDSGNDSGND
SGNDSGND
IC2
L4931CZ33
1
GND
2
3V3 POWER SUPPLY
J7
SGND
SGND
MUTE
1 3
STBY
1 3
39K
J8
SGND
IN
3
100nF
R3
C1
1uF
C2
1uF
SGNDSGNDSGND
For
Single-Ended
Input
FREQUENCY SHIFT
3
2
R9
120K
SGND
For
Single-Ended
Input
C11
1uF
C12
1uF
2
2
C9
SGND
SGND
C5
100nF
1
6.8k
D1
18V
22R
100nF
Q1
R13
R14
VDDS
120k
R8
R7
C6
R4
R2
33k
VCC
68k
47k
DIAG
FS
SGND
+
+
C3
1nF
SGNDSGND
C4
1nF
SGNDSGND
VDDS
R1
100k
C10
100nF
C13
SGNDSGND
C14
SGNDSGND
C15
2.2uF
SGND
SGND
16V
2.2uF
SGND
SYNC
1nF
1nF
C7
16V
R6
22R
C30
1uF
C27
330pF
R5
22R
C31
1uF
C21
330pF
L4
22uH
*
C26
680nF
220nF
*
220nF
C28
C24
*
*
L3
22uH
*
2200uF
C23
50V
L1
22uH
*
C20
680nF
C18
220nF
C22
220nF
L2
22uH
*
LC FILTER COMPONENT
Load
L1,L2,L3,L4
6 ohm
22 uH
8 ohm
22 uH 470 nF
R15
8R
C40
220nF
Load=6 ohm
C41
220nF
R16
8R
1
VCC
+
2
GND
J2
R17
*
8R
C42
220nF
*
C43
220nF
*
R18
8R
C20,C26 C18,C22,C24,C28
680 nF
220 nF
220 nF
J3
OUTPUT
L+
L-
R-
R+
1
2
3
4
1
SUB_GND
22
INPA
23
INNA
27
SGND
26
VDDS
28
DIAG
19
VDDPW
18
PGND
25
SYNCLK
24
ROSC
30
J5
GAIN0
31
GAIN1
J6
35
SVCC
36
VSS
32
INPB
33
INNB
21
MUTE
20
STBY
IC1
TDA7498L
OUTPA
OUTPA
PGNDA
PGNDA
PVCCA
PVCCA
OUTNA
OUTNA
OUTPB
OUTPB
PVCCB
PVCCB
PGNDB
PGNDB
OUTNB
OUTNB
VREF
SVR
16
17
14
15
100nF
12
13
10
11
7
6
100nF
5
4
9
8
C25
3
2
C19
34
C17
10uF 10V
SGND
29
C16
10uF
SGND
10V
TDA7498L
CLASS-D AMPLIFIER

5.2 Mode selection

The three operating modes of the TDA7498L are set by the two inputs, STBY (pin 20) and MUTE (pin 21).
Standby mode: all circuits are turned off, very low current consumption.
Mute mode: inputs are connected to ground and the positive and negative PWM
outputs are at 50% duty cycle.
Play mode: the amplifiers are active.
18/27 Doc ID 16504 Rev 3
TDA7498L Applications information
The protection functions of the TDA7498L are enabled by pulling down the voltages of the STBY and MUTE inputs shown in Figure 21. The input current of the corresponding pins must be limited to 200 µA.

Table 7. Mode settings

Mode STBY MUTE
Standby L
Mute H
(1)
(1)
X (don’t care)
L
Play H H
1. Drive levels defined in Table 6: Electrical specifications on page 9

Figure 21. Standby and mute circuits

0 V
0 V
Standby
3.3 V
Mute
3.3 V
R2 30 kΩ
R4 30 kΩ
C7
2.2 µF
C15
2.2 µF
STBY
TDA7498L
MUTE

Figure 22. Turn on/off sequence for minimizing speaker “pop”

Doc ID 16504 Rev 3 19/27
Applications information TDA7498L

5.3 Gain setting

The gain of the TDA7498L is set by the two inputs, GAIN0 (pin 30) and GAIN1 (pin 31). Internally, the gain is set by changing the feedback resistors of the amplifier.

Table 8. Gain settings

GAIN0 GAIN1 Nominal gain, Gv (dB)
LL25.6
LH31.6
HL 35.6
HH37.6

5.4 Input resistance and capacitance

The input impedance is set by an internal resistor Ri = 60 kΩ (typical). An input capacitor (Ci) is required to couple the AC input signal.
The equivalent circuit and frequency response of the input components are shown in
Figure 23. For Ci = 470 nF the high-pass filter cutoff frequency is below 20 Hz:
fC = 1 / (2 * π * Ri * Ci)

Figure 23. Input circuit and frequency response

Input signal
Input
Ci
pin
Ri
Rf
20/27 Doc ID 16504 Rev 3
TDA7498L Applications information

5.5 Internal and external clocks

The clock of the class-D amplifier can be generated internally or can be driven by an external source.
If two or more class-D amplifiers are used in the same system, it is recommended that all devices operate at the same clock frequency. This can be implemented by using one TDA7498L as master clock, while the other devices are in slave mode, that is, externally clocked. The clock interconnect is via pin SYNCLK of each device. As explained below, SYNCLK is an output in master mode and an input in slave mode.

5.5.1 Master mode (internal clock)

Using the internal oscillator, the output switching frequency, fSW, is controlled by the resistor, R
fSW = 106 / ((R
where R
In master mode, pin SYNCLK is used as a clock output pin whose frequency is:
f
SYNCLK
For master mode to operate correctly then resistor R below in Ta bl e 9 .
, connected to pin ROSC:
OSC
* 16 + 182) * 4) kHz
OSC
is in kΩ.
OSC
= 2 * fSW
must be less than 60 kΩ as given
OSC

5.5.2 Slave mode (external clock)

In order to accept an external clock input the pin ROSC must be left open, that is, floating. This forces pin SYNCLK to be internally configured as an input as given in Ta bl e 9 .
The output switching frequency of the slave devices is:
f
= f
SW
SYNCLK
Table 9. How to set up SYNCLK
Master R
Slave Floating (not connected) Input
Figure 24. Master and slave connection
/ 2
Mode ROSC SYNCLK
OSC
Master Slave
TDA7498L
ROSC SYNCLK
Cosc 100 nF
Rosc 39 kΩ
< 60 kΩ Output
TDA7498L
SYNCLK ROSC
Output
Input
Doc ID 16504 Rev 3 21/27
Applications information TDA7498L

5.6 Output low-pass filter

To avoid EMI problems, it may be necessary to use a low-pass filter before the speaker. The cutoff frequency should be larger than 22 kHz and much lower than the output switching frequency. It is necessary to choose the L and C component values depending on the loudspeaker impedance. Some typical values, which give a cutoff frequency of 27 kHz, are shown in Figure 25 and Figure 26 below.
Figure 25. Typical LC filter for a 8-Ω speaker
0?-70
.?-7
0
(U
&P
&N
MHO
(U
Figure 26. Typical LC filter for a 6-Ω speaker
0
?-70
.?-70
(U
&P
&N
MHO
(U
MHO
&N
&N
MHO
&N
&N
MHO
MHO
&N
&N
MHO
&N
&N
MHO
22/27 Doc ID 16504 Rev 3
TDA7498L Applications information

5.7 Protection functions

The TDA7498L is fully protected against overvoltages, undervoltages, overcurrents and thermal overloads as explained here.
Overvoltage protection (OVP)
If the supply voltage exceeds the value for V
given in Table 6: Electrical specifications on
OVP
page 9 the overvoltage protection is activated which forces the outputs to the
high-impedance state. When the supply voltage falls back to within the operating range, the device restarts.
Undervoltage protection (UVP)
If the supply voltage drops below the value for V
specifications on page 9 the undervoltage protection is activated which forces the outputs to
the high-impedance state. When the supply voltage recovers to within the operating range, the device restarts.
given in Table 6: Electrical
UVP
Overcurrent protection (OCP)
If the output current exceeds the value for I
page 9 the overcurrent protection is activated which forces the outputs to the
high-impedance state. Periodically, the device attempts to restart. If the overcurrent condition is still present then the OCP remains active. The restart time, T by the R-C components connected to pin STBY.
given in Table 6: Electrical specifications on
OCP
, is determined
OC
Thermal protection (OTP)
If the junction temperature, Tj, reaches 145 °C (nominally), the device goes to mute mode and the positive and negative PWM outputs are forced to 50% duty cycle. If the junction temperature reaches the value for T device shuts down and the output is forced to the high-impedance state. When the device cools sufficiently, the device restarts.
given in Table 6: Electrical specifications on page 9 the
j

5.8 Diagnostic output

The output pin DIAG is an open-drain transistor. When any protection is activated it switches to the high-impedance state. The pin can be connected to a power supply (< 36 V) by a pull­up resistor whose value is limited by the maximum sinking current (200 µA) of the pin.

Figure 27. Behavior of pin DIAG for various protection conditions

VDD
Overcurrent protection
VDD
TDA7498L
Protection logic
Restart
Doc ID 16504 Rev 3 23/27
DIAG
R1
OV, UV, OT protection
Restart
Package mechanical data TDA7498L

6 Package mechanical data

The TDA7498L comes in a 36-pin PowerSSO package with exposed pad up.
Figure 28 shows the package outline and Ta ble 1 0 gives the dimensions.

Table 10. PowerSSO-36 EPU dimensions

Dimensions in mm Dimensions in inches
Symbol
Min Typ Max Min Typ Max
A 2.15 - 2.45 0.085 - 0.096
A2 2.15 - 2.35 0.085 - 0.093
a1 0 - 0.10 0 - 0.004
b 0.18 - 0.36 0.007 - 0.014
c 0.23 - 0.32 0.009 - 0.013
D 10.10 - 10.50 0.398 - 0.413
E 7.40 - 7.60 0.291 - 0.299
e - 0.5 - - 0.020 -
e3 - 8.5 - - 0.335 -
F - 2.3 - - 0.091 -
G- - 0.10 - - 0.004
H 10.10 - 10.50 0.398 - 0.413
h- - 0.40 - - 0.016
k 0 - 8 degrees - - 8 degrees
L 0.60 - 1.00 0.024 - 0.039
M - 4.30 - - 0.169 -
N - - 10 degrees - - 10 degrees
O - 1.20 - - 0.047 -
Q - 0.80 - - 0.031 -
S - 2.90 - - 0.114 -
T - 3.65 - - 0.144 -
U - 1.00 - - 0.039 -
X 4.10 - 4.70 0.161 - 0.185
Y 4.90 - 7.10 0.193 - 0.280
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK
®
packages, depending on their level of environmental compliance. ECOPACK®
®
is an ST trademark.
24/27 Doc ID 16504 Rev 3
Doc ID 16504 Rev 3 25/27

Figure 28. PowerSSO-36 EPU outline drawing

TDA7498L Package mechanical data
h x 45°
Revision history TDA7498L

7 Revision history

Table 11. Document revision history

Date Revision Changes
04-Dec-2009 1 Initial release.
Removed datasheet preliminary status, updated features list and updated Device summary table on page 1
02-Jul-2010 2
12-Sep-2011 3 Updated OUTNA in Table 2: Pin description list; minor textual updates
Updated minimum supply voltage and temperature range in Ta bl e 5 :
Recommended operating conditions on page 8
Updated typical power output for 8 Ω at 32 V in Tabl e 6 : E l ectric a l
specifications on page 9
26/27 Doc ID 16504 Rev 3
TDA7498L
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Doc ID 16504 Rev 3 27/27
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