ST TDA7498L User Manual

80 watt + 80 watt dual BTL class-D audio amplifier

Features

■ 80 W + 80 W output power at

THD = 10% with R

■ 70 W + 70 W output power at

THD = 10% with R

■ Wide-range single-supply operation (14 - 36 V)

■ High efficiency (η = 90%)

■ Four selectable, fixed gain settings of

nominally 25.6 dB, 31.6 dB, 35.1 dB and

37.6 dB

■ Differential inputs minimize common-mode

noise

■ Standby and mute features

■ Short-circuit protection

■ Thermal overload protection

■ Externally synchronizable

= 6 Ω and V

L

= 8 Ω and V

L

CC

CC

= 32 V

= 34 V

TDA7498L

PowerSSO-36
with exposed pad up

Description

The TDA7498L is a dual BTL class-D audio
amplifier with single power supply designed for
home systems and active speaker applications.

It comes in a 36-pin PowerSSO package with
exposed pad up (EPU) to facilitate mounting a
separate heatsink.

Table 1. Device summary

Order code Temperature range Package Packaging

TDA7498L -40 to 85 °C PowerSSO-36 (EPU) Tube

TDA7498LTR -40 to 85 °C PowerSSO-36 (EPU) Tape and reel

September 2011 Doc ID 16504 Rev 3 1/27

www.st.com

27

Contents TDA7498L

Contents

1 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

1.1 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

1.2 Pin list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.3 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.4 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3 Characterizations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

3.1 Test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

3.2 Characterization curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3.2.1 For RL = 6 Ω . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

3.2.2 For R

= 8 Ω . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

L

4 Applications information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

4.1 Applications circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

4.2 Mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

4.3 Gain setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

4.4 Input resistance and capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

4.5 Internal and external clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

4.5.1 Master mode (internal clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

4.5.2 Slave mode (external clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

4.6 Output low-pass filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

4.7 Protection functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4.8 Diagnostic output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

5 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

2/27 Doc ID 16504 Rev 3

TDA7498L List of figures

List of figures

Figure 1. Internal block diagram (showing one channel only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 2. Pin connections (top view, PCB view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 3. Test circuit for characterizations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 4. Test board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 5. Output power (THD = 10%) vs. supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 6. THD vs. output power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 7. THD vs. frequency (1 W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 8. THD vs. frequency (100 mW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 9. Frequency response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 10. FFT performance (0 dBFS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 11. FFT performance (-60 dBFS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 12. Output power (THD = 10%) vs. supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 13. THD vs. output power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 14. THD vs. frequency (1 W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 15. THD vs. frequency (100 mW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 16. Frequency response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 17. FFT performance (0 dB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 18. FFT performance (-60 dB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 19. Applications circuit for 6- or 8-Ω speakers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 20. Standby and mute circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 21. Turn on/off sequence for minimizing speaker “pop” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 22. Input circuit and frequency response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 23. Master and slave connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 24. Typical LC filter for a 8-Ω speaker . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 25. Typical LC filter for a 6-Ω speaker . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 26. Behavior of pin DIAG for various protection conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 27. PowerSSO36 EPU outline drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Doc ID 16504 Rev 3 3/27

List of tables TDA7498L

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table 2. Pin description list. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 3. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Table 4. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Table 5. Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Table 6. Electrical specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Table 7. Mode settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 8. Gain settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Table 9. How to set up SYNCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 10. PowerSSO-36 EPU dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 11. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

4/27 Doc ID 16504 Rev 3

TDA7498L Device block diagram

1 Device block diagram

Figure 1 shows the block diagram of one of the two identical channels of the TDA7498L.

Figure 1. Internal block diagram (showing one channel only)

Doc ID 16504 Rev 3 5/27

Pin description TDA7498L

2 Pin description

2.1 Pinout

Figure 2. Pin connections (top view, PCB view)

36

35

34

33

32

31

30

29

28

27

26

25

24

VSS

SVCC

VREF

INNB

INPB

GAIN1

GAIN0

SVR

DIAG

SGND

VDDS

SYNCLK

ROSC

SUB_GND

OUTPB

OUTPB

PGNDB

PGNDB

PVCCB

PVCCB

OUTNB

OUTNB

OUTNA

OUTNA

PVCCA

PVCCA

1

2

3

4

5

6

7

8

9

10

11

12

13

23

INNA

22

INPA

21

MUTE

20

STBY

19

VDDPW

6/27 Doc ID 16504 Rev 3

EP, exposed pad
Connect to ground

PGNDA

PGNDA

OUTPA

OUTPA

PGND

14

15

16

17

18

TDA7498L Pin description

2.2 Pin list

Table 2. Pin description list

Number Name Type Description

1 SUB_GND PWR Connect to the frame

2,3 OUTPB O Positive PWM for right channel

4,5 PGNDB PWR Power stage ground for right channel

6,7 PVCCB PWR Power supply for right channel

8,9 OUTNB O Negative PWM output for right channel

10,11 OUTNA O Negative PWM output for left channel

12,13 PVCCA PWR Power supply for left channel

14,15 PGNDA PWR Power stage ground for left channel

16,17 OUTPA O Positive PWM output for left channel

18 PGND PWR Power stage ground

19 VDDPW O

3.3-V (nominal) regulator output referred to ground for power
stage

20 STBY I Standby mode control

21 MUTE I Mute mode control

22 INPA I Positive differential input of left channel

23 INNA I Negative differential input of left channel

24 ROSC O Master oscillator frequency-setting pin

25 SYNCLK I/O Clock in/out for external oscillator

26 VDDS O

3.3-V (nominal) regulator output referred to ground for signal
blocks

27 SGND PWR Signal ground

28 DIAG O Open-drain diagnostic output

29 SVR O Supply voltage rejection

30 GAIN0 I Gain setting input 1

31 GAIN1 I Gain setting input 2

32 INPB I Positive differential input of right channel

33 INNB I Negative differential input of right channel

34 VREF O Half VDDS (nominal) referred to ground

35 SVCC PWR Signal power supply decoupling

36 VSS O 3.3-V (nominal) regulator output referred to power supply

- EP - Exposed pad for heatsink, to be connected to ground

Doc ID 16504 Rev 3 7/27

Electrical specifications TDA7498L

3 Electrical specifications

3.1 Absolute maximum ratings

Table 3. Absolute maximum ratings

Symbol Parameter Value Unit

V

CC_MAX

V

L_MAX

T

j_MAX

T

stg

DC supply voltage for pins PVCCA, PVCCB 44 V

Voltage limits for input pins STBY, MUTE, INNA, INPA,
INNB, INPB, GAIN0, GAIN1

Operating junction temperature 0 to 150 °C

Storage temperature -40 to 150 °C

-0.3 to 3.6 V

Warning: Stresses beyond those listed under “Absolute maximum

ratings” make cause permanent damage to the device. These
are stress ratings only, and functional operation of the device
at these or any other conditions beyond those indicated
under “Recommended operating condition” are not implied.
Exposure to absolute-maximum-rated conditions for
extended periods may affect device reliability. In the real
application, the power supply with the nominal value rated in
the recommended operating conditions, may rise beyond the
maximum operating condition for a short time when no or
very low current is sunk (amplifier in mute state). In this case
the reliability of the device is guaranteed, provided that the
absolute maximum rating is not exceeded.

3.2 Thermal data

Table 4. Thermal data

Symbol Parameter Min Typ Max Unit

R

th j-case

Thermal resistance, junction to case - 2 3 °C/W

3.3 Recommended operating conditions

Table 5. Recommended operating conditions

Symbol Parameter Min Typ Max Unit

V

CC

T

amb

8/27 Doc ID 16504 Rev 3

Supply voltage for pins PVCCA, PVCCB 14 - 36 V

Ambient operating temperature -20 - 85 °C

TDA7498L Electrical specifications

3.4 Electrical specifications

Unless otherwise stated, the results in Ta bl e 6 below are given for the conditions:
V

=32V, RL (load) = 6 Ω, R

CC

Ta mb = 2 5 ° C.

Table 6. Electrical specifications

Symbol Parameter Condition Min Typ Max Unit

= R3 = 39 kΩ, C8 = 100 nF, f = 1 kHz, GV = 25.6 dB and

OSC

I

q

I

qSTBY

Total quiescent current No LC filter, no load - 40 60 mA

Quiescent current in standby - - 1 10 µA

Play mode -100 - 100

V

I

OCP

T

R

V

V

OS

jS

i

OVP

UVP

Output offset voltage

Mute mode -60 - 60

Overcurrent protection threshold RL = 0 Ω 5.0 6.0 - A

Junction temperature at thermal
shutdown

- - 150 - °C

Input resistance Differential input 48 60 - kΩ

Overvoltage protection threshold - 42 43 - V

Undervoltage protection
threshold

- --8V

High side - 0.2 -

R

dsON

Power transistor on resistance

Low side - 0.2 -

THD = 10% - 80 -

P

o

P

o

P

D

η Efficiency P

THD Total harmonic distortion P

Output power

Output power

Dissipated power

THD = 1% - 65 -

= 8 Ω, THD = 10%,

R

L

VCC= 32V

P

= 80 W + 80 W,

o

THD = 10%

= 80 W + 80W - 90 - %

o

= 1 W - 0.1 - %

o

GAIN0 = L, GAIN1 = L 24.6 25.6 26.6

GAIN0 = L, GAIN1 = H 30.6 31.6 32.6

G

V

Closed-loop gain

GAIN0 = H, GAIN1 = L 34.1 35.1 36.1

GAIN0 = H, GAIN1 = H 36.6 37.6 38.6

ΔG

V

Gain matching - -1 - 1 dB

CT Crosstalk f = 1 kHz, P

A Curve, G

eN Total input noise

f = 22 Hz to 22 kHz - 25 50

mV

Ω

W

-65-W

-16-W

dB

= 1 W 5070- dB

o

= 20 dB - 15 -

V

µV

SVRR Supply voltage rejection ratio

, T

T

r

Rise and fall times - - 50 - ns

f

Doc ID 16504 Rev 3 9/27

fr = 100 Hz, Vr = 0.5 Vpp,
C

= 10 µF

SVR

-70-dB