Figure 1 shows the block diagram of one of the two identical channels of the TDA7498L.
Figure 1.Internal block diagram (showing one channel only)
Doc ID 16504 Rev 35/27
Pin descriptionTDA7498L
2 Pin description
2.1 Pinout
Figure 2.Pin connections (top view, PCB view)
36
35
34
33
32
31
30
29
28
27
26
25
24
VSS
SVCC
VREF
INNB
INPB
GAIN1
GAIN0
SVR
DIAG
SGND
VDDS
SYNCLK
ROSC
SUB_GND
OUTPB
OUTPB
PGNDB
PGNDB
PVCCB
PVCCB
OUTNB
OUTNB
OUTNA
OUTNA
PVCCA
PVCCA
1
2
3
4
5
6
7
8
9
10
11
12
13
23
INNA
22
INPA
21
MUTE
20
STBY
19
VDDPW
6/27Doc ID 16504 Rev 3
EP, exposed pad
Connect to ground
PGNDA
PGNDA
OUTPA
OUTPA
PGND
14
15
16
17
18
TDA7498LPin description
2.2 Pin list
Table 2.Pin description list
NumberNameTypeDescription
1SUB_GNDPWRConnect to the frame
2,3OUTPBOPositive PWM for right channel
4,5PGNDBPWRPower stage ground for right channel
6,7PVCCBPWRPower supply for right channel
8,9OUTNBONegative PWM output for right channel
10,11OUTNAONegative PWM output for left channel
12,13PVCCAPWRPower supply for left channel
14,15PGNDAPWRPower stage ground for left channel
16,17OUTPAOPositive PWM output for left channel
18PGNDPWRPower stage ground
19VDDPWO
3.3-V (nominal) regulator output referred to ground for power
stage
20STBYIStandby mode control
21MUTEIMute mode control
22INPAIPositive differential input of left channel
23INNAINegative differential input of left channel
24ROSCOMaster oscillator frequency-setting pin
25SYNCLKI/OClock in/out for external oscillator
26VDDSO
3.3-V (nominal) regulator output referred to ground for signal
blocks
27SGNDPWRSignal ground
28DIAGOOpen-drain diagnostic output
29SVROSupply voltage rejection
30GAIN0IGain setting input 1
31GAIN1IGain setting input 2
32INPBIPositive differential input of right channel
33INNBINegative differential input of right channel
34VREFOHalf VDDS (nominal) referred to ground
35SVCCPWRSignal power supply decoupling
36VSSO3.3-V (nominal) regulator output referred to power supply
-EP-Exposed pad for heatsink, to be connected to ground
Doc ID 16504 Rev 37/27
Electrical specificationsTDA7498L
3 Electrical specifications
3.1 Absolute maximum ratings
Table 3.Absolute maximum ratings
SymbolParameterValueUnit
V
CC_MAX
V
L_MAX
T
j_MAX
T
stg
DC supply voltage for pins PVCCA, PVCCB44V
Voltage limits for input pins STBY, MUTE, INNA, INPA,
INNB, INPB, GAIN0, GAIN1
Operating junction temperature 0 to 150°C
Storage temperature-40 to 150°C
-0.3 to 3.6V
Warning:Stresses beyond those listed under “Absolute maximum
ratings” make cause permanent damage to the device. These
are stress ratings only, and functional operation of the device
at these or any other conditions beyond those indicated
under “Recommended operating condition” are not implied.
Exposure to absolute-maximum-rated conditions for
extended periods may affect device reliability. In the real
application, the power supply with the nominal value rated in
the recommended operating conditions, may rise beyond the
maximum operating condition for a short time when no or
very low current is sunk (amplifier in mute state). In this case
the reliability of the device is guaranteed, provided that the
absolute maximum rating is not exceeded.
3.2 Thermal data
Table 4.Thermal data
SymbolParameterMinTypMaxUnit
R
th j-case
Thermal resistance, junction to case-23°C/W
3.3 Recommended operating conditions
Table 5.Recommended operating conditions
SymbolParameterMinTypMaxUnit
V
CC
T
amb
8/27Doc ID 16504 Rev 3
Supply voltage for pins PVCCA, PVCCB14-36V
Ambient operating temperature-20-85°C
TDA7498LElectrical specifications
3.4 Electrical specifications
Unless otherwise stated, the results in Ta bl e 6 below are given for the conditions:
V
=32V, RL (load) = 6 Ω, R
CC
Ta mb = 2 5 ° C.
Table 6.Electrical specifications
SymbolParameterConditionMinTypMaxUnit
= R3 = 39 kΩ, C8 = 100 nF, f = 1 kHz, GV = 25.6 dB and
OSC
I
q
I
qSTBY
Total quiescent currentNo LC filter, no load-4060mA
Figure 20 on page 18 shows the test circuit with which the characterization curves, shown in
the next sections, were measured. Figure 3 below shows the PCB layout.
4.1 PCB layout
Figure 3.Test board
To p view
Bottom view
Top copper
Bottom copper
Doc ID 16504 Rev 311/27
Characterization curvesTDA7498L
4.2 Characterization curves
Unless otherwise stated the measurements were made under the following conditions:
V
= 32 V, f = 1 kHz, GV = 25.6 dB, R
CC
4.2.1 For RL = 6 Ω
Figure 4.Output power vs. supply voltage
= 39 kΩ, C
OSC
= 100 nF, Tamb = 25 °C
OSC
Figure 5.THD vs. output power (1 kHz)
10
5
2
1
0.5
0.2
0.1
%
0.05
0.02
0.01
0.005
0.002
0.001
100m90200m500m125102050
W
12/27Doc ID 16504 Rev 3
TDA7498LCharacterization curves
Figure 6.THD vs. output power (100 Hz)
10
5
2
1
0.5
0.2
0.1
%
0.05
0.02
0.01
0.005
0.002
0.001
100m90200m500m125102050
W
Figure 7.THD vs. frequency (1 W)
1
0.5
0.2
0.1
%
0.05
0.02
0.01
0.005
2020k501002005001k2k5k10k
Figure 8.THD vs. frequency (100 mW)
1
0.5
0.2
0.1
%
0.05
Hz
0.02
0.01
2020k501002005001k2k5k10k
Hz
Doc ID 16504 Rev 313/27
Characterization curvesTDA7498L
Figure 9.Frequency response
+3
+2.5
+2
+1.5
+1
+0.5
d
B
+0
r
A
-0.5
-1
-1.5
-2
-2.5
-3
2020k501002005001k2k5k10k
Hz
Figure 10. FFT performance (0 dBFS)
+0
-10
-20
-30
-40
-50
-60
d
B
-70
r
-80
A
-90
-100
-110
-120
-130
-140
-150
2020k501002005001k2k5k10k
Hz
Figure 11. FFT performance (-60 dBFS)
+0
-10
-20
-30
-40
-50
-60
d
B
-70
r
-80
A
-90
-100
-110
-120
-130
-140
-150
2020k501002005001k2k5k10k
14/27Doc ID 16504 Rev 3
Hz
TDA7498LCharacterization curves
4.2.2 For RL = 8 Ω
Figure 12. Output power vs. supply voltage
Figure 13. THD vs. output power (1 kHz)
10
5
2
1
0.5
0.2
0.1
%
0.05
0.02
0.01
0.005
0.002
0.001
100m90200m500m125102050
W
Doc ID 16504 Rev 315/27
Characterization curvesTDA7498L
Figure 14. THD vs. output power (100 Hz)
10
5
2
1
0.5
0.2
0.1
%
0.05
0.02
0.01
0.005
0.002
0.001
100m90200m500m125102050
W
Figure 15. THD vs. frequency (1 W)
1
0.5
0.2
0.1
%
0.05
0.02
0.01
0.005
2020k501002005001k2k5k10k
Figure 16. THD vs. frequency (100 mW)
1
0.5
0.2
0.1
%
0.05
Hz
0.02
0.01
2020k501002005001k2k5k10k
Hz
16/27Doc ID 16504 Rev 3
TDA7498LCharacterization curves
Figure 17. Frequency response
+3
+2.5
+2
+1.5
+1
+0.5
d
B
+0
r
A
-0.5
-1
-1.5
-2
-2.5
-3
2020k501002005001k2k5k10k
Hz
Figure 18. FFT performance (0 dBFS)
+0
-10
-20
-30
-40
-50
-60
d
B
-70
r
-80
A
-90
-100
-110
-120
-130
-140
-150
2020k501002005001k2k5k10k
Hz
Figure 19. FFT performance (-60 dBFS)
+0
-10
-20
-30
-40
-50
-60
d
B
-70
r
-80
A
-90
-100
-110
-120
-130
-140
-150
2020k501002005001k2k5k10k
Doc ID 16504 Rev 317/27
Hz
Applications informationTDA7498L
5 Applications information
5.1 Applications circuit
Figure 20. Applications circuit
J1
INPUT
L-
3
L+
4
R-
1
R+
2
3V3
3V3
J4
OUT
C29
2.2uF
SGND
SGNDSGND
C8
100nF
FS
FS
S2
S1
SGND
SGND
SGNDSGNDSGND
SGNDSGND
IC2
L4931CZ33
1
GND
2
3V3 POWER SUPPLY
J7
SGND
SGND
MUTE
1
3
STBY
1
3
39K
J8
SGND
IN
3
100nF
R3
C1
1uF
C2
1uF
SGNDSGNDSGND
For
Single-Ended
Input
FREQUENCY SHIFT
3
2
R9
120K
SGND
For
Single-Ended
Input
C11
1uF
C12
1uF
2
2
C9
SGND
SGND
C5
100nF
1
6.8k
D1
18V
22R
100nF
Q1
R13
R14
VDDS
120k
R8
R7
C6
R4
R2
33k
VCC
68k
47k
DIAG
FS
SGND
+
+
C3
1nF
SGNDSGND
C4
1nF
SGNDSGND
VDDS
R1
100k
C10
100nF
C13
SGNDSGND
C14
SGNDSGND
C15
2.2uF
SGND
SGND
16V
2.2uF
SGND
SYNC
1nF
1nF
C7
16V
R6
22R
C30
1uF
C27
330pF
R5
22R
C31
1uF
C21
330pF
L4
22uH
*
C26
680nF
220nF
*
220nF
C28
C24
*
*
L3
22uH
*
2200uF
C23
50V
L1
22uH
*
C20
680nF
C18
220nF
C22
220nF
L2
22uH
*
LC FILTER COMPONENT
Load
L1,L2,L3,L4
6 ohm
22 uH
8 ohm
22 uH470 nF
R15
8R
C40
220nF
Load=6 ohm
C41
220nF
R16
8R
1
VCC
+
2
GND
J2
R17
*
8R
C42
220nF
*
C43
220nF
*
R18
8R
C20,C26 C18,C22,C24,C28
680 nF
220 nF
220 nF
J3
OUTPUT
L+
L-
R-
R+
1
2
3
4
1
SUB_GND
22
INPA
23
INNA
27
SGND
26
VDDS
28
DIAG
19
VDDPW
18
PGND
25
SYNCLK
24
ROSC
30
J5
GAIN0
31
GAIN1
J6
35
SVCC
36
VSS
32
INPB
33
INNB
21
MUTE
20
STBY
IC1
TDA7498L
OUTPA
OUTPA
PGNDA
PGNDA
PVCCA
PVCCA
OUTNA
OUTNA
OUTPB
OUTPB
PVCCB
PVCCB
PGNDB
PGNDB
OUTNB
OUTNB
VREF
SVR
16
17
14
15
100nF
12
13
10
11
7
6
100nF
5
4
9
8
C25
3
2
C19
34
C17
10uF
10V
SGND
29
C16
10uF
SGND
10V
TDA7498L
CLASS-D AMPLIFIER
5.2 Mode selection
The three operating modes of the TDA7498L are set by the two inputs, STBY (pin 20) and
MUTE (pin 21).
●Standby mode: all circuits are turned off, very low current consumption.
●Mute mode: inputs are connected to ground and the positive and negative PWM
outputs are at 50% duty cycle.
●Play mode: the amplifiers are active.
18/27Doc ID 16504 Rev 3
TDA7498LApplications information
The protection functions of the TDA7498L are enabled by pulling down the voltages of the
STBY and MUTE inputs shown in Figure 21. The input current of the corresponding pins
must be limited to 200 µA.
Table 7.Mode settings
ModeSTBY MUTE
StandbyL
MuteH
(1)
(1)
X (don’t care)
L
PlayHH
1. Drive levels defined in Table 6: Electrical specifications on page 9
Figure 21. Standby and mute circuits
0 V
0 V
Standby
3.3 V
Mute
3.3 V
R2
30 kΩ
R4
30 kΩ
C7
2.2 µF
C15
2.2 µF
STBY
TDA7498L
MUTE
Figure 22. Turn on/off sequence for minimizing speaker “pop”
Doc ID 16504 Rev 319/27
Applications informationTDA7498L
5.3 Gain setting
The gain of the TDA7498L is set by the two inputs, GAIN0 (pin 30) and GAIN1 (pin 31).
Internally, the gain is set by changing the feedback resistors of the amplifier.
Table 8.Gain settings
GAIN0GAIN1Nominal gain, Gv (dB)
LL25.6
LH31.6
HL 35.6
HH37.6
5.4 Input resistance and capacitance
The input impedance is set by an internal resistor Ri = 60 kΩ (typical). An input capacitor
(Ci) is required to couple the AC input signal.
The equivalent circuit and frequency response of the input components are shown in
Figure 23. For Ci = 470 nF the high-pass filter cutoff frequency is below 20 Hz:
fC = 1 / (2 * π * Ri * Ci)
Figure 23. Input circuit and frequency response
Input
signal
Input
Ci
pin
Ri
Rf
20/27Doc ID 16504 Rev 3
TDA7498LApplications information
5.5 Internal and external clocks
The clock of the class-D amplifier can be generated internally or can be driven by an
external source.
If two or more class-D amplifiers are used in the same system, it is recommended that all
devices operate at the same clock frequency. This can be implemented by using one
TDA7498L as master clock, while the other devices are in slave mode, that is, externally
clocked. The clock interconnect is via pin SYNCLK of each device. As explained below,
SYNCLK is an output in master mode and an input in slave mode.
5.5.1 Master mode (internal clock)
Using the internal oscillator, the output switching frequency, fSW, is controlled by the
resistor, R
fSW = 106 / ((R
where R
In master mode, pin SYNCLK is used as a clock output pin whose frequency is:
f
SYNCLK
For master mode to operate correctly then resistor R
below in Ta bl e 9 .
, connected to pin ROSC:
OSC
* 16 + 182) * 4) kHz
OSC
is in kΩ.
OSC
= 2 * fSW
must be less than 60 kΩ as given
OSC
5.5.2 Slave mode (external clock)
In order to accept an external clock input the pin ROSC must be left open, that is, floating.
This forces pin SYNCLK to be internally configured as an input as given in Ta bl e 9 .
The output switching frequency of the slave devices is:
f
= f
SW
SYNCLK
Table 9.How to set up SYNCLK
MasterR
SlaveFloating (not connected)Input
Figure 24. Master and slave connection
/ 2
ModeROSCSYNCLK
OSC
MasterSlave
TDA7498L
ROSCSYNCLK
Cosc
100 nF
Rosc
39 kΩ
< 60 kΩOutput
TDA7498L
SYNCLKROSC
Output
Input
Doc ID 16504 Rev 321/27
Applications informationTDA7498L
5.6 Output low-pass filter
To avoid EMI problems, it may be necessary to use a low-pass filter before the speaker. The
cutoff frequency should be larger than 22 kHz and much lower than the output switching
frequency. It is necessary to choose the L and C component values depending on the
loudspeaker impedance. Some typical values, which give a cutoff frequency of 27 kHz, are
shown in Figure 25 and Figure 26 below.
Figure 25. Typical LC filter for a 8-Ω speaker
0?-70
.?-7
0
(U
&P
&N
MHO
(U
Figure 26. Typical LC filter for a 6-Ω speaker
0
?-70
.?-70
(U
&P
&N
MHO
(U
MHO
&N
&N
MHO
&N
&N
MHO
MHO
&N
&N
MHO
&N
&N
MHO
22/27Doc ID 16504 Rev 3
TDA7498LApplications information
5.7 Protection functions
The TDA7498L is fully protected against overvoltages, undervoltages, overcurrents and
thermal overloads as explained here.
Overvoltage protection (OVP)
If the supply voltage exceeds the value for V
given in Table 6: Electrical specifications on
OVP
page 9 the overvoltage protection is activated which forces the outputs to the
high-impedance state. When the supply voltage falls back to within the operating range, the
device restarts.
Undervoltage protection (UVP)
If the supply voltage drops below the value for V
specifications on page 9 the undervoltage protection is activated which forces the outputs to
the high-impedance state. When the supply voltage recovers to within the operating range,
the device restarts.
given in Table 6: Electrical
UVP
Overcurrent protection (OCP)
If the output current exceeds the value for I
page 9 the overcurrent protection is activated which forces the outputs to the
high-impedance state. Periodically, the device attempts to restart. If the overcurrent
condition is still present then the OCP remains active. The restart time, T
by the R-C components connected to pin STBY.
given in Table 6: Electrical specifications on
OCP
, is determined
OC
Thermal protection (OTP)
If the junction temperature, Tj, reaches 145 °C (nominally), the device goes to mute mode
and the positive and negative PWM outputs are forced to 50% duty cycle. If the junction
temperature reaches the value for T
device shuts down and the output is forced to the high-impedance state. When the device
cools sufficiently, the device restarts.
given in Table 6: Electrical specifications on page 9 the
j
5.8 Diagnostic output
The output pin DIAG is an open-drain transistor. When any protection is activated it switches
to the high-impedance state. The pin can be connected to a power supply (< 36 V) by a pullup resistor whose value is limited by the maximum sinking current (200 µA) of the pin.
Figure 27. Behavior of pin DIAG for various protection conditions
VDD
Overcurrent
protection
VDD
TDA7498L
Protection logic
Restart
Doc ID 16504 Rev 323/27
DIAG
R1
OV, UV, OT
protection
Restart
Package mechanical dataTDA7498L
6 Package mechanical data
The TDA7498L comes in a 36-pin PowerSSO package with exposed pad up.
Figure 28 shows the package outline and Ta ble 1 0 gives the dimensions.
Table 10.PowerSSO-36 EPU dimensions
Dimensions in mmDimensions in inches
Symbol
MinTypMaxMinTypMax
A2.15-2.450.085-0.096
A22.15-2.350.085-0.093
a10-0.100-0.004
b0.18-0.360.007-0.014
c0.23-0.320.009-0.013
D10.10-10.500.398-0.413
E7.40-7.600.291-0.299
e-0.5--0.020-
e3-8.5--0.335-
F-2.3--0.091-
G--0.10 --0.004
H10.10-10.500.398-0.413
h--0.40 --0.016
k0-8 degrees--8 degrees
L0.60-1.000.024-0.039
M-4.30--0.169-
N--10 degrees--10 degrees
O-1.20--0.047-
Q-0.80--0.031-
S-2.90--0.114-
T-3.65--0.144-
U-1.00--0.039-
X4.10-4.700.161-0.185
Y4.90-7.100.193-0.280
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK
®
packages, depending on their level of environmental compliance. ECOPACK®
®
is an ST trademark.
24/27Doc ID 16504 Rev 3
Doc ID 16504 Rev 325/27
Figure 28. PowerSSO-36 EPU outline drawing
TDA7498LPackage mechanical data
h x 45°
Revision historyTDA7498L
7 Revision history
Table 11.Document revision history
DateRevisionChanges
04-Dec-20091Initial release.
Removed datasheet preliminary status, updated features list and
updated Device summary table on page 1
02-Jul-20102
12-Sep-20113Updated OUTNA in Table 2: Pin description list; minor textual updates
Updated minimum supply voltage and temperature range in Ta bl e 5 :
Recommended operating conditions on page 8
Updated typical power output for 8 Ω at 32 V in Tabl e 6 : E l ectric a l
specifications on page 9
26/27Doc ID 16504 Rev 3
TDA7498L
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