The TDA7419 is a high performance signal
processor specifically designed for car radio
applications. The device includes a high
performance audioprocessor with fully integrated
audio filters.
Table 1.Device summary
Order codePackagePacking
TDA7419SO-28Tube
TDA7419TRSO-28Tape and reel
The digital control allows programming in a wide
range of filter characteristics. By the use of
BICMOS-process and linear signal processing
low distortion and low noise are obtained.
–programmable center frequency (400Hz/800Hz/2400Hz)
–15 dB with 1 dB steps
–selectable low and high frequency boost
–selectable flat-mode (constant attenuation)
●Vol u me
–+15 dB to -79 dB with 1 dB step resolution
–soft-step control with programmable blend times
●Bass
–2
–center frequency programmable in 4 steps (60 Hz/80 Hz/100 Hz/200 Hz)
–Q programmable 1.0/1.25/1.5/2.0
–DC gain programmable
–-15 to 15 dB range with 1 dB resolution
●Middle
–2
–center frequency programmable in 4 steps (500Hz/1KHz/1.5KHz/2.5KHz)
–Q programmable 0.5/0.75/1.0/1.25
–DC gain programmable
–-15 to 15dB range with 1dB resolution
●Tre bl e
–2
–center frequency programmable in 4 steps (10KHz/12.5KHz/15KHz/17.5KHz)
–-15 to 15dB range with 1dB resolution
●Spectrum analyzer
–seven bandpass filters
–2
order frequency response
nd
order frequency response
nd
order frequency response
nd
order frequency response
nd
order frequency response
14/40
TDA7419Description of the audio processor
–programmable Q factor for different visual appearance
–analog output
–controlled by external serial clock
●Speaker
–4 independent soft-step speaker controls, +15dB to -79dB with 1dB steps
–Independent programmable mix input with 50% mixing ratio for front speakers
–direct mute
●Subwoofer
–2nd order low pass filter with programmable cut off frequency
–single-ended mono output independent soft-step level control, +15dB to -79dB
with 1dB steps
●Mute functions
–direct mute
–digitally controlled Soft-mute with 3 programmable mute-
times(0.48ms/0.96ms/123ms)
●Effect
–gain effect, or high pass effect with fixed external components
4.2 Input stages
In the basic configuration, one stereo quasi-differential and three (two in case of HPS
applications) single ended stereo inputs are available.
4.2.1 Quasi-differential stereo input (QD)
The QD input is implemented as a buffered quasi-differential stereo stage with 100 kΩ inputimpedance at each input. The attenuation is fixed to -3 dB in order to adapt the incoming
signal level.
The input impedance at each input is 100 kΩ and the attenuation is fixed to -3dB for
incoming signals. The input for SE3 is also configurable as part of the interface for external
filters in HPS applications (AC2IN)
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Description of the audio processorTDA7419
Figure 3.Input stage
QD_L
QD_G
QD_R
QD
QD
Main
Source
AC2IN_L/SE3L
AC2IN_R/SE3R
4.3 AutoZero
The AutoZero allows a reduction of the number of pins as well as external components by
canceling any offset generated by or before the In-Gain-stage (Please notice that externally
generated offsets, e.g. generated through the leakage current of the coupling capacitors,
are not canceled).
SE1_L
SE1_R
SE2_L
SE2_R
SE1
SE2
SE3
SE4
SE1
SE2
SE3
Second
Source
In Gain
Output Stage
The auto-zeroing is started every time the input source is changed and needs max. 0.3ms
for the alignment. To avoid audible clicks the Audio processor is muted before the loudness
stage during this time. The AutoZero feature is only present in the main signal-path.
4.3.1 AutoZero remain
In some cases, for example if the µP is executing a refresh cycle of the I2C bus
programming, it is not useful to start a new AutoZero action because no new source is
selected and an undesired mute would appear at the outputs. For such applications, it can
be switched in the AutoZero remain mode (bit 6 of the subaddress byte). If this bit is set to
high, the AutoZero will not be invoked and the old adjustment-value remains.
4.4 Loudness
There are four parameters programmable in the loudness stage:
4.4.1 Attenuation
Figure 4 shows the attenuation as a function of frequency at fP = 400 Hz
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TDA7419Description of the audio processor
Figure 4.Loudness attenuation @ fP = 400 Hz.
5
0
-5
-10
-15
-20
10
4.4.2 Peak frequency
Figure 5 shows the three possible peak frequencies 400 Hz, 800 Hz and 2.4 kHz.
Figure 5.Loudness center frequencies @ Attn. = 15 dB
5
0
-5
-10
-15
100
1K
10K
-20
10
100
1K
10K
17/40
Description of the audio processorTDA7419
4.4.3 Low and high frequency boost
Figure 6 shows the different loudness shapes in low and high frequency boost.
Figure 6.Loudness attenuation, f
5
0
-5
-10
-15
-20
10
4.4.4 Flat mode
100
= 2.4 kHz
C
1K
10K
In flat mode the loudness stage works as a 0 dB to -15 dB attenuator.
4.5 Soft-mute
The digitally controlled soft-mute stage allows muting/demuting the signal with a I2C bus
programmable slope. The mute process can either be activated by the soft-mute pin or by
2
the I
C bus. This slope is realized in a special S-shaped curve to mute slow in the critical
regions (see Figure 7).
For timing purposes the bit 0 of the I
until the end of demuting.
2
C bus output register is set to 1 from the start of muting
18/40
TDA7419Description of the audio processor
Figure 7.Soft-mute timing
1
EXT.
MUTE
+SIGNAL
REF
-SIGNAL
1
2
I
C BUS
OUT
D97AU634
Time
1. Please notice that a started mute-action is always terminated and could not be interrupted by a change of
the mute -signal
4.5.1 Soft-step volume
When the volume level is changed audible clicks could appear at the output. The root cause
of those clicks
could either be a DC-Offset before the volume-stage or the sudden change of the envelope
of the audiosignal. With the soft-step feature both kinds of clicks could be reduced to a
minimum and are no more audible. The blend-time from one step to the next is
programmable in four steps.
Figure 8.Soft-step timing
V
OUT
1dB
0.5dB
SS Time
-0.5dB
-1dB
D00AU1170
1. For steps more than 0.5dB the Soft-step mode should be deactivated because it could generate a hard
1dB step during the blend-time.
Time
4.6 Bass
There are four parameters programmable in the bass stage:
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Description of the audio processorTDA7419
4.6.1 Attenuation
Figure 9 shows the attenuation as a function of frequency at a center frequency of 80 Hz.
Figure 9.Bass control @ f
15.0
10.0
5.0
dB
0.0
-5.0
-10.0
-15.0
10.0100.01.0K10.0K
= 80 Hz, Q = 1
C
Hz
20/40
TDA7419Description of the audio processor
4.6.2 Center frequency
Figure 10 shows the four possible center frequencies 60, 80, 100 and 200 Hz.
Figure 10. Bass center frequencies @ gain = 15 dB, Q = 1
16
12
8
4
0
-4
10
4.6.3 Quality factors
Figure 11 shows the four possible quality factors 1, 1.25, 1.5 and 2.
Figure 11. Bass quality factors @ gain = 14 dB, f
15.0
12.5
10.0
7.5
5.0
2.5
100
1K
= 80 Hz
C
10K
0.0
10.0100.01.0K10.0K
21/40
Description of the audio processorTDA7419
4.6.4 DC mode
It is used for cut only for shelving filter. In this mode the DC gain is increased by 4.4 dB. In
addition the programmed center frequency and quality factor is decreased by 25 % which
can be used to reach alternative center frequencies or quality factors.
Figure 12. Bass normal and DC mode @ gain = 14 dB, f
1. The center frequency, Q and DC-mode can be set fully independently.
4.7 Middle
There are three parameters programmable in the middle stage:
= 80 Hz
C
15.0
12.5
10.0
7.5
5.0
2.5
0.0
10.0100.01.0K10.0K
4.7.1 Attenuation
Figure 13 shows the attenuation as a function of frequency at a center frequency of 1 kHz.
Figure 13. Middle control @ f
22/40
= 1 kHz, Q = 1
C
TDA7419Description of the audio processor
4.7.2 Center frequency
Figure 14 shows the four possible center frequencies 500 Hz, 1 kHz, 1.5 kHz and 2.5 kHz.
Figure 14. Middle center frequencies @ gain = 14 dB, Q = 1
4.7.3 Quality factors
Figure 15 shows the four possible quality factors 0.5, 0.75, 1 and 1.25.
Figure 15. Middle quality factors @ gain = 14 dB, fc = 1 kHz
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Description of the audio processorTDA7419
4.8 Treble
There are two parameters programmable in the treble stage:
4.8.1 Attenuation
Figure 16 shows the attenuation as a function of frequency at a center frequency of 17.5 kHz.
Figure 16. Treble control @ fC = 17.5 kHz
20
15
10
5
0
-5
-10
-15
-20
10
4.8.2 Center frequency
Figure 17 shows the four possible center frequencies 10k, 12.5k, 15k and 17.5 kHz.
Figure 17. Treble center frequencies @ gain = 15 dB
20
15
10
5
0
100
1K
10K
-5
10
100
24/40
1K
10K
TDA7419Description of the audio processor
4.9 Subwoofer filter
The subwoofer lowpass filter has butterworth characteristics with programmable cut-off
frequency (80/120/160 Hz)
Figure 18. Subwoofer control
4.10 Spectrum analyzer
A fully integrated seven-band spectrum analyzer with programmable quality factor is
present. The spectrum analyzer consists of seven band pass filters with rectifier and sample
capacitor that stores the maximum peak signal level since the last read cycle. This peak
signal level can be read by a microprocessor at the SAout pin. To allow easy interfacing to
an analog port of the microprocessor, the output voltage at this pin is referred to device
ground.
The microprocessor starts a read cycle with the negative going clock edge at the SAclk
input. On the following positive clock edges, the peak signal level for the band pass filters is
subsequently switched to SAout. Each analog output data is valid after the time t
reset of the sample capacitors is induced whenever SAclk remains high for the time t
Note that a proper reset requires the clock signal SAclk to be held at high potential. Figure
20 shows the block diagram and figure 21 illustrates the read cycle timing of the spectrum
analyzer.
Figure 19. Spectrum analyzer block diagram
Sadel
. A
intres
.
25/40
Description of the audio processorTDA7419
Figure 20. Timing of the spectrum analyzer
4.11 AC coupling
In some applications additional signal manipulations are desired, such as additional band
equalizations. For this purpose, an AC coupling can be placed before the loudness
attenuator or speaker-attenuators, which can be activated or internally shorted by I
In short condition, the input-signal of the speaker-attenuator is available at the AC outputs.
The input-impedance of this AC inputs is 50 kΩ.
2
C bus.
Figure 21. Diagram of AC coupling
ACOUTRACOUTL
From Input MUX
InGain
Filters
ACINL
ACINR
Speakers
To Output
26/40
TDA7419Description of the audio processor
4.12 HPF applications
For HPF applications, HPF filter is available for additional processing after the speaker
control. It is a 2
nd
order butterworth highpass filter with selectable flat mode. Figure 22
shows the diagram of the HPF that includes an external RC network.
Figure 22. HPF diagram
External RC network
ACOUT
/AC2OUT
From speaker
SE3IN
/AC2IN
4.13 Output selector and mixing
ACIN
/FILO
Gain Control
To
output
The output-selector allows the front and rear speakers to connect to different sources. The
setup of the output selector is shown in Figure 24. A Mixing-stage is placed after the front
speaker-attenuator and can be set to mixing-mode. Having a full volume-attenuator for the
mix-signal, the stage offers a wide flexibility to adapt the mixing levels.
Figure 23. Output selector
Mix_in
Main
Second
BassL+BassR
Attenuator
Attenuator
Attenuator
Subwoofer
filter
Attenuator
Front
Rear
Subwoofer
output
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Description of the audio processorTDA7419
4.14 Audioprocessor testing
In the test mode, which can be activated by setting bit D7 of the IIC subaddress byte and bit
D0 of the testing audioprocessor byte, several internal signals are available at the SE1R pin.
In this mode, the input resistance of 100kOhm is disconnected from the pin. Internal signals
available for testing are listed in the data-byte specification.
4.15 Test circuit
Figure 24. Test circuit
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TDA7419I2C bus specification
5 I2C bus specification
5.1 Interface protocol
The interface protocol comprises:
●a start condition (S)
●a chip address byte (the LSB determines read/write transmission)
●a subaddress byte
●a sequence of data (N-bytes + acknowledge)
●a stop condition (P)
●the max. clock speed is 500 kbits/s
●3.3 V logic compatible
5.1.1 Receive mode
S 1 0 0 0 1 0 0 R/W ACK TS AZ AI A4 A3 A2 A1 A0 ACK DATA ACK P
S = Start
R/W = "0" -> Receive Mode (Chip can be programmed by μP)
"1" -> Transmission Mode (Data could be received by μP)
ACK = Acknowledge
P = Stop
TS = Testing mode
AZ = AutoZero remain
AI = Auto increment
5.1.2 Transmission mode
S1000100R/WACKXXXXXXXSMACKP
SM = Soft-mute activated for main channel
X = Not Used
The transmitted data is automatic updated after each ACK. Transmission can be repeated
without new chip address.
5.1.3 Reset condition
A Power on reset is invoked if the supply voltage is below than 3.5 V. After that the following
data is written automatically into the registers of all subaddresses:
DC Coupling (without HPF)
AC coupling after In gain
DC Coupling (with HPF)
AC coupling after Bass
Table 19.Testing audio processor (17)
MSBLSB
D7D6D5D4D3D2D1D0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
x
x
x
x
x
x
x
x
Function
Audio processor testing mode
off
on
Test multiplexer
Left In gain
Left In gain
Left Loudness
Left Loudness
Left Volume
Left Volume
Left Treble
Left Treble
Left Middle
SMCLK
Left Bass
VrefSCR
VGB1.26
SSCLK
Clock200
Mon
Ref5V5
BPout<1>
BPout<2>
BPout<3>
BPout<4>
BPout<5>
BPout<6>
BPout<7>
xxNot used
37/40
Package informationTDA7419
6 Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
®
packages, depending on their level of environmental compliance. ECOPACK
®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK
®
is an ST trademark.
Figure 25. SO-28 mechanical data and package dimensions
DIM.
A2.650.104
a10.10.30.0040.012
b0.350.49 0.0140.019
b10.230.32 0.0090.013
C0.50.020
c145° (typ.)
D17.718.1 0.6970.713
E1010.65 0.3940.419
e1.270.050
e316.510.65
F7.47.60.2910.299
L0.41.27 0.0160.050
S8
mminch
MIN. TYP. MAX. MIN. TYP. MAX.
(max.)
°
OUTLINE AND
MECHANICAL DATA
SO-28
38/40
TDA7419Revision history
7 Revision history
Table 20.Document revision history
DateRevisionChanges
20-Nov-20041Initial release.
16-Mar-20052Inserted new values in electrical characteristics table.
10-Jun-20053Modified the figure 2 block diagram.
08-Oct-20054Minor correction
13-Dec-20055Updated “Absolute maximum ratings” table 3 and “Supply” table 2.
13-Feb-20096
Document reformatted.
Updated Section 6: Package information on page 38.
39/40
TDA7419
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