ST TDA7266D User Manual

5W+5W DUAL BRIDGE AMPLIFIER

■ WIDE SUPPLY VOLTAGE RA NGE (3 .5 - 12V)

■ OUTPUT POWER

5+5W @THD = 10%, R

■ SINGLE SUPPLY

■ MINIMUM EXTERNAL COMPONENTS

– NO SVR CAPACITOR – NO BOOT STRAP – NO BOUCHEROT CELLS – INTERNALLY FIXED GAIN

■ STAND-BY & MUTE FUNCTIONS

■ SHORT CIRCUIT PROTECTION

■ THERMAL OVERLOAD PROTECTION

DESCRIPTION

The TDA7266D is a dual bridge amplifier specially

= 8Ω, VCC = 9.5V

L

TDA7266D

PRELIMINARY DATA

TECHNOLOGY BI20II

PowerSO20 Slug Down

ORDERING NUMBER: TDA7266D

designed for LCD TV/Monitor, PC Motherboard, TV and Portable Audio applications.

TEST AND APPLICATION CIRCUIT

V

CC

R1

47K

+5V

JP1

R2

47K

ST-BY

MUTE

IN1

R3 10K

IN2

R4 10K

PW-GND

C3 0.22µF

C4

10µF

C5 0.22µF

C6

1µF

S-GND

7

13

9

14

8

1 10 11 20

Vref

156

+

-

+

-

+

2

5

19

16

C1

470µFC2100nF

OUT1+

OUT1-

OUT2+

OUT2-

D02AU1407

C7

100nF

May 2003

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

1/13

TDA7266D

ABSOLUTE MAXIMUM RATINGS

Symbol Parameter Value Unit

Supply Voltage 20 V

s

Output Peak Current (internally limited) 1.5 A Total Power Dissipation (T Operating Temperature 0 to 70 °C Storage and Junction Temperature -40 to 150 °C

= 70°C 25 W

amb

P T

T

stg, Tj

V

I

O

tot

op

THERMAL DATA

Symbol Parameter Value Unit

R

th j-case

R

th j-amb

Notes: 1. See Application note AN668, available on WEB FR4 with 15 via holes and ground layer.

Thermal Resistance Junction-case 2.1 °C/W Thermal Resistance Junction-ambient (on recomended PCB) note1 15 °C/W

PIN CONNECTION

2/13

PW GND

OUT1+

N.C. N.C.

OUT1-

V

CC

IN1 MUTE ST BY N.C.

1 2 3 4 5 6 7 8 9

PW GND 10

D02AU1408

20 19 18 17 16 15 14 13 12 11 PW GND

PW GND OUT2+ N.C. N.C. OUT2-

CC

V IN2SGND

TDA7266D

ELECTRICAL CHARACTERISTCS

(Refer to test circuit) VCC = 9.5V, RL = 8Ω, f = 1KHz, T

= 25°C unless

amb

otherwise specified)

Symbol Parameter Test Condition Min. Typ. Max. Unit

V

P

THD Total Harmonic Distortion PO = 1W 0.05 0.2 %

SVR Supply Voltage Rejection f = 100Hz, VR =0.5V 40 56 dB

CT Crosstalk 46 60 dB

A

MUTE

G

∆G

Supply Range 3.5 9.5 12 V

CC

Total Quiescent Current 50 60 mA

I

q

Output Offset Voltage 120 mV

OS

Output Power THD 10% 4.3 5 W

O

PO = 0.1W to 2W

1%

f = 100Hz to 15KHz

Mute Attenuation 60 80 dB Thermal Threshold 150 °C

T

w

Closed Loop Voltage Gain 25 26 27 dB

V

Voltage Gain Matching 0.5 dB

V

R

Input Resistance 25 30 KΩ

i

VT

I

MUTE

ST-BY

e

N

Mute Threshold for VCC > 6.4V; Vo = -30dB 2.3 2.9 4.1 V

for VCC < 6.4V; Vo = -30dB VCC/2-1VCC/2

-0.75

VCC/2

-0.5

V

St-by Threshold 0.8 1.3 1.8 V St-by Current V6 = GND 100 µA Total Output Voltage A Curve 150 µV

3/13

TDA7266D

APPLICATIVE SUGGESTIONS

STAND-BY AND MUTE FUNCTIONS

(A) Microprocessor Application

In order to avoid annoying "Pop-Noise" during Turn-On/Off transients, it is necessary to guarantee the right Stby and mute signals sequence.It is quite simple to obtain this function using a microprocessor (Fig. 1 and 2).

µ

At first St-by signal (from ponentially. The external RC network is intended to turn-on slowly the biasing circuits of the amplifier, this to avoid "POP" and "CLICK" on the outputs.

When this voltage reaches the St-by threshold level, the amplifier is switched-on and the external capacitors in series to the input terminals (C1, C3) start to charge.

It's necessary to mantain the mute signal low until the capacitors are fully charged, this to avoid that the device goes in play mode causing a loud "Pop Noise" on the speakers.

A delay of 100-200ms between St-by and mute signals is suitable for a proper operation.

Figure 1. Microprocessor Application

P) goes high and the voltage across the St-by terminal (Pin 9) starts to increase ex-

V

CC

C5

470µFC6100nF

OUT1+

ST-BY

IN1

C1 0.22µF

R1 10K

C2

10µF

7

9

+

-

156

2

µP

MUTE

IN2

R2 10K

PW-GND

S-GND

C3 0.22µF

C4

1µF

13

OUT1-

Vref

14

8

1 10 11 20

-

+

-

+

5

19

OUT2+

16

OUT2-

D02AU1409

4/13

Figure 2. Microprocessor Dri ving Sig nals

+VS(V)

+18

V

IN

(mV)

V

ST-BY

pin 9

1.8

1.3

0.8

V

MUTE

pin 8

4.1

2.9

2.3

TDA7266D

I

q

(mA)

V

OUT

(V)

OFF

ST-BY

MUTE

PLAY MUTE ST-BY

OFF

D02AU1411

B) Low Cost Application

In low cost applications where the mP is not present, the suggested circuit is shown in fig.3. The St-by and mute terminals are tied together and they are connected to the supply l ine via an external v oltage

divider. The device is switched-on/off from the supply line and the external capacitor C4 is intended to delay the St-by

and mute threshold exceeding, avoiding "Popping" problems. So to avoid any popping or clicking sond, it is important to clock:

a Correct Sequenc e: At turn-ON, the Stand-by m ust be removed a t first, then the Mut e must be re-

leased after a delay of abo ut 100-200ms . On the contra ry at turn-OFF the M ute must be a ctivated as first and then the Stand-by. With the values suggested in the Application circuit the right operation is guaranteed.

b Correct Threshold Voltages: In order to avoid that due to the spread in the internal thresholds (see

the above li mits) a wrong external voltage causes unc ertain c om mu tations for t he tw o f unct ions we suggest to use the following values:

Mute for Vcc>6.4V : VT = 2.3V Mute for Vcc<6.4V : VT = Vcc/2 - 1 Stand-by : VT = 0.8V

5/13

TDA7266D

Figure 3. Stand-alone low-cost Application

V

CC

R1

47K

R2

47K

C4

10µF

C3 0.22µF

IN1

C5 0.22µF

IN2

PW-GND

ST-BY

S-GND

MUTE

7

9

13

Vref

14

8

1 10 11 20

156

+

-

+

-

+

2

5

19

16

C1

470µFC2100nF

OUT1+

OUT1-

OUT2+

OUT2-

D02AU1410

C7

100nF

PCB Layout and External Components:

Regarding the PCB layout care must be taken for three main subjects:

c) Signal and Power Gnd separation d) Dissipating Copper Area e) Filter Capacitors positioning

)Signal and Power Gnd separation:

c To the Signal GND must be referred the A udio Input Signals, the M ute and Stand-by Voltage s and

the device PIN.13. This Gnd path must be as clean as possible in order to improve the device THD+Noise and to avoid spurious oscillations across the speakers. The Power GND is directly connected to the Output power Stage transistors (Emitters) and is crossed by large amount of current, this path is also used in this device to dissipate the heating generated (no needs of external heatsinker). Referring to the typical application circuit, the separation between the two GND paths must be obtained connecting them separately (star routing) to the bulk Electrolithic capacitor C1 (470µF). Regarding the Power Gnd dimensioning we have to consider the Dissipated Power the Thermal Protection Threshold and the Package thermal Characteristics.

6/13

TDA7266D

d Dissipating Copper Area:

Dissipated Power: The max dissipated power happens for a THD near 1% and is given by the formula:

2

V

P

dmax W()

This gives for: Vcc = 9.5V, Rl = 8Ω ,Iq = 50mA a dissipated power of Pd = 5W.

Thermal Protection: The thermal protection threshold is placed at a junction temperature of 150°C.

Package Thermal Characteristics: The thermal resistance Junction to Ambient obtainable with a GND copper Area of 3x3 cm and with 16 via

holes (see picture) is about 15°C/W. This means that with the above mentioned max dissipated Power (Pd=5W) we can expect a 75°C, this gives a safety margin before the thermal protection intervention in the consumer environments where a 50°C ambient is specified as maximum

2

------------- - IqVCC+⋅= π

CC 2Rl

----- -

2

The Thermal constraints determine the max supply voltage that can be used for the different Load Impedances, this in order to avoid the thermal Protection Intervention.

The max. dissipate d powe r must be not i n exce ss of 5W , this at turns giv es the follow ing operating s upply voltages:

Load (Ohm) Supply Voltage (V)

4 6.5 6 8.5 8 9.5 16 14

e Filter Capacitors Positioning:

The two Ceramic capacitors C2/C7 (100nF) must be placed as close as possible respectively to the two Vcc pins ( 6 - 15) in order to avoid the possibiltiy of oscillations arising on the output Audio signals.

Package Informations:

You can find a complete description for the PowerSO package into the APPLICATION NOTE AN668 available on web.

Here we want to focalize the attention only on the the Dissipating elements and ground layer.

7/13

TDA7266D

Considering the dissipated power involved in the TDA7266D application that is in the range of 5W, as explained in a previous section, we suggest via holes ( see fig. 4).

Using via holes a more direct thermal path is obtained from the slug to the ground layer.The number of vias is chosen accordingly to the desired performance (in our demonstration board we use 15 vias).

In fig.4 is shown as an example the footprint to be used to create the vias.

Figure 4.

The above metioned mounting solution is enough to dissipate the power involved In the most part of the application using the TDA7266D. If necessary a further improvement in the Rth J-Ambient can be obtained as shown in fig.5 where the

PowerSO20 is soldered onto a via hole structure with a metal plate glued on the opposite side of the board.

Figure 5. Mounting on epoxy FR4 using via Holes for heat transfer and external metal plate

8/13

TDA7266D

Figure 6. Dis to rti on v s Frequency

THD(%)

10

Vcc = 9.5 V

1

0.1

0.010

Rl = 8 ohm

Pout = 100mW

Pout = 2W

100 1k 10k 20k

frequency (Hz)

Figure 7. Gain vs Frequency

Level(dBr)

5.0000

4.0000

3.0000

2.0000

1.0000

0.0

-1.000

-2.000

-3.000

-4.000

-5.000 10 100 1k 10k 100 k

Vcc = 9.5V Rl = 8 ohm Pout = 1W

frequency (Hz)

Figure 9. Sta nd- By attenuati on vs Vpin 9

Atte nu a tio n (d B )

10

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4

V p in .7 ( V )

Figure 10.

Quiesc ent Cur rent vs Supp ly Voltage

Iq (mA)

70 65 60 55 50 45 40 35 30

3456789101112

Vsupply(V)

Fig u re 8. M u te At tenuation vs Vpin.8

Attenuation (dB)

10

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

11.522.533.544.55

Vpin.6(V)

Figure 11. Total Power Dissipation & Efficiency vs Pout

Pd(W)

6

5

4

3

2

1

0

Vcc= 9.5V

Rl = 8 ohm

f=1KHZ

2 Channels

2345

1

2345

2 X Pout (W)

70

Eff(%)

60

50

40

30

20

10

9/13

TDA7266D

Figure 12. THD+N vs Output Power Figure 13. THD+N vs Output Power

THD(%)

10

THD(%)

5

Vcc=9.5V

2

2 1

1

0.5

0.2

0.1

100m 6200m 300m 500m 700m 1 2 3 4 5

Vcc=9.5V Rl=8ohm

Rl=8ohm

f=1KHz

Pout(W)

Figure 14. PC Board Component Layout

THD(%)

10

5

2

1

0.5

0.2

0.1

0.05

0.02

0.01

0.01 100m 5200m 300m 500m 700m 1 2 3 4

100m 5200m 300m 500m 700m 1 2 3 4

Vcc=12V

Rl=16 ohm

f = 1K Hz

Pout(W)

10/13

Figure 15. Evaluation Board Top Layer Layout

TDA7266D

Figure 16. Evaluation Board Bottom Layer Layout

11/13

TDA7266D

DIM.

MIN. TYP. MAX. MIN. TYP. MAX.

mm inch

A 3.6 0.142 a1 0.1 0.3 0.004 0.012 a2 3.3 0.130 a3 0 0.1 0.000 0.004

b 0.4 0.53 0.016 0.021

c 0.23 0.32 0.009 0.013

D (1) 15.8 16 0.622 0.630

D1 9.4 9.8 0.370 0.386

E 13.9 14.5 0.547 0.570

e 1.27 0.050 e3 11.43 0.450

E1 (1) 10.9 11.1 0.429 0.437

E2 2.9 0.114 E3 5.8 6.2 0.228 0.244

G 0 0.1 0.000 0.004

H 15.5 15.9 0.610 0.626

h 1.1 0.043

L 0.8 1.1 0.031 0.043

N 8˚ (typ.)

S 8˚ (max.)

T 10 0 .394

(1) “D and E1” do not include mold flash or protusions.

- Mold flash or protusions shall not exceed 0.15m m (0. 006”)

- Critical dimensions: “E”, “G” and “a3”.

OUTLINE AND

MECHANICAL DA TA

Weight:

1.9gr

JEDEC MO-166

PowerSO20

E2

NN

a2

b

h x 45

DETAIL A

e3

H

D

T

110

e

1120

E1

A

DETAIL B

PSO20MEC

R

lead

a3

Gage Plane

BOTTOM VIEW

E

DETAIL B

0.35

S

D1

L

c

a1

DETAIL A

slug

- C -

SEATING PLANE

GC

(COPLANARITY)

E3

0056635

12/13

TDA7266D

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implic ation or otherwise under any patent or patent r i ghts of STM i croelectr oni cs. Specifications mentioned in thi s publicati on are subj ect to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics product s are not authorized for use as cri tical comp onents in lif e support devi ces or systems without express written approval of STMicroelectronics.

The ST logo is a registered trademark of STMicroelectronics

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ST TDA7266D User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual