ST STW82103B User Manual

STW82103B

RF down converter with embedded integer-N synthesizer

Features

■High linearity:

–IIP3: +25 dBm

–2FRF-2FLO spurious rejection: 80 dBc

■Noise figure:

–NF: 10.5 dB

■Conversion gain

–CG: 8 dB

■RF range: 2300 MHz to 2700 MHz

■Wide IF amplifier frequency range: 70 MHz to 400 MHz

■Integrated RF balun with internal matching

■Dual differential integrated VCOs with automatic center frequency calibration:

–LOA: 2200 to 2550 MHz

–LOB: 2500 to 3000 MHz

Datasheet −production data

Applications

■Cellular infrastructure equipment:

–IF sampling receivers

–Digital PA linearization loops

■Other wireless communication systems.

Table 1.	Device summary
Part number		Package	Packaging
STW82103B		VFQFPN-44	Tray
STW82103BTR		VFQFPN-44	Tape and reel

■ Embedded integer-N synthesizer

Description

–Dual modulus programmable prescaler (16/17 or 19/20)

–Programmable reference frequency divider (10 bits)

–Adjustable charge pump current

–Digital lock detector

–Excellent integrated phase noise

–Fast lock time: 150 µs

■Integrated DAC with dual current output

■Supply: 3.3 V and 5 V analog, 3.3 V digital

■Dual digital bus interface: SPI and I2C bus (fast mode) with 3 bit programmable address (1101A2A1A0)

■Process: 0.35 µm BICMOS SiGe

■Operating temperature range -40 to +85oC

■44-lead exposed pad VFQFPN package 7x7x1.0 mm

The STMicroelectronics STW82103B is an integrated down converter providing 8 dB of gain, 10.5 dB NF, and a very high input linearity by means of its passive mixer.

Embedding two wide band auto calibrating VCOs and an integer-N synthesizer, the STW82103B is suitable for both Rx and Tx requirements for Cellular infrastructure equipment.

The integrated RF balun and internal matching permit direct 50 ohm single-ended interface to RF port. The IF output is suitable for driving 200-ohm impedance filters.

By embedding a DAC with dual current output to drive an external PIN diode attenuator, the STW82103B replaces several costly discrete components and offers a significant footprint reduction.

The STW82103B device is designed with STMicroelectronics advanced 0.35 µm

SiGe process. Its performance is specified over a -40 °C to +85 °C temperature range.

April 2012

Doc ID 018517 Rev 2

1/67

This is information on a product in full production.

www.st.com

Contents	STW82103B

Contents

1	Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. 7
2	Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		8
3	Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		11
4	Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		12
5	Test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		14
6	Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		15
7	Typical performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .		20
8	General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		23
	8.1	Circuit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	23

8.1.1 Reference input stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 8.1.2 Reference divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 8.1.3 Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 8.1.4 A and B counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 8.1.5 Phase frequency detector (PFD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 8.1.6 Lock detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 8.1.7 Mute until lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 8.1.8 Charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 8.1.9 Voltage controlled oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 8.1.10 Output stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 8.1.11 External VCO buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 8.1.12 Mixer and IF amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 8.1.13 Dual output current DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

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STW82103B Contents

9	I2C bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		33
	9.1	I2C general features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	33

9.1.1 Data validity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 9.1.2 START and STOP conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 9.1.3 Byte format and acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 9.1.4 Device addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 9.1.5 Single-byte write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 9.1.6 Multi-byte write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 9.1.7 Current byte address read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

9.2	I2C timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		36
	9.2.1	Data and clock timing specification . . . . . . . . . . . . . . . . . . . . . . . . . . . .	36
	9.2.2	I2C START and STOP timing specification . . . . . . . . . . . . . . . . . . . . . .	36
	9.2.3	I2C acknowledge timing specification . . . . . . . . . . . . . . . . . . . . . . . . . .	37

9.3 I2C registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

9.3.1 I2C register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 9.3.2 I2C register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

9.4 Device calibration through the I2C interface . . . . . . . . . . . . . . . . . . . . . . . 45

9.4.1 VCO calibration procedure (I2C interface) . . . . . . . . . . . . . . . . . . . . . . . 45 9.4.2 Power ON sequence (I2C interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 9.4.3 VCO calibration auto-restart procedure (I2C interface) . . . . . . . . . . . . . 46

10	SPI digital interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		47
	10.1	SPI general features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	47
	10.2	SPI timing specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	49

10.2.1 Data, clock and load timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

10.3 SPI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

10.3.1 SPI register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 10.3.2 SPI register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

10.4 Device calibration through the SPI interface . . . . . . . . . . . . . . . . . . . . . .

53

10.4.1 VCO calibration procedure (SPI interface) . . . . . . . . . . . . . . . . . . . . . . . 53 10.4.2 Power ON sequence (SPI interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 10.4.3 VCO calibration auto-restart procedure (SPI interface) . . . . . . . . . . . . . 54

11	Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		55
	11.1	Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	55
	11.2	Standard Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	57

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Contents			STW82103B
	11.3	Diversity mode operation with same LO frequency . . . . . . . . . .	. . . . . . . 58
	11.4	Diversity mode operation with different LO frequencies . . . . . . . .	. . . . . . 59
	11.5	External VCO standard mode operation . . . . . . . . . . . . . . . . . . .	. . . . . . 60
	11.6	External VCO diversity mode operation with same LO . . . . . . . .	. . . . . . 61
12	Evaluation kit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. . . . . . 62
13	Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. . . . . . 63
14	Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. . . . . 65

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STW82103B	List of tables

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Table 2. Pin list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Table 3. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table 4. Operating conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Table 5. Digital logic levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Table 6. Down converter mixer and IF amplifier electrical characteristics . . . . . . . . . . . . . . . . . . . . 15 Table 7. Pin diode attenuator driver (dual output current DAC) electrical characteristics. . . . . . . . . 16 Table 8. Integer-N synthesizer electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 9. Phase noise performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 10. Current values for CPSEL[2:0] selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 11. VCOA performance against amplitude setting (frequency = 4.6 GHz) . . . . . . . . . . . . . . . . 30 Table 12. VCOB performance against amplitude setting (frequency = 2.8 GHz) . . . . . . . . . . . . . . . . 30 Table 13. Suggested CAP[2:0] values for LO Frequency range mixer. . . . . . . . . . . . . . . . . . . . . . . . 31

Table 14. Linearity performance against IFAMP[1:0] configuration (typical condition) . . . . . . . . . . . . 32 Table 15. I2C data and clock timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Table 16. I2C START and STOP timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Table 17. I2C acknowledge timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Table 18. I2C register list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 19. Address decoder and outputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Table 20. SPI timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Table 21. SPI register list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Table 23. Evaluation kit order code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Table 24. VFQFPN-44 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Table 25. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

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List of figures	STW82103B

List of figures

Figure 1. STW82103B block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 2. STW82103B pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 3. Conversion gain against RF frequency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 4. Noise figure against RF frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 5. IIP3 against RF frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 6. 2RF-2LO response against RF frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 7. LOA (VCOA div. by 2) closed-loop phase noise at 2.38 GHz,

(FSTEP = 200 kHz, ICP = 3 mA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 8. LOB (VCOB div. by 2) closed-loop phase noise at 2.75 GHz,

(FSTEP = 200 kHz, ICP = 3 mA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 9. Reference frequency input buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 10. VCO divider diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 11. PFD diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 12. Loop filter connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 13. VCO typical sub-band characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Figure 14. Data validity waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Figure 15. START and STOP condition waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 16. Byte format and acknowledge waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Figure 17. I2C data and clock waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Figure 18. I2C START and STOP timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Figure 19. I2C acknowledge timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 20. I2C first programming timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Figure 21. SPI input and output bit order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Figure 22. SPI data structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Figure 23. SPI timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Figure 24. SPI first programming timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Figure 25. Typical STW82103B application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Figure 26. Standard mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Figure 27. Diversity mode operation with same LO frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Figure 28. Diversity mode operation with different LO frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Figure 29. External VCO standard mode operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Figure 30. External VCO diversity mode operation with same LO. . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Figure 31. VFQFPN-44 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

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STW82103B	Block diagram

1 Block diagram

Figure 1. STW82103B block diagram

VDD ALC

VSS ALC

I PINDRV1

I PINDRV2

REXT DAC

VDD DAC

VSS DAC

TEST ALC

TEST2

TEST1

VDD IFAMP

VSS IFAMP

VDD_RFESD

DAC

VSS_RFESD

RF_IN

IF

IF_OUTP

RF_VSS

AMP

IF_OUTN

RF_CT

MIXDRV_CT

DBUS_SEL

VDD_MIXDRV

MIX

SDA/DATA

VSS_MIXDRV

DRV

DBUS

SCL/CLK

VDD_DIV

LOAD

VSS_DIV

ADD0

VDD_OUTBUF

VCO

ADD1

ADD2

VSS_OUTBUF

calibrator

LO

DIV2

OUT

CAL_VCO

VDD_DIG

OUTBUFN

VSS_DIG

OUTBUFP

LO/2xLO

LOCK_DET

OUT

VCO

divider

UP

EXTVCO_INP

EXT

BUF

CHP

ICP

DN

LO/VCO

EXTVCO_INN

BUF

REF

divider

VDD_VCO

VCO

VSS_VCO

BUFF

VDD_PLL

VDD_IO

BUF

VSS_PLL

VSS_IO

CAL_VCO

VDD PSCBUF

VSS PSCBUF

VCTRL

REF CLK

EXT PD

VDD CP

VSS CP

REXT CP

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Pin description	STW82103B

2 Pin description

Figure 2. STW82103B pin configuration

44			43			42			41			40			39			38			37			36			35			34

I PINDRV2

I PINDRV1

VDD MIXDRV

VDD ALC

MIXDRV CT

VDD RFESD

RF IN

RF CT

TEST ALC

TEST1

TEST2

1

VDD_DAC

2

REXT_DAC

3

VDD_DIV

4

VDD_VCO

5

EXTVCO_INN

STW82103B

6

EXTVCO_INP

VFQFPN44

7

EXT_PD

8

ADD2

9

ADD1

VDD_IFAMP 33

IF_OUTP 32

IF_OUTN 31

NC 30

LOAD 29

SCL/CLK 28

SDA/DATA 27

VDD_DIG 26

DBUS_SEL 25

10 ADD0

11 VDD_IO

	VDD PSCBUF		NC			NC			VDD OUTBUF			OUTBUFN				OUTBUFP			VCTRL			ICP			REXT CP		VDD CP			LOCK DET
12			13			14			15			16			17			18			19			20			21			22

VDD_PLL 24

REF_CLK 23

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	STW82103B			Pin description
	Table 2.	Pin list
	Pin No	Name	Description	Observation
	1	VDD_DAC	DAC power supply	Vsupply analog1= 3.3 V
	2	REXT_DAC	External resistance connection for DAC	-
	3	VDD_DIV	Divider by 2 power supply	Vsupply analog1= 3.3 V
	4	VDD_VCO	VCOs and External VCO Buffer power supply	Vsupply analog1= 3.3 V
				Diversity Slave Mode and External
	5	EXTVCO_INN	External VCO (LO) negative input	VCO Modes; otherwise it must be
				connected to GND
				Diversity Slave Mode and External
	6	EXTVCO_INP	External VCO (LO) positive input	VCO Modes; otherwise it must be
				connected to GND
	7	EXT_PD	Hardware power down:	CMOS Input
			‘0’ device ON; ‘1’ device OFF
	8	ADD2	I2CBUS address select pin	CMOS Input
	9	ADD1	I2CBUS address select pin	CMOS Input
	10	ADD0	I2CBUS address select pin	CMOS Input
	11	VDD_IO	Digital IO power supply	Vsupply digital = 3.3 V
	12	VDD_PSCBUF	Prescaler input buffer power supply	Vsupply analog1= 3.3 V
	13	NC	Not connected	-
	14	NC	Not connected	-
	15	VDD_OUTBUF	Power supply for LO buffer	Vsupply analog1= 3.3 V
	16	OUTBUFN	LO Output buffer negative output	Open collector @ 3.3 V
	17	OUTBUFP	LO Output buffer positive output	Open collector @ 3.3 V
	18	VCTRL	Control voltage for VCOs	-
	19	ICP	PLL charge pump output	-
	20	REXT_CP	External resistance connection for PLL charge	-
			pump current
	21	VDD_CP	Power supply for charge pump	Vsupply analog1= 3.3 V
	22	LOCK_DET	Lock detector	CMOS Output
	23	REF_CLK	Reference frequency input	-
	24	VDD_PLL	PLL digital power supply	Vsupply analog1= 3.3 V
	25	DBUS_SEL	Digital Bus Interface select	CMOS Input
	26	VDD_DIG	Power supply for digital bus interface	Vsupply digital = 3.3 V
	27	SDA/DATA	I2CBUS /SPI data line	CMOS Bidir Schmitt triggered
	28	SCL/CLK	I2CBUS /SPI clock line	CMOS Input Schmitt triggered
	29	LOAD	SPI load line	CMOS Input Schmitt triggered
	30	NC	Not connected	-
	31	IF_OUTN	IF amplifier negative output	Open collector @ 5 V(1)

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	Pin description			STW82103B
	Table 2.	Pin list (continued)
	Pin No	Name	Description	Observation
	32	IF_OUTP	IF Amplifier positive output	Open collector @ 5 V(1)
	33	VDD_IFAMP	IF Amplifier power supply	Vsupply analog1 = 3.3 V
	34	TEST2	Test input 2	Test purpose only; it must be
				connected to GND
	35	TEST1	Test input 1	Test purpose only; it must be
				connected to GND
	36	TEST_ALC	Test output	Test purpose only; it must be
				connected to GND
	37	RF_CT	RF balun central tap	-
	38	RF_IN	RF input	-
	39	VDD_RFESD	RF ESD positive rail power supply	Vsupply analog1 = 3.3 V
	40	MIXDRV_CT	Mixer driver balun central tap	Vsupply analog2 = 5 V(1)
	41	VDD_ALC	ALC power supply	Vsupply analog1 = 3.3 V
	42	VDD_MIXDRV	Mixer driver power supply	Vsupply analog1 = 3.3 V
	43	I_PINDRV1	DAC current output for external PIN Diode	PMOS Open drain
			attenuator
	44	I_PINDRV2	DAC current output for external PIN Diode	PMOS Open drain
			attenuator
	1. Supply voltage @ 3.3 V in low-current mode operation

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STW82103B			Absolute maximum ratings
3	Absolute maximum ratings
Table 3.	Absolute maximum ratings
	Symbol	Parameter		Values	Unit
AVCC1		Analog supply voltage		0 to 4.6	V
AVCC2		Analog supply voltage		0 to 6	V
DVCC		Digital supply voltage		0 to 4.6	V
Tstg		Storage temperature		+150	°C
		HBM on pins 16, 17, 31, 32		0.8
		HBM on pin 37, 38, 40		1
ESD		HBM on all remaining pins		2	kV
(Electro-static discharge)
		CDM-JEDEC Standard on pin 38, 40		0.25
		CDM-JEDEC Standard on all remaining pins		0.5
		MM		0.2

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Operating conditions	STW82103B

	4	Operating conditions
	Table 4.	Operating conditions
	Symbol	Parameter	Test conditions	Min	Typ	Max	Unit
	AVCC1	Analog Supply voltage	-	3.15	3.3	3.45	V
	AVCC2	Analog Supply voltage	-	4.75	5	5.25	V
	DVCC	Digital Supply voltage	-	3.15	3.3	3.45	V
			Standard mode	-	130	150	mA
			External VCO standard mode	-	110	130	mA
	ICC3.3V	Current Consumption at 3.3 V	Diversity slave mode	-	105	120	mA
			Diversity master mode	-	155	180	mA
			External VCO diversity master	-	145	165	mA
			mode
	ICC5V	Current Consumption	High current mode at 5 V	-	160	185	mA
			Low current mode at 3.3 V	-	90	105	mA
	TA	Operating ambient temperature	-	-40		85	°C
	TJ	Maximum junction temperature	-	-		125	°C
	ΘJA	Junction to ambient package thermal	Multi-layer JEDEC board	-	33	-	°C/W
		(1)
		resistance
	ΘJB	Junction to board package thermal	Multi-layer JEDEC board	-	19	-	°C/W
		(1)
		resistance
	ΘJC	Junction to case package thermal	Multi-layer JEDEC board	-	3	-	°C/W
		(1)
		resistance
	ΨJB	Thermal characterization parameter	Multi-layer JEDEC board	-	18	-	°C/W
		(1)
		junction to board
	ΨJT	Thermal characterization parameter	Multi-layer JEDEC board	-	0.3	-	°C/W
		(1)
		junction to top case

1.Refer to JEDEC standard JESD 51-12 for a detailed description of the thermal resistances and thermal parameters.

Data here presented are referring to a Multi-layer board according to JEDEC standard.

TJ = TA + ΘJA * Pdiss (in order to estimate TJ if ambient temperature TA and dissipated power Pdiss are known) TJ = TB + ΨJB * Pdiss (in order to estimate TJ if board temperature TB and dissipated power Pdiss are known) TJ = TT + ΨJT * Pdiss (in order to estimate TJ if top case temperature TT and dissipated power Pdiss are known)

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Doc ID 018517 Rev 2

STW82103B					Operating conditions
Table 5.	T
	Digital logic levels
Symbol	Parameter		Test conditions	Min	Typ	Max	Unit
Vil	Low level input voltage	-		-	-	0.2*Vdd	V
Vih	High level input voltage	-		0.8*Vdd	-	-	V
Vhyst	Schmitt trigger hysteresis	-		0.8	-	-	V
Vol	Low level output voltage	-		-	-	0.4	V
Voh	High level output voltage	-		0.85*Vdd	-	-	V

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Test conditions	STW82103B

5 Test conditions

Unless otherwise specified the following test conditions are applied:

●Vsupply digital = 3.3 V

●Vsupply analog1 = 3.3 V

●Vsupply analog2 = 5 V

●FIF = 150 MHz

●MIX = 0111

●T ambient = 27 ° C

Refer also to Section 11: Application information.

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STW82103B			Electrical characteristics
6	Electrical characteristics
Note:	Vsupply digital = 3.3 V, Vsupply analog1 = 3.3 V, Vsupply analog2 = 5V, FRF = 2500 MHz,
	FLO = 2350 MHz, TA = +25*C, RF power = 0 dBm, unless otherwise specified.
Table 6.	Down converter mixer and IF amplifier electrical characteristics(1)
	)
Symbol	Parameter	Conditions	Min		Typ	Max	Unit
FRF	RF Frequency	-	2300		-	2700	MHz
FLO	LO Frequency	VCOA divided by 2	2200		-	2550	MHz
		VCOB	2500		-	3000	MHz
FIF	IF Center Frequency(2)	FIF = ABS(FLO-FRF)	70		-	400	MHz
CG	Power Conversion Gain	Rin = 50 ohm, Rout = 200 ohm	7.5		8	8.5	dB
		RFin = 0 dBm
CG T	Power Conversion Gain over	T= -40 to +85 °C	-		±0.7	-	dB
	(3)
	Temperature
IP1dB	Input P1dB	High current Mode	-		14	-	dBm
		Low current Mode	-		8	-
IIP3	Third-order input intercept	High current Mode	23.5		25	-	dBm
	point(4)
		Low current Mode	17.5		19	-
IIP3 T	IIP3 variation over	T= -40 to +85 °C	-		±0.5	-	dB
	(3)
	temperature
		2FRF-2FLO FRFin = -5 dBm,	-		80	-	dBc
nFRF-nFLO	Spurious rejection at IF(3)	FIF = 150 MHz
		3FRF-3FLO FRFin = -5 dBm,	-		76	-	dBc
		FIF = 150 MHz
NFSSB	Noise figure	High-current mode, MIX = 0011	-		10.5	11	dB
		Low-current mode, MIX = 0011	-		10.5	11	dB
-	LO to IF Leakage	1xLO	-		-45	-	dBm
		2xLO			-38
-	LO to RF Leakage	-	-		-28	-	dBm
-	RF to IF Isolation	-	-		58	-	dB
RFRL	RF Return Loss	Matched to 50 ohm	-		20	-	dB
IFRL	IF Return Loss	Matched to 200 ohm	-		22	-	dB
		Maximum deviation from Fc over ±10
		MHz. For any Fc within each TX	-0.05		-	+0.05	dB
-	Gain Flatness for TX	observation path band.
	observation path(5)
		Maximum deviation from Fc over ±30
		MHz. For any Fc within each TX	-0.10		-	+0.10	dB
		observation path band.

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	Electrical characteristics					STW82103B
	Table 6.	Down converter mixer and IF amplifier electrical characteristics(1) (continued)
	Symbol	Parameter	Conditions	Min	Typ	Max	Unit
			Maximum deviation from linear phase
			at Fc over ±10 MHz. For any Fc within	-0.3	-	+0.3	deg
	-	Phase Flatness for TX	each TX observation path band.
		observation path(5)
			Maximum deviation from linear phase
			at Fc over ±30 MHz. For any Fc within	-0.7	-	+0.7	deg
			each TX observation path band.
	-	Gain Flatness for RX path(5)	Maximum ripple over a 4 MHz band.	-	-	0.1	dB
			For any Fc within each RX path band.				pk-pk
	-	Phase Flatness for RX path(5)	Maximum ripple over a 4 MHz band.	-	-	0.6	deg
			For any Fc within each RX path band.				pk-pk
		Mixer Driver Current	3.3 V Supply (pin 41, 42)	-	45	-	mA
		Consumption	5 V Supply (pin 40)	-	55	-	mA
	ICCMD
		Mixer Driver Current	3.3 V Supply (pin 41, 42)	-	20	-	mA
		Consumption (Low Current
			3.3 V Supply (pin 40)	-	35	-	mA
		Mode)
		IFAMP Current Consumption	3.3 V Supply (pin 33)	-	10	-	mA
	ICCIFAM		5 V Supply (pin 31, 32)	-	107	-	mA
		IFAMP Current Consumption	3.3 V Supply (pin 33)	-	6	-	mA
		(Low Current Mode)
			3.3 V Supply (pin 31, 32)	-	55	-	mA

1.All linearity and NF performances are intended at maximum LO amplitude (LO_A[1:0]=[11]), tuning capacitors (CAP[2:0]) programmed according to the selected frequency, mixer bias (MIX[3:0]) set to maximize performance and the device operated in high current mode. The performances of conversion gain, NF and linearity are intended at the SMA connectors of a typical application board.

2.The IF frequency range supported by the IF Amplifier is from 70 to 400 MHz. The exact IF frequency range supported for a specific RF frequency can be calculated as FIF = ABS(FLO-FRF) where FLO is inside the specified LO frequency range.

3.Guaranteed by design and characterization

4.RFin = 0 dBm/tone, RF tone spacing = 5 MHz

5.Guaranteed by design

Table 7.	Pin diode attenuator driver (dual output current DAC) electrical characteristics
Symbol	Parameters	Conditions	Min	Typ	Max		Unit
R	Resolution	-	-	10	-		Bit
DNL	Differential non linearity	-	-0.05	-	0.05		LSB
INL	Integral non linearity	-	-0.45	-	0.45		LSB
IFS	Full Scale current (1)	-	0.28	-	2.8		mA
-	Current Mismatch	-	-	-	2		%
-	Output voltage compliance	-	0	-	3		V
	range
VREXT_DAC	Voltage Reference	-	-	1.19			V
REXT_DAC	REXT DAC Range	-	10	-	100		kΩ
Iccstatic	Static current consumption	(Iout = 0 mA; pin 1)	-	2.5	-		mA

1.See relationship between IDAC and REXT_DAC in the Circuit Description section (Dual Output Current DAC)

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	STW82103B			Electrical characteristics
	Table 8.	Integer-N synthesizer electrical characteristics
	Symbol	Parameter	Conditions	Min	Typ	Max	Unit
	VCO dividers
	N	VCO Divider Ratio (N)	Prescaler 16/17	256	-	65551	-
			Prescaler 19/20	361	-	77836	-
	Reference clock and phase frequency detector
	Fref	Reference input frequency	-	10	19.2	200	MHz
	-	Reference input sensitivity	-	0.35	1	1.5	Vpeak
	R	Reference Divider Ratio	-	2	-	1023
	FPFD	PFD input frequency	-	-	-	16	MHz
			Prescaler 16/17	FLO/	-	FLO/	Hz
	FSTEP	Frequency step (1)		65551		256
			Prescaler 19/20	FLO/	-	FLO/	Hz
				77836		361
	Charge pump
	ICP	ICP sink/source (2)	3bit programmable	-	-	5	mA
	VOCP	Output voltage compliance range	-	0.4	-	Vdd-0.3	V
	-	Spurious(3)	-	-	-70	-	dBc
	VCOs
			Higher frequency range	-	85	-	MHz/V
	KVCOA	VCOA sensitivity	Intermediate frequency	-	75	-	MHz/V
			range
			Lower frequency range	-	65	-	MHz/V
			Higher frequency range	-	85	-	MHz/V
	KVCOB	VCOB sensitivity	Intermediate frequency	-	70	-	MHz/V
			range
			Lower frequency range	-	60	-	MHz/V
	TLKA	VCOA Maximum Temperature	CALTYPE [0]	-	-	100	° C
		variation for continuous lock (4)
			CALTYPE [1]	-	-	125	° C
	TLKB	VCOB Maximum Temperature	CALTYPE [0]	-	-	125	° C
		variation for continuous lock (4)
			CALTYPE [1]	-	-	125	° C
	-	VCO A Pushing	-	-	8	-	MHz/V
		VCO B Pushing	-	-	14	-	MHz/V
	VCTRL	VCO control voltage	-	0.4		Vdd-0.3	V
	-	LO Harmonic Spurious	-	-		-20	dBc
	IVCO	VCO and VCO buffer current	Amplitude [11] (pin 4)	-	35	-	mA
		consumption
	IDIV2	DIVIDER by 2 consumption	(pin 3)	-	20	-	mA

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	Electrical characteristics					STW82103B
	Table 8.	Integer-N synthesizer electrical characteristics (continued)
	Symbol	Parameter	Conditions	Min	Typ	Max	Unit
	2 x LO output buffer (test purpose only)
	FOUT	Frequency range	-	4.4	-	5.1	GHz
	POUT	Output level	-	-	0	-	dBm
	RL	Return Loss	Matched to 50 ohm	-	10	-	dB
	I2LOBUF	Current Consumption	(pin 15, 16, 17)	-	35	-	mA
	LO output buffer
	FOUT	Frequency range	-	2.2	-	3	GHz
	POUT	Output level	-	-	0	-	dBm
	RL	Return Loss	Matched to 50ohm	-	10	-	dB
	ILOBUF	Current Consumption	(pin 15, 16, 17)	-	30	-	mA
	External VCO (LO) buffer
	fINVCO	Frequency range	-	2.2	-	3	GHz
	PIN	Input level	-	-	0	-	dBm
	IEXTBUF	Current Consumption	External VCO Buffer	-	25	-	mA
			(pin 4)
	PLL miscellaneous
			Input Buffer, Prescaler,
	IPLL	PLL Current Consumption	Digital Dividers, misc.	-	8	-	mA
			(pin 24)
	IPRE	Prescaler input buffer Current	(pin 12)	-	3	-	mA
		Consumption
	ICP	Charge Pump Current Consumption	CPSEL=[111], REXT_CP	-	4	-	mA
			= 4.7 kΩ (pin 21)
		Lock up time(5)	25 kHz PLL bandwidth;
	tLOCK		within 1ppm of frequency	-	150	-	µs
			error

1.The frequency step is related to the PFD input frequency as follows: FSTEP=FPFD/2)

2.See relationship between ICP and REXT_CP in the Circuit Description section (Charge Pump)

3.The level of spurs may change depending on PFD frequency, Charge Pump current, selected channel and PLL loop BW.

4.When setting a specified output frequency, the VCO calibration procedure must be run first in order to select the best

subrange for the VCO covering the desired frequency. Once programmed at the initial temperature T0 inside the operating temperature range (-40 ° C to +85 ° C), the synthesizer is able to maintain the lock status if the temperature drift (in either

direction) is within the limit specified by TLK, provided that the final temperature T1 is still inside the nominal range.

5.Frequency jump form 2450 to 2300 MHz; it includes the time required by the VCO calibration procedure (7 x FPFD cycles =17.5 µs with FPFD =400 kHz))

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	STW82103B				Electrical characteristics
	Table 9.	Phase noise performance(1)
	Parameters		Conditions	Min.	Typ.	Max.	Unit
	In band phase noise floor, closed loop(2)
	Normalized In Band Phase Noise			-	-224	-	dBc/Hz
	Floor (LO)
			ICP=4 mA, PLL BW = 50 kHz
	In Band Phase Noise Floor (LO)			-230+20log(N)+10log(FPFD)
	VCOA divided by 2		(including reference clock
			contribution)				dBc/Hz
	In Band Phase Noise Floor (LO)			-224+20log(N)+10log(FPFD)
	VCOB direct
	PLL integrated phase noise
	Integrated Phase Noise		FLO=2.200 GHz, FSTEP=200 kHz,	-	-44.9	-	dBc
	(single sided)
	100 Hz to 40 MHz		ICP=3 mA, PLL BW = 25 kHz	-	0.46	-	° rms
	LOA (2200 MHz to 2550 MHz) – open loop
	Phase Noise @ 1 kHz		-	-	-63	-	dBc/Hz
	Phase Noise @ 10 kHz		-	-	-89	-	dBc/Hz
	Phase Noise @ 100 kHz		-	-	-113	-	dBc/Hz
	Phase Noise @ 1 MHz		-	-	-134	-	dBc/Hz
	Phase Noise @ 10 MHz		-	-	-151	-	dBc/Hz
	Phase Noise Floor @ 40 MHz		-	-	-155	-	dBc/Hz
	LOB (2500 MHz to 3000 MHz) – open loop
	Phase Noise @ 1 kHz		-	-	-64	-	dBc/Hz
	Phase Noise @ 10 kHz		-	-	-91	-	dBc/Hz
	Phase Noise @ 100 kHz		-	-	-113	-	dBc/Hz
	Phase Noise @ 1 MHz		-	-	-134	-	dBc/Hz
	Phase Noise @ 10 MHz		-	-	-153	-	dBc/Hz
	Phase Noise Floor @ 40 MHz		-	-	-162	-	dBc/Hz

1.Phase Noise SSB. VCO amplitude set to maximum value [11]. All the closed-loop performances are specified using a Reference Clock signal at 76.8 MHz with phase noise of -144 dBc/Hz @1 kHz offset, -157 dBc/Hz @10 kHz offset and -168 dBc/Hz of noise floor.

2.Normalized PN = Measured LO PN – 20log(N) – 10log(FPFD) where N is the VCO divider ratio (N=B*P+A) and FPFD is the comparison frequency at the PFD input

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Typical performance characteristics		STW82103B
7	Typical performance characteristics
Note:	Vsupply digital = 3.3 V, Vsupply analog1 = 3.3 V, Vsupply analog2 = 5 V, FIF = 150 MHz,
	TA = +25 °C, RF power = 0 dBm, unless otherwise specified.

Figure 3. Conversion gain against RF frequency

Figure 4. Noise figure against RF frequency

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STW82103B		Typical performance characteristics
	Figure 5.	IIP3 against RF frequency

Figure 6. 2RF-2LO response against RF frequency

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