ST STW82103B User Manual

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RF down converter with embedded integer-N synthesizer

Features

■High linearity:

– IIP3: +25 dBm – 2FRF-2FLO spurious rejection: 80 dBc

■ Noise figure:

– NF: 10.5 dB

■ Conversion gain

– CG: 8 dB

■ RF range: 2300 MHz to 2700 MHz

■ Wide IF amplifier frequency range: 70 MHz to

400 MHz

■ Integrated RF balun with internal matching

■ Dual differential integrated VCOs with

automatic center frequency calibration: – LOA: 2200 to 2550 MHz – LOB: 2500 to 3000 MHz

■ Embedded integer-N synthesizer

– Dual modulus programmable prescaler

(16/17 or 19/20)

– Programmable reference frequency divider

(10 bits) – Adjustable charge pump current – Digital lock detector – Excellent integrated phase noise – Fast lock time: 150 µs

■ Integrated DAC with dual current output

■ Supply: 3.3 V and 5 V analog,

3.3 V digital

■ Dual digital bus interface: SPI and I

mode) with 3 bit programmable address (1101A

■ Process: 0.35 µm BICMOS SiGe

■ Operating temperature range -40 to +85

■ 44-lead exposed pad VFQFPN package

2A1A0

)

7x7x1.0 mm

C bus (fast

STW82103B

Datasheet − production data

Applications

■ Cellular infrastructure equipment:

– IF sampling receivers – Digital PA linearization loops

■ Other wireless communication systems.

Table 1. Device summary

Part number Package Packaging

STW82103B VFQFPN-44 Tray

STW82103BTR VFQFPN-44 Tape and reel

Description

The STMicroelectronics STW82103B is an integrated down converter providing 8 dB of gain,

10.5 dB NF, and a very high input linearity by means of its passive mixer.

Embedding two wide band auto calibrating VCOs and an integer-N synthesizer, the STW82103B is suitable for both Rx and Tx requirements for Cellular infrastructure equipment.

The integrated RF balun and internal matching permit direct 50 ohm single-ended interface to RF port. The IF output is suitable for driving 200-ohm impedance filters.

By embedding a DAC with dual current output to drive an external PIN diode attenuator, the STW82103B replaces several costly discrete components and offers a significant footprint reduction.

The STW82103B device is designed with STMicroelectronics advanced 0.35 µm SiGe process. Its performance is specified over a

-40 °C to +85 °C temperature range.

April 2012 Doc ID 018517 Rev 2 1/67

This is information on a product in full production.

www.st.com

Contents STW82103B

Contents

1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

4 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

5 Test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

7 Typical performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

8 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

8.1 Circuit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

8.1.1 Reference input stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

8.1.2 Reference divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

8.1.3 Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

8.1.4 A and B counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

8.1.5 Phase frequency detector (PFD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

8.1.6 Lock detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

8.1.7 Mute until lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

8.1.8 Charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

8.1.9 Voltage controlled oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

8.1.10 Output stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

8.1.11 External VCO buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

8.1.12 Mixer and IF amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

8.1.13 Dual output current DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

2/67 Doc ID 018517 Rev 2

STW82103B Contents

9 I2C bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

9.1 I2C general features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

9.1.1 Data validity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

9.1.2 START and STOP conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

9.1.3 Byte format and acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

9.1.4 Device addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

9.1.5 Single-byte write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

9.1.6 Multi-byte write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

9.1.7 Current byte address read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

9.2 I2C timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

9.2.1 Data and clock timing specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

9.2.2 I

9.2.3 I

9.3 I2C registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

9.3.1 I2C register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

9.3.2 I

C START and STOP timing specification . . . . . . . . . . . . . . . . . . . . . . 36

C acknowledge timing specification . . . . . . . . . . . . . . . . . . . . . . . . . . 37

C register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

9.4 Device calibration through the I2C interface . . . . . . . . . . . . . . . . . . . . . . . 45

9.4.1 VCO calibration procedure (I2C interface) . . . . . . . . . . . . . . . . . . . . . . . 45

9.4.2 Power ON sequence (I

9.4.3 VCO calibration auto-restart procedure (I

C interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

C interface) . . . . . . . . . . . . . 46

10 SPI digital interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

10.1 SPI general features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

10.2 SPI timing specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

10.2.1 Data, clock and load timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

10.3 SPI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

10.3.1 SPI register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

10.3.2 SPI register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

10.4 Device calibration through the SPI interface . . . . . . . . . . . . . . . . . . . . . . 53

10.4.1 VCO calibration procedure (SPI interface) . . . . . . . . . . . . . . . . . . . . . . . 53

10.4.2 Power ON sequence (SPI interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

10.4.3 VCO calibration auto-restart procedure (SPI interface) . . . . . . . . . . . . . 54

11 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

11.1 Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

11.2 Standard Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Doc ID 018517 Rev 2 3/67

Contents STW82103B

11.3 Diversity mode operation with same LO frequency . . . . . . . . . . . . . . . . . 58

11.4 Diversity mode operation with different LO frequencies . . . . . . . . . . . . . . 59

11.5 External VCO standard mode operation . . . . . . . . . . . . . . . . . . . . . . . . . 60

11.6 External VCO diversity mode operation with same LO . . . . . . . . . . . . . . 61

12 Evaluation kit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

13 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

14 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

4/67 Doc ID 018517 Rev 2

STW82103B List of tables

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table 2. Pin list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Table 3. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Table 4. Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Table 5. Digital logic levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Table 6. Down converter mixer and IF amplifier electrical characteristics . . . . . . . . . . . . . . . . . . . . 15

Table 7. Pin diode attenuator driver (dual output current DAC) electrical characteristics. . . . . . . . . 16

Table 8. Integer-N synthesizer electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 9. Phase noise performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 10. Current values for CPSEL[2:0] selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 11. VCOA performance against amplitude setting (frequency = 4.6 GHz) . . . . . . . . . . . . . . . . 30

Table 12. VCOB performance against amplitude setting (frequency = 2.8 GHz) . . . . . . . . . . . . . . . . 30

Table 13. Suggested CAP[2:0] values for LO Frequency range mixer . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 14. Linearity performance against IFAMP[1:0] configuration (typical condition) . . . . . . . . . . . . 32

Table 15. I Table 16. I Table 17. I Table 18. I

Table 19. Address decoder and outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Table 20. SPI timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Table 21. SPI register list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Table 23. Evaluation kit order code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Table 24. VFQFPN-44 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Table 25. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

C data and clock timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

C START and STOP timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

C acknowledge timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

C register list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Doc ID 018517 Rev 2 5/67

List of figures STW82103B

List of figures

Figure 1. STW82103B block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 2. STW82103B pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 3. Conversion gain against RF frequency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 4. Noise figure against RF frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 5. IIP3 against RF frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 6. 2RF-2LO response against RF frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 7. LOA (VCOA div. by 2) closed-loop phase noise at 2.38 GHz,

Figure 8. LOB (VCOB div. by 2) closed-loop phase noise at 2.75 GHz,

Figure 9. Reference frequency input buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 10. VCO divider diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 11. PFD diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 12. Loop filter connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 13. VCO typical sub-band characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 14. Data validity waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 15. START and STOP condition waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 16. Byte format and acknowledge waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 17. I Figure 18. I Figure 19. I

Figure 20. I2C first programming timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Figure 21. SPI input and output bit order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Figure 22. SPI data structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Figure 23. SPI timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Figure 24. SPI first programming timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Figure 25. Typical STW82103B application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Figure 26. Standard mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Figure 27. Diversity mode operation with same LO frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Figure 28. Diversity mode operation with different LO frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Figure 29. External VCO standard mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Figure 30. External VCO diversity mode operation with same LO. . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Figure 31. VFQFPN-44 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

= 200 kHz, ICP = 3 mA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

STEP

= 200 kHz, ICP = 3 mA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

STEP

C data and clock waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

C START and STOP timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

C acknowledge timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

6/67 Doc ID 018517 Rev 2

STW82103B Block diagram

1 Block diagram

Figure 1. STW82103B block diagram

VDD_DAC

VDD_ALC

VSS_ALC

I_PINDRV1

I_PINDRV2

REXT_DAC

VSS_DAC

TEST_ALC

TEST2

TEST1

VDD_IFAMP

VSS_IFAMP

VDD_RFESD

VSS_RFESD

RF_IN

RF_VSS

RF_CT

MIXDRV_CT

VDD_MIXDRV

VSS_MIXDRV

VDD_DIV

VSS_DIV

VDD_OUTBUF VSS_OUTBUF

OUTBUFN

OUTBUFP

EXTVCO_INP

EXTVCO_INN

VDD_VCO

VSS_VCO

VDD_IO

VSS_IO

OUT

LO/2xLO

OUT

EXT LO/VCO BUF

MIX DRV

DIV2

VCO BUFF

CAL_VCO

DAC

VCO

divider

REF

divider

BUF

VCO

calibrator

CAL_VCO

BUF

AMP

DBUS

CHP

IF_OUTP

IF_OUTN

DBUS_SEL

SDA/DATA

SCL/CLK

LOAD

ADD0 ADD1 ADD2

VDD_DIG

VSS_DIG

LOCK_DET

ICP

VDD_PLL

VSS_PLL

VDD_PSCBUF

VSS_PSCBUF

VCTRL

REF_CLK

EXT_PD

VSS_CP

VDD_CP

REXT_CP

Doc ID 018517 Rev 2 7/67

Pin description STW82103B

2 Pin description

Figure 2. STW82103B pin configuration

44 43 42 41 40 39 38 37 36 35 34

VDD_DAC

REXT_DAC

VDD_DIV

VDD_VCO

EXTVCO_INN

EXTVCO_INP

EXT_PD

ADD2

ADD1

ADD0

VDD_IO

RF_IN

RF_CT

VDD_MIXDRV

VDD_ALC

MIXDRV_CT

VDD_RFESD

I_PINDRV1

I_PINDRV2

TEST_ALC

TEST1

TEST2

VDD_IFAMP

IF_OUTP

IF_OUTN

LOAD

STW82103B

VFQFPN44

SCL/CLK

SDA/DATA

VDD_DIG

DBUS_SEL

VDD_PLL

REF_CLK

VDD_PSCBUF

VDD_OUTBUF

OUTBUFN

OUTBUFP

VCTRL

12 13 14 15 16 17 18 19 20 21 22

8/67 Doc ID 018517 Rev 2

ICP

REXT_CP

VDD_CP

LOCK_DET

STW82103B Pin description

Table 2. Pin list

Pin No Name Description Observation

1 VDD_DAC DAC power supply Vsupply analog1= 3.3 V

2 REXT_DAC External resistance connection for DAC -

3 VDD_DIV Divider by 2 power supply Vsupply analog1= 3.3 V

4 VDD_VCO VCOs and External VCO Buffer power supply Vsupply analog1= 3.3 V

Diversity Slave Mode and External

5 EXTVCO_INN External VCO (LO) negative input

6 EXTVCO_INP External VCO (LO) positive input

7 EXT_PD

8 ADD2 I

9 ADD1 I

10 ADD0 I

Hardware power down: ‘0’ device ON; ‘1’ device OFF

CBUS address select pin CMOS Input

11 VDD_IO Digital IO power supply Vsupply digital = 3.3 V

12 VDD_PSCBUF Prescaler input buffer power supply Vsupply analog1= 3.3 V

13 NC Not connected -

VCO Modes; otherwise it must be connected to GND

Diversity Slave Mode and External VCO Modes; otherwise it must be connected to GND

CMOS Input

14 NC Not connected -

15 VDD_OUTBUF Power supply for LO buffer Vsupply analog1= 3.3 V

16 OUTBUFN LO Output buffer negative output Open collector @ 3.3 V

17 OUTBUFP LO Output buffer positive output Open collector @ 3.3 V

18 VCTRL Control voltage for VCOs -

19 ICP PLL charge pump output -

20 REXT_CP

External resistance connection for PLL charge pump current

21 VDD_CP Power supply for charge pump Vsupply analog1= 3.3 V

22 LOCK_DET Lock detector CMOS Output

23 REF_CLK Reference frequency input -

24 VDD_PLL PLL digital power supply Vsupply analog1= 3.3 V

25 DBUS_SEL Digital Bus Interface select CMOS Input

26 VDD_DIG Power supply for digital bus interface Vsupply digital = 3.3 V

27 SDA/DATA I

28 SCL/CLK I

CBUS /SPI data line CMOS Bidir Schmitt triggered

CBUS /SPI clock line CMOS Input Schmitt triggered

29 LOAD SPI load line CMOS Input Schmitt triggered

30 NC Not connected -

31 IF_OUTN IF amplifier negative output Open collector @ 5 V

(1)

Doc ID 018517 Rev 2 9/67

Pin description STW82103B

Table 2. Pin list (continued)

Pin No Name Description Observation

32 IF_OUTP IF Amplifier positive output Open collector @ 5 V

33 VDD_IFAMP IF Amplifier power supply Vsupply analog1 = 3.3 V

34 TEST2 Test input 2

35 TEST1 Test input 1

Test purpose only; it must be connected to GND

(1)

36 TEST_ALC Test output

Test purpose only; it must be connected to GND

37 RF_CT RF balun central tap -

38 RF_IN RF input -

39 VDD_RFESD RF ESD positive rail power supply Vsupply analog1 = 3.3 V

40 MIXDRV_CT Mixer driver balun central tap Vsupply analog2 = 5 V

41 VDD_ALC ALC power supply Vsupply analog1 = 3.3 V

42 VDD_MIXDRV Mixer driver power supply Vsupply analog1 = 3.3 V

43 I_PINDRV1

44 I_PINDRV2

1. Supply voltage @ 3.3 V in low-current mode operation

DAC current output for external PIN Diode attenuator

PMOS Open drain

(1)

10/67 Doc ID 018517 Rev 2

STW82103B Absolute maximum ratings

3 Absolute maximum ratings

Table 3. Absolute maximum ratings

Symbol Parameter Values Unit

AVCC1 Analog supply voltage 0 to 4.6 V

AVCC2 Analog supply voltage 0 to 6 V

DVCC Digital supply voltage 0 to 4.6 V Tstg Storage temperature +150 °C

HBM on pins 16, 17, 31, 32 0.8

HBM on pin 37, 38, 40 1

ESD (Electro-static discharge)

HBM on all remaining pins 2

CDM-JEDEC Standard on pin 38, 40 0.25

CDM-JEDEC Standard on all remaining pins 0.5

MM 0.2

Doc ID 018517 Rev 2 11/67

Operating conditions STW82103B

4 Operating conditions

Table 4. Operating conditions

Symbol Parameter Test conditions Min Typ Max Unit

AVCC1 Analog Supply voltage - 3.15 3.3 3.45 V

AVCC2 Analog Supply voltage - 4.75 5 5.25 V

DVCC Digital Supply voltage - 3.15 3.3 3.45 V

Standard mode - 130 150 mA

External VCO standard mode - 110 130 mA

CC3.3V

Current Consumption at 3.3 V

Diversity slave mode - 105 120 mA

Diversity master mode - 155 180 mA

External VCO diversity master mode

-145165mA

High current mode at 5 V - 160 185 mA

CC5V

Current Consumption

Low current mode at 3.3 V - 90 105 mA

Operating ambient temperature - -40 85 °C

Maximum junction temperature - - 125 °C

Junction to ambient package thermal resistance

Junction to board package thermal resistance

Junction to case package thermal resistance

Thermal characterization parameter junction to board

(1)

Multi-layer JEDEC board - 33 - °C/W

Multi-layer JEDEC board - 19 - °C/W

Multi-layer JEDEC board - 3 - °C/W

Multi-layer JEDEC board - 18 - °C/W

1. Refer to JEDEC standard JESD 51-12 for a detailed description of the thermal resistances and thermal parameters.

Data here presented are referring to a Multi-layer board according to JEDEC standard. T

= TA + ΘJA * Pdiss (in order to estimate TJ if ambient temperature TA and dissipated power Pdiss are known)

= TB + ΨJB * Pdiss (in order to estimate TJ if board temperature TB and dissipated power Pdiss are known)

= TT + ΨJT * Pdiss (in order to estimate TJ if top case temperature TT and dissipated power Pdiss are known)

Thermal characterization parameter junction to top case

(1)

Multi-layer JEDEC board - 0.3 - °C/W

12/67 Doc ID 018517 Rev 2

STW82103B Operating conditions

Table 5. Digital logic levels

Symbol Parameter Test conditions Min Typ Max Unit

Vil Low level input voltage - - - 0.2*Vdd V

Vih High level input voltage - 0.8*Vdd - - V

Vhyst Schmitt trigger hysteresis - 0.8 - - V

Vol Low level output voltage - - - 0.4 V

Voh High level output voltage - 0.85*Vdd - - V

Doc ID 018517 Rev 2 13/67

Test conditions STW82103B

5 Test conditions

Unless otherwise specified the following test conditions are applied:

● Vsupply digital = 3.3 V

● Vsupply analog1 = 3.3 V

● Vsupply analog2 = 5 V

● F

● MIX = 0111

● T ambient = 27 ° C

Refer also to Section 11: Application information.

= 150 MHz

14/67 Doc ID 018517 Rev 2

STW82103B Electrical characteristics

6 Electrical characteristics

Note: Vsupply digital = 3.3 V, Vsupply analog1 = 3.3 V, Vsupply analog2 = 5V, FRF = 2500 MHz,

= 2350 MHz, TA = +25*C, RF power = 0 dBm, unless otherwise specified.

Table 6. Down converter mixer and IF amplifier electrical characteristics

)

Symbol Parameter Conditions Min Typ Max Unit

CG Power Conversion Gain

ΔT

RF Frequency - 2300 - 2700 MHz

VCOA divided by 2 2200 - 2550 MHz

LO Frequency

VCOB 2500 - 3000 MHz

IF Center Frequency

(2)

FIF = ABS(FLO-FRF)70-400MHz

Rin = 50 ohm, Rout = 200 ohm RFin = 0 dBm

Power Conversion Gain over Temperature

(3)

T= -40 to +85 °C - ±0.7 - dB

(1)

7.5 8 8.5 dB

1dB

IIP3

ΔT

nFRF-nFLOSpurious rejection at IF

Input P1dB

Third-order input intercept

(4)

point

IIP3 variation over temperature

(3)

Low current Mode - 8 -

High current Mode 23.5 25 -

Low current Mode 17.5 19 -

T= -40 to +85 °C - ±0.5 - dB

-2FLO F

= 150 MHz

-3FLO F

= 150 MHz

RFin

= -5 dBm,

-80-dBc

-76-dBc

dBm

High-current mode, MIX = 0011 - 10.5 11 dB

High current Mode - 14 -

SSB

Noise figure

Low-current mode, MIX = 0011 - 10.5 11 dB

1xLO - -45 - dBm

- LO to IF Leakage 2xLO -38

- LO to RF Leakage - - -28 - dBm

- RF to IF Isolation - - 58 - dB

RF Return Loss Matched to 50 ohm - 20 - dB

IF Return Loss Matched to 200 ohm - 22 - dB

Maximum deviation from Fc over ±10 MHz. For any Fc within each TX

Gain Flatness for TX observation path

(5)

observation path band.

Maximum deviation from F

over ±30

MHz. For any Fc within each TX

-0.05 - +0.05 dB

-0.10 - +0.10 dB

observation path band.

Doc ID 018517 Rev 2 15/67

Electrical characteristics STW82103B

Table 6. Down converter mixer and IF amplifier electrical characteristics

(1)

(continued)

Symbol Parameter Conditions Min Typ Max Unit

Maximum deviation from linear phase

Phase Flatness for TX observation path

(5)

- Gain Flatness for RX path

- Phase Flatness for RX path

Mixer Driver Current Consumption

ICC

Mixer Driver Current Consumption (Low Current Mode)

IFAMP Current Consumption

ICC

IFAM

IFAMP Current Consumption (Low Current Mode)

at Fc over ±10 MHz. For any Fc within each TX observation path band.

Maximum deviation from linear phase at F

over ±30 MHz. For any Fc within

each TX observation path band.

Maximum ripple over a 4 MHz band.

(5)

For any F

Maximum ripple over a 4 MHz band.

(5)

For any F

within each RX path band.

3.3 V Supply (pin 41, 42) - 45 - mA

5 V Supply (pin 40) - 55 - mA

3.3 V Supply (pin 41, 42) - 20 - mA

3.3 V Supply (pin 40) - 35 - mA

3.3 V Supply (pin 33) - 10 - mA

5 V Supply (pin 31, 32) - 107 - mA

3.3 V Supply (pin 33) - 6 - mA

3.3 V Supply (pin 31, 32) - 55 - mA

-0.3 - +0.3 deg

-0.7 - +0.7 deg

--0.1

--0.6

dB pk-pk

deg pk-pk

1. All linearity and NF performances are intended at maximum LO amplitude (LO_A[1:0]=[11]), tuning capacitors (CAP[2:0]) programmed according to the selected frequency, mixer bias (MIX[3:0]) set to maximize performance and the device operated in high current mode. The performances of conversion gain, NF and linearity are intended at the SMA connectors of a typical application board.

2. The IF frequency range supported by the IF Amplifier is from 70 to 400 MHz. The exact IF frequency range supported for a specific RF frequency can be calculated as F

3. Guaranteed by design and characterization

4. RFin = 0 dBm/tone, RF tone spacing = 5 MHz

5. Guaranteed by design

Table 7. Pin diode attenuator driver (dual output current DAC) electrical characteristics

Symbol Parameters

= ABS(FLO-FRF) where FLO is inside the specified LO frequency range.

Conditions Min Typ Max Unit

R Resolution - - 10 - Bit

DNL Differential non linearity - -0.05 - 0.05 LSB

INL Integral non linearity - -0.45 - 0.45 LSB

Full Scale current

(1)

-0.28-2.8mA

- Current Mismatch - - - 2 %

EXT_DAC

Icc

static

1. See relationship between IDAC and R

Output voltage compliance range

-0-3V

Voltage Reference - - 1.19 V

REXT DAC Range - 10 - 100 kΩ

Static current consumption (Iout = 0 mA; pin 1) - 2.5 - mA

in the Circuit Description section (Dual Output Current DAC)

EXT_DAC

16/67 Doc ID 018517 Rev 2

STW82103B Electrical characteristics

Table 8. Integer-N synthesizer electrical characteristics

Symbol Parameter Conditions Min Typ Max Unit

VCO dividers

Prescaler 16/17 256 - 65551 -

N VCO Divider Ratio (N)

Prescaler 19/20 361 - 77836 -

Reference clock and phase frequency detector

ref

Reference input frequency - 10 19.2 200 MHz

- Reference input sensitivity - 0.35 1 1.5 Vpeak

R Reference Divider Ratio - 2 - 1023

PFD

STEP

PFD input frequency - - - 16 MHz

Frequency step

(1)

Prescaler 16/17

Prescaler 19/20

65551

77836

256

361

Charge pump

OCP

ICP sink/source

Output voltage compliance range - 0.4 - Vdd-0.3 V

- Spurious

(3)

(2)

3bit programmable - - 5 mA

---70-dBc

VCOs

Higher frequency range - 85 - MHz/V

VCOA

VCOA sensitivity

Intermediate frequency range

- 75 - MHz/V

Lower frequency range - 65 - MHz/V

Higher frequency range - 85 - MHz/V

VCOB

VCOB sensitivity

Intermediate frequency range

- 70 - MHz/V

Lower frequency range - 60 - MHz/V

ΔT

LKA

LKB

VCOA Maximum Temperature variation for continuous lock

VCOB Maximum Temperature variation for continuous lock

(4)

CALTYPE [0] - - 100 °C

CALTYPE [1] - - 125 °C

CALTYPE [0] - - 125 °C

CALTYPE [1] - - 125 °C

VCO A Pushing - - 8 - MHz/V

VCO B Pushing - - 14 - MHz/V

CTRL

VCO control voltage - 0.4 Vdd-0.3 V

- LO Harmonic Spurious - - -20 dBc

VCO

IDIV

VCO and VCO buffer current consumption

Amplitude [11] (pin 4) - 35 - mA

DIVIDER by 2 consumption (pin 3) - 20 - mA

Doc ID 018517 Rev 2 17/67

Electrical characteristics STW82103B

Table 8. Integer-N synthesizer electrical characteristics (continued)

Symbol Parameter Conditions Min Typ Max Unit

2 x LO output buffer (test purpose only)

OUT

Frequency range - 4.4 - 5.1 GHz

Output level - - 0 - dBm

RL Return Loss Matched to 50 ohm - 10 - dB

2LOBUF

Current Consumption (pin 15, 16, 17) - 35 - mA

LO output buffer

OUT

Frequency range - 2.2 - 3 GHz

Output level - - 0 - dBm

RL Return Loss Matched to 50ohm - 10 - dB

LOBUF

Current Consumption (pin 15, 16, 17) - 30 - mA

External VCO (LO) buffer

INVCO

EXTBUF

Frequency range - 2.2 - 3 GHz

Input level - - 0 - dBm

Current Consumption

External VCO Buffer (pin 4)

-25 -mA

PLL miscellaneous

Input Buffer, Prescaler,

PLL

PLL Current Consumption

Digital Dividers, misc.

-8 -mA

(pin 24)

PRE

LOCK

Prescaler input buffer Current Consumption

Charge Pump Current Consumption

Lock up time

(5)

(pin 12) - 3 - mA

CPSEL=[111], REXT_CP = 4.7 kΩ (pin 21)

-4 -mA

25 kHz PLL bandwidth; within 1ppm of frequency

-150 -µs

error

1. The frequency step is related to the PFD input frequency as follows: F

2. See relationship between ICP and R

3. The level of spurs may change depending on PFD frequency, Charge Pump current, selected channel and PLL loop BW.

4. When setting a specified output frequency, the VCO calibration procedure must be run first in order to select the best subrange for the VCO covering the desired frequency. Once programmed at the initial temperature T temperature range (-40 ° C to +85 ° C), the synthesizer is able to maintain the lock status if the temperature drift (in either direction) is within the limit specified by ΔT

5. Frequency jump form 2450 to 2300 MHz; it includes the time required by the VCO calibration procedure (7 x F =17.5 µs with F

=400 kHz))

PFD

in the Circuit Description section (Charge Pump)

EXT_CP

, provided that the final temperature T

STEP=FPFD

/2)

inside the operating

is still inside the nominal range.

PFD

cycles

18/67 Doc ID 018517 Rev 2

STW82103B Electrical characteristics

Table 9. Phase noise performance

(1)

Parameters Conditions Min. Typ. Max. Unit

In band phase noise floor, closed loop

Normalized In Band Phase Noise Floor (LO)

In Band Phase Noise Floor (LO) VCOA divided by 2

In Band Phase Noise Floor (LO) VCOB direct

(2)

ICP=4 mA, PLL BW = 50 kHz (including reference clock contribution)

--224-

-230+20log(N)+10log(F

-224+20log(N)+10log(F

PFD

dBc/Hz

)

dBc/Hz

)

PLL integrated phase noise

Integrated Phase Noise (single sided) 100 Hz to 40 MHz

=2.200 GHz, F

=3 mA, PLL BW = 25 kHz

STEP

=200 kHz,

- -44.9 - dBc

- 0.46 - ° rms

LOA (2200 MHz to 2550 MHz) – open loop

Phase Noise @ 1 kHz - - -63 - dBc/Hz

Phase Noise @ 10 kHz - - -89 - dBc/Hz

Phase Noise @ 100 kHz - - -113 - dBc/Hz

Phase Noise @ 1 MHz - - -134 - dBc/Hz

Phase Noise @ 10 MHz - - -151 - dBc/Hz

Phase Noise Floor @ 40 MHz - - -155 - dBc/Hz

LOB (2500 MHz to 3000 MHz) – open loop

Phase Noise @ 1 kHz - - -64 - dBc/Hz

Phase Noise @ 10 kHz - - -91 - dBc/Hz

Phase Noise @ 100 kHz - - -113 - dBc/Hz

Phase Noise @ 1 MHz - - -134 - dBc/Hz

Phase Noise @ 10 MHz - - -153 - dBc/Hz

Phase Noise Floor @ 40 MHz - - -162 - dBc/Hz

1. Phase Noise SSB. VCO amplitude set to maximum value [11]. All the closed-loop performances are specified using a Reference Clock signal at 76.8 MHz with phase noise of -144 dBc/Hz @1 kHz offset, -157 dBc/Hz @10 kHz offset and

-168 dBc/Hz of noise floor.

2. Normalized PN = Measured LO PN – 20log(N) – 10log(F comparison frequency at the PFD input

) where N is the VCO divider ratio (N=B*P+A) and F

PFD

is the

Doc ID 018517 Rev 2 19/67

Typical performance characteristics STW82103B

7 Typical performance characteristics

Note: Vsupply digital = 3.3 V, Vsupply analog1 = 3.3 V, Vsupply analog2 = 5 V, F

= +25 °C, RF power = 0 dBm, unless otherwise specified.

Figure 3. Conversion gain against RF frequency

= 150 MHz,

Figure 4. Noise figure against RF frequency

20/67 Doc ID 018517 Rev 2

STW82103B Typical performance characteristics

Figure 5. IIP3 against RF frequency

Figure 6. 2RF-2LO response against RF frequency

Doc ID 018517 Rev 2 21/67

Typical performance characteristics STW82103B

Figure 7. LOA (VCOA div. by 2) closed-loop phase noise at 2.38 GHz,

= 200kHz, ICP = 3mA)

STEP

Figure 8. LOB (VCOB div. by 2) closed-loop phase noise at 2.75 GHz,

= 200kHz, ICP = 3mA)

STEP

22/67 Doc ID 018517 Rev 2

STW82103B General description

8 General description

The STW82103B (see Figure 1: STW82103B block diagram on page 7) consists of a high linearity passive CMOS mixer with integrated RF balun, an IF amplifier, a 10-bit current steering DAC with dual output, and an integrated integer-N synthesizer.

The synthesizer embeds 2 internal low-noise VCOs with buffer blocks, a divider by 2, a low noise PFD (Phase Frequency Detector), a precise charge pump, a 10-bit programmable reference divider, two programmable counters and a dual-modulus prescaler. The A-counter (5 bits) and B counter (12 bits) counters, in conjunction with the dual modulus prescaler P/P+1 (16/17 or 19/20), implement an N integer divider, where N = B*P+A.

The device is controlled through a digital interface (I2C bus interface or SPI digital interface).

All internal devices operate with a power supply of 3.3 V except for the IF Amplifier output stage and the mixer driver stage operating at 5 V power supply in order to maximize the linearity performance. If the application requires a reduced linearity and noise figure performance the device is programmed in a low-current mode by using the minimum LO amplitude and the minimum biasing current in the IF amplifier. In low-current mode operation the device can use only the 3.3 V power supply thus dissipating less power.

8.1 Circuit description

8.1.1 Reference input stage

The reference input stage is shown in Figure 9. The resistor network feeds a DC bias at the F

input while the inverter used as the frequency reference buffer is AC coupled.

ref

Figure 9. Reference frequency input buffer

ref

VDD

Inverter

Buffer

Power Down

Doc ID 018517 Rev 2 23/67

General description STW82103B

8.1.2 Reference divider

The 10-bit programmable reference counter allows the input reference frequency to be

divided to produce the input clock to the PFD. The division ratio is programmed through the digital interface.

8.1.3 Prescaler

The dual-modulus prescaler P/P+1 takes the CML clock from the VCO buffer and divides it down to a manageable frequency for the CMOS A and B counters. The modulus (P) is programmable and can be set to 16 or 19. It is based on a synchronous 4/5 core which division ratio depends on the state of the modulus input.

8.1.4 A and B counters

The A (5 bits) and B (12 bits) counters, in conjunction with the selected dual modulus (16/17 or 19/20) prescaler make it possible to generate output frequencies which are spaced only by the reference frequency divided by the reference division ratio. Thus, the division ratio and the VCO output frequency are given by the following formulae:

NBPA+×=

VCO

BPA+×()F

-----------------------------------------------=

ref

where:

: VCO output frequency.

VCO

P: modulus of dual modulus prescaler (16 or 19 selected through the digital interface).

B: division ratio of the main counter.

A: division ratio of the swallow counter.

: input reference frequency.

ref

R: division ratio of the reference counter.

N: division ratio of the PLL

The following points should be noted:

● For the VCO divider to work correctly, B must be higher than A.

● A can take any value from 0 to 31.

● Two PLL division ratio (N) ranges are possible, depending on the value of P:

– 256 to 65551 (when P=16)

– 361 to 77836 (when P=19).

24/67 Doc ID 018517 Rev 2

STW82103B General description

Figure 10. VCO divider diagram

VCOBUF-

VCOBUF+

Prescaler

16/17 or 19/20

modulus

5-bit

A counter

8.1.5 Phase frequency detector (PFD)

The PFD takes inputs from the reference and the VCO dividers and produces an output proportional to the phase error. The PFD includes a delay gate that controls the width of the anti-backlash pulse. This pulse ensures that there is no dead zone in the PFD transfer function.

Figure 11 is a simplified schematic of the PFD.

Figure 11. PFD diagram

VDD

ref_DIV

To P F D

12-bit

B counter

VCO_div

VDD

Delay

Down

ABL

Doc ID 018517 Rev 2 25/67

General description STW82103B

8.1.6 Lock detect

This signal indicates that the difference between rising edges of both UP and DOWN PFD signals is found to be shorter than the fixed delay (roughly 5 ns). The Lock Detect signal is high when the PLL is locked. The Lock Detector consumes current only during PLL transients.

8.1.7 Mute until lock

This (software controlled) function shuts down the following elements until the PLL achieves the lock status:

● RF output stage

● LO output buffer

● mixer

● IF amplifier circuitry

Under this setting there is no signal at the IF output stage or the LO output during a frequency jump.

8.1.8 Charge pump

This block drives two matched current sources, Iup and Idown, which are controlled respectively by the UP and DOWN PFD outputs. The nominal value of the output current is controlled by an external resistor (to be connected to the REXT input pin) and the selection of one of 8 possible values by a 3-bit word.

The minimum value of the output current is: IMIN = 2*VBG/REXT_CP (VBG~1.17 V)

Table 10. Current values for CPSEL[2:0] selection

CPSEL2 CPSEL1 CPSEL0 Current Value for REXT=4.7 kΩ

000I

0012*I

0103*I

0114*I

1005*I

1016*I

1107*I

1118*I

MIN

0.5 mA

1.00 mA

1.50 mA

2.00 mA

2.50 mA

3.00 mA

3.50 mA

4.00 mA

Note: The current is output on pin ICP. During the VCO auto calibration, ICP and VCTRL pins are

forced to VDD/2.

26/67 Doc ID 018517 Rev 2

STW82103B General description

Figure 12. Loop filter connection

VDD

Buffer

8.1.9 Voltage controlled oscillators

VCO selection

Within the STW82103B two low-noise VCOs are integrated to cover a wide band from 2200 MHz to 2550 MHz after the division by 2, and from 2500 MHz to 3000 MHz:

● VCO A frequency range is 4400 MHz to 5100 MHz

● VCO B frequency range is 2500 MHz to 3000 MHz

Charge

pump

Cal bit

VCTRL

ICP

VCO frequency calibration

Both VCOs can operate on 32 frequency ranges that are selected by adding or subtracting capacitors to the resonator. These frequency ranges are intended to cover the wide band of operation and compensate for process variations on the VCO center frequency.

An automatic range selection is performed when the bit SERCAL rises from ‘0’ to ‘1’ . The charge pump is inhibited and the pins ICP and VCTRL are set at a fixed calibration voltage (VCAL). The frequency ranges are then tested to select the nearest one to the desired output frequency (F charge pump is once again enabled and the PLL performs a fine adjustment around VCAL on the loop filter voltage to lock F

Two calibration algorithms are selectable by setting the CALTYPE bit.

Setting the CALTYPE bit to ‘1’ guarantees the PLL lock versus temperature variations. Once programmed at the initial temperature, T +85 °C), the synthesizer is able to maintain the lock status if the temperature drift (in either direction) is within the limit specified by ΔT still inside the nominal range.

Setting the CALTYPE bit to ‘0’ fixes VCAL to the mid point of the charge pump output (VDD/2). Optimum PLL phase noise performance versus temperature variations with a reduced ΔT

The ΔT

s guaranteed in this case.

parameter, specific to each VCO and calibration type, in the STW82103B is

specified in Table 8: Integer-N synthesizer electrical characteristics.

OUT

= N*F

/R) with VCAL input voltage applied. After this selection, the

ref

, thus enabling a fast settling time.

OUT

, within the operating temperature range (-40 °C to

, and provided that the final temperature, T

, is

Doc ID 018517 Rev 2 27/67

General description STW82103B

Figure 13. VCO typical sub-band characteristics

00000 00001

01111

FREQ (Hz)

11111

Calibrator lock

range

0.00

0.50

1.00

1.50

VCTRL (V)

2.00

2.50

3.00

3.50

The SERCAL bit should be set to ’1’ at each division ratio change. The calibration takes approximately 7 periods of the Comparison Frequency and the SERCAL bit is automatically reset to ’0’ at the end of each calibration.

The maximum allowed F

to perform the calibration process is 1 MHz. If a higher F

PFD

used the following procedure should be adopted:

1. Calibrate the VCO at the desired frequency with an F

2. Set the A, B and R dividers ratio for the desired F

PFD

lower than 1 MHz

PFD

For calibration details refer to Section 9.4.1: VCO calibration procedure (I2C interface) or

Section 10.4.1: VCO calibration procedure (SPI interface).

28/67 Doc ID 018517 Rev 2

STW82103B General description

VCO calibration auto-restart feature

The VCO Calibration Auto-Restart feature, once activated, allows the calibration procedure to be restarted when the Lock Detector reports that the PLL has moved to an unlock condition (trigger on ‘1’ to ‘0’ transition of Lock Detector signal).

This situation could happen if the device experiences a significant temperature variation and the CALTYPE bit is set for optimum PLL phase noise performance (CALTYPE [0]).By enabling the VCO Calibration Auto-Restart feature (through the AUTO_CAL bit), the device re-selects the proper VCO frequency sub-range, without any external user command.

This feature can be enabled only when the FPFD is lower than 1 MHz.

VCO voltage amplitude control

The voltage swing of the VCOs can be adjusted over 4 levels by means of two dedicated programming bits (PLL_A1 and PLL_A0). This setting trades current consumption with phase noise performances of the VCO. Higher amplitudes provide best phase noise while lower ones save power.

Doc ID 018517 Rev 2 29/67

General description STW82103B

Ta bl e 1 1 and Ta bl e 12 give the current consumption and the phase noise at 1 MHz.

Table 11. VCOA performance against amplitude setting (frequency = 4.6 GHz)

PLL_A[1:0]

00 23 -124

01 24 -125

10 32 -127

11 35 -128

Table 12. VCOB performance against amplitude setting (frequency = 2.8 GHz)

PLL_A[1:0]

00 16 -129

01 18 -131

10 27 -133

11 30 -134

8.1.10 Output stage

The differential output signal of the synthesizer after the Divider by 2 for VCOA and directly for VCOB is available on pins 16 and 17.

The output stage is selected by programming the PD[4:0] bits.

Current

Consumption (mA)

Current

Consumption (mA)

PN @ 1 MHz

The output stage is an open-collector structure which is able to meet different requirements over the desired output frequency range by proper connections on the PCB. See Figure 27:

Diversity mode operation with same LO frequencies.

8.1.11 External VCO buffer

Although the STW82103B includes two wideband and low-noise VCOs, external VCO use capability is also provided.

The external VCO buffer can be used to manage a signal coming from an external VCO in order to build a local oscillator signal by using the STW82103B internal synthesizer as a PLL. This is only possible when External VCO standard mode or External VCO diversity master mode operation are selected. See Figure 29: External VCO standard mode

operation and Figure 30: External VCO diversity mode operation with same LO.

If the STW82103B is operated in Diversity slave mode, the external VCO buffer manage the signal coming from the synthesizer output stage of another STW82103B device See

Figure 27: Diversity mode operation with same LO frequencies and Figure 30: External VCO diversity mode operation with same LO.

The selection of the external VCO buffer is done by setting the PD[4:0] bits.

The external VCO signal can range from 2200 MHz to 3000 MHz and its minimum power level must be -10 dBm.

30/67 Doc ID 018517 Rev 2

STW82103B General description

8.1.12 Mixer and IF amplifier

LO mixer driver

The LO signal is fed through a driver in order to achieve the high power level needed to drive the passive mixer for maximum performance of linearity and NF.

The LO Mixer Driver is coupled to the mixer with an integrated LO balun. The LO signal level is adjusted by means of an Automatic Level Control loop (ALC) controlled by the bits LO_A[1:0].

In low current mode the configuration LO_A[1:0]=’00’ (minimum LO amplitude) should be selected and the power supply on pin 40 can be set to 3.3 V.

The LO balun resonating frequency can be adjusted by means of the bits CAP[2:0] in order to match the selected LO frequency.

Table 13. Suggested CAP[2:0] values for LO Frequency range mixer

CAP[2:0] LO frequency range

000 2875 MHz ÷ 3000MHz

001 2750 MHz ÷ 2875 MHz

010 2640 MHz ÷ 2750 MHz

011 2530 MHz ÷ 2640 MHz

100 2435 MHz ÷ 2530 MHz

101 2350 MHz ÷ 2435 MHz

110 2280 MHz ÷ 2350 MHz

111 2200 MHz ÷ 2280 MHz

Mixer

A doubly balanced CMOS passive mixer is internally driven by the high level LO signal in order to achieve high linearity and low noise performance.

The RF integrated balun permits the removal of external components and it is internally matched to 50 ohms.

The gate bias of the CMOS devices in the mixer is programmable with 4 bits (MIX[3:0]) to optimize the input matching and the gain of the signal chain.

Higher values of gate bias (higher decimal values of MIX[3:0]) are suggested to maximize linearity and lower values to maximize the performance of Gain and NF.

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General description STW82103B

IF amplifier

The integrated IF stage permits a 200-ohm load to be driven (typically a SAW filter) ensuring high linearity.

It is an open collector stage (pin 31, 32) and should be biased to 5 V with choke inductors. The typical output impedance is 200 ohms. The linearity performances are controlled by the bits IFAMP[1:0]. In low current mode the configuration IFAMP[1:0]=’00’ (minimum linearity) should be selected and the open collector stage can be biased to 3.3 V with choke inductors.

Table 14. Linearity performance against IFAMP[1:0] configuration (typical

condition)

IFAMP[1:0] Linearity performance

00 19 dB

01 21 dB

10 23 dB

11 25 dB

8.1.13 Dual output current DAC

The STW82103B embeds a 10-bit Dual Output steering current DAC especially suited to drive an external PIN diode attenuator. This provides power level calibration capability at the RF input for the TX observation path applications.

The current sourced by the DAC is related to the R following formulae (where VR

IDAC

LSB

IDAC

With a 10 kΩ R

EXT_DAC

the FS current is approximately 2.8 mA.

EXT_DAC

-- -

is approximately 1.19 V):

3VR

EXT_DAC

----------------------------------------

EXT_DAC

3VR

EXT_DAC

----------------------------------------

EXT_DAC

××= LSB DAC current

1023

------------ -

××= Full scale current

EXT_DAC

------

resistor according to the

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STW82103B I2C bus interface

9 I2C bus interface

The I2C bus interface is selected by hardware connection of the pin 25 (DBUS_SEL) to 0 V.

Data transmission from a microprocessor to the STW82103B takes place through the 2 wires (SDA and SCL) I

The I

C-bus protocol defines any device that sends data on to the bus as a transmitter and

C-bus interface. The STW82103B is always a slave device.

any device that reads the data as receiver. The device that controls the data transfer is known as the master and the others as slaves. The master always initiates the transfer and provides the serial clock for synchronization.

The STW82103B I

C bus supports Fast Mode operation (clock frequency up to 1 MHz).

9.1 I2C general features

9.1.1 Data validity

Data changes on the SDA line must only occur when the SCL is LOW. SDA transitions while the clock is HIGH identify START or STOP conditions.

Figure 14. Data validity waveform

SDA

SCL

Data line stable

data valid

Change

data allowed

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I2C bus interface STW82103B

9.1.2 START and STOP conditions

Figure 15. START and STOP condition waveform

SCL

SDA

START

START condition

A START condition is identified by a HIGH to LOW transition of the data bus SDA while the clock signal SCL is stable in the HIGH state. A Start condition must precede any command for data transfer.

STOP condition

A STOP condition is identified by a transition of the data bus SDA from LOW to HIGH while the clock signal SCL is stable in the HIGH state.. A STOP condition terminates communications between the STW82103B and the Bus Master.

9.1.3 Byte format and acknowledge

Every byte (8 bits long) transferred on the SDA line must contain bits. Each byte must be followed by an acknowledge bit. The MSB is transferred first.

An acknowledge bit indicates a successful data transfer. The transmitter, either master or slave, releases the SDA bus after sending 8 bits of data. During the 9th clock pulse the receiver pulls the SDA low to acknowledge the receipt of 8 bits of data.

Figure 16. Byte format and acknowledge waveform

STOP

SCL

SDA

MSB

START

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Acknowledgement from receiver

STOP

STW82103B I2C bus interface

9.1.4 Device addressing

To start the communication between the Master and the STW82103B, the master must initiate with a START condition. Following this, the master sends onto the SDA line 8 bits (MSB first) corresponding to the device select address and read or write mode.

The first 7 MSBs are the device address identifier, corresponding to the I For the STW82103B the address is set as ’1101A

’, 3-bits programmable. The 8th bit

2A1A0

C-Bus definition.

(LSB) is the read or write operation bit (the RW bit is set to 1 in read mode and to 0 in write mode).

After a START condition the STW82103B identifies the device address on the bus and, if matched, it acknowledge the identification on SDA bus during the 9th clock pulse.

9.1.5 Single-byte write mode

Following a START condition the master sends a device select code with the RW bit set to 0. The STW82103B gives an acknowledge and waits for the internal sub-address (1 byte). This byte provides access to any of the internal registers.

After reception of the internal byte sub-address the STW82103B again responds with an acknowledge. A single-byte write to sub-address 0x00 would affect DATA_OUT[47:40], a single-byte write with sub-address 0x04 would affect DATA_OUT[15:8] and so on.

S 1101A2A1A

0ack

9.1.6 Multi-byte write mode

The multi-byte write mode can start from any internal address. The master sends the data bytes and each one is acknowledged. The master terminates the transfer by generating a STOP condition.

The sub-address determines the starting byte. For example, a multi-byte write with subaddress 0x01 and 4 DATA_IN bytes affects 4 bytes starting at address 0x01 (registers at addresses 0x01, 0x02, 0x03 and 0x04 are modified).

S 1101A2A1A00ack

sub-address

byte

9.1.7 Current byte address read

In the current byte address read mode, following a START condition, the master sends the device address with the RW bit set to 1 (No sub-address is needed as there is only 1 byte read register). The STW82103B acknowledges this and outputs the data byte. The master does not acknowledge the received byte, but terminates the transfer with a STOP condition.

S 1101A2A1A

sub-address

byte

ack DATA IN ack ..

1 ack DATA OUT No ack P

ack DATA IN ack P

DATA

ack P

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I2C bus interface STW82103B

9.2 I2C timing specifications

9.2.1 Data and clock timing specification

Figure 17. I2C data and clock waveforms

SDA

SCL

cwl

Table 15. I

C data and clock timing parameters

cwh

Symbol Parameter Min Unit

cwh

cwl

Data to clock set up time 2

Data to clock hold time 2

Clock pulse width high 10

Clock pulse width low 5.5

9.2.2 I2C START and STOP timing specification

Figure 18. I2C START and STOP timing waveforms

SDA

SCL

start

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stop

STW82103B I2C bus interface

Table 16. I2C START and STOP timing parameters

Symbol Parameter Min Unit

start

stop

Clock to data start time 2

Data to clock down stop time 2

9.2.3 I2C acknowledge timing specification

Figure 19. I2C acknowledge timing waveforms

SDA

SCL

Table 17. I2C acknowledge timing parameters

Symbol Parameter Max Unit

Ack begin delay 2

Ack end delay 2

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I2C bus interface STW82103B

9.3 I2C registers

STW82103B has 9 write-only registers and 1 read-only register.

9.3.1 I2C register summary

The following table gives a short description of the write-only registers list.

Table 18. I2C register list

Offset Register name Description Page

0x00 FUNCTIONAL_MODE Functional mode register on page 39

0x01 B_COUNTER B counter register on page 39

0x02 A_COUNTER A counter register on page 40

0x03 REF_DIVIDER Reference clock divider ratio register on page 40

0x04 CONTROL PLL control register on page 41

0x05 MUTE_&_CALIBRATION Mute and calibration control register on page 42

0x06 DAC_CONTROL DAC control register on page 42

0x07 MIXER_CONTROL Mixer control register on page 43

0x08 IFAMP_LO_CONTROL IF amplifier LO control register on page 43

0x09 READ_ONLY_REGISTER Device ID and calibration status register on page 44

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STW82103B I2C bus interface

9.3.2 I2C register definitions

FUNCTIONAL_MODE Functional mode register

76543210

ALC_PD PKD_EN PD[4:0] B11

WWWW

Address: 0x00

Type: W

Reset: 0x00

[7] ALC_PD: for test purpose only must be set to ’0’. (ALC ON)

[6] PKD_EN: for test purpose only must be set to ’0’. (Peak detector output on pin 36 OFF)

[5:1] PD[4:0]: bits used to select different functional modes for the STW82103B according to

the following table 00000: (0 decimal) Power down mode 00001: (1 decimal) Standard Mode VCOA (VCOA and RX chain ON) 00010: (2 decimal) Standard Mode VCOB (VCOB and RX chain ON) 00011: (3 decimal). Diversity Slave Mode (ExtVCO/LO input buffer and RX Chain ON;

internal synthesizer OFF) 00100: (4 decimal) Diversity Master Mode VCOA (VCOA, RX Chain and LO output

buffer ON) 00101: (5 decimal) Diversity Master Mode VCOB (VCOB, RX Chain and LO output

buffer ON) 00110: (6 decimal) External LO Standard Mode (RX Chain ON; PLL and ExtVCO/LO

input buffer ON) 00111: (7 decimal) External LO Diversity Master Mode (RX Chain ON; PLL, ExtVCO/LO

input buffer and LO output buffer ON)

[0] B11: B counter value (bits B[10:0] in the B_COUNTER and A_COUNTER registers)

B_COUNTER B counter register

76543210

B[10:3]

Address: 0x01

Type: W

Reset: 0x00

Description: Most significant bits of the B counter value

[7:0] B[10:3]: B counter value (bit B11 in the FUNCTIONAL_MODE register, bits B[2:0] in the

A_COUNTER register)

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I2C bus interface STW82103B

A_COUNTER A counter register

76543210

B[2:0] A[4:0]

W W

Address: 0x02

Type: W

Reset: 0x00

Description: Least significant bits of the B-counter value. A-counter value.

[7:5] B[2:0]: B Counter value (bit B11 in the FUNCTIONAL_MODE register, bits B[10:3] in

the B_COUNTER register).

[4:0] A[4:0]: A counter value

REF_DIVIDER Reference clock divider ratio register

76543210

R[9:2]

Address: 0x03

Type: W

Reset: 0x00

Description: Most significant bits of the reference clock divider ratio value.

[7:0] R[9:2]: Reference clock divider ratio (bits R[1:0] in the CONTROL register)

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STW82103B I2C bus interface

CONTROL PLL control register

76543210

[R1:0] PLL_A[1:0] CPSEL[2:0] PSC_SEL

WW WW

Address: 0x04

Type: W

Reset: 0x00

Description: Least significant bits of the reference clock divider ratio value and PLL control bits.

[7:6] R[1:0]: Reference clock divider ratio (bits R[9:2] in the REF_DIVIDER register)

[5:4] PLL_A[1:0]:

[3:1] CPSEL[2:0]: Charge Pump output current

[0] PSC_SEL: Prescaler Modulus select (‘0’ for P=16, ‘1’ for P=19)

The LO output frequency is programmed by setting the proper value for A, B and R according to the following formula

VCO amplitude

ref

BPA+⋅()

⋅⋅=

--------- -

Where: –DR equals 0.5 for VCOA (VCO output frequency divided by 2) or 1 for VCOB (VCO

output frequency)

– P is the selected Prescaler Modulus

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I2C bus interface STW82103B

MUTE_&_CALIBRATION Mute and calibration control register

76543210

CALTYPE

WWWWWWWW

SERCAL

SELEXTCAL

MUTE_EN

MUTE_TYPE

MUTE_LOOUT_EN

MUTE_MIX_EN

Address: 0x05

Type: W

Reset: 0x00

Description: For test purposes only

[7] CALTYPE: Calibration algorithm selection

0: standard calibration to optimize the phase noise versus temperature 1: enhanced calibration to maximize the ΔT

[6] SERCAL:

1: starts the VCO auto-calibration (automatically reset to ’0’ at the end of calibration)

[5] SELEXTCAL: test purpose only; must be set to ‘0’

[4] MUTE_EN:

0: mute function disabled 1: mute function enabled

[3] MUTE_TYPE: must be set to '1' while the mute function is enabled (mute the IF output

on Unlock state)

range

MUTE_IFAMP_EN

[2] MUTE_LOOUT_EN:

To be set to ’1’ to mute the LO output buffer

[1] MUTE_MIX_EN:

To be set to ’1’ mute the Mixer circuitry

[0] MUTE_IFAMP_EN: To be set to '1' to mute the IF amplifier circuitry

DAC_CONTROL DAC control register

76543210

DAC[9:2]

Address: 0x06

Type: W

Reset: 0x00

Description: Most significant bits of the DAC control word

[7:0] DAC[9:2]: DAC input word for DAC current control (bits DAC[1:0] in the

MIXER_CONTROL register).

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STW82103B I2C bus interface

MIXER_CONTROL Mixer control register

76543210

DAC[1:0]

WWWW

MIX[3:0]

PD_DAC

Address: 0x07

Type: W

Reset: 0x00

Description: Least significant bits of DAC control word and mixer control bit fields

[7:6] DAC[1:0]: DAC input word for DAC current control (bits DAC[9:2] in the DAC_CONTROL

[5:2] MIX[3:0]: Mixer bias control value

[1] PD_DAC: DAC power down

[0] CAL_AUTOSTART_EN: VCO calibration auto-restart enable (’1’ active), permits to

automatically restart the VCO calibration procedure in case of PLL unlock

IFAMP_ LO_CONTROL IF amplifier LO control register

76543210

IFAMP[1:0] CAP[2:0] LO_A[1:0] LPMUX_EN

WWWW

CAL_AUTOSTART_EN

Address: 0x08

Type: W

Reset: 0x00

[7:6] IFAMP[1:0]: power consumption/linearity control

[5:3] CAP[2:0]: Tuning capacitors control

[2:1] LO_A[1:0]: LO amplitude control

[0] LPMUX_EN: for test purpose only (low power mode for MUX); must be set to ’0’

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I2C bus interface STW82103B

READ-ONLY REGISTER Device ID and calibration status register

76543210

ID[1:0] LOCK_DET INTCAL[4:0]

RR R

Address: 0x09

Type: R

Reset: 0x00

Description: This register is automatically addressed in the ‘current byte address read mode’

[7:6] ID[1:0]: device identification ’11’ for STW82103B

[5] LOCK_DET: ’1’ when PLL is locked

[4:0] INTCAL[4:0]: internal value of the VCO calibration control word

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STW82103B I2C bus interface

9.4 Device calibration through the I2C interface

9.4.1 VCO calibration procedure (I2C interface)

The calibration of the VCO center frequency is activated by setting the SERCAL bit of the MUTE & CALIBRATION register to ’1’.

To program the device ensuring a correct VCO calibration, the following procedure is required before every channel change:

1. Program all the Registers using a multi-byte write sequence with the desired setting:

– Functional Mode

– B and A counters

– R counter

– VCO amplitude

– Charge Pump

– Prescaler Modulus

–DAC

– Mixer and LO Control

– all bits of the MUTE & CALIBRATION Register (0x05) set to ’0’.

2. Program the MUTE & CALIBRATION register using a single-byte write sequence (subaddress 0x05) with the SERCAL bit set to ’1’.

The maximum allowed PFD frequency (F the desired F

is higher than 1 MHz the following steps are needed:

PFD

3. Perform all the step of the above calibration procedure programming the desired VCO frequency with a proper setting of R, B and A counter so that F 1MHz.

4. Once calibration is completed, program all the Registers by using a multi-byte write sequence (Functional Mode, B and A counters, R counter, VCO amplitude, Charge Pump, Prescaler Modulus, DAC, Mixer and LO Control) with the proper settings for the desired VCO and PFD frequencies.

9.4.2 Power ON sequence (I2C interface)

At power-on the device is configured in power-down mode.

In order to guarantee correct setting of the internal circuitry after the power on, the following steps must be followed:

1. Power up the device

2. Provide the Reference clock

3. Implement the first programming sequence with a proper delay time between the STOP condition of the multi-byte write sequence and that of the single-byte write sequence (see Figure 20). The T

value must respect the following condition:

delay

) to perform the calibration process is 1 MHz. If

results lower than

PFD

1023

--------- -

×>

ref

is the reference clock frequency.

ref

Doc ID 018517 Rev 2 45/67

I2C bus interface STW82103B

Figure 20. I2C first programming timing

START

CLK

START

STOP STOP

Tdelay > 1023/F

DATA

MSB

LSB

Multi-byte sequence Single-byte sequence

MSB

9.4.3 VCO calibration auto-restart procedure (I2C interface)

The VCO calibration auto-restart feature is enabled in two steps:

1. Set the desired frequency ensuring VCO calibration procedure as described above (Section 9.4.1).

2. Program the MIXER_CONTROL register (sub-address 0x07) using a single-byte write sequence with the CAL_AUTOSTART_EN bit set to '1' while keeping the others unchanged.

ref

LSB

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STW82103B SPI digital interface

10 SPI digital interface

10.1 SPI general features

The SPI digital interface is selected by hardware connection of the pin 25 (DBUS_SEL) to

3.3 V.

The STW82103B IC is programmed by means of a high-speed serial-to-parallel interface with write option only. The 3-wires bus can be clocked at a frequency as high as 100 MHz to allow fast programming of the registers containing the data for RF IC configuration.

The programming of the chip is done through serial words with whole length of 26 bits. The first 2 MSB represent the address of the registers. The others 24 LSB represent the value of the registers.

Each data bit is stored in the internal shift register on the rising edge of the CLOCK signal.

On the rising edge of the LOAD signal the outputs of the selected register are sent to the device.

Figure 21. SPI input and output bit order

Last

DATA

bit sent (LSB) 0

25 (MSB)

LOAD

Reg. #0

Reg. #1

Address decoder

LOAD #4

00 (LSB)

Reg. #4

Doc ID 018517 Rev 2 47/67

SPI digital interface STW82103B

Figure 22. SPI data structure

MSB

Address

A1 A0 D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

Table 19. Address decoder and outputs

Data for register (24 bits)

Note: MSB is sent first

Address Outputs

A1 A0

DATABITS

D23-D0

Name Function

0 0 24 0 ST1 DAC, Mixer, Tuning capacitors, LO_amplitude

01 24 1ST2

Reference divider, VCO amplitude, VCO Calibration, Charge Pump current, Prescaler Modulus, Mute functions

1 0 24 2 ST3 Functional modes, VCO dividers

1 1 24 3 ST4 Reserved

LSB

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STW82103B SPI digital interface

10.2 SPI timing specification

10.2.1 Data, clock and load timing

Figure 23. SPI timing waveforms

setup

hold

DATA

CLOCK

LOAD

Table 20. SPI timing parameters

MSB LSBMSB - 1

clk

clk_loadr

load

clk_loadf

Parameter Description Min. Typ. Max. Unit

setup

hold

clk

load

clk_loadr

clk_loadf

DATA to CLOCK setup time 1 - - ns

DATA to clock hold time 0.5 - - ns

CLOCK cycle period 10 - - ns

LOAD pulse width 3 - - ns

CLOCK to LOAD rising edge 0.6 - - ns

CLOCK to LOAD falling edge 2.5 - - ns

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SPI digital interface STW82103B

10.3 SPI registers

10.3.1 SPI register summary

Table 21. SPI register list

Offset Register name Description Page

0x00 ST1 SPI register 1 on page 50

0x01 ST2 SPI register 2 on page 51

0x10 ST3 SPI register 3 on page 52

10.3.2 SPI register definitions

ST1 SPI register 1

23222120191817161514131211109876543210

Address: 0x00

Type: W

CAL_AUTOSTART_EN

IF[1:0]

CAP[2:0]

LO_A[1:0]

DAC[9:0]

WWWWWWWW

MIX[3:0]

PWD_DAC

LPMUX_EN

Reset: 0x00

[23:14]

[13:10]

[9]

[8]

[7:6]

[5:3]

[2:1]

[0]

DAC[9:0]: DAC input word

MIX[3:0]: Mixer bias control

PWD_DAC: DAC power down

CAL_AUTOSTART_EN: VCO calibration auto-restart enable

IF[1:0]: Power consumption/linearity control

CAP[2:0]: Tuning capacitors control

LO_A[1:0]: LO amplitude control

LPMUX_EN: For test purpose only. Must be set to ‘0’

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STW82103B SPI digital interface

ST2 SPI register 2

23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R[9:0]

W W W WWWWWWWWW

PLL_A[1:0]

CPSEL[2:0]

PSC_SEL

CAL_TYPE

SERCAL

SELEXTCAL

MUTE_EN

MUTE_TYPE

MUTE_LOOUT_EN

Address: 0x01

Type: W

Reset: 0x00

[23:14]

[13:12]

R[9:0]: Reference clock divider ratio

PLL_A[1:0]: VCO amplitude control

[11:9]

CPSEL[2:0]: Charge pump output current control

[8]

PSC_SEL: Prescaler modulus select (‘0’ for P=16, ‘1’ for P=19)

[7] CAL_TYPE: Calibration algorithm selection

0: standard calibration to optimize the phase noise versus temperature 1: enhanced calibration to maximize the ΔTLK range

[6] SERCAL:

at ‘1’ starts the VCO auto-calibration (automatically reset to ‘0’ at the end of calibration)

[5]

SELEXTCAL: test purpose only. Must be set to ‘0’

MUTE_MIX_EN

MUTE_IFAMP_EN

[4] MUTE_EN:

0: mute function disabled 1: mute function enabled

[3] MUTE_TYPE: must be set to '1' while the mute function is enabled (mute IF output on

Unlock state)

[2] MUTE_LOOUT_EN:

To be set to ’1’ to mute the LO output buffer

[1] MUTE_MIX_EN:

To be set to ’1’ to mute the Mixer circuitry

[0] MUTE_IFAMP_EN:

To be set to ’1’ to mute the IF amplifier circuitry

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SPI digital interface STW82103B

ST3 SPI register 3

23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ALC_PD

WW W W W

PKD_EN

PD[4:0]

B[11:0]

A[4:0]

Address: 0x10

Type: W

Reset: 0x00

[23]

ALC_PD: Test purpose only; must be set to ‘0’ (ALC ON)

[22] PKD_EN: for test purpose only; must be set to ‘0’

[21:17] PD[4:0]:

00000: (0 decimal) Power down mode 00001: (1 decimal) Standard Mode VCOA (VCOA and RX chain ON) 00010: (2 decimal) Standard Mode VCOB (VCOB and RX chain ON) 00011: (3 decimal). Diversity Slave Mode (ExtVCO/LO input buffer and RX Chain ON;

internal synthesizer OFF) 00100: (4 decimal) Diversity Master Mode VCOA (VCOA, RX Chain and LO output

buffer ON) 00101: (5 decimal) Diversity Master Mode VCOB (VCOB, RX Chain and LO output

buffer ON) 00110: (6 decimal) External LO Standard Mode (RX Chain ON; PLL and ExtVCO/LO

input buffer ON) 00111: (7 decimal) External LO Diversity Master Mode (RX Chain ON; PLL, ExtVCO/LO

input buffer and LO output buffer ON)

[16:5] B[11:0]: B counter bits

[4:0]

A[4:0]: A Counter Bits

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STW82103B SPI digital interface

10.4 Device calibration through the SPI interface

10.4.1 VCO calibration procedure (SPI interface)

The calibration of the VCO center frequency is activated by setting to ’1’ the SERCAL bit (ST2 Register bit [6]).

In order to program properly the device while ensuring the VCO calibration, the following procedure is required before every channel change:

1. Program the ST1 Register with the desired setting (DAC, Mixer, LO Control)

2. Program the ST3 Register with the desired setting (Functional mode, B and A counters)

3. Program the ST2 Register with the desired setting (R counter, VCO amplitude, Charge Pump, Prescaler Modulus) and SERCAL bit set to ’1’

The maximum allowed PFD frequency (F the desired F

is higher than 1 MHz the following steps are needed:

PFD

4. Perform all the steps of the above calibration procedure programming the desired VCO frequency with a proper setting of R, B and A counter so that F MHz.

5. Once calibration is completed program the device with the proper setting for the desired VCO and PFD frequencies according to the following steps:

a) Program the ST3 Register with the desired setting (Functional mode, B and A

counters)

b) Program the ST2 Register with the desired setting (R counter, VCO amplitude,

Charge Pump, Prescaler Modulus) with the SERCAL bit set to ’0’.

10.4.2 Power ON sequence (SPI interface)

At power-on the device is configured in power-down mode.

In order to guarantee correct setting of the internal circuitry after the power on, the following steps must be followed:

1. Power up the device

2. Provide the reference clock

3. Implement the first programming sequence with a proper delay time between the ST3 and ST2 load rising edges (see Figure 24). The T condition:

) to perform the calibration process is 1 MHz; if

results lower than 1

PFD

value must respect the following

delay

is the reference clock frequency.

ref

Doc ID 018517 Rev 2 53/67

delay

1023

--------- -

×>

ref

SPI digital interface STW82103B

Figure 24. SPI first programming timing

delay

ST2

> 1023/F

ref

DATA

LOAD

MSB MSB-1

ST3

LSB-1

LSB

MSB

MSB-1

10.4.3 VCO calibration auto-restart procedure (SPI interface)

The VCO calibration auto-restart feature is enabled in two steps:

1. Set the desired frequency ensuring VCO calibration as described in Section 10.4.1.

2. Program the ST1 register with the CAL_AUTOSTART_EN bit set to '1' while keeping unchanged the others.

LSB-1

LSB

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STW82103B Application information

11 Application information

11.1 Application circuit

Figure 25. Typical STW82103B application circuit

3.3V_LN4

External VCO

5V_1

3.3V_LN1

VDD_DAC

REXT_DAC

VDD_DIV

VDD_VCO

EXTVCO_INN

EXTVCO_INP

EXT_PD

ADD2

ADD1

ADD0

VDD_IO

I_PINDRV2

I_PINDRV1

VDD_PSCBUF

VDD_MIXDRV

VFQFPN-44

3.3V_LN1

VDD_ALC

VDD_OUTBUF

MIXDRV_CT

OUTBUFN

3.3V_LN1

LO_Output

RF_IN

C19

RF_IN

VDD_RFESD

VCTRL

OUTBUFP

18 19

LOCK_DET

3.3V_LN3

IF_out

5V_2

C17

R10

3.3V_LN2

REF_CLK

LOAD

SLC/CLK

SDA/DATA

3.3V_LN2

C15 C16

C14

C13

C12

SPI

I2C

C11

C18

3.3V_LN2

TEST1

RF_CT

ICP

TEST2

TEST_ALC

VDD_IFAMP

IF_OUTP

IF_OUTN

LOAD

SLC/CLK

SDA/DATA

VDD_DIG

DBUS_SEL

VDD_PLL

REF_CLK

REXT_CP

VDD_CP

LOCK_DET

3.3V_LN1

C10

Doc ID 018517 Rev 2 55/67

Application information STW82103B

Table 22. Application circuit component values

Designation Quantity Description Supplier

C1, C15 2 4.7 µF capacitors COG (0402)

C2, C11 2 1 nF capacitors COG (0402)

C3 1 10 pF capacitor COG (0402)

C4,C5 2 3.3 pF capacitors COG (0402)

C6, C7 2 1.1 pF capacitor COG (0402)

C8 1 270 pF capacitor COG (0402)

C9 1 2.7 nF capacitor COG (0402)

C10 1 68 pF capacitor COG (0402)

C12, C13, C14 3 15 pF capacitors COG (0402)

C16 1 100 nF capacitor COG (0402)

C17 1 100 pF capacitor COG (0402)

C18 1 180 pF capacitor COG (0402)

C19 1 6.8 pF capacitor COG (0402)

R1 1 100 ohm resistors (0402) -

R2,R3,R7 3 50 ohm resistors (0402) -

R4 1 2.2 kohm resistor (0402) -

R5 1 8.2 kohm resistor (0402) -

Murata Manufacturing Co., Ltd

R6 1 4.7 kohm resistor (0402) -

R8, R9, R10 3 100 ohm resistors (0402) -

U1, U2 2 Balun JTI - 2450BL15K100 JOHANSON TECHNOLOGY

U3 1 Balun ADT4-5WT Mini Circuits

X1 1 7.5 nH inductor CS (0402) Coilcraft, Inc

X2 1 0.2 pF capacitor COG (0402) Murata Manufacturing Co., Ltd

X3 1 10 nH inductor CS (0402) Coilcraft, Inc

X4 0 NC -

X5 0 NC -

X6, X8 2 12 nH inductor CS (0402) Coilcraft, Inc

X7 0 NC -

X9 1 1 pF capacitor COG (0402) Murata Manufacturing Co., Ltd

L1, L2 2 11 nH inductors CS (0402)

Coilcraft, Inc

L3, L4 2 220 nH inductors CS (1206)

Note: 1 For optimum performance a low-noise 3.3 V power supply must be used.

2 The 3.3 V and 5 V power supplies are split in order to maximize the isolation between RF,

LO, IF and digital sections.

56/67 Doc ID 018517 Rev 2

STW82103B Application information

11.2 Standard Mode Operation

The STW82103B can be used in Standard Mode for both RX path and TX observation path (RX Chain ON and Synthesizer ON).

In such a case the 10-bit internal DAC can drive an external PIN diode attenuator in order to calibrate the signal level at the input of the device.

Figure 26. Standard mode operation

RF_IN2

RF_IN

I_PINDRV1

I_PINDRV2

RF_IN

RF_VSS

RF_CT

MIXDRV_CT

DAC

VCTRL

MIX DRV

DIV2

VCO

BUFF

REXT_DAC

STW82103B

4:1

IF_OUT

50 Ω

CAL_VCO

PLL

ICP

VCO

calibrator

CAL_VCO

PFD

IF AMP

DBUS

IF_OUTP

IF_OUTN

DBUS_SEL

SDA/DATA

SCL/CLK

LOAD

BUF

REF_CLK

LOCK_DET

CHP

REXT_CP

Doc ID 018517 Rev 2 57/67

Application information STW82103B

11.3 Diversity mode operation with same LO frequency

The STW82103B supports the Diversity mode with the same LO frequency by using one STW82103B in Master Mode (RX Chain ON, Synthesizer ON and LO output buffer ON) and the other in Slave Mode (RX Chain ON, Synthesizer OFF and EXT VCO/LO buffer ON). This operation mode is suitable for antenna diversity.

Figure 27. Diversity mode operation with same LO frequencies

RF_IN_M

3.3V

50 Ω

RF_IN

RF_VSS

RF_CT

MIXDRV_CT

50 Ω

OUTBUFP

OUTBUFN

OUT

VCTRL

MIX DRV

DIV2

VCO

BUFF

STW82103B Master

PLL

CAL_VCO

ICP

to DAC

VCO

calibrator

CAL_VCO

PFD

IF AMP

DBUS

4:1

IF_OUTP

IF_OUTN

DBUS_SEL

SDA/DATA

SCL/CLK LOAD

BUF

CHP

REF_CLK

LOCK_DET

REXT_CP

IF_M

50 Ω

STW82103B Slave

RF_IN_S

EXTVCO_INP

100 Ω

EXTVCO_INN

MIXDRV_CT

RF_IN

RF_VSS

RF_CT

EXT LO/VCO BUF

MIX DRV

58/67 Doc ID 018517 Rev 2

DBUS

IF AMP

DBUS_SEL

SDA/DATA SCL/CLK LOAD

IF_OUTP

IF_OUTN

4:1

IF_S

50 Ω

STW82103B Application information

11.4 Diversity mode operation with different LO frequencies

The STW82103B is particularly suitable for Diversity schemes using different LO frequencies such as the Interferer Diversity. In these schemes two STW82103Bs are used, each one set in Standard Mode and with different LO frequencies.

Figure 28. Diversity mode operation with different LO frequencies

RF_IN1

RF_IN2

RF_IN

RF_VSS

RF_CT

MIXDRV_CT

RF_IN

RF_VSS

RF_CT

MIXDRV_CT

VCTRL

LO1

MIX DRV

DIV2

VCO

BUFF

LO2

MIX DRV

DIV2

VCO

BUFF

STW82103B Master

PLL

CAL_VCO

STW82103B Diversity

PLL

ICP

VCO

calibrator

VCO

calibrator

CAL_VCO

PFD

CAL_VCO

PFD

IF AMP

DBUS

IF AMP

DBUS

4:1

IF_OUTP

IF_OUTN

DBUS_SEL

SDA/DATA

SCL/CLK

LOAD

CHP

REF_CLK

LOCK_DET

REXT_CP

IF_OUTP

IF_OUTN

DBUS_SEL

SDA/DATA SCL/CLK LOAD

REF_CLK

LOCK_DET

REXT_CP

BUF

IF_OUT1

50 Ω

4:1

IF_OUT2

50 Ω

VCTRL

CAL_VCO

ICP

Doc ID 018517 Rev 2 59/67

Application information STW82103B

11.5 External VCO standard mode operation

The STW82103B can be used in Ext VCO Mode for both RX path and TX observation path (RX Chain ON, Synthesizer ON, EXT VCO/LO buffer ON and with an external VCO).

In such a case the 10-bit internal DAC can drive an external PIN diode attenuator in order to calibrate the signal level at the input of the device.

Figure 29. External VCO standard mode operation

RF_IN2

RF_IN

I_PINDRV1

I_PINDRV2

RF_IN

RF_VSS

RF_CT

MIXDRV_CT

EXTVCO_INP

EXTERNAL

VCO

DAC

LO/VCO

MIX DRV

EXT

BUF

REXT_DAC

EXTVCO_INN

STW82103B

PLL

PFD

IF AMP

DBUS

4:1

IF_OUTP

IF_OUTN

DBUS_SEL

SDA/DATA SCL/CLK

LOAD

BUF

REF_CLK

LOCK_DET

CHP

REXT_CP

ICP

IF_OUT

50 Ω

60/67 Doc ID 018517 Rev 2

STW82103B Application information

11.6 External VCO diversity mode operation with same LO

The STW82103B can be used in Diversity mode using one STW82103B in Master Mode (RX Chain ON, Synthesizer ON, EXT VCO/LO buffer ON, LO output buffer ON and with an external VCO) and the other one in Slave Mode (RX Chain ON, Synthesizer OFF and EXT VCO/LO buffer ON).

Figure 30. External VCO diversity mode operation with same LO

RF_IN_M

3.3V

50 Ω

EXTVCO_INP

100 Ω

EXTVCO_INN

RF_IN

RF_VSS

RF_CT

MIXDRV_CT

50 Ω

OUTBUFP

OUTBUFN

LO/2xLO

OUT

EXTVCO_INP

EXTERNAL

VCO

EXT LO/VCO BUF

MIX DRV

VCO

BUFF

EXTVCO_INN

STW82103B Master

to DAC

PLL

STW82103B Slave

PFD

IF AMP

DBUS

BUF

CHP

ICP

IF_OUTP

IF_OUTN

DBUS_SEL

SDA/DATA SCL/CLK

LOAD

REF_CLK

LOCK_DET

REXT_CP

DBUS_SEL

SDA/DATA SCL/CLK LOAD

4:1

IF_M

50 Ω

RF_IN_S

MIXDRV_CT

RF_IN

RF_VSS

RF_CT

MIX DRV

4:1

IF_S

50 Ω

IF AMP

IF_OUTP

IF_OUTN

Doc ID 018517 Rev 2 61/67

Evaluation kit STW82103B

12 Evaluation kit

An evaluation kit can be delivered upon request, including the following:

● Evaluation board

● GUI (graphical user interface) to program the device

● PLLSim software for PLL loop filter design and noise simulation

When ordering, please specify the following order code:

Table 23. Evaluation kit order code

Part number Description

STW82103B-EVB STW82103B evaluation kit, 2.3 to 2.7 GHz RF frequency range

62/67 Doc ID 018517 Rev 2

STW82103B Package mechanical data

13 Package mechanical data

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK

Figure 31. VFQFPN-44 package outline

packages, depending on their level of environmental compliance. ECOPACK®

is an ST trademark.

Doc ID 018517 Rev 2 63/67

Package mechanical data STW82103B

Table 24. VFQFPN-44 package dimensions

Dimensions in mm

Symbol

Min Typ Max

A 0.80 0.90 1.00

A1 - 0.02 0.05

A2 - 0.65 1.00

A3 - 0.200 -

b 0.18 0.25 0.30

D 6.85 7.00 7.15

D1 - 6.750 -

D2 3.80 3.90 4.00

D3 - 4.90 -

E 6.85 7.00 7.15

E1 - 6.750 -

E2 3.80 3.90 4.00

E3 - 4.90 -

e - 0.50 -

L 0.35 0.55 0.75

P--0.60

K (degree) - - 12

ddd - - 0.08

Note: 1 VFQFPN stands for Thermally Enhanced Very thin Fine pitch Quad Flat Package No lead.

Very thin: A=1.00 Max.

2 Details of terminal 1 identifier are optional but must be located on the top surface of the

package by using either a mold or marked features.

64/67 Doc ID 018517 Rev 2

STW82103B Revision history

14 Revision history

Table 25. Document revision history

Date Revision Changes

11-Mar-2011 1 First release

Cover page: – IIP3 value changed to +25 dBm – 2FRF-2FLO spurious rejection changed to 80 dBc – Noise figure NF changed to 10.5 dB – Removed ‘Preliminary Data’ tags. Table 3 moved to new Section 3: Absolute maximum ratings Section 2.1 becomes Section 4: Operating conditions Section 2.2 becomes Section 5: Test conditions Section 2.3 becomes Section 6: Electrical characteristics

Table 4: Operating conditions updated current consumption:

. Updated typical values of diversity master modes. Added maximum

CC3.3V

values.

. Updated typical and added maximum values.

CC5V

updated high-current mode value

1dB

RF-nFLO modified typical values

added maximum values

SSB

typical value modified

3.3 V on pins 41 and 42, modified typical values

5 V supply value on pins 31 and 32, modified typical value

IFAM

typical values for high and intermediate frequency ranges

VCOA

typical values for all frequency ranges

VCOB

split into ΔT

LK A

and ΔT

(for VCOA and VCOB). Specified as

LK B

maximum values.

noise floor @ 40 MHz

phase noise floor @ 40 MHz

19-Apr-2012 2

–I

Section 6: Electrical characteristics. Added note about Vsupply, RF frequency

range, ambient temperature and RF power conditions.

Table 6: Down converter mixer and IF amplifier electrical characteristics :

updated: – CG added minimum and max values. –IP – IIP3 added minimum values and updated typical values –nF –NF – LO to RF leakage typical value modified – RF to IF isolation typical value modified –IF –ICC –ICC

Table 8: Integer-N synthesizer electrical characteristics updated:

–K –K – ΔT

– modified table footnote 4

Table 9: Phase noise performance updated typical values of:

– Integrated Phase Noise (single sided) 100 Hz to 40 MHz – LOA open-loop phase noise @ 1 kHz, 10 kHz, 100 kHz, 10 MHz and phase

– LOB open-loop phase noise @ 1 kHz, 10 kHz, 100 kHz, 1 MHz, 10 MHz and

Doc ID 018517 Rev 2 65/67

Revision history STW82103B

Table 25. Document revision history (continued)

Date Revision Changes

Added Section 7: Typical performance characteristics.

Section 8.1.9: Voltage controlled oscillators. Modified :

– VCO frequency calibration – VCO calibration auto-restart feature – Table 12: VCOB performance against amplitude setting (frequency = 2.8

GHz) values of PN @1 MHz

Table 12: VCOB performance against amplitude setting (frequency = 2.8 GHz),

19-Apr-2012 2

modified values of linearity performance.

Section 9.3.2: I

and MUTE_TYPE in registers MUTE_&_CALIBRATION Added Section 9.4.2: Power ON sequence (I – modified Figure 23: SPI timing waveforms – modified Table 20: SPI timing parameters minimum values of t

clk_loadf.

Section 10.3.2: SPI register definitions: updated

– description of bitfields CALTYPE and MUTE_TYPE in register ST2 – description of bitfield PD[4:0] in register ST3 Added Section 10.4.2: Power ON sequence (SPI interface) Added Section 12: Evaluation kit.

C register definitions. Updated description of bitfield CALTYPE

C interface)

clk_loadr

and

66/67 Doc ID 018517 Rev 2

STW82103B

Please Read Carefully:

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Doc ID 018517 Rev 2 67/67

ST STW82103B User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Table 1. Device summary

1 Block diagram

Figure 1. STW82103B block diagram

2 Pin description

Figure 2. STW82103B pin configuration

3 Absolute maximum ratings

Table 3. Absolute maximum ratings

4 Operating conditions

Table 4. Operating conditions

Table 5. Digital logic levels

5 Test conditions

6 Electrical characteristics

Table 7. Pin diode attenuator driver (dual output current DAC) electrical characteristics

Table 9. Phase noise performance

7 Typical performance characteristics

Figure 3. Conversion gain against RF frequency

Figure 4. Noise figure against RF frequency

Figure 5. IIP3 against RF frequency

Figure 6. 2RF-2LO response against RF frequency

8 General description

8.1 Circuit description

8.1.1 Reference input stage

Figure 9. Reference frequency input buffer

8.1.2 Reference divider

8.1.3 Prescaler

8.1.4 A and B counters

Figure 10. VCO divider diagram

8.1.5 Phase frequency detector (PFD)

Figure 11. PFD diagram

8.1.6 Lock detect

8.1.7 Mute until lock

8.1.8 Charge pump

Table 10. Current values for CPSEL[2:0] selection

Figure 12. Loop filter connection

8.1.9 Voltage controlled oscillators

Figure 13. VCO typical sub-band characteristics

Table 11. VCOA performance against amplitude setting (frequency = 4.6 GHz)

Table 12. VCOB performance against amplitude setting (frequency = 2.8 GHz)

8.1.10 Output stage

8.1.11 External VCO buffer

8.1.12 Mixer and IF amplifier

Table 13. Suggested CAP[2:0] values for LO Frequency range mixer

8.1.13 Dual output current DAC

9 I2C bus interface

9.1 I2C general features

9.1.1 Data validity

Figure 14. Data validity waveform

9.1.2 START and STOP conditions

Figure 15. START and STOP condition waveform

9.1.3 Byte format and acknowledge

Figure 16. Byte format and acknowledge waveform

9.1.4 Device addressing

9.1.5 Single-byte write mode

9.1.6 Multi-byte write mode

9.1.7 Current byte address read

9.2 I2C timing specifications

9.2.1 Data and clock timing specification

Figure 17. I2C data and clock waveforms

9.2.2 I2C START and STOP timing specification

Figure 18. I2C START and STOP timing waveforms

Table 16. I2C START and STOP timing parameters

9.2.3 I2C acknowledge timing specification

Figure 19. I2C acknowledge timing waveforms

Table 17. I2C acknowledge timing parameters

9.3 I2C registers

9.3.1 I2C register summary

Table 18. I2C register list

9.3.2 I2C register definitions

9.4 Device calibration through the I2C interface

9.4.1 VCO calibration procedure (I2C interface)

9.4.2 Power ON sequence (I2C interface)

Figure 20. I2C first programming timing

9.4.3 VCO calibration auto-restart procedure (I2C interface)

10 SPI digital interface

10.1 SPI general features

Figure 21. SPI input and output bit order