ST STV7733 User Manual

STV7733

320 output dot-matrix display driver

Features

■High-voltage, row/column driver IC

■320, tri-level (high-voltage, medium voltage and ground) power outputs:

–capable of operating at 90V, absolute max.

–capable of sinking or sourcing 2mA

–Hi-Z

■Logic supply range: 2.5V to 3.3V

■Slim shape die for COG, COF and TCP solutions

■Interface:

–four dual (2-bit) input serial buses:

DBA[1:2], DBB[1:2], DBC[1:2] and DBD[1:2] operating at shift clock frequency of 10MHz, max.

–three control inputs: shift clock direction (DIR), chip select (/CS) and data latch (/DL)

–two “all output” stage control inputs: AOC1 and AOC2

■Power supplies:

–high-voltage for power outputs: 90V, max.

–logic supply suitable for battery powered applications: 2.5V, min.

Description

The STV7733 device is a low-power, controller/driver IC for dot-matrix displays. Data is encoded on two bits to select one of four possible output states: high level, medium level, ground or high impedance (Hi-Z).

Preliminary Data

The STV7733 communicates with the host controller through an 8-bit parallel interface. The input data bus is organized as four, 2 x 80-bit shift registers operating in parallel at a maximum clock frequency of 10MHz.

Logic inputs are LVCMOS compatible.

The STV7733 is available in bumped die form. Bumped die can be assembled in either a TCP or COG module.

Figure 1. Block diagram

		DIR	/CS	SCLK	VDD
DBA1					VSSL
				2 x 80-bit shift register
DBA2
		Shift register direction
DBB1	Data decoding			2 x 80-bit shift register
DBB2
					STBTEST
DBC1				2 x 80-bit shift register	OE
DBC2
DBD1				2 x 80-bit shift register
DBD2
	Q1 Q2 Q3 Q4			Q320
/DL			2 x 320-bit latch
AOC1
AOC2			Output control		VSSS
POE
HVDD					HVDD
MVDD		Tri-level output buffer stage			MVDD
VSSP					VSSP
	OUT1	OUT2		OUT320

Inputs AOC1 and AOC2 control the all output stages simultaneously to select one of five possible configurations: high level, medium level, ground, Hi-Z or data through.

Except for the data through mode, the configuration selected by AOC1 and AOC2 is applied to all outputs at the same time.

May 2007	Rev 1	1/28
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to		www.st.com
change without notice.

Contents	STV7733

Contents

1	Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 3
2	Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	4
3	Die pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	5
4	Data bus configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	6
5	Power output stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	7
6	Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	8
7	Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	9
8	AC timing requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	11
9	AC Timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	12
10	Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	13
11	Pad dimensions (in microns)/pad positions . . . . . . . . . . . . . . . . . . . .	14
12	Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	27
13	Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	27

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STV7733	Block diagram

1 Block diagram

Figure 2. STV7733 block diagram

DIR			/CS			SCLK			VDD

DBA1

DBA2

DBB1

DBB2

DBC1 DBC2

DBD1 DBD2

Data decoding	Shift register direction

2 x 80-bit shift register

2 x 80-bit shift register

2 x 80-bit shift register

2 x 80-bit shift register

						Q1 Q2 Q3 Q4	Q320
/DL							2 x 320-bit latch

AOC1

AOC2 Output control

POE

HVDD

MVDD Tri-level output buffer stage

VSSP

VSSL

STBTEST

OE

VSSS

HVDD

MVDD

VSSP

OUT1 OUT2 OUT320

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Pin description						STV7733
2	Pin description
		Table 1.	STV7733 pin description
			Pin name		Pin type	Pin description
					(I/O)
				HVDD	I	Output buffer - high-voltage supply
				MVDD	I	Output buffer - medium voltage supply
		Power		VSSP	I	Output buffer - ground level
		supplies		VDD	I	Logic power supply
				VSSL	I	Logic ground
				VSSS	I	Chip substrate level
				DBA[1:2]	I	Input data bus, 2-bit serial interface
				DBB[1:2]	I	Input data bus, 2-bit serial interface
				DBC[1:2]	I	Input data bus, 2-bit serial interface
		Input logic		DBD[1:2]	I	Input data bus, 2-bit serial interface
				SCLK	I	Data shift clock
		block
				DIR	I	Shift clock direction
				/CS	I	Chip select (0 = select, 1 = un-select)
				/DL	I	Data latch. Shift register data is transferred to the
						driver outputs at the falling edge of this pulse.
				AOC1	I	“All-output” control (all HVDD, all MVDD, all VSSP,
						data through mode) selection pin
		Power output
						“All-output” control (all HVDD, all MVDD, all VSSP,
		control		AOC2	I
						data through mode) selection pin
				POE	I	Power output enable
		Power		OUT1to OUT320	O	High-voltage power outputs
		outputs
		Test		STBTEST	I	Must be grounded
				OE	I	Must be grounded

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STV7733

3 Die pinout

Figure 3. Die pinout

VSSP

VSSP

HVDD

HVDD

MVDD

MVDD

VSSL

VSSS

VDD

DUMMY

DUMMY

DUMMY

DUMMY

OUT1

OUT2

OUT3

OUT4

OUT5

X

Y 0/0

OUT316

OUT317

OUT318

OUT319

OUT320

VSSP

VSSP

HVDD

HVDD

MVDD

MVDD

VSSL

VSSS

VDD

DUMMY

DUMMY

DUMMY

DUMMY

Die pinout

DUMMY

DUMMY

DUMMY

DUMMY

DUMMY

DUMMY

DUMMY

DUMMY

DUMMY

DUMMY

DUMMY

VDD

VSSS

VSSL

OE

DBD2

DBD1

DBC2

DBC1

DUMMY

DUMMY

DUMMY

DUMMY

DBB2

DBB1

DBA2

DBA1

VDD

VSSS

VSSL

CS

SCLK

DL

VSSL

VSSS

VDD

AOC2

AOC1

DUMMY

DUMMY

POE

DIR

STBTEST

VSSL

VSSS

VDD

DUMMY

DUMMY

DUMMY

DUMMY

DUMMY

DUMMY

DUMMY

DUMMY

DUMMY

DUMMY

DUMMY

DUMMY

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Data bus configuration	STV7733

4 Data bus configuration

Below, Table 2 describes the position of the first data sampled by the first rising edge of the SCLK clock. For the first configuration described in Table 2, that is, with input DIR = “H”, data on the 2-bit bus DBA is sampled by the first SCLK clock pulse and appears on power output OUT1. After 80 clock pulses, data on OUT1 will be shifted to OUT317 - on the high-to-low transition of input /DL. Input /CS is the chip select.

	Table 2.			Data bus configuration
	/CS		DIR		Input	Position				SCLK pulse number					Comment
									OUT1	OUT2	…	OUT79		OUT80
					DBA[1:2]	OUT			01	05		313		317
	L		H		DBB[1:2]	OUT			02	06		314		318	Left/Right shift
					DBC[1:2]	OUT			03	07		315		319
					DBD[1:2]	OUT			04	08		316		320
					DBA[1:2]	OUT			320	316		08		04
	L		L		DBB[1:2]	OUT			319	315		07		03	Right/Left shift
					DBC[1:2]	OUT			318	314		06		02
					DBD[1:2]	OUT			317	313		05		01
Note:	Data is transferred from the shift register to a latch block and then on to power output stages
	on the falling edge of input /DL, see Figure 2.

All output data is stored and held in the latch block on the rising edge of the input /DL, see Figure 2.

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STV7733	Power output stage

5 Power output stage

The power output stage is defined by a set of three switches that can select three different output voltages (HVDD, MVDD or VSSP). These switches can also be all opened to configure the output stage in a high impedance (Hi-Z) mode.

Depending on the configuration of logic inputs AOC1 and AOC2, the power output stage is configured in either a “data through” mode or a “si multaneous” mode. In the “data through” mode (for AOC1 = AOC2 = “L”), the power output stage converts the 2-bit encoded data that was loaded into the latch stage for each column into a high-voltage level that appears on the output pin. When AOC1 and AOC2 are not both “L”, the power outputs can all operate simultaneously - going to VSSP, MVDD or HVDD depending on AOC1 and AOC2 as described below in Table 3.

Table 3.	Power output truth table
DBn[1]	DBn[2]	POE	AOC1	AOC2	OUTn	Comment
X	X	L	X	X	All Hi-Z	(1)
L	L	H	L	L	Hi-Z	(2)
H	L	H	L	L	VSSP	(2)
H	H	H	L	L	MVDD	(2)
L	H	H	L	L	HVDD	(2)
X	X	H	H	L	All VSSP	(3)
X	X	H	L	H	All MVDD	(3)
X	X	H	H	H	All HVDD	(3)

1. With input POE = “L”, all power outputs are not a ctive, that is, they are all in Hi-Z.

2.Data through mode: each power output depends on the DBn[1:2] value at the falling edge of input /DL.

3.Output simultaneous mode: all power outputs depend on the “H”/”L” input values for AOC1 and AOC2.

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Absolute maximum ratings	STV7733

6 Absolute maximum ratings

Table 4.	Absolute maximum ratings
Symbol	Parameter	Value	Units
VDD	Logic supply range	-0.3, +7	V
HVDD	Driver supply range	-0.3, +90	V
MVDD	Driver supply range	-0.3, +HVdd -10	V
VIN	Logic input voltage range	-0.3, VDD + 0.3	V
IPOUT	Driver output current	±5	mA
VOUT	Power output voltage range	-0.3, +90	V
VESD	ESD susceptibility, Human Body model	2.0	kV
	(100pF discharged through 1.5kohms)
Tjmax	Maximum junction temperature	100	°C
Tstg	Storage temperature range	-50, +150	°C

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STV7733	Electrical characteristics

7 Electrical characteristics

VDD = 3V, HVDD = 70V, MVDD = 35V, VSSP = 0V, VSSL = 0V, VSSS = 0V, Tamb = 25°C, F = 10MHz, unless otherwise specified.

	Table 5.		Electrical characteristics
	Symbol			Parameter	Min.	Typ.	Max.	Units
	Supply
	VDD	VDD supply voltage			2.5	3	3.3	V
	IDD	VDD supply current with no clock, all logic inputs set to either
		0V or VDD and all power outputs in Hi-Z			-	-	0.5	µA
	IDD1	VDD dynamic supply current @ clock frequency = 5MHz
		(data frequency is 2.5MHz)			-	3	-	mA
	IDD2	V	DD	dynamic supply current @ clock frequency = 100kHz
				(1)	-	0.1	-	mA
		(data frequency = 50kHz
	HVDD	HVDD supply voltage			15		80	V
	MVDD	MVDD supply voltage(2)			15		70	V
	IPP	HVDD supply current in steady state			-	-	10	µA
	OUT1 to OUT320
	VHPOUTH	Power output high level (voltage difference versus HVDD)
		@ IHPOUTH = -0.5mA and HVDD = 80V			-	-	-10	V
		Power output medium level (voltage difference versus
	VMPOUTH	MVDD)			-	-	+10	V
		@ IMPOUTH = + 0.5mA and MVDD = 40V
		@ IMPOUTL = - 0.5mA and MVDD = 40V			-	-	-10	V
	VPOUTL	Power output low level
		@ IPOUTL = + 0.5mA			-	-	+10	V
		Output current from HVDD, MVDD (see Figure 4)
	IPOUTH	1) HVDD = 80V, MVDD = 40V			-1.42		-	mA
		2) HVDD = 60V, MVDD = 30V			-0.7			mA
		Output current from output to MVDD (Figure 4)
	IPOUTM	1) HVDD = 80V and MVDD = 40V			+1.5			mA
		2) HVDD = 60V and MVDD = 30V			+0.7			mA
	IPOUTL	Output current from output to VSSP @ Vdd=2.5V (Figure 4)			+1.5		-	mA
		1) HVDD = 80V and MVDD = 40V
	IHiZ	Output current during Hi-Z mode			-		10	µA
		@ VDD = 2.5V, HVDD = 80V and MVDD = 40V

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