ST STV7623 User Manual

Features

■ 2-level high voltage output gate driver

■ 480 channels with -40/+35 mA source/sink

output current capability

■ 75 V output swing within +/- 45 V limits

■ 3.0 to 3.6 V digital power supply

■ 1.8 V CMOS input signal compatibility

■ Selectable 480 or 400 outputs

■ Direct input to bidirectional shift registers

■ Selectable polarity and blanking function

■ High voltage BCD process technology

■ Bumped dice in tray

■ Output stage similar to STV7622

■ PCB-less compatible dice

STV7623

480 output high-voltage gate driver

STV7623 die

Description

The STV7623 is a 1-bit x 480 shift register with
dual rail high voltage/medium current output, with
global blank and polarity control.

Table 1. Device summary

Order code Temperature Package Packing

STV7623WPB3 -25

The maximum shift frequency starts from 1 MHz
for a 1.8 V type input signal, up to 10 MHz for a

3.3 V type input signal. This generic device can
be used for segmented/dot matrix
electroluminescent displays to drive an array of
organic electronic transistors, or for technologies
related to e-Paper/e-Reader/digital signage
solutions.

The device can be daisy-chained for various
display resolutions.

°C to +70°C Bumped dice 3-inch tray

August 2011 Doc ID 018939 Rev 1 1/27

www.st.com

27

Contents STV7623

Contents

1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1.1 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.1 Device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.2 Device power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.3 Power sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3 Truth tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

4 Absolute maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

5.1 DC electrical characteristics (DGND = 0 V) . . . . . . . . . . . . . . . . . . . . . . . 11

5.2 AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

5.3 Timing requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

6 Packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

7 Pad information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

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STV7623 Description

^ ^ ^ ^ ^ ^ ^ ^

B LA NK

48 0 bi ts bi - dir ec tion al sh ift r eg ist er

S TV 1

S TV 2

C LK

D IR

V P

V N

LE N GTH

TE ST

JU ST IFY

1 Description

Figure 1. STV7623 block diagram

OUT1 OUT2 OUT3 OUT4

POL

OUT477 OUT478 OUT 479 OUT480

Level Shifter

DVDD

DGND

AM08731V1

Doc ID 018939 Rev 1 3/27

Description STV7623

1.1 Pin description

Figure 2. PCB-Less COF pinout diagram

Test20

Test20
Test19
Test18
Test17
Test16
Test15
Test14
Test13
Test12
Test11

OUT480

VP
DVDD
DGND

VN

STV2
TEST

DIR
CLK

BLANK

POL

BLANK

CLK
DIR

LENGTH

STV1

VN
DGND
DVDD

VP

0UT1

Test10

Test9
Test8
Test7
Test6
Test5
Test4
Test3
Test2
Test1

Test20
Test19

Test19
Test18

Test18
Test17

Test17
Test16

Test16
Test15

Test15
Test14

Test14
Test13

Test13
Test12

Test12
Test11

Test11

OUT480

VP
DVDD
DGND

VN

STV2
TEST

DIR

DVDD

CLK

BLANK

POL

DGND

POL

BLANK

CLK

JUSTIFY

DIR

LENGTH

STV1

VN
DGND
DVDD

VP

0UT1

Test10

Test10

Test9

Test9
Test8

Test8
Test7

Test7
Test6

Test6
Test5

Test5
Test4

Test4
Test3

Test3
Test2

Test2
Test1

Test1

Test20

Test20
Test19

Test19
Test18

Test18
Test17

Test17
Test16

Test16
Test15

Test15
Test14

Test14
Test13

Test13
Test12

Test12
Test11

Test11
Out480

Out480
Out479

Out479
Out478

Out478
Out477

Out477

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

Out4

Out4
Out3

Out3
Out2

Out2
Out1

Out1

Test10

Test10

Test9

Test9
Test8

Test8
Test7

Test7
Test6

Test6
Test5

Test5
Test4

Test4
Test3

Test3
Test2

Test2
Test1

Test1

Figure 2 shows the possible design of a custom COF with wire on array (WOA) routing

(PCB-less). This example supports only 480 outputs.

Table 2. Pin description

Pin name I/O Function Description

CLK In Shift clock Input

DIR In

STV1
STV2

BLANK In

I/O

Shift direction
Control pin

Start pulse
input/output pin

Output enable
control

4/27 Doc ID 018939 Rev 1

Clock input for the chip internal shift register. Data
is shifted at each rising edge of this clock.

This pin controls the output shifting direction.

These pins are used to control the channel start
pulse input or output pin. The function of these
two pins depends on the status of DIR pin (refer
to the Section 3: Truth tables)

This pin is used to control the channel output.
When BLANK is high, the shift register is
bypassed (overriden) and all driver outputs are
fixed to VN level instantly, (when POL= L).

It is assumed this signal affect few outputs

STV7623 Description

Table 2. Pin description (continued)

Pin name I/O Function Description

When POL is low, VP and VN are swapped

POL In Polarity pin

OUT1..OUT480 Out Driver output pins

VP Power Power supply High voltage supply (eg +50 V)

DVDD Power Power supply Digital power supply

DGND Power Power supply Digital ground

VN Power Power supply Negative supply

TEST In Test pin Test pin (must be grounded in application)

functionally at the output pins level.
This signal is assumed static.

The output voltage is either VP or VN for driving
the gate electrode, depending on the data stored
in the shift register. It is assumed that only up to 4
outputs are changing level simultaneously.

LENGTH In

JUSTIFY In

Nb of active
outputs

Partial output
justify mode

In the pinout diagram:

● TEST is used to test the device.

When LENGTH =0, enable 480 outputs
When LENGTH =1, enable 400 outputs
This signal is assumed static

Only applicable when LENGTH=1
When JUSTIFY = 0, use outputs 0 to 399
When JUSTIFY = 1, use outputs 80 to 479
This signal is assumed static.

Doc ID 018939 Rev 1 5/27

Functional description STV7623

2 Functional description

The STV7623 includes all the logic and power circuits necessary to drive the thin-film
transistor (TFT) of an active matrix display backplane. A low-voltage logic block manages
data information, and a high-voltage block converts the low-voltage information stored in the
logic block into high-voltage signals applied to the display gate lines.

2.1 Device operation

In the condition of DIR=L, the STV1 start pulse input is sensed at the rising edge of CLK and
stored in the first stage of shift register, which causes the first scan signal is outputted from
the OUT1 output pin. While stored data is transferred to the next stage of the shift register at
the rising edge of the CLK signal, new data of STV1 is sensed and stored simultaneously.

The output pin (OUT1 to OUT480) supplies VP or VN voltage to the gate lines depending on
the data stored in the shift register. For normal operation, a VP voltage is outputted one by
one like a shift token from OUT1 to OUT480, in sync with CLK pulse.

STV2 goes up to high level at the 400/480th falling edge of CLK and goes down to low level
at the 401/481th falling edge of CLK. This STV2 is connected to the next driver IC STV1
signal to cascade (daisy chain) them.

When STV2 is an output, the signal is activated for 1/2 clock later.

When the chip is configured in 400 output mode, only the first 400 bits entering the shift
register are used, the remaining 80 outputs are removed from the shift register.

Figure 3. Example of input/output timing DIR = H

Example of input/output timing (DIR=0)

1 2 3 4 5 6 7 479 480 481 482

CLK

STV1
BLANK

OUT1

OUT2

OUT3

OUT4

OUT5
OUT6

OUT480

STV2

6/27 Doc ID 018939 Rev 1

STV7623 Functional description

2.2 Device power supply

The STV7623 must be used with the following conditions when operating:

– VP - VN < 75 V

– VP-DGND > 10 V

–DGND-VN>10V

Figure 4. Device power supply

Output 1 to 480

VP

DVD D
DGND

VN

2.3 Power sequencing

To prevent the device from being damaged by latchup, the power ON/OFF sequence it is
recommended to follow the procedure below:

– Power OFF => ON: DVDD -> VN -> VP

– Power ON => OFF, VP -> VN -> DVDD

Logic input

AM08733V1

Doc ID 018939 Rev 1 7/27

Functional description STV7623

Figure 5. Power sequencing

VP

DVDD

DGND

VN

AM08734V1

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STV7623 Truth tables

3 Truth tables

Table 3. Output level truth table

Input pins

Data bit Blank POL OUTn

001 VP (+)

101 VN (-)

X 1 1 VP (+)

X 1 0 VN (-)

100 VP (+)

000 VN (-)

Table 4. Output ordering truth table

Configurations

Comments

Length Justify Dir In First Last Out

0 0 0 STV1 OUT1 OUT480 STV2 All outputs

0 1 0 STV1 OUT1 OUT480 STV2 All outputs

1 0 0 STV1 OUT1 OUT400 STV2 1..400

1 1 0 STV1 OUT81 OUT480 STV2 81..480

0 0 1 STV2 OUT480 OUT1 STV1 All outputs

0 1 1 STV2 OUT480 OUT1 STV1 All outputs

1 0 1 STV2 OUT400 OUT1 STV1 1..400

1 1 1 STV2 OUT480 OUT81 STV1 81..480

When only 400 outputs are used, the remaining 80 outputs remain static.

Doc ID 018939 Rev 1 9/27