The STV7623 is a 1-bit x 480 shift register with
dual rail high voltage/medium current output, with
global blank and polarity control.
Table 1.Device summary
Order codeTemperaturePackagePacking
STV7623WPB3-25
The maximum shift frequency starts from 1 MHz
for a 1.8 V type input signal, up to 10 MHz for a
3.3 V type input signal. This generic device can
be used for segmented/dot matrix
electroluminescent displays to drive an array of
organic electronic transistors, or for technologies
related to e-Paper/e-Reader/digital signage
solutions.
The device can be daisy-chained for various
display resolutions.
Figure 2 shows the possible design of a custom COF with wire on array (WOA) routing
(PCB-less). This example supports only 480 outputs.
Table 2.Pin description
Pin nameI/OFunctionDescription
CLKInShift clock Input
DIRIn
STV1
STV2
BLANKIn
I/O
Shift direction
Control pin
Start pulse
input/output pin
Output enable
control
4/27Doc ID 018939 Rev 1
Clock input for the chip internal shift register. Data
is shifted at each rising edge of this clock.
This pin controls the output shifting direction.
These pins are used to control the channel start
pulse input or output pin. The function of these
two pins depends on the status of DIR pin (refer
to the Section 3: Truth tables)
This pin is used to control the channel output.
When BLANK is high, the shift register is
bypassed (overriden) and all driver outputs are
fixed to VN level instantly, (when POL= L).
It is assumed this signal affect few outputs
STV7623Description
Table 2.Pin description (continued)
Pin nameI/OFunctionDescription
When POL is low, VP and VN are swapped
POLInPolarity pin
OUT1..OUT480OutDriver output pins
VPPowerPower supplyHigh voltage supply (eg +50 V)
DVDDPowerPower supplyDigital power supply
DGNDPowerPower supplyDigital ground
VNPowerPower supplyNegative supply
TESTInTest pinTest pin (must be grounded in application)
functionally at the output pins level.
This signal is assumed static.
The output voltage is either VP or VN for driving
the gate electrode, depending on the data stored
in the shift register. It is assumed that only up to 4
outputs are changing level simultaneously.
LENGTHIn
JUSTIFYIn
Nb of active
outputs
Partial output
justify mode
In the pinout diagram:
●TEST is used to test the device.
When LENGTH =0, enable 480 outputs
When LENGTH =1, enable 400 outputs
This signal is assumed static
Only applicable when LENGTH=1
When JUSTIFY = 0, use outputs 0 to 399
When JUSTIFY = 1, use outputs 80 to 479
This signal is assumed static.
Doc ID 018939 Rev 15/27
Functional descriptionSTV7623
2 Functional description
The STV7623 includes all the logic and power circuits necessary to drive the thin-film
transistor (TFT) of an active matrix display backplane. A low-voltage logic block manages
data information, and a high-voltage block converts the low-voltage information stored in the
logic block into high-voltage signals applied to the display gate lines.
2.1 Device operation
In the condition of DIR=L, the STV1 start pulse input is sensed at the rising edge of CLK and
stored in the first stage of shift register, which causes the first scan signal is outputted from
the OUT1 output pin. While stored data is transferred to the next stage of the shift register at
the rising edge of the CLK signal, new data of STV1 is sensed and stored simultaneously.
The output pin (OUT1 to OUT480) supplies VP or VN voltage to the gate lines depending on
the data stored in the shift register. For normal operation, a VP voltage is outputted one by
one like a shift token from OUT1 to OUT480, in sync with CLK pulse.
STV2 goes up to high level at the 400/480th falling edge of CLK and goes down to low level
at the 401/481th falling edge of CLK. This STV2 is connected to the next driver IC STV1
signal to cascade (daisy chain) them.
When STV2 is an output, the signal is activated for 1/2 clock later.
When the chip is configured in 400 output mode, only the first 400 bits entering the shift
register are used, the remaining 80 outputs are removed from the shift register.
Figure 3.Example of input/output timing DIR = H
Example of input/output timing (DIR=0)
1234567479 480 481 482
CLK
STV1
BLANK
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT480
STV2
6/27Doc ID 018939 Rev 1
STV7623Functional description
2.2 Device power supply
The STV7623 must be used with the following conditions when operating:
–VP - VN < 75 V
–VP-DGND > 10 V
–DGND-VN>10V
Figure 4.Device power supply
Output 1 to 480
VP
DVD D
DGND
VN
2.3 Power sequencing
To prevent the device from being damaged by latchup, the power ON/OFF sequence it is
recommended to follow the procedure below:
–Power OFF => ON: DVDD -> VN -> VP
–Power ON => OFF, VP -> VN -> DVDD
Logic input
AM08733V1
Doc ID 018939 Rev 17/27
Functional descriptionSTV7623
Figure 5.Power sequencing
VP
DVDD
DGND
VN
AM08734V1
8/27Doc ID 018939 Rev 1
STV7623Truth tables
3 Truth tables
Table 3.Output level truth table
Input pins
Data bitBlankPOLOUTn
001VP (+)
101VN (-)
X11VP (+)
X10VN (-)
100VP (+)
000VN (-)
Table 4.Output ordering truth table
Configurations
Comments
Length JustifyDirInFirstLastOut
000STV1OUT1OUT480STV2All outputs
010STV1OUT1OUT480STV2All outputs
100STV1OUT1OUT400STV21..400
110STV1OUT81OUT480STV281..480
001STV2OUT480OUT1STV1All outputs
011STV2OUT480OUT1STV1All outputs
101STV2OUT400OUT1STV11..400
111STV2OUT480OUT81STV181..480
When only 400 outputs are used, the remaining 80 outputs remain static.
Doc ID 018939 Rev 19/27
Absolute maximum ratingSTV7623
4 Absolute maximum rating
Stressing the device above the rating listed in the “absolute maximum ratings” table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the operating sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Table 5.Absolute maximum ratings (V
=0V, 25°C)
SS
SymbolParameterValueUnit
V
DD
Digital supply range -0.3 to +4.0V
VPPositive voltage supply-0.3 to +50V
VNNegative voltage supply+0.3 to -50V
Vp-VnVoltage difference90V
V
I
pout
I
dout
V
out
Logic input voltage range-0.3 to DVDD+0.3mV
IN
Driver output current x
Diode output current
(1) (2) (3)
(1) (2) (3)
- 70 to +35mA
-200 to +300mA
Output voltage range-0.3 to +90V
ESD susceptibility, human body model (100 pF
V
ESD
discharged through 1.5 KΩ), on all except the V
CC
2kV
pins(4)
T
jmax
T
stg
1. Measurements done on one single output, x. The other outputs are either not used or are connected to
output x. Assumes junction temperature remains less than Tjmax during measurement.
2. All transient current measurements are made under conditions close to those encountered in a typical
application (that is, with duration of any output current spike always less than 300 ns).
3. These parameters are measured during STMicroelectronics’ internal qualification which includes
temperature characterization on standard as well as corner batches of the process. These parameters are
not tested in production.
Maximum junction temperature-40 to +100°C
Storage temperature range (die)-65 to +150°C
10/27Doc ID 018939 Rev 1
STV7623Electrical characteristics
5 Electrical characteristics
5.1 DC electrical characteristics (D
D
= 3.3 V, VP = 30 V, VN = -45V, T
VDD
Table 6.Electrical characteristics - supply
SymbolParameter
D
VDD
I
DD
I
DDL
I
DD
V
P
V
N
V
P-VN
I
PPH
1. For 3.3V CMOS input logic levels (0 or 3.3 V)
2. All input data is switched at 0.5 MHz rate.
Digital supply voltage 3.03.33.6V
Digital supply current
(1)
Digital dynamic supply
current (CLK1 freq =
(2)
1MHz)
Digital supply current at
V
= 2.0 V
IH
DC power output positive
supply voltage
DC power output negative
supply voltage
Voltage gap Vp-Vn20–80V
Power output supply current
(steady outputs)
AMB
= 25 °C, f
=0V)
GND
= 1 MHz, unless otherwise specified.
CLK
Val ue
Unit
MinTypMax
–60– µA
–900– µA
–80– µA
+10––V
––-10V
––500µA
Table 7.Electrical characteristics -
SymbolParameter
Power output high level
Vpouth
Vpoutl
Vdouth
Vdoutl
(voltage drop versus VP)
at Ipouth = -20 mA and VP =
30 V
Power output low level at Ipoutl
= +20 mA
, VN=-45 V
Output upper diode voltage
drop at Idouth = +30 mA
Output lower diode voltage
drop at Idoutl = -30 mA
Doc ID 018939 Rev 111/27
OUT1 to OUT480
Val ue
Unit
MinTypMax
–4–V
–6–V
–12V
-2-1–V
Electrical characteristicsSTV7623
Table 8.Electrical characteristics - standard mode,
All dimensions are in Microns.
Pad Placement values correspond to each pad center coordinates.
Pad Placement Origin is the center of the die.
LEAD PAD NAME PAD PLACEMENTS PAD DIMENSIONS
X = Y = X = Y =
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