ST STV-6301-E01, STV-5301-R01, STV-5301-E01, STV-6301-R01 Datasheet
®
Mono and Colour QSIF Digital Video CMOS Image Sensors
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VV5301 & VV6301
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The VV5301 and VV6301 are highly integrated digital
output imaging devices based on STMicroelectronics’s
unique CMOS sensor technology. Both of these sensors
require minimal support circuitry and provide an ideal low
cost imaging solution.
VV5301 (monochrome) and VV6301 (colourised) produce
digital video output. The video streams from both devices
contain embedded control data that can be used to enable
frame grabbing applications.
The pixel array of the VV6301 has colour filters forming a
Bayer colour pattern. This sensor requires software to
perform colour processing to allow an image to be
displayed on a PC.
The sensor can perform automatic black calibration to
remove voltage offsets in the video signal path that lead to
offsets in the output image. These offsets are removed
using 2 Digital to Analogue Convertors (DACs). The
automatic black calibration algorithmmonitorsthe average
level of the sensor black pixels and adjusts the input level
to the 2 DACs to remove the offset.
A 2 wire serial interface allows the sensor to be
reconfigured if required.
Functional block diagram
SAMPLE & HOLD
HORIZONTAL SHIFT REGISTER
PHOTO DIODE ARRAY
ANALOG
VOLTAGE
REFS.
DIGITAL
CONTROL
LOGIC
SDA
SCL
D[7:0]
VERTICAL
SHIFT
REGISTER
CLKI
CLKO
CLOCK
CIRCUIT
IMAGE
FORMAT
A/D CONVERTOR
SIN
FST
QCK
Key Features
• QSIF resolution sensor
• Automatic exposure/gain control
• Multiple digital output formats available
• I2C interface for sensor control
• Integrated 8bit ADC
• On board voltage regulator
• Automatic Black Calibration
• Variable frame rate
• Reduced flicker operating modes
Application Areas
• Toys
• Automotive systems
• Intelligent Imaging sensors
Specifications
Maximum pixel
resolution
164 x 124
Effective image
size after colour
processing
160 x 120
Pixel size 12.0µm x 12.0µm
Array size 1.92mm x 1.44mm
Exposure control Automatic ( to +44dB)
Analogue gain +18dB
Signal/Noise ratio 36dB
Supply voltage 5V DC +/− 5%
Supply current
VV5301-VV6301
2.9mA (standby)
14.6mA (active)
Operating
temperature
(ambient)
0
o
C - 40oC
(for extended temperature information please contact STMicroelectronics)
Package type 48BGA
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Table of Contents
2. Introduction ...................................................................................................................... 5
2.1 Overview...........................................................................................................................................5
2.2 Exposure, Clock Division and Gain Control......................................................................................5
2.3 Digital Interface.................................................................................................................................5
3. Operating Modes.............................................................................................................. 7
3.1 Video Timing.....................................................................................................................................7
3.2 Pixel Array.........................................................................................................................................7
3.3 System Clock Generation...............................................................................................................10
3.4 Calculating Sensor Framerate........................................................................................................10
4. Auto Black Calibration................................................................................................... 12
5. Exposure Control........................................................................................................... 13
4. Auto Black Calibration................................................................................................... 12
5. Exposure Control........................................................................................................... 13
5.1 Calculating Exposure Period...........................................................................................................13
5.2 Automatic Exposure Control...........................................................................................................13
5.3 Updating Exposure, Gain and Clock Division Settings...................................................................13
5.4 Clock Control ..................................................................................................................................13
5.5 Gain Setting....................................................................................................................................14
6. Timed Serial Interface Parameters ............................................................................... 15
6.1 Listing and Categorizing the Parameters........................................................................................15
6.2 Timed Parameter Update Points.....................................................................................................15
7. Digital Video Interface Format ...................................................................................... 16
7.1 Embedded control data...................................................................................................................16
7.2 8-Wire Parallel Mode ......................................................................................................................18
7.3 4-Wire Parallel Mode ......................................................................................................................18
7.4 Video Frame Composition ..............................................................................................................19
7.5 Qualifying the Output Data..............................................................................................................23
8. Serial Control Bus.......................................................................................................... 27
8.1 General Description........................................................................................................................27
8.2 Serial Communication Protocol.......................................................................................................27
8.3 Data Format....................................................................................................................................27
8.4 Message Interpretation...................................................................................................................28
8.5 The Programmers Model ................................................................................................................29
8.6 Types of messages.........................................................................................................................39
8.7 Serial Interface Timing....................................................................................................................41
9. Detailed AC/DC Specification........................................................................................ 43
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9.1 VV5301/VV6301 AC/DC Specification............................................................................................43
9.2 VV5301/VV6301 Power Consumption............................................................................................43
9.3 Digital Input Pad Pull-up and Pull-down Resistors..........................................................................43
10. Pinout and Pin Descriptions ......................................................................................... 44
11. VV5301/VV6301 Recommended Reference Design..................................................... 46
12. Package Details (48 pin BGA (VV5301/VV6301) .......................................................... 47
13. Evaluation kits (EVK’s) .................................................................................................. 48
14. Ordering Details .............................................................................................................49
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1. Document Revision History
Revision Date Comments
1.0 03/07/2000 Preliminary release
1.1 05/07/2000 Full datasheet release, correcting formatting of document
Table 1 : Document Revison History
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2. Introduction
2.1 Overview
VV5301/VV6301 is a QSIF format CMOS image sensor. The VV5301 sensor is a monochrome device and the VV6301 is the
colourised variant.
Important: The sensors’ output video data stream only contains raw data. A microprocessor and supporting software are
required to generate a video waveform that can be displayed on a VDU
VV5301/VV6301 have an on-board 8bit ADC, this limits the number of components required to form a complete digital imaging
system.
The VV5301/VV6301 sensor will output an image size of 164 x 124. This is an oversized QSIF image. The extra pixels that the
form the 2 pixel deep border that surrounds the true QSIF image are made available to the external colour processing algorithm.
2.2 Exposure, Clock Division and Gain Control
VV5301/VV6301 have an internal automatic exposure/gain control algorithm. This algorithm can be disabled allowing the user to
externally control the exposure. The externally calculated exposure, clock division and gain control settings would then be written
to the sensor via the I2C interface.
2.3 Digital Interface
VV5301/VV6301 have a flexible digital interface, the main components of which are listed below:
1. A tri-stateable 8-wire data bus (D[7:0]) for sending both video data and embedded timing references.
2. 4-wire and 8-wire data bus alternatives available.
3. A data qualification clock, QCK, which can be programmablevia the serial interface to behave in a number of different ways
(Tri-stateable).
4. A line start signal, LST (Tri-stateable).
5. A frame start signal, FST (Tri-stateable).
6. OEB tri-states all 5 data bus lines, D[4:0], the qualification clock, QCK and FST.
7. The ability to synchronise the operation of multiple cameras (sensor produces a synchronisation out pulse, SNO).
8. A 2-wire serial interface (SDA,SCL) for controlling and setting up the device.
2.3.1 Digital Data Bus
Along with the pixel data, codes representing the start and end of fields and the start and end of lines are embedded within the
video data stream to allow a co-processor to synchronise with video data the camera module is generating Section 7.defines the
format for the output video data stream.
2.3.2 Frame Grabber Control Signals
To complement the embedded control sequences the data qualification clock (QCK) and the field start signal (FST) signals can
be independently set-up as follows:
1. Disabled
2. Free-running.
3. Qualify only the control sequences and the pixel data.
4. Qualify the pixel data only
Mode
Input Clock
(MHz)
Note
System
Clock
Divisor
Image Size
Line Time
(µs)
Lines
per
Frame
FrameRate
(fps)
QSIF - 25 fps
14.318 1 164 x 124 271.502 147 25.06
QSIF - 30 fps
17.73 1 164 x 124 227.36 147 29.92
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2.3.3 2-wire Serial Interface
The 2-wire serial interface provides complete control over sensor setup and operation. Two serial interface broadcast addresses
are supported. One allows all sensors to be written to in parallel while the other allows all sensors and co-processors to be written
to in parallel.
Section 8. defines the serial interface communications protocol and the register map of all the locations which can be accessed
via the serial interface.
2.4 Other Features
2.4.1 Tristating Digital Outputs
The QCK, FST and Databus[7:0] pins can be tristated. The QCK pin can be independently tristated by driving the QCKTRI pin
low. The QCK, FST and upper nibble of the Databus can also be tristated via a serial register control bit, see register[116] for
more details. The lower nibble of the Databus can also be independently tristated using a different control bit in register[116].
2.4.2 Synchronising Video Timing
The video timing logic in VV5301/VV6301 can be synchronised, i.e. reset to the beginning of a timing field, by an external pin,
SIN. This pin is normally low. To enable the synchronising feature the user must drive the pin high for a number of clock periods,
c.10 CLKI periods, then drive it low again. This synchronisation should only be done every other field as the sensor has a 2 field
repeat cycle requirement for the video timing. If the SIN pin was asserted every field the exposure controller and application of
new external exposure and gain settings would not operate correctly.
2.4.3 Pixel Hold Feature
The HPIX signal can be used to freeze the internal ADC, forcing the sensor to stop converting new pixel values. If the HPIX is
driven high then the ADC will maintain the currently converted pixel value. This feature is intended to function as an external pixel
defect correction system, albeit a ver basic example.
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3. Operating Modes
3.1 Video Timing
The video format mode on power-up is QSIF 30fps by default, although a 25fps mode can also be selected, see serial
register[17], bit 6. The number of active video lines in each mode is the same (124) for both the QSIF modes. The slower frame
rate (25 fps) is implemented by simply extending the line period from 203 pixel periods to 301 pixel periods.
Table 2 details the setup for each of the video timing modes.
3.2 Pixel Array
The physical pixel array is 168 x 124 pixels. The pixel size is 12.0 µm by 12.0 µm. The output video image size is 164 x 124
pixels. The border pixels from the array are used as a shield from edge effects.
Figure 3 shows how the 164 x 124 is aligned within the bigger 168 x 124 pixel array. Image read-out is flexible. By default the
sensor read out is configured to be horizontally ‘non-shuffled’ non-interlaced raster scan. The horizontally ‘shuffled’ raster scan
order differs from a conventional raster in that the pixels of individual rows are re-ordered, with the even pixels within a row readout first, followed by the odd pixels. This ‘shuffled’ read-out within a line, groups pixels of the same colour (according to the Bayer
pattern - Figure 1) together, reducing cross talk between the colour channels. The horizontal shuffle option would normally only
be selected with the colour sensor variant, VV6301.
Video
Mode
Clock
(MHz)
System Clock Divisor Video Data Line Length Field
Length
Output
Mode
QSIF (30fps) 14.318 1 164 x 124 203 147 4-wire
QSIF (25fps) 17.73 1 164 x 124 301 147 4-wire
Table 2 : Video Timing Modes
Figure 1 : Bayer Colourisation Pattern (VV6301 only)
Green 1
Blue Green 2
Red
Odd Rows
(0,2,4,6,...)
Even Rows
(1,3,5,7,...)
Odd
Columns
(0,2,4,6,...)
Even
Columns
(1,3,5,7,...)
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RRRRRRGGGGGGGRGRGRGRGRGR
Where G - Green and R - Red
Figure 2 : Horizontal Shuffle Enabled
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Blue Green
Green Red
Blue Green
Green Red
164 Pixels
124 Pixels
4321
2
4
3
1
65
1,2,3,4,5,6,... ..., 164,165,166,167,168
1,2,3,4,5,6,8,...
.120.,121,122,123,124
Blue Green
Green Red
6
5
87
164163162161 166165
168167
168Pixels
Blue Green
Green Red
Blue Green
Green Red
Blue Green
Green Red
Blue Green
Green Red
Blue Green
Green Red
Blue Green
Green Red
Blue Green
Green Red
Blue Green
Green Red
Blue Green
Green Red
Blue Green
Green Red
Blue Green
Green Red
Blue Green
Green Red
Blue Green
Green Red
Blue Green
Green Red
Blue Green
Green Red
Blue Green
Green Red
Blue Green
Green Red
Blue Green
Green Red
Blue Green
Green Red
Blue Green
Green Red
Blue Green
Green Red
The colour dyes included in this
diagram are only applicable to
VV6301. The monochrome device
VV5301 has exactly the same
readout structure and array size as
VV6301 - but no colourised pixels
120
122
121
119
124
123
Figure 3 : Image Readout Order
Please note the column read out order. If the
readout is unshuffled then the readout order is
even,odd,even etc. If the readout is shuffled, to
avoid colour channel crosstalk, then all the even
columns are readout first followed by the odd
columns.
3 pixel band
1 pixel band
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3.3 System Clock Generation
VV5301/VV6301 generates a system clock when a quartz crystal or ceramic resonator circuit is connected to the CLKI and CLKO
pins. The device can also be driven directly from an external clock source driving CLKI.
Figure 4 : Camera Clock Source
For greater flexibility the input frequency can be divided by 1, 2, 4 or 8 to select the pixel clock frequency. Two bits in the clock
division register in the serial interface select the input clock frequency divisor. The table below gives the different frame rates that
can be selected, when CLKI = 14.318MHz, for up to 30frames per second, for each divisor.
3.4 Calculating Sensor Framerate
The VV5301/VV6301 frame rate depends upon:
• the frequency of the system clock (CLKI)
• the ADC conversion accuracy (8-bit)
• the internal clock divisor selected (1, 2, 4, or 8)
• the output format is a constant 2
User can set their own values for CLKI and also the clock divisor setting. The frame rate is determined as follows
An example is given with a clock input of 14.318MHz, 160 x120 (164 x 124) image format, 8-bit ADC conversion rate and a clock
divisor of 2.
1. Determine clock input (CLKI) frequency - 14.318MHz
2. Pixel period = (divisor x conversion factor x output format factor) / CLKI
CLKI (MHz) Divisor Pixel Period (us) Frame Rate Comments
14.318 1 1.1175 29.99 default
14.318 2 2.235 15.01
14.318 4 4.47 7.5
14.318 8 8.94 3.75
Table 3 : Clock Division (60Hz Video Mode)
X1
C2
C1
R1
32 31
CKIN
CKOUT
CLK
VV5301/VV6301
3231
CKIN
CKOUT
CMOS Driver
Clock
Source
R2
C1=C2=47pF
R1=1MΩ
R2=510Ω
X1= 14.318MHz (up to 30fps)
17.73MHz (up to 25fps)
CLOCK
DIVISION
CLK
CLOCK
DIVISION
VV5301/VV6301
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Clock divisor = 1, 2, 4 or 8.
Conversion factor = 8 for 8-bit ADC accuracy
Output format factor is 2
Example: Pixel period = (2 x 8 x 2) / 14.318MHz = 2.235µs
3. Line period = (no. of visible pixels + line overhead) x pixel period
The number of visible pixels per line is 160. The interline pixel period overhead (including the 4 border pixels that can be enabled
to qualify extra video information) is mode dependent, 43 pixel periods for 60Hz mode or 141 pixel periods for 50Hz mode.
Example: Line period = (160 + 43) x 2.235µs = 453.705µs
4. Frame period = (no. of visible lines + frame overhead) x line period
For the purposes of calculating the effective frame rate the number of active lines is assumed to be fixed at 120. The frame
overhead (which includes the 4 border lines that can be enabled to qualify extra video information) has a constant value of 27 line
periods.
Example: Frame period = (120 + 27) x 453.705µs = 66.694ms
giving a frame rate = 1 / frame period = 15 frames per second
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4. Auto Black Calibration
Black calibration is used to remove voltage offsets that cause shifts in the black level of the video signal. The VV5/6301 is
equipped with an automatic function that continually monitors the output black level and calibrates if it has moved out of range.
The signal is corrected using two “Black-Cal” DACs, B0 and B1, shown below
Figure 5 : Block Diagram of Black Calibration System
Black calibration can be split into two stages, monitor (1 cycle over 2 lines) and update (3 cycles, each cycle takes 2 lines).
During the monitor phase the current black level is compared against two threshold values. If the current value falls outside the
threshold window then an update cycle is triggered. The update cycle can also be triggered by a change in the gain applied to
sensor core or via the serial interface.
4.1 Monitor Procedure
The decision on when to re-calibrate the black level is made during the first cycle through the black reference lines. The decision
area for the black monitor is by default the last 16 pixels of the middle 128 pixels of the second designated black line, line 2.
However if this set of pixels fail to give a “good” black level then it is possible to use the penultimate group of 16 pixels.
The black reference pixels are summed, averaged and then compared with the monitor window. If the average falls outside the
window a flag is then set to force a re-calibration of the DAC values.
4.2 Update
The black calibration update sequence requires three phases and is performed over the remaining black lines at the start of the
video field, lines 3 to 8. During the first phase initial B0 DAC calibration is performed. In the second, the B1 DAC is calibrated
within the limitation of its step size. In the final phase the black level is fine tuned by re-calibrating the BO DAC.This is due to the
B1 DAC having a relatively coarse step size when high gain is applied.
The two calibration phases for the B0 DAC differ in that the first time it is calibrated it is working on common mode data. During
the final phase the B0 DAC is fine-tuned using black reference pixels.
G2:0]
DATA[7:0]
S/H
amp
ADCLK
Blk
Sig
8bit ADC
B1 DAC (8bit)
B0 DAC (8bit)
Vsig
Vref
From Sensor
ADSAM
Array
to digital logic
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5. Exposure Control
5.1 Calculating Exposure Period
The exposure time, comprising coarse and fine components, for a pixel and the analogue gain are programmable via the serial
interface.
The coarse exposure value sets the number of complete lines a pixel exposes for, while the fine exposure sets the number of
additional pixel clock cycles a pixel integrates for. The sum of the two gives the overall exposure time for the pixel array.
Exposure Time = ((Coarse setting x Line Period) + (Fine setting)) x (CLKI clock period) x Clock Divider Ratio
note1
note1: Clock Divider Ratio = 1/(Basic Clock Division * Optional Pixel Clock Divisor)
5.2 Automatic Exposure Control
With automatic exposure control selected VV5301/VV6301 uses a complex algorithm to automatically set the exposure value for
the current scene. When combined with clock control and gain control the VV5301/VV6301 can operate over a very wide range of
illumination levels.
5.3 Updating Exposure, Gain and Clock Division Settings
Although the user can write a new exposure, gain or clock division parameter at any point within the field the sensor will only
consume these new external values at a certain point. The exception to this behaviour are when the user has selected immediate
update of gain If the user has selected the former then the new gain value will be applied as soon as the serial interface message
has completed. The fine and coarse exposure values are always written in a “timed” manner. There are two “update pending”
flags available to the user (see Status0 reg[2] for details) that allows the user to detect when the sensor has consumed one of the
timed parameters. In the next section of this document we will detail all the timed parameters and describe when they are
updated.
It is important to realise that there is a 1 frame latency between a new exposure value being applied to the sensor array and the
results of this new exposure value being read-out. The same latency does not exist for the gain value. To ensure that the effect of
the new exposure and gain values are coincident the sensor delays the application of the new gain value by approximately one
frame relative to the application of the new exposure value.
If the user is using the autoincrement option in the serial interface when writing a new series of exposure/gain and clock division
parameters then it is important to ensure that the sensor receives the complete message bunch before updating any of the
parameters. It is also important that the timed parameters are updated in the correct order, we will discuss this fully in the next
section. If an autoincrement message sequence is in progress but we have reached the point in the field timing where the gain
value would normally be updated, we actually inhibit the update. We inhibit the update to ensure that the gain change is not
passed to the sensor while a change in the exposure is still pending.
5.4 Clock Control
The system clock can be divided down internally to extend the operating range of VV5301/VV6301 by allowing longer exposure
times. The clock divisor options are as follows:
If the user increases the clock divisor setting then the effective exposure period is also increased.
Clock divisor register Effective clock division
2’b00 1
2’b01 2
2’b10 4
2’b11 8
Table 4 : Available clock division
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5.5 Gain Setting
An external gain value can be written to the sensor as follows.
If the image is to dark and the exposure is already close to its maximum the automatic exposure algorithm will attempt to use
extra steps of gain to improve the image brightness. Each change applied by the internal algorithm will double the current value.
To compensate for this increase in gain the current exposure is set to half of the maximum value. This should ensure that the
user will not be aware of a step change in the scene brightness.
Similarly if the image is too bright and the integration period is short then gain will be reduced by one step (i.e. divide by two). As
before, the exposure value is set to half the maximum integration period. The exposure controller can then adjust the exposure
value as necessary to provide a correctly exposed image.
If the user disables the automatic exposure/gain controller then the extra gain settings detailed in Table 5 above are available.
Gain binary code Effective system gain
000 1.000
001 2.000
010 1.333
011 4.000
100 1.143
101 2.667
110 1.600
111 8.000
Table 5 : Gain settings
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6. Timed Serial Interface Parameters
The previous section, Exposure Control, introduced the concept of a “timed parameter”, that is information that is written via the
serial interface but will not be used immediately by the sensor, rather there will be a delay before the information is passed to the
internal registers (referred to as the working registers) from the serial interface registers (referred to as the shadow registers). It is
the contents of the working registers that will determine sensor behaviour.
6.1 Listing and Categorizing the Parameters
The timed parameters are split into 2 categories as follows:
• fine and coarse exposure
• gain
There is a “pending” flag for each of the above categories. These flags are stored in Status0 Register[2] in bits [0] and [2]. If one
of the flags is high this indicates that the working register/s controlled by that flag have yet to be updated from the according
shadow register/s. This feedback information could be useful if a user is, for example, attempting to write an external exposure
controller. The status of the pending flags allows accurate timing of the serial interface communications.
6.1.1 Fine and Coarse Exposure
The exposure category comprises registers[32,33] and [34,35].
6.1.2 Gain
The gain category simply comprises register[36].
6.2 Timed Parameter Update Points
The timed parameter categories are updated as follows:
note: We refer to odd and even fields in the table below. Each field is identical in length but we have to be able to differentiate
between fields to enable correct updating of register parameters.
If a change in exposure and gain are pending at the same time then the exposure value will be updated first followed by the gain.
This will ensure image illumination continuity from field to field.
Timed parameter category Updated point
fine and coarse exposure During the interline period between the last line of the odd field and the first
line of the even field.
gain During the interline period between line 143 and line 144 in the even field.
Table 6 : Timed Parameter Update Points
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