ST STSR3 User Manual

■ SUPPLY VOLTAGE RANGE: 4V TO 5.5V

■ TYPICAL PEAK OUTPUT CURRENT:

(SOURCE 2A, SINK 3.5A)

■ OPERATING FREQUENCY: 30 TO 750 KHz

■ SMART TURN-OFF ANTICIPATION TIMING

■ AUTOMATICTURN OFF FOR DUTY CYCLE

LESS THAN 14%

■ POSSIBILITY TO OPERATEIN

DISCONTINUOUS MODE

STSR3

SYNCHRONOUS RECTIFIERS

SMART DRIVER FOR FLYBACK

SO-8

DESCRIPTION

STSR3 Smart Driver IC provides a high current
outputs to properly drive secondary Power
Mosfets used as Synchronous Rectifier in low
output voltage, high efficiency Flyback
Converters. From a synchronizing clock input,
withdrawn on the secondary side of the isolation
transformer, the IC generates a drivi ng s ignal with
set dead time s with respect to the primary side
PWM signal .
The IC operation prevents secondary side
shoot-through conditions at t urn-on of the primary

SCHEMATIC DIAGRAM

switch providing anticipation in turn-off the output.
This sm art function is implemented by a fast
cycle-after-cycle logic control mechanism, based
on a high frequency oscillator synchronized by the
clock signal. This anticipation is externally set
through external component. A special Inhibit
function allows to shut-off the drive output. This
feature make s discontinuous conducti on mode
possible and avoids reverse conduction of the
synchronous rectifier.

Vcc

2

BIAS

UVLO

+

5.7V

CK

INHIBIT

PEAK

4

DETECTOR

+

HIGH

5

FREQUENCY
OSCILLATOR

­+

25mV

DIGITAL

CONTROL

6

SGLGND

ANTICIPATION

8

PWRGND

SETANT

SET

OUTPUT
BUFFER

3

+

OUT

GATE

7

N/C

1

1/12June 2003

STSR3

ABSOLUTE MAXIMUM RATINGS

Symbol Parameter Value Unit

V

V

OUTGATE

V

INHIBIT

V

P

TOT

ESD Human Body Model Pins 1,2, 4, 5, 6, 7, 8 ±1KV

T

T

Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition is
not implied.
(*) A higher positive voltage level can be applied to the pin with a resistor which limits the current flowing into the pin to 10mA maximum

THERMAL DATA

Symbol Parameter SO-8 Unit

R

thj-amb

R

thj-amb

(*) This value is referred to one layer pcb board with minimum copper connections for the leads. a minimum value of 120 °C/W can be
obtained improving thermal conductivity of the board

DC Input Voltage

CC

Max Gate Drive Output Voltage -0.3 to V
Max INHIBIT Voltage (*) -0.6 to V
Clock Input Voltage Range (*) -0.3 to V

CK

-0.3 to 6 V

CC
CC
CC

Continuous Power Dissipation at TA=105°C without heatsink 270 mW

Pin 3 ±0.9 KV

Storage Temperature Range

stg

Operating Junction Temperature Range -40 to +125 °C

op

Thermal Resistance Junction-case
Thermal Resistance Junction-ambient (*)

-55 to +150 °C

40 °C/W

160 °C/W

V
V
V

ORDERING CODES

TYPE SO-8 SO-8 (T&R)

STSR3 STSR3CD STSR3CD-TR

CONNECTION DIAGRAM (top view)

2/12

PIN DESCRIPTION

Pin N° Symbol Name and Function

1 NC No internally connected
2V

3 SET

CC

ANT

4 CK This input provides synchronization for IC’s operations, being the transitions

5 INHIBIT This input enables OUT

6 SGLGND Reference for all the control logic signals. This pin is completely separated from

7OUT

GATE

8 PWRGND Reference for power signals, this pin carries the full peak currents for the two

The supply voltage range from 4.0V to 5.5V allows applications with logic gate
threshold mosfets. UVLO feature guarantees proper start-up while it avoids
undesirable driving during eventual dropping of the supply voltage.

The voltage on this pin sets the anticipation (t
possible to choose among three different anticipation times by discrete

partitioning of the supply voltage.

between the two output conditions based on a positive threshold, equal for the
two slopes. A smart internal control logic mechanism using a 15MHz internal
oscillator generates proper anticipation timing at the turn-off of each output. This
feature allows safe turn-off of Synchronous Rectifier avoiding any eventual
shoot-through situation on secondary side at both transitions. Smart clock
revelation mechanism makes these operations independent by false triggering
pulses generated in light load conditions. Absolute maximum voltage rating of the
pin can be exceeded limiting the current flowing into the pin to 10mA max.

to work when its voltage is lower than the negative

GATE

threshold voltage (V

INHIBIT<VH

minimum conduction time (t

). If V

ON(GATE)

INHIBIT>VH

). In typical flyback converter application, it is

possible to turn off the synchronous MOSFET when the current through it tends to
reverse, allowing discontinuous conduction mode and providing protection to the
converter from eventual sinking current from the load.Absolute maximum voltage
rating of the pin can be exceeded limiting the current flowing into the pin to 10mA
max.

the PWRGND to prevent eventual disturbances to affect the control logic.
Gate Drive signal for synchronous MOSFET. Anticipation [t
OUT

is provided during the transition in which the clock input goes to high

GATE

level.

outputs.

) in turning off the OUT

ANT

the OUT

will be high for a

GATE

] in turning off

ANT

STSR3

It is

GATE

3/12

STSR3

ELECTRICAL CHARACTERISTICS(VCC=5V, CK= 250kHz, duty -c ycle =50%, V

INHIBIT

=-200mV, TJ=-40

to 125°C, unles s otherwise specified.)

Symbol Parameter Test Conditions Min. Typ. Max. Unit

SUPPLY INPUT AND UNDER VOLTAGE LOCK OUT

V

CCON

V

CCOFF

V

I

GATE DRIVER OUTPUTS

V
V

I

OUT

R

OUT

TURN-OFF ANTICIPATION TIME

t

ANT

I

SETANT

INHIBIT OUT

V

t

ON(GATE)

SYNCHRONIZATION INPUT

V

D

Note1:tRis measured between 10% and 90% of the final voltage; tFis measuredbetween 90%and 10% on theinitialvoltage
Note2: Parameter guaranteed by design

Start Threshold 3.8 4 V
Turn OFF Threshold After

3.5 3.6 V

Start
Zener Voltage CK=0V IZ= 2mA 5.5 5.8 6 V

Z

Unloaded Supply Current OUT

CC

Output Low Voltage I

OL

Output High Voltage I

OH

Output Source Peak

CK=0V OUT

OUTGATE
OUTGATE

= no load 15 20 mA

GATE

= no load 3 5

GATE

=-200mA 0.10 0.16 V
=200mA 4.70 4.85 V

2A

Current
Output Sink Peak Current 3.5
Output Series Source

Resistance
Output Series Sink

Resistance
OUT

t

R

t

F

t

P

GATE

OUT

GATE

Clock Propagation Delay to
Turn ON of OUT

OUT

GATE

Anticipation Time

Rise Time C
Fall Time C

GATE

Turn-off

I

OUTGATE

I

OUTGATE

=-200mA 0.75 1.5 Ω

=200mA 0.5 0.8

=5nF (Note 1) 40 ns

LOAD

=5nF (Note 1) 30 ns

LOAD

No Load 50 ns

V

= 0 to 1/3VCC; no load 75 ns

ANT

= 1/3VCCto 2/3VCC; no load 150

V

ANT

= 2/3VCCto VCC; no load 225

V

ANT

Leakage Current (Note 2) -0.1 0.1 µA

ENABLE

GATE

Threshold Voltage TJ= 25°C -30 -25 mV

H

Leakage Current (Note 2) V

I

H

V

Minimum OUT

Reference Voltage TJ= 25°C 2.6 2.8 V

CK

Duty Cycle Shut Down TJ= 25°C 13 14 %

OFF

Duty Cycle Turn ON after

GATE

On time V

T

Shut Down

= 200mV -400 nA

INHIBIT

= -200mV 1 µA

INHIBIT

= +200mV 250 ns

INHIBIT

= 25°C 18 20

J

4/12

TIMING DIAGRAM

APPLICATION INFORMATION: STSR3 IN FLYBACK CONVERTER SE CONDARY SIDE

STSR3

Feedback

Loop

TRANSFORMER

Cout

MosfetN

PWM

7

OUTGate

D3

current paths.

R3

R4

CC

4

Ck

voltage;

STSR3

CC

+5V

option

NOTES

1) Ceramic Capacitors C1 and C2 must be placed very close to the IC;

2)R1andR2settheanticipationtimebypartitioningtheV

3) R3 and R4 is a resistor divider meant to provide the correct CK voltage range;

4) R5 limits the current flowing through diode D2 when Freewheeling drain voltage is high;

5) D1 could be necessary to protect INHIBIT pin from negative voltages.

6) D2 could be necessary to protect INHIBIT pin from voltages higher than V

7) D3 could be necessary to protect CK pin from voltages higher than VCC.

8) SGLGND layout trace must not include OUT

9) A capacitor in parallel with R4 could be necessary to eliminate turn off voltage spike.

GATE

C1
100nF

8

PWRGND

INHIBIT

5

R5

D1

2

Vcc

SGLGND

SETANT

D2

VoutVin

6

3

+5V

C2
100nF

+5V

R1

R2

5/12

STSR3

EXAMPLE OF COMPONENTS S ELECTION FOR A FLYBACK CONVERTER

Flyback Specification:

=36-72V

V

IN

V

=3.3V

OUT

n=Np/Ns=4.5

and R4are calculated assuring a minimum voltage of 2.8V at Ck pin. At 36V input, t he voltage on the

R

3

secondary winding is 36/4.5=8V. Choosing R

V

×

--------------------------------------------------------------- -

R

≥ 1kΩ

4

V

INICK 2.8()

=1kΩ is cho se n. At 72V input the current at Ck pin is calculated as:

R

4

CKR3

– R3V

I

CK

–×

V

IN max()

-----------------------------------------------------

This v alue is below the maximum allowabl e current flowing into the Ck pin (10mA). If the 10mA value is
exceeded an external diode co nnec ted to V

and R2values set the anticipation time for OUT

R

1

=10kΩ,t

R

1=R2

The RC group composed by R

=150ns; for R1=0 and R2=∞,t

ANT

and the parasitic capacitance of Inhibit pin (typically 5pF) delays the

5

signal on Inhibit comparator. Th is d elay must be lower than 200ns. This condition imposes a maximum
value for R

In general a suggested value for R

of about 20kΩ.

5

is 10kΩ. At 72V input, the secondary voltage is 16V, so the maximum

5

current flowing int o Inhibit pin is 16V /10kΩ=1.6mA which is below the maximum allowable cu rren t for the
pin (10mA). If the 10mA value is exceeded an external di ode (D2) connected to V

The maximum negative voltage of –0.6V must be guaranteed for the Inhibit pin. If this negative vol tage is
exceeded the current must be limited to 50mA. If necessary, a diode (D1) connected to SGLGND can be
added to satisfy this specification.

=1.5KΩ,R4results to be:

3

------------------------------------------------------------------------- -

× 862Ω==

CK

V

– 0.3–

R

3

CC

8V 220µA– 1.5kΩ 2.8V–×

CC

must be added (D3).

GATE

=225ns.

ANT

2.8V 1.5kΩ×

16 5– 0.3–

----------------------------- -

1.5kΩ

7.13mA===

.ForR1=∞and R2=0, t

ANT

must be added.

CC

=75ns; for

6/12

STSR3

INHIBIT O P ERATION OF OUT

INHIBIT O P ERATION OF OUT

IN DIS CONTINUOUS CONDUCTION MODE

GATE

GATE

7/12

STSR3

TYPICAL PERFORMANCE CHARACTE RISTICS (unless otherwise specified Tj=25°C
Figure1 : Zener Characteristics

Figure2 : Ris e and Fall Time vs Load Capacitor

Figure4 : Sink-Source ON Resistance vs

Temperature

Figure5 : Clock Threshold Voltage vs
Temperature

Figure3 : OUT

8/12

vs Characteristics

GATE

Figure6 : INHI B IT Threshold Voltage vs
Temperature

STSR3

Figure7 : Supply Current vs Load Cap ac itor

Figure8 : Supply Current vs Clock Frequency

Figure10 : Duty Cycle Shu t Down vs

Temperature

Figure11 : Duty Cycle Turn ON After Shut Down
vs Temperature

Figure9 : G ATE ON Time vs Temperature

Figure12 : Clock Leakage Current vs Clock

Voltage

9/12

STSR3

SO-8 MECHANICAL DATA

DIM.

A 1.35 1.75 0.053 0.069
A1 0.10 0.25 0.04 0.010
A2 1.10 1.65 0.043 0.065

B 0.33 0.51 0.013 0.020

C 0.19 0.25 0.007 0.010

D 4.80 5.00 0.189 0.197

E 3.80 4.00 0.150 0.157

e 1.27 0.050

H 5.80 6.20 0.228 0.244

h 0.25 0.50 0.010 0.020

L 0.40 1.27 0.016 0.050

k ˚ (max.)

ddd 0.1 0.04

MIN. TYP MAX. MIN. TYP. MAX.

mm. inch

8

10/12

0016023/C

Tape & Reel SO-8 MECHANICAL DATA

mm. inch

DIM.

MIN. TYP MAX. MIN. TYP. MAX.

A 330 12.992

C 12.8 13.2 0.504 0.519

D 20.2 0.795

N 60 2.362

T 22.4 0.882
Ao 8.1 8.5 0.319 0.335
Bo 5.5 5.9 0.216 0.232
Ko 2.1 2.3 0.082 0.090
Po 3.9 4.1 0.153 0.161

P 7.9 8.1 0.311 0.319

STSR3

11/12

STSR3

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the
consequences of use o f suc h inf ormat ion n or f or an y infr ingeme nt of paten ts or oth er ri gh ts of third part ies whic h may resul t f rom
its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications
mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information
previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or
systems without express written approval of STMicroelectronics.

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