ST STR71xF User Manual

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Page 1

August 2006 Rev 9 1/74

STR71xF

ARM7TDMI™ 32-bit MCU with Flash, USB, CAN

5 timers, ADC, 10 communications interfaces

■ Core

– ARM7TDMI 32-bit RISC CPU – 59 MIPS @ 66 MHz from SRAM – 45 MIPS @ 50 MHz from Flash

■ Memories

– Up to 256Kbytes Flash program memory

(10 kcycles endurance, 20 yrs retention @ 85° C)

– 16K bytes Flash data memory

(100 kcycles endurance, 20 yrs retention@

85° C) – Up to 64 Kbytes RAM – External Memory Interface (EMI) for up to 4

banks of SRAM, Flash, ROM – Multi-boot capability

■ Clock, Reset and Supply Management

– 3.0 to 3.6V application supply and I/Os – Internal 1.8V regulator for core supply – Clock input from 0 to 16.5 MHz – Embedded RTC oscillator running from

external 32 kHz crystal – Embedded PLL for CPU clock – Realtime Clock for clock-calendar function – 5 power saving modes: SLOW, WAIT,

LPWAIT, STOP and STANDBY modes

■ Nested interrupt controller

– Fast interrupt handling with multiple vectors – 32 vectors with 16 IRQ priority levels – 2 maskable FIQ sources

■ Up to 48 I/O ports

– 30/32/48 multifunctional bidirectional I/Os

– Up to 14 ports with interrupt capability

■ 5 Timers

– 16-bit watchdog timer – 3 16-bit timers with 2 input captures, 2

output compares, PWM and pulse counter

– 16-bit timer for timebase functions

■ 10 Communications Interfaces

–2 I

C interfaces (1 multiplexed with SPI) – 4 UART asynchronous serial interfaces – Smart Card ISO7816-3 interface on UART1 – 2 BSPI synchronous serial interfaces – CAN interface (2.0B Active) – USB Full Speed (12Mbit/s) Device Function

with Suspend and Resume

– HDLC synchronous communications

■ 4-channel 12-bit A/D Converter

– Sampling frequency up to 1kHz – Conversion range: 0 to 2.5V

■ Development Tools support

LQFP64

10 x 10

LQFP144

20 x 20

LFBGA64 8 x 8 x 1.7

LFBGA144 10 x 10 x 1.7

LFBGA64 8 x 8 x 1.7

Table 1. Device summary

Features

STR710

FZ1

STR710

FZ2

STR710RZSTR711

FR0

STR711

FR1

STR711

FR2

STR712

FR0

STR712

FR1

STR712

FR2

STR715

FRx

Flash - Kbytes 128+16 256+16 0 64+16 128+16 256+16 64+16 128+16 256+16 64+16

RAM - Kbytes 32 64 64 16 32 64 16 32 64 16

Peripheral Functions CAN, EMI, USB, 48 I/Os USB, 30 I/Os CAN, 32 I/Os 32 I/Os

Operating Voltage 3.0 to 3.6V

Operating Temp. -40 to +85°C

Packages

T=LQFP144 20 x 20

H=LFBGA144 10 x10

T=LQFP64 10 x10 / H=LFBGA64 8 x 8 x 1.7

www.st.com

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Contents STR71xF

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Contents

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.2 On-Chip Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

1.3 Related Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

1.4 Pin Description for 144-Pin Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

1.5 Pin description for 64-pin packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

1.6 External Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

1.7 I/O Port Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

1.8 Memory Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

2 Electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

2.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

2.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

2.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

2.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

2.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

2.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

2.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

2.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

2.3.1 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

2.3.2 Clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

2.3.3 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

2.3.4 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

2.3.5 I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

2.3.6 TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

2.3.7 EMI - Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

2.3.8 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

2.3.9 ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

3 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

3.1 Package Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

3.2 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

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4 Product history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

5 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Note: For detailed information on the STR710 Microcontroller memory, registers and peripherals,

please refer to the STR710 Reference Manual.

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Introduction STR71xF

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1 Introduction

This datasheet provides the STR71x Ordering Information, Mechanical and Electrical Device Characteristics.

For complete information on the STR710 Microcontroller memory, registers and peripherals. please refer to the STR710 Reference Manual.

For information on programming, erasing and protection of the internal Flash memory please refer to the STR7 Flash Programming Reference Manual

For information on the ARM7TDMI core please refer to the ARM7TDMI Technical Reference Manual.

1.1 Overview

ARM® core with embedded Flash & RAM

The STR710 series is a family of ARM-powered 32-bit Microcontrollers with embedded Flash and RAM. It combines the high performance ARM7TDMI CPU with an extensive range of peripheral functions and enhanced I/O capabilities. STR71xF devices have on-chip high-speed single voltage FLASH memory and high-speed RAM. STR710R devices have high-speed RAM but no internal Flash. The STR710 family has an embedded ARM core and is therefore compatible with all ARM tools and software.

Extensive tools support

STMicroelectronics’ 32-bit, ARM core-based microcontrollers are supported by a complete range of high-end and low-cost development tools to meet the needs of application developers. This extensive line of hardware/software tools includes starter kits and complete development packages all tailored for ST’s ARM core-based MCUs. The range of development packages includes third-party solutions that come complete with a graphical development environment and an in-circuit emulator/programmer featuring a JTAG application interface. These support a range of embedded operating systems (OS), while several royalty-free OSs are also available.

For more information, please refer to ST MCU site http://www.st.com/mcu

Package Choice: Low Pin-Count 64-pin or Feature-Rich 144-pin LQFP or BGA

The STR710 family is available in 5 main versions.

The 144-pin versions have the full set of all features including CAN, USB and External Memory Interface (EMI).

● STR710F: 144-pin BGA or LQFP with CAN, USB and EMI

● STR710R: Flashless 144-pin BGA or LQFP with CAN, USB and EMI (no internal Flash

memory)

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The three 64-pin versions (BGA or LQFP) do not include External Memory Interface.

● STR715F: 64-pin BGA or LQFP without CAN or USB

● STR711F: 64-pin BGA or LQFP with USB

● STR712F: 64-pin BGA or LQFP with CAN

High Speed Flash Memory (STR71xF)

The Flash program memory is organized in two banks of 32-bit wide Burst Flash memories enabling true read-while-write (RWW) operation. Device Bank 0 is up to 256 Kbytes in size, typically for the application program code. Bank 1 is 16K bytes, typically used for storing data constants. Both banks are accessed by the CPU with zero wait states @ 33 MHz

Bank 0 memory endurance is 10K write/erase cycles and Bank 1 endurance is 100K write/erase cycles. Data retention is 20 years at 85°C on both banks. The two banks can be accessed independently in read or write. Flash memory can be accessed in two modes:

● Burst mode: 64-bit wide memory access at up to 50 MHz.

● Direct 32-bit wide memory access for deterministic operation at up to 33 MHz.

The STR7 embedded Flash memory can be programmed using In-Circuit Programming or In-Application programming.

IAP (In-Application Programming): The IAP is the ability to re-program the Flash memory of a microcontroller while the user program is running.

ICP (In-Circuit Programming): The ICP is the ability to program the Flash memory of a microcontroller using JTAG protocol while the device is mounted on the user application board.

The Flash memory can be protected against different types of unwanted access (read/write/erase). There are two types of protection:

● Sector Write Protection

● Flash Debug Protection (locks JTAG access)

Refer to the STR7 Flash Programming Reference manual for details.

Optional External Memory (STR710)

The non-multiplexed 16-bit data/24-bit address bus available on the STR710 (144-pin) supports four 16-Mbyte banks of external memory. Wait states are programmable individually for each bank allowing different memory types (Flash, EPROM, ROM, SRAM etc.) to be used to store programs or data.

Figure 1 shows the general block diagram of the device family.

Flexible Power Management

To minimize power consumption, you can program the STR710 to switch to SLOW, WAIT, LPWAIT (low power wait), STOP or STANDBY mode depending on the current system activity in the application.

Flexible Clock Control

Two external clock sources can be used, a main clock and a 32 kHz backup clock. The embedded PLL allows the internal system clock (up to 66 MHz) to be generated from a main clock frequency of 16 MHz or less. The PLL output frequency can be programmed using a wide selection of multipliers and dividers. The microcontroller core, APB1 and APB2 peripherals are in separate clock domains and can be programmed to run at different frequencies during application runtime. The clock to each peripheral is gated with an

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individual control bit to optimize power usage by turning off peripherals any time they are not required.

Volt a g e R e gul a tor s

The STR710 requires an external 3.0-3.6V power supply. There are two internal Voltage Regulators for generating the 1.8V power supply for the core and peripherals. The main VR is switched off during low power operation.

Low Voltage Detectors

Each voltage regulator has an embedded LVD that monitors the internal 1.8V supply. If the regulated voltage drops below a certain threshold, the LVD will reset the STR710. This enhances the security of the system by preventing the MCU from going into an unpredictable state.

An external reset circuit must be used to provide the RESET at V

power-up. It is not sufficient to rely on the RESET generated by the LVD in this case. This is because LVD operation is guaranteed only when V

is within the specification.

1.2 On-Chip Peripherals

CAN Interface (STR710 and STR712)

The CAN module is compliant with the CAN specification V2.0 part B (active). The bit rate can be programmed up to 1 MBaud.

USB Interface (STR710 and STR711)

The full-speed USB interface is USB V2.0 compliant and provides up to 16 bidirectional/32 unidirectional endpoints, up to 12 Mb/s (full-speed), support for bulk transfer, isochronous transfers and USB Suspend/Resume functions.

Standard Timers

Each of the four timers have a 16-bit free-running counter with 7-bit prescaler

Three timers each provide up to two input capture/output compare functions, a pulse counter function, and a PWM channel with selectable frequency.

The fourth timer is not connected to the I/O ports. It can be used by the application software for general timing functions.

Realtime Clock (RTC)

The RTC provides a set of continuously running counters driven by the 32 kHz external crystal. The RTC can be used as a general timebase or clock/calendar/alarm function. When the STR710 is in Standby mode the RTC can be kept running, powered by the low power voltage regulator and driven by the 32 kHz external crystal.

UARTs

The 4 UARTs allow full duplex, asynchronous, communications with external devices with independently programmable TX and RX baud rates up to 1.25 Mb/s.

Smart Card Interface

UART1 is configurable to function either as a general purpose UART or as an asynchronous Smart Card interface as defined by ISO 7816-3. It includes Smart Card clock generation and provides support features for synchronous cards.

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Buffered Serial Peripheral Interfaces (BSPI)

Each of the two SPIs allow full duplex, synchronous communications with external devices, master or slave communication at up to 5.5Mb/s in Master mode and 4 Mb/s in Slave mode.

C Interfaces

The two I

C Interfaces provide multi-master and slave functions, support normal and fast

C mode (400 kHz) and 7 or 10-bit addressing modes.

One I

C Interface is multiplexed with one SPI, so either 2xSPI+1x I2C or 1xSPI+2x I2C may

be used at a time.

HDLC interface

The High Level Data Link Controller (HDLC) unit supports full duplex operation and NRZ, NRZI, FM0 or MANCHESTER protocols. It has an internal 8-bit baud rate generator.

A/D Converter

The Analog to Digital Converter, converts in single channel or up to 4 channels in singleshot or round robin mode. Resolution is 12-bit with a sampling frequency of up to 1 kHz. The input voltage range is 0-2.5V.

Watchdog

The 16-bit Watchdog Timer protects the application against hardware or software failures and ensures recovery by generating a reset.

I/O Ports

The 48 I/O ports are programmable as Inputs or Outputs.

External Interrupts

Up to 14 external interrupts are available for application use or to wake-up the application from STOP mode.

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Figure 1. STR710 Block Diagram

APB BUS

USBDP USBDN

P0[15:0]

I/O PORT 0

FLASH*

Program Memory

64/128/256K

I2C0

I2C1

BSPI0

BSPI1

UART0

UART1 /

UART2

UART3

USB

CAN

HDLC

APB

BRIDGE 1

APB

BRIDGE 2

APB BUS

TIMER1

TIMER2

TIMER3

RTC

EXT INT (XTI)

WATCHDOG

INTERRUPT CTL(EIC)

A/D

POWER SUPPLY

PRCCU/PLL

RAM

16/32/64K

JTAG

ARM7TDMI

CPU

EXT. MEM.

STDBY

2 AF

4 AF

2 AF

3 AF

2 AF

3 AF

4 AF

2 AF

4 AF

A[19:0] D[15:0]

RDN

WEN[1:0]

RTCXTO

RTCXTI

WAKEUP

JTDI

JTCK

JTMS

JTRST

JTDO

CKOUT

RSTIN

V18[1:0] V33[6:0]

VSS[9:0]

V18BKP

14 AF

OSC

DBGRQS

BOOTEN

VREG

AVDD

AVSS

P1[15:0]

I/O PORT 1

P2[15:0]

I/O PORT 2

TIMER0

ARM7 NATIVE BUS

CS[3:0)

2 AF

1 AF

AF: alternate function on I/O port pin

INTERFACE (EMI)

A[23:20] (AF)

SMARTCARD

16K Data FLASH*

*Flash present in STR710F, not in STR710R

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1.3 Related Documentation

Available from www.arm.com:

ARM7TDMI Technical Reference Manual

Available from http://www.st.com:

STR71x Reference Manual

STR7 Flash Programming Reference Manual

AN1774 - STR710 Software development getting started

AN1775 - STR710 Hardware development getting started

AN1776 - STR710 Enhanced Interrupt Controller

AN1777 - STR710 Memory Mapping

AN1780 - Real Time Clock with STR710

AN1781 - Four 7 Segment Display Drive Using the STR710

The above is a selected list only, a full list STR71x application notes can be viewed at

http://www.st.com.

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1.4 Pin Description for 144-Pin Packages

Figure 2. STR710 LQFP Pinout

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36

108 107 106 105 104 103 102 101 100

99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73

3738394041424344454647484950515253545556575859606162636465666768697071

144

143

142

141

140

139

138

137

136

135

134

133

132

131

130

129

128

127

126

125

124

123

122

121

120

119

118

117

116

115

114

113

112

111

110

109

P0.10/U1.RX/U1.TX/SCDATA

RDn

P0.11/U1.TX/BOOT.1

P0.12/SCCLK

VSS

V33 P2.0/CSn.0 P2.1/CSn.1

P0.13/U2.RX/T2.OCMPA

P0.14/U2.TX/T2.ICAPA

P2.2/CSn.2 P2.3/CSn.3

P2.4/A.20 P2.5/A.21 P2.6/A.22

BOOTEN

P2.7/A.23

P2.8 N.C. N.C. VSS

V33

P2.9 P2.10 P2.11 P2.12 P2.13 P2.14 P2.15

JTDI JTMS JTCK JTDO

JTRSTn

TEST

P1.14/HRXD/I0.SDA P1.13/HCLK/I0.SCL P1.10/USBCLK P1.9 V33 VSS A.4 A.3 A.2 A.1 A.0 D.15 D.14 D.13 D.12 D.11 D.10 USBDN USBDP P1.12/CANTX P1.11/CANRX N.C. P1.8 P1.7/T1.OCMPA VSSIO-PLL V33IO-PLL D.9 D.8 D.7 D.6 D.5 P1.6/T1.OCMPB P1.5/T1.ICAPB P1.4/T1.ICAPA P1.3/T3.ICAPB/AIN.3 P1.2/T3.OCMPA/AIN.2

N.C.

TEST

N.C.

V33IO-PLL

N.C.

VSSIO-PLL

N.C.

DBGRQS

CKOUT

P0.15/WAKEUP

N.C.

RTCXTI

RTCXTO

STDBY

RSTIN

N.C.

VSSBKP

V18BKP

N.C.

V18

VSS18

N.C.

D.0

D.1

D.2

D.3

D.4

AVDD

AVSS

N.C.

P1.0/T3.OCMPB/AIN.0

P1.1/T3.ICAPA/AIN.1

P0.9/U0.TX/BOOT.0

P0.8/U0.RX/U0.TX

P0.7/S1.SSN

P0.6/S1.SCLK

P0.5/S1.MOSI

VSS

V33

WEn.0

WEn.1

A.19

A.18

A.17

A.16

A.15

A.14

V18

VSS18

P0.4/S1.MISO

P0.3/S0.SSN/I1.SDA

P0.2/S0.SCLK/I1.SCL

P0.1/S0.MOSI/U3.RX

P0.0/S0.MISO/U3.TX

A.13

A.12

A.11

A.10

A.9

A.8

A.7

A.6

A.5

V33

VSS

P1.15/HTXD

N.C.

LQFP144

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Legend / Abbreviations for Tab le 3 :

Type: I = input, O = output, S = supply, HiZ= high impedance,

In/Output level: C = CMOS 0.3V

/0.7V

CT= CMOS 0.3VDD/0.7VDD with input trigger

= TTL 0.8V/2V with input trigger

C/T = Programmable levels: CMOS 0.3V

/0.7VDD or TTL 0.8V / 2V

Port and control configuration:

Input: pu/pd= software enabled internal pull-up or pull down

pu= in reset state, the internal 100kΩ weak pull-up is enabled.

pd = in reset state, the internal 100kΩ weak pull-down is enabled.

Output: OD = open drain

(logic level) PP = push-pull T = true OD, (P-Buffer and protection diode to V

not implemented),

5V tolerant.

Table 2. STR710 BGA Ball Connections

ABCDEFGHJ K LM

1 P0.10 P2.0 P2.1 VSS P2.2 P2.6

BOOT

P2.12 P2.13 P2.15 JTDI N.C.

2 VSS RDn P0.11 V33 P2.3 P2.8 P2.9 JTMS

JTRST

TEST TEST N.C.

3 V33 P0.9 P0.12 P0.13 P2.4 N.C. P2.10 JTCK NU V33 N.C.

DBG RQS

4 P0.6 P0.7 P0.8 P0.14 P2.5 N.C. P2.11 JTDO CK CKOUT

VSSIO-

PLL

N.C.

5 A.19 WEn.1 WEn.0 P0.5 P2.7 VSS P2.14 N.C.

RTCX-

RTCXTI N.C. P0.15

6 P0.3 A.15 A.16 A.17 A.18 V33 V18 N.C. N.C.

V18BKPVSS

BKP

STDBY

7 P0.2 P0.1 P0.4 VSS18 V18 A.14 D.12 D.1 D.0 nc VSS18 RSTIN

8 A.9 A.10 A.11 A.13 P0.0 A.0 D.11

P1.12/

CANTX

N.C. AVSS D.3 D.2

9 VSS V33 A.5 A.6 V33 D.15 D.10 P1.8 D.9 P1.0 N.C. N.C.

10 A.8 N.C. P1.15 P1.13 VSS D.14 USBDN P1.7 D.8 P1.5 P1.1 D.4

11 A.7 N.C. P1.14 P1.10 A.2 D.13 USBDP VSS D.5 P1.4 P1.3 AVDD

12 A.12 A.4 A.3 P1.9 A.1

P1.11/

CANRX

N.C.

V33IO-

PLL

P1.6 D.7 D.6 P1.2

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Table 3. STR710 Pin Description

Pin n°

Pin Name

Typ e

Reset State

Input Output

Active in Stdby

Main

function

(after

reset)

Alternate function

LQFP144

BGA144

Input Level

interrupt

Capability

1A1

P0.10/U1.RX/ U1.TX/ SC.DATA

I/O pd CTX 4mA T Port 0.10

UART1: Receive Data input

UART1: Transmit data output.

Note: This pin may be used for Smartcard DataIn/DataOut or single wire UART (half duplex) if programmed as Alternate Function Output. The pin will be tri-stated except when UART transmission is in progress

2B2RD

External Memory Interface: Active low read signal for external memory. It maps to the OE_N input of the external components.

3C2

P0.11/BOOT.1 /U1.TX

I/O pd C

4mA X X Port 0.11

Select Boot Configuration input

UART1: Transmit data output.

4 C3 P0.12/SC.CLK I/O pd C

4mA X X Port 0.12 Smartcard reference clock output

5D1V

S Ground voltage for digital I/Os

6D2V

S Supply voltage for digital I/Os

7 B1 P2.0/CS.0 I/O

8mA X X Port 2.0

External Memory Interface: Select Memory Bank 0 output

Note: This pin is forced to output push-pull 1 mode at reset to allow boot from external memory

8 C1 P2.1/CS

.1 I/O

8mA X X Port 2.1

External Memory Interface: Select Memory Bank 1 output

9D3

P0.13/U2.RX/ T2.OCMPA

I/O pu C

X 4mA X X Port 0.13

UART2: Receive Data input

Timer2: Output Compare A output

10 D4

P0.14/U2.TX/ T2.ICAPA

I/O pu C

4mA X X Port 0.14

UART2: Transmit data output

Timer2: Input Capture A input

11 E1 P2.2/CS.2 I/O

8mA X X Port 2.2

External Memory Interface: Select Memory Bank 3 output

12 E2 P2.3/CS

.3 I/O

8mA X X Port 2.3

External Memory Interface: Select Memory Bank 4 output

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13 E3 P2.4/A.20 I/O

8mA X X Port 2.4

External Memory Interface: address bus

14 E4 P2.5/A.21 I/O

8mA X X Port 2.5

15 F1 P2.6/A.22 I/O

8mA X X Port 2.6

16 G1 BOOTEN I C

Boot control input. Enables sampling of BOOT[1:0] pins

17 E5 P2.7/A.23 I/O

8mA X X Port 2.7

External Memory Interface: address bus

18 F2 P2.8 I/O pu C

X 4mA X X Port 2.8 External interrupt INT2

19 F3 N.C. Not connected (not bonded)

20 F4 N.C. Not connected (not bonded)

21 F5 V

S Ground voltage for digital I/Os4)

22 F6 V

S Supply voltage for digital I/Os4)

23 G2 P2.9 I/O pu C

X 4mA X X Port 2.9 External interrupt INT3

24 G3 P2.10 I/O pu C

X 4mA X X Port 2.10 External interrupt INT4

25 G4 P2.11 I/O pu C

X 4mA X X Port 2.11 External interrupt INT5

26 H1 P2.12 I/O pu C

4mA X X Port 2.12

27 J1 P2.13 I/O pu C

4mA X X Port 2.13

28 G5 P2.14 I/O pu C

4mA X X Port 2.14

29 K1 P2.15 I/O pu C

4mA X X Port 2.15

30 L1 JTDI I T

JTAG Data input. External pull-up required.

31 H2 JTMS I T

JTAG Mode Selection Input. External pull-up required.

32 H3 JTCK I C

JTAG Clock Input. External pull-up or pull-down required.

33 H4 JTDO O 8mA X JTAG Data output. Note: Reset state = HiZ.

34 J2 JTRST I T

JTAG Reset Input. External pull-up required.

35 J3 NU Reserved, must be forced to ground.

36 K2 TEST Reserved, must be forced to ground.

37 M1 N.C. Not connected (not bonded)

38 L2 TEST Reserved, must be forced to ground.

39 L3 N.C. Not connected (not bonded)

Table 3. STR710 Pin Description

Pin n°

Pin Name

Typ e

Reset State

Input Output

Active in Stdby

Main

function

(after

reset)

Alternate function

LQFP144

BGA144

Input Level

interrupt

Capability

Page 14

Introduction STR71xF

14/74

40 K3 V

33IO-PLL

Supply voltage for digital I/O circuitry and for PLL reference

41 M4 N.C. Not connected (not bonded)

42 L4 V

SSIO-PLL

Ground voltage for digital I/O circuitry and for PLL reference

43 M2 N.C. Not connected (not bonded)

44 M3 DBGRQS I C

Debug Mode request input (active high)

45 K4 CKOUT O 8mA X

Clock output (f

PCLK2

) Note: Enabled by CKDIS

46 J4 CK I C Reference clock input

47 M5

P0.15/ WAKEU P

Port 0.15 Wakeup from Standby mode input.

Note: This port is input only.

48 L5 N.C. Not connected (not bonded)

49 K5 RTCXTI

Realtime Clock input and input of 32 kHz oscillator amplifier circuit

50 J5 RTCXTO Output of 32 kHz oscillator amplifier circuit

51 M6 STDBY

I/O C

4mA X X

Input: Hardware Standby mode entry input active low. Caution: External pull-up to V

required to

select normal mode. Output: Standby mode active low output following

Software Standby mode entry. Note: In Standby mode all pins are in high

impedance except those marked Active in Stdby

52 M7 RSTIN

X Reset input

53 H5 N.C. Not connected (not bonded)

54 L6 V

SSBKP

S X Stabilization for low power voltage regulator.

55 K6 V

18BKP

Stabilization for low power voltage regulator. Requires external capacitors of at least 1µF between V

18BKP

and V

SS18BKP

. See Figure 5. Note: If the low power voltage regulator is bypassed, this pin can be connected to an external 1.8V supply.

56 J6 N.C. Not connected (not bonded)

57 H6 N.C. Not connected (not bonded)

58 G6 V

Stabilization for main voltage regulator. Requires external capacitors of at least 10µF + 33nF between V

and V

SS18

. See Figure 5.

Table 3. STR710 Pin Description

Pin n°

Pin Name

Typ e

Reset State

Input Output

Active in Stdby

Main

function

(after

reset)

Alternate function

LQFP144

BGA144

Input Level

interrupt

Capability

Page 15

STR71xF Introduction

15/74

59 L7 V

SS18

S Stabilization for main voltage regulator.

60 K7 N.C. Not connected (not bonded)

61 J7 D.0 I/O

8mA

External Memory Interface: data bus

62 H7 D.1 I/O

8mA

63 M8 D.2 I/O

8mA

64 L8 D.3 I/O

8mA

65 M10 D.4 I/O

8mA

66 M11 V

DDA

S Supply voltage for A/D Converter

67 K8 V

SSA

S Ground voltage for A/D Converter

68 J8 N.C. Not connected (not bonded)

69 M9 N.C. Not connected (not bonded)

70 L9 N.C. Not connected (not bonded)

71 K9

P1.0/T3.OCM PB/AIN.0

I/O pu C

4mA X X Port 1.0

Timer 3: Output Compare B

ADC: Analog input 0

72 L10

P1.1/T3.ICAP A/T3.EXTCLK/ AIN.1

I/O pu C

4mA X X Port 1.1

Timer 3: Input Capture A or External Clock input

ADC: Analog input 1

73 M12

P1.2/T3.OCM PA/AIN.2

I/O pu C

4mA X X Port 1.2

Timer 3: Output Compare A

ADC: Analog input 2

74 L11

P1.3/T3.ICAP B/AIN.3

I/O pu C

4mA X X Port 1.3

Timer 3: Input Capture B

ADC: Analog input 3

75 K11

P1.4/T1.ICAP A/T1.EXTCLK

I/O pu C

4mA X X Port 1.4

Timer 1: Input Capture A

Timer 1: External Clock input

76 K10

P1.5/T1.ICAP B

I/O pu C

4mA X X Port 1.5

Timer 1: Input Capture B

77 J12

P1.6/T1.OCM PB

I/O pu C

4mA X X Port 1.6

Timer 1: Output Compare B

78 J11 D.5 I/O

8mA

External Memory Interface: data bus

79 L12 D.6 I/O

8mA

80 K12 D.7 I/O

8mA

81 J10 D.8 I/O

8mA

82 J9 D.9 I/O

8mA

Table 3. STR710 Pin Description

Pin n°

Pin Name

Typ e

Reset State

Input Output

Active in Stdby

Main

function

(after

reset)

Alternate function

LQFP144

BGA144

Input Level

interrupt

Capability

Page 16

Introduction STR71xF

16/74

83 H12 V

33IO-PLL

Supply voltage for digital I/O circuitry and for PLL reference

84 H11 V

SSIO-PLL

Ground voltage for digital I/O circuitry and for PLL reference

85 H10

P1.7/T1.OCM PA

I/O pu C

4mA X X Port 1.7

Timer 1: Output Compare A

86 H9 P1.8 I/O pd C

4mA X X Port 1.8

87 G12 N.C. Not connected (not bonded)

88 F12 P1.11/CANRX I/O pu C

X 4mA X X Port 1.11

CAN: receive data input Note: On STR710 and STR712 only

89 H8 P1.12/CANTX I/O pu C

4mA X X Port 1.12

CAN: Transmit data output Note: On STR710 and STR712 only

90 G11 USBDP I/O C

USB bidirectional data (data +). Reset state = HiZ Note: On STR710 and STR711 only This pin requires an external pull-up to V

maintain a high level.

91 G10 USBDN I/O C

USB bidirectional data (data -). Reset state = HiZ Note: On STR710 and STR711 only.

92 G9 D.10 I/O

8mA

External Memory Interface: data bus

93 G8 D.11 I/O

8mA

94 G7 D.12 I/O

8mA

95 F11 D.13 I/O

8mA

96 F10 D.14 I/O

8mA

97 F9 D.15 I/O

8mA

98 F8 A.0 O

8mA X

External Memory Interface: address bus

99 E12 A.1 O

8mA X

100 E11 A.2 O

8mA X

101 C12 A.3 O

8mA X

102 B12 A.4 O

8mA X

103 E10 V

S Ground voltage for digital I/O circuitry

104 E9 V

S Supply voltage for digital I/O circuitry

105 D12 P1.9 I/O pd C

4mA X X Port 1.9

106 D11

P1.10/ USBCLK

I/O pd

4mA X X Port 1.10

USB: 48 MHZ clock input

Table 3. STR710 Pin Description

Pin n°

Pin Name

Typ e

Reset State

Input Output

Active in Stdby

Main

function

(after

reset)

Alternate function

LQFP144

BGA144

Input Level

interrupt

Capability

Page 17

STR71xF Introduction

17/74

107 D10

P1.13/HCLK/ I0.SCL

I/O pd C

X 4mA X X Port 1.13

HDLC: reference clock input

I2C clock

108 C11

P1.14/HRXD/ I0.SDA

I/O pu C

X 4mA X X Port 1.14

HDLC: Receive data input

I2C serial data

109 B11 N.C. Not connected (not bonded)

110 B10 N.C. Not connected (not bonded)

111 C10 P1.15/HTXD I/O pu C

4mA X X Port 1.15 HDLC: Transmit data output

112 A9 V

S Ground voltage for digital I/O circuitry

113 B9 V

S Supply voltage for digital I/O circuitry

114 C9 A.5 O

8mA X

External Memory Interface: address bus

115 D9 A.6 O

8mA X

116 A11 A.7 O

8mA X

117 A10 A.8 O

8mA X

118 A8 A.9 O

8mA X

119 B8 A.10 O

8mA X

120 C8 A.11 O

8mA X

121 A12 A.12 O

8mA X

122 D8 A.13 O

8mA X

123 E8

P0.0/S0.MISO /U3.TX

I/O pu C

4mA X X Port 0.0

SPI0 Master in/Slave out data

UART3 Transmit data output

Note: Programming AF function selects UART by default. BSPI must be enabled by SPI_EN bit in the BOOTCR register.

124 B7

P0.1/S0.MOSI /U3.RX

I/O pu C

X4mA X X Port 0.1

BSPI0: Master out/Slave in data

UART3: Receive Data input

Note: Programming AF function selects UART by default. BSPI must be enabled by SPI_EN bit in the BOOTCR register.

Table 3. STR710 Pin Description

Pin n°

Pin Name

Typ e

Reset State

Input Output

Active in Stdby

Main

function

(after

reset)

Alternate function

LQFP144

BGA144

Input Level

interrupt

Capability

Page 18

Introduction STR71xF

18/74

125 A7

P0.2/S0.SCLK /I1.SCL

I/O pu C

X4mA X X Port 0.2

BSPI0: Serial Clock

I2C1: Serial clock

Note: Programming AF function selects I2C by default. BSPI must be enabled by SPI_EN bit in the BOOTCR register.

126 A6

P0.3/S0.SS

I1.SDA

I/O pu C

4mA X X Port 0.3

SPI0: Slave Select input active low.

I2C1: Serial Data

Note: Programming AF function selects I2C by default. BSPI must be enabled by SPI_EN bit in the BOOTCR register.

127 C7 P0.4/S1.MISO I/O pu C

4mA X X Port 0.4 SPI1: Master in/Slave out data

128 D7 V

SS18

S Stabilization for main voltage regulator.

129 E7 V

Stabilization for main voltage regulator. Requires external capacitors of at least 10µF + 33nF between V

and V

SS18

. See Figure 5.

130 F7 A.14 O

8mA X

External Memory Interface: address bus

131 B6 A.15 O

8mA X

132 C6 A.16 O

8mA X

133 D6 A.17 O

8mA X

134 E6 A.18 O

8mA X

135 A5 A.19 O

8mA X

136 B5 WE.1 O

8mA X

External Memory Interface: active low MSB write enable output

137 C5 WE

.0 O

8mA X

External Memory Interface: active low LSB write enable output

138 A3 V

S Supply voltage for digital I/Os

139 A2 V

S Ground voltage for digital I/Os

140 D5 P0.5/S1.MOSI I/O pu C

4mA X X Port 0.5 SPI1: Master out/Slave In data

141 A4 P0.6/S1.SCLK I/O pu C

X 4mA X X Port 0.6 SPI1: Serial Clock

142 B4 P0.7/S1.SS

I/O pu C

4mA X X Port 0.7 SPI1: Slave Select input active low

Table 3. STR710 Pin Description

Pin n°

Pin Name

Typ e

Reset State

Input Output

Active in Stdby

Main

function

(after

reset)

Alternate function

LQFP144

BGA144

Input Level

interrupt

Capability

Page 19

STR71xF Introduction

19/74

1. The Reset configuration of the I/O Ports is IPUPD (input pull-up/pull down). Refer to Table 7 on page 28. The Port bit configuration at reset is PC0=1, PC1=1, PC2=0. The port data register bit (PD) value depends on the pu/pd column which specifies whether the pull-up or pull-down is enabled at reset

2. In reset state, these pins configured as Input PU/PD with weak pull-up enabled. They must be configured by software as Alternate Function (see Table 7: Port Bit Configuration Table on page 28) to be used by the External Memory Interface.

3. In reset state, these pins configured as Input PU/PD with weak pull-down enabled to output Address 0x0000 0000 using the External Memory Interface. To access memory banks greater than 1Mbyte, they need to be configured by software as Alternate Function (see Table 7: Port Bit Configuration Table on

page 28).

4. V

33IO-PLL

and V33 are internally connected. V

SSIO-PLL

and VSS are internally connected.

5. During the reset phase, these pins are in input pull-up state. When reset is released, they are configured as Output Push-Pull.

6. During the reset phase, these pins are in input pull-up state. When reset is released, they are configured as Hi-Z.

7. During the reset phase, these pins are in input pull-down state. When reset is released, they are configured as Output Push-Pull.

8. During the reset phase, this pin is in input floating state. When reset is released, it is configured as Output Push-Pull.

143 C4

P0.8/U0.RX/ U0.TX

I/O pd CTX4mA T

Por t 0.8

UART0: Receive Data input

UART0: Transmit data output.

Note: This pin may be used for single wire UART (half duplex) if programmed as Alternate Function Output. The pin will be tri-stated except when UART transmission is in progress

144 B3

P0.9/U0.TX/ BOOT.0

I/O pd C

4mA X X Port 0.9

Select Boot Configuration input

UART0: Transmit data output

Table 3. STR710 Pin Description

Pin n°

Pin Name

Typ e

Reset State

Input Output

Active in Stdby

Main

function

(after

reset)

Alternate function

LQFP144

BGA144

Input Level

interrupt

Capability

Page 20

Introduction STR71xF

20/74

1.5 Pin description for 64-pin packages

Figure 3. STR712/STR715 LQFP64 Pinout

646362616059585756555453525150

P1.14/HRXD/I0.SDA P1.13/HCLK/I0.SCL P1.10 P1.9 VSS P1.12/CANTX

P1.11/CANRX

P1.8 P1.7/T1.OCMPA VSSIO-PLL V33IO-PLL P1.6/T1.OCMPB P1.5/T1.ICAPB P1.4/T1.ICAPA P1.3/T3.ICAPB/AIN.3 P1.2/T3.OCMPA/AIN.2

V33IO-PLL

VSSIO-PLL

P0.15/WAKEUP

RTCXTI

RTCXTO

STDBY

RSTIN

VSSBKP

V18BKP

V18

VSS18

AVD D

AVSS

P1.0/T3.OCMPB/AIN.0

P1.1/T3.ICAPA/AIN.1

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

171819202122232425262728293031

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33

P0.10/U1.RX/U1.TX/SCDATA

P0.11/U1.TX/BOOT.1

P0.12/SCCLK

VSS

P0.13/U2.RX/T2.OCMPA

P0.14/U2.TX/T2.ICAPA

BOOTEN

VSS

V33

JTDI JTMS JTCK JTDO

nJTRST

TEST

P0.9/U0.TX/BOOT.0

P0.8/U0.RX/U0.TX

P0.7/S1.SSN

P0.6/S1.SCLK

P0.5/S1.MOSI

VSS

V18

VSS18

P0.4/S1.MISO

P0.3/S0.SSN/I1.SDA

P0.2/S0.SCLK/I1.SCL

P0.1/S0.MOSI/U3.RX

P0.0/S0.MISO/U3.TX

V33

VSS

P1.15/HTXD

LQFP64

1)CANTX and CANRX in STR712F only, in STR715F they are general purpose I/Os.

Page 21

STR71xF Introduction

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Figure 4. STR711 LQFP64 Pinout

646362616059585756555453525150

P1.14/HRXD/I0.SDA P1.13/HCLK/I0.SCL P1.10/USBCLK P1.9 VSS USBDN USBDP P1.8 P1.7/T1.OCMPA VSSIO-PLL V33IO-PLL P1.6/T1.OCMPB P1.5/T1.ICAPB P1.4/T1.ICAPA P1.3/T3.ICAPB/AIN.3 P1.2/T3.OCMPA/AIN.2

V33IO-PLL

VSSIO-PLL

P0.15/WAKEUP

RTCXTI

RTCXTO

STDBY

RSTIN

VSSBKP

V18BKP

V18

VSS18

AVD D

AVS S

P1.0/T3.OCMPB/AIN.0

P1.1/T3.ICAPA/AIN.1

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

171819202122232425262728293031

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33

P0.10/U1.RX/U1.TX/SCDATA

P0.11/U1.TX/BOOT.1

P0.12/SCCLK

VSS

P0.13/U2.RX/T2.OCMPA

P0.14/U2.TX/T2.ICAPA

BOOTEN

VSS

V33

JTDI

JTMS

JTCK

JTDO

nJTRST

TEST

P0.9/U0.TX/BOOT.0

P0.8/U0.RX/U0.TX

P0.7/S1.SSN

P0.6/S1.SCLK

P0.5/S1.MOSI

VSS

V18

VSS18

P0.4/S1.MISO

P0.3/S0.SSN/I1.SDA

P0.2/S0.SCLK/I1.SCL

P0.1/S0.MOSI/U3.RX

P0.0/S0.MISO/U3.TX

V33

VSS

P1.15/HTXD

LQFP64

Table 4. STR711 BGA Ball Connections

ABCDE FGH

1 P0.10 P0.11 P0.12 P0.14 V33 JTCK TEST

V33IO-

PLL

2 P0.9 VSS P0.13 VSS JTMS JTRSTn P0.15

VSSIO-

PLL

3 P0.5 P0.7 BOOTEN JTDI NU STDBY

RTCXTI CK

4 VSS18 VSS P0.8 JTDO AVDD V18BKP RSTIN

RTCXTO

5 P0.2 P0.4 V18 P0.6 P1.9 P1.0 V18 VSSBKP

6 V33 P0.1 P0.3 P1.13 USBDP

VSSIO-

PLL

AVSS VSS18

7 VSS P0.0 P1.10 USBDN P1.7 P1.6 P1.5 P1.1

8 P1.15 P1.14 VSS P1.8

V33IO-

PLL

P1.4 P1.3 P1.2

Page 22

Introduction STR71xF

22/74

CANTX and CANRX in STR712F only, in STR715F they are general purpose I/Os.

Legend / Abbreviations for Table 6:

Type: I = input, O = output, S = supply, HiZ= high impedance,

In/Output level: C = CMOS 0.3V

/0.7V

CT= CMOS 0.8V / 2V with input trigger T

= TTL 0.3V/0.7VDD with input trigger

C/T = Programmable levels: CMOS 0.3V

/0.7VDD or TTL 0.8V / 2V

Port and control configuration:

Input: pu/pd= software enabled internal pull-up or pull down

pu= in reset state, the internal 100kΩ weak pull-up is enabled. pd = in reset state, the internal 100kΩ weak pull-down is enabled.

Output: OD = open drain

(logic level) PP = push-pull T = true OD, (P-Buffer and protection diode to V

not implemented),

5V tolerant.

Table 5. STR712/715 BGA Ball Connections

ABCDEFGH

1 P0.10 P0.11 P0.12 P0.14 V33 JTCK TEST

V33IO-

PLL

2 P0.9 VSS P0.13 VSS JTMS JTRSTn P0.15

VSSIO-

PLL

3 P0.5 P0.7 BOOTEN JTDI NU STDBY

RTCXTI CK

4 VSS18 VSS P0.8 JTDO AVDD V18BKP RSTIN

RTCXTO

5 P0.2 P0.4 V18 P0.6 P1.9 P1.0 V18 VSSBKP

6 V33 P0.1 P0.3 P1.13

P1.11/

CANRX

VSSIO-

PLL

AVSS VSS18

7 VSS P0.0 P1.10

P1.12/

CANTX

P1.7 P1.6 P1.5 P1.1

8 P1.15 P1.14 VSS P1.8

V33IO-

PLL

P1.4 P1.3 P1.2

Page 23

STR71xF Introduction

23/74

Table 6. STR711/STR712/STR715 Pin Description

Pin n°

Pin Name

Typ e

Reset State

Input Output

Active in Stdby

Main

function

(after

reset)

Alternate function

LQFP64

BGA64

Input Level

interrupt

Capability

1A1

P0.10/U1.RX/ U1.TX/ SC.DATA

I/O pd CTX 4mA T Port 0.10

UART1: Receive Data input

UART1: Transmit data output.

2B1

P0.11/BOOT.1 /U1.TX

I/O pd C

4mA X X Port 0.11

Select Boot Configuration input

UART1: Transmit data output.

3 C1 P0.12/SC.CLK I/O pd C

4mA Port 0.12 Smartcard reference clock output

4B2V

S Ground voltage for digital I/Os

5C2

P0.13/U2.RX/ T2.OCMPA

I/O pu CTX4mAX X Port 0.13

UART2: Receive Data input

Timer2: Output Compare A output

6D1

P0.14/U2.TX/ T2.ICAPA

I/O pu C

4mA X X Port 0.14

UART2: Transmit data output

Timer2: Input Capture A input

7C3BOOTEN I C

Boot control input. Enables sampling of BOOT[1:0] pins

8D2V

S Ground voltage for digital I/Os2)

9E1V

S Supply voltage for digital I/Os2)

10 D3 JTDI I T

JTAG Data input. External pull-up required.

11 E2 JTMS I T

JTAG Mode Selection Input. External pull-up required.

12 F1 JTCK I C

JTAG Clock Input. External pull-up or pull-down required.

13 D4 JTDO O 8mA X JTAG Data output. Note: Reset state = HiZ.

14 F2 JTRST I T

JTAG Reset Input. External pull-up required.

15 E3 NU Reserved, must be forced to ground.

16 G1 TEST Reserved, must be forced to ground.

17 H1 V

33IO-PLL

Supply voltage for digital I/O circuitry and for PLL reference

18 H2 V

SSIO-PLL

Ground voltage for digital I/O circuitry and for PLL reference

19 H3 CK I C Reference clock input

Page 24

Introduction STR71xF

24/74

20 G2

P0.15/ WAKEUP

ITTXX

Port 0.15 Wakeup from Standby mode input.

Note: This port is input only.

21 G3 RTCXTI

Realtime Clock input and input of 32 kHz oscillator amplifier circuit

22 H4 RTCXTO Output of 32 kHz oscillator amplifier circuit

23 F3 STDBY

I/O C

4mA X X

Input: Hardware Standby mode entry input active low. Caution: External pull-up to V33 required to select normal mode.

Output: Standby mode active low output following Software Standby mode entry.

Note: In Standby mode all pins are in high impedance except those marked Active in Stdby.

24 G4 RSTIN

X Reset input

25 H5 V

SSBKP

S X Stabilization for low power voltage regulator.

26 F4 V

18BKP

Stabilization for low power voltage regulator. Requires external capacitors of at least 1µF between V

18BKP

and V

SS18BKP

. See Figure 5. Note: If the low power voltage regulator is bypassed, this pin can be connected to an external

1.8V supply.

27 G5 V

Stabilization for main voltage regulator. Requires external capacitors of at least 10µF + 33nF between V

and V

SS18

. See Figure 5.

28 H6 V

SS18

S Stabilization for main voltage regulator.

29 E4 V

DDA

S Supply voltage for A/D Converter

30 G6 V

SSA

S Ground voltage for A/D Converter

31 F5

P1.0/T3.OCM PB/AIN.0

I/O pu C

4mA X X Port 1.0

Timer 3: Output Compare B

ADC: Analog input 0

32 H7

P1.1/T3.ICAP A/T3.EXTCLK /AIN.1

I/O pu C

4mA X X Port 1.1

Timer 3: Input Capture A or External Clock input

ADC: Analog input 1

33 H8

P1.2/T3.OCM PA/AIN.2

I/O pu C

4mA X X Port 1.2

Timer 3: Output Compare A

ADC: Analog input 2

34 G8

P1.3/T3.ICAP B/AIN.3

I/O pu C

4mA X X Port 1.3

Timer 3: Input Capture B

ADC: Analog input 3

35 F8

P1.4/T1.ICAP A/T1.EXTCLK

I/O pu C

4mA X X Port 1.4

Timer 1: Input Capture A

Timer 1: External Clock input

Table 6. STR711/STR712/STR715 Pin Description

Pin n°

Pin Name

Typ e

Reset State

Input Output

Active in Stdby

Main

function

(after

reset)

Alternate function

LQFP64

BGA64

Input Level

interrupt

Capability

Page 25

STR71xF Introduction

25/74

36 G7

P1.5/T1.ICAP B

I/O pu C

4mA X X Port 1.5

Timer 1: Input Capture B

37 F7

P1.6/T1.OCM PB

I/O pu C

4mA X X Port 1.6

Timer 1: Output Compare B

38 E8 V

33IO-PLL

Supply voltage for digital I/O circuitry and for PLL reference

39 F6 V

SSIO-PLL

Ground voltage for digital I/O circuitry and for PLL reference

40 E7

P1.7/T1.OCM PA

I/O pu C

4mA X X Port 1.7

Timer 1: Output Compare A

41 D8 P1.8 I/O pd C

4mA X X Port 1.8

42 E6 P1.11/CANRX I/O pu CTX4mA X X Port 1.11

CAN: receive data input Note: On STR710 and STR712 only

43 D7 P1.12/CANTX I/O pu C

4mA X X Port 1.12

CAN: Transmit data output Note: On STR710 and STR712 only

42 E6 USBDP I/O C

USB bidirectional data (data +). Reset state = HiZ Note: On STR710 and STR711 only This pin requires an external pull-up to V

maintain a high level.

43 D7 USBDN I/O C

USB bidirectional data (data -). Reset state = HiZ Note: On STR710 and STR711 only.

44 C8 V

S Ground voltage for digital I/O circuitry

45 E5 P1.9 I/O pd C

4mA X X Port 1.9

46 C7

P1.10/USBCL K

I/O pd

4mA X X Port 1.10

USB: 48 MHZ clock input

47 D6

P1.13/HCLK/I

0.SCL

I/O pd C

X4mA X X Port 1.13

HDLC: reference clock input

I2C clock

48 B8

P1.14/HRXD/I

0.SDA

I/O pu CTX4mA X X Port 1.14

HDLC: Receive data input

I2C serial data

49 A8 P1.15/HTXD I/O pu C

4mA X X Port 1.15 HDLC: Transmit data output

50 A7 V

S Ground voltage for digital I/O circuitry

51 A6 V

S Supply voltage for digital I/O circuitry

Table 6. STR711/STR712/STR715 Pin Description

Pin n°

Pin Name

Typ e

Reset State

Input Output

Active in Stdby

Main

function

(after

reset)

Alternate function

LQFP64

BGA64

Input Level

interrupt

Capability

Page 26

Introduction STR71xF

26/74

52 B7

P0.0/S0.MISO /U3.TX

I/O pu C

4mA X X Port 0.0

SPI0 Master in/Slave out data

UART3 Transmit data output

Note: Programming AF function selects UART by default. BSPI must be enabled by SPI_EN bit in the BOOTCR register.

53 B6

P0.1/S0.MOSI /U3.RX

I/O pu C

X4mA X X Port 0.1

BSPI0: Master out/Slave in data

UART3: Receive Data input

Note: Programming AF function selects UART by default. BSPI must be enabled by SPI_EN bit in the BOOTCR register.

54 A5

P0.2/S0.SCLK /I1.SCL

I/O pu C

X4mA X X Port 0.2

BSPI0: Serial Clock

I2C1: Serial clock

Note: Programming AF function selects I2C by default. BSPI must be enabled by SPI_EN bit in the BOOTCR register.

55 C6

P0.3/S0.SS

/I1

.SDA

I/O pu C

4mA X X Port 0.3

SPI0: Slave Select input active low.

I2C1: Serial Data

Note: Programming AF function selects I2C by default. BSPI must be enabled by SPI_EN bit in the BOOTCR register.

56 B5 P0.4/S1.MISO I/O pu C

4mA X X Port 0.4 SPI1: Master in/Slave out data

57 A4 V

SS18

S Stabilization for main voltage regulator.

58 C5 V

Stabilization for main voltage regulator. Requires external capacitors of at least 10µF + 33nF between V

and V

SS18

. See Figure 5.

59 B4 V

S Ground voltage for digital I/Os

60 A3 P0.5/S1.MOSI I/O pu C

4mA X X Port 0.5 SPI1: Master out/Slave In data

61 D5 P0.6/S1.SCLK I/O pu C

X 4mA X X Port 0.6 SPI1: Serial Clock

62 B3 P0.7/S1.SS

I/O pu C

4mA X X Port 0.7 SPI1: Slave Select input active low

Table 6. STR711/STR712/STR715 Pin Description

Pin n°

Pin Name

Typ e

Reset State

Input Output

Active in Stdby

Main

function

(after

reset)

Alternate function

LQFP64

BGA64

Input Level

interrupt

Capability

Page 27

STR71xF Introduction

27/74

2. V

33IO-PLL

and V33 are internally connected. V

SSIO-PLL

and VSS are internally connected.

1.6 External Connections

Figure 5. Recommended External Connection of V

18 and V18BKP

pins

63 C4

P0.8/U0.RX/U

0.TX

I/O pd CTX4mA T

Por t 0.8

UART0: Receive Data input

UART0: Transmit data output.

Note: This pin may be used for single wire UART (half duplex) if programmed as Alternate Function Output. The pin will be tri-stated except when UART transmission is in progress

64 A2

P0.9/U0.TX/B OOT.0

I/O pd C

4mA X X Port 0.9

Select Boot Configuration input

UART0: Transmit data output

Table 6. STR711/STR712/STR715 Pin Description

Pin n°

Pin Name

Typ e

Reset State

Input Output

Active in Stdby

Main

function

(after

reset)

Alternate function

LQFP64

BGA64

Input Level

interrupt

Capability

LQFP144

LQFP64

129 128

33 nF

10 µF

33 nF

1µF

18BKP

Page 28

Introduction STR71xF

28/74

1.7 I/O Port Configuration

Legend:

AIN: Analog Input

CMOS: CMOS Input levels

IPUPD: Input Pull Up /Pull Down

TTL: TTL Input levels

N.A.: not applicable. In Output mode, a read access to the port gets the output latch value.

Table 7. Port Bit Configuration Table

Configuration Mode

Input

Buffer

PxD

PxC2

PxC1

PxC0

Read

access

Write

access

INPUT

TTL Input Floating TTL floating I/O pin don’t care 0 0 1

CMOS Input Floating CMOS floating I/O pin don’t care 0 1 0

CMOS Input Pull-Down (IPUPD)

CMOS Pull-

Down

I/O pin 0 0 1 1

CMOS Input Pull-Up (IPUPD)

CMOS

Pull-Up

I/O pin 1 0 1 1

Analog input AIN 0 don’t care 0 0 0

OUTPUT

Output Open-Drain N.A. I/O pin 0 or 1 1 0 0

Output Push-Pull N.A.

last value

written

0 or 1 1 0 1

Alternate Function Open-Drain CMOS floating I/O pin don’t care 1 1 0

Alternate Function Push-Pull CMOS floating I/O pin don’t care 1 1 1

Page 29

STR71xF Introduction

29/74

1.8 Memory Mapping

Figure 6. Memory Map

APB BRIDGE 2 REGS

Addressable Memory Space

0x2000 0000

0x4000 0000

0x6000 0000

0x8000 0000

0xA000 0000

0xC000 0000

0xE000 0000

0xFFFF FFFF

0xC000 0000

0xC000 1000

0xC000 2000

0xC000 3000

0xC000 4000

0xC000 5000

0xC000 6000

0xC000 7000

0xC000 8000

0xC000 9000

0xC000 A000

0xC000 B000

0xC000 C000

0xE000 1000

0xE000 2000

0xE000 3000

0xE000 4000

0xFFFF FFFF

0x0000 0000

APB Memory Space

4 Gbytes

FLASH/RAM/EMI

EXTMEM

64MB

0xFFFF F800

EIC

0xFFFF F800

APB BRIDGE 1 REGS

Reserved

FLASH

256K+16K+36b

B0F0

B0F4

B0F5

B0F6

B1F0

0x4000 0000

32K

64K

FLASH Memory Space

272 Kbytes + regs

0x4000 4000

0x4000 6000

0x4001 0000

0x4002 0000

0x4003 0000

Reserved

(*) FLASH aliased at 0x0000 0000h

by system decoder for booting with valid instruction upon RESET from Block B0 (8 Kbytes)

0xE000 0000

0xE000 5000

0xE000 6000

0xE000 7000

0xE000 8000

0xE000 9000

0xE000 A000

0xE000 B000

I2C 0

I2C 1

reserved

UART 0

UART 1

UART 2

UART 3

USB + RAM

BSPI 0

BSPI 1

XTI

reserved

IOPORT 1

IOPORT 2

ADC

CLKOUT

TIMER 3

RTC

WDG

0xE000 E000

0xE000 D000

0xE000 C000

0xC000 D000

0xC000 E000

PRCCU

CAN

B0F7

0x400C 0000

0x400C 4000

0x4010 0000

reserved

TIMER 0

TIMER 1

TIMER 2

reserved

HDLC + RAM

reserved

0xC001 0000

0xC000 F000

B1F1

0x400C 2000

reserved

0x4004 0000

0x4010 DFBF

36b

FLASH Registers

0x4000 2000

RAM

64K

APB1

APB2

EIC

B0F2

B0F1

reserved

IOPORT 0

64K

B0F3

0x4000 8000

See Figure 8

Page 30

Introduction STR71xF

30/74

Figure 7. Mapping of Flash Memory Versions

B0F0

B0F4

reserved

B1F0

0x4000 0000

32K

64K

FLASH Memory Space

64 Kbytes + 16K RWW + regs

0x4000 4000

0x4000 6000

0x4001 0000

0x4002 0000

0x4003 0000

reserved

0x400C 0000

0x400C 4000

0x4010 0000

reserved

B1F1

0x400C 2000

reserved

0x4004 0000

0x4010 DFBF

36b

FLASH Registers

0x4000 2000

B0F2 B0F1

B0F3

0x4000 8000

B0F0

B0F4

B0F5

reserved

B1F0

0x4000 0000

32K

64K

FLASH Memory Space

128 Kbytes + 16K RWW + regs

0x4000 4000

0x4000 6000

0x4001 0000

0x4002 0000

0x4003 0000

reserved

0x400C 0000

0x400C 4000

0x4010 0000

reserved

B1F1

0x400C 2000

reserved

0x4004 0000

0x4010 DFBF

36b

FLASH Registers

0x4000 2000

B0F2 B0F1

B0F3

0x4000 8000

B0F0

B0F4

B0F5

B0F6

B1F0

0x4000 0000

32K

64K

FLASH Memory Space

256 Kbytes + 16K RWW + regs

0x4000 4000

0x4000 6000

0x4001 0000

0x4002 0000

0x4003 0000

B0F7

0x400C 0000

0x400C 4000

0x4010 0000

reserved

B1F1

0x400C 2000

reserved

0x4004 0000

0x4010 DFBF

36b

FLASH Registers

0x4000 2000

B0F2 B0F1

B0F3

0x4000 8000

STR715FR0xx STR711FR0xx STR712FR0xx

STR711FR1xx STR712FR1xx

STR710F72xx STR711FR2xx STR712FR2xx

STR710FZ1xx

Table 8. RAM Memory Mapping

Part Number RAM Size Start Address End Address

STR715FR0xx STR711FR0xx STR712FR0xx

16 Kbytes 0x2000 0000 0x2000 3FFF

STR710FZ1xx STR711FR1xx STR712FR1xx

32 Kbytes 0x2000 0000 0x2000 7FFF

STR710FR2xx

STR710Rxx STR711FR2xx STR712FR2xx

64 Kbytes 0x2000 0000 0x2000 FFFF

Page 31

STR71xF Introduction

31/74

Figure 8. External Memory Map

Drawing not in sc ale

Addressable Memory Space

0x2000 0000

0x4000 0000

0x6000 0000

0x8000 0000

0xA000 0000

0xC000 0000

0xE000 0000

0xFFFF FFFF

0x0000 0000

4 Gbytes

FLASH/RAM/EMI

EXTMEM

0xFFFF F800

Reserved

FLASH

BCON3

Bank3

Bank2

0x6000 0000

16M

0x6200 0000

0x6400 0000

0x6600 0000

Reserved

PRCCU

Bank1

RAM

APB1

APB2

EIC

BCON1

BCON2

BCON0

0x6C00 0000

0x6C00 0004

0x6C00 0008

0x6C00 000C

Bank0

External Memory Space

64 MBytes

CSn.0

CSn.1

CSn.2

CSn.3

0x60FF FFFF

0x62FF FFFF

0x64FF FFFF

0x66FF FFFF

Page 32

Electrical parameters STR71xF

32/74

2 Electrical parameters

2.1 Parameter conditions

Unless otherwise specified, all voltages are referred to VSS.

2.1.1 Minimum and maximum values

Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at T

=25°C and TA=TAmax (given by the

selected temperature range).

Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean±3Σ).

2.1.2 Typical values

Unless otherwise specified, typical data are based on TA=25°C, V33=3.3V (for the

3.0V≤V

≤3.6V voltage range) and V18=1.8V. They are given only as design guidelines and

are not tested.

Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated

(mean±2Σ).

2.1.3 Typical curves

Unless otherwise specified, all typical curves are given only as design guidelines and are not tested.

2.1.4 Loading capacitor

The loading conditions used for pin parameter measurement are shown in Figure 9.

2.1.5 Pin input voltage

The input voltage measurement on a pin of the device is described in Figure 10.

Figure 9. Pin loading conditions Figure 10. Pin input voltage

=50pF

STR7 PIN

Page 33

STR71xF Electrical parameters

33/74

2.2 Absolute maximum ratings

Stresses above those listed as “absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

Table 9. Voltage characteristics

Symbol Ratings Min Max Unit

V33- V

External 3.3V Supply voltage (including AV

and V

33IO-

PLL

)

-0.3 4.0

18BKP

- V

SSBKP

Digital 1.8V Supply voltage

on V

18BKP

backup supply

-0.3 2.0

Input voltage on true open

drain pin (P0.10)

VSS-0.3

+5.5

Input voltage on any other

VSS-0.3 V33+0.3

|∆V

33x

Variations between different

3.3V power pins

50 50

|∆V

18x

Variations between different

1.8V power pins

25 25

SSX

- VSS|

Variations between all the different ground pins

50 50

ESD(HBM)

Electro-static discharge voltage (Human Body Model)

see : Absolute Maximum Ratings

(Electrical Sensitivity) on page 47

ESD(MM)

Electro-static discharge voltage (Machine Model)

Page 34

Electrical parameters STR71xF

34/74

Notes:

1. I

INJ(PIN)

must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum

cannot be respected, the injection current must be limited externally to the I

INJ(PIN)

value. A positive injection is induced by VIN>V33 while a negative injection is induced by VIN<VSS. For true open-drain pads, there is no positive injection current, and the corresponding VIN maximum must always be respected

2. All 3.3V power (V

, AVDD, V

33IO-PLL

) and ground (VSS, AVSS, V

SSIO-PLL

) pins must always be connected

to the external 3.3V supply.

3. Negative injection disturbs the analog performance of the device. See note in Section 2.3.9: ADC

characteristics on page 62.

4. When several inputs are submitted to a current injection, the maximum

INJ(PIN)

is the absolute sum of the positive and negative injected currents (instantaneous values). These results are based on characterization with

INJ(PIN)

maximum current injection on four I/O port pins of the device.

5. Only when using external 1.8V power supply. All the power (V

, V

18BKP

) and ground (V

SS18

, V

SSBKP

) pins

must always be connected to the external 1.8V supply.

Table 10. Current characteristics

Symbol Ratings Max. Unit

V33

Total current into V33/V

33IO-PLL

power lines (source)

150

VSS

Total current out of VSS/V

SSIO-PLL

ground lines (sink)

150

Output current sunk by any I/O and control pin 25

Output current source by any I/Os and control pin - 25

INJ(PIN)

1) & 3)

Injected current on RSTIN pin ± 5

Injected current on CK pin ± 5

Injected current on any other pin

± 5

ΣI

INJ(PIN)

Total injected current (sum of all I/O and control pins)

± 25

Table 11. Thermal characteristics

Symbol Ratings Value Unit

STG

Storage temperature range -65 to +150 °C

Maximum junction temperature (see Section 3.2: Thermal characteristics on

page 69)

Page 35

STR71xF Electrical parameters

35/74

2.3 Operating conditions

Subject to general operating conditions for V33, and TA.

1. Data guaranteed by characterization, not tested in production

Table 12. General Operating Conditions

Symbol Parameter Conditions Min Max Unit

MCLK

Internal CPU Clock frequency

Accessing SRAM or external memory with 0 wait states

0 66

MHz

Accessing FLASH in burst mode

050

Executing from FLASH with RWW

Accessing FLASH with 0 wait states

033

PCLK

Internal APB Clock frequency

0 33 MHz

Standard Operating Voltage (includes V

33I0_PLL)

3.0 3.6 V

18BKP

Backup Operating Voltage 1.4 1.8 V

Ambient temperature range 6 Partnumber Suffix -40 85 °C

Table 13. Operating Conditions at power-up / power-down

Symbol Parameter Conditions Min

Typ

Max Unit

V33

V33 rise time rate

Subject to general operating conditions for T

20 µs/V

20 ms/V

Page 36

Electrical parameters STR71xF

36/74

2.3.1 Supply current characteristics

The current consumption is measured as described in Figure 9 on page 32 and Figure 10

on page 32.

Total current consumption

The MCU is placed under the following conditions:

● All I/O pins in input mode with a static value at V

or VSS (no load)

● All peripherals are disabled except if explicitly mentioned.

● Embedded Regulators are used to provide 1.8V (except if explicitly

mentioned)

Subject to general operating conditions for V

, and TA.

Notes:

1. Typical data are based on T

=25°C, V33=3.3V.

2. Data based on characterization results, tested in production at V

, f

MCLK

max. and TA max.

3. Based on device characterisation, device power consumption in STOP mode at T

25°C is predicted to be

30µA or less in 99.730020% of parts.

4. The conditions for these consumption measurements are described in application note AN2100.

Table 14. Total Current consumption

Symbol Parameter Conditions

Typ

Max

Unit

Supply current in RUN mode

MCLK

=66 MHz, RAM execution

73.6 100

MCLK

=32 MHz, Flash non-burst

execution

49.3

Supply current in STOP mode

=25°C

µA

Supply current in STANDBY mode

OSC32K bypassed 12 30 µA

Page 37

STR71xF Electrical parameters

37/74

Table 15. Typical power consumption data

Symbol Parameter Conditions

Typica l current

on V33

Unit

DDRUN

RUN mode

current from

RAM

All periphs ON

MCLK = 16 MHz, PCLK = FCLK = 16 MHz 23

MCLK = 32 MHz, PCLK = FCLK = 32 MHz 40

MCLK = 48 MHz, PCLK = FCLK = 24 MHz 50

MCLK = 64 MHz, PCLK = FCLK = 32 MHz 63

All periphs OFF

MCLK = 16 MHz 16

MCLK = 32 MHz 26

MCLK = 48 MHz 39

MCLK = 64 MHz 48

RUN mode

current from

FLASH

All periphs ON

MCLK = 16 MHz, PCLK = FCLK = 16 MHz 27

MCLK = 32 MHz, PCLK = FCLK = 32 MHz 47

MCLK = 48 MHz, PCLK = FCLK = 24 MHz 62

All periphs OFF

MCLK = 16 MHz 21

MCLK = 32 MHz 36

MCLK = 48 MHz 53

DDSLOW

SLOW mode current MCLK = CK_AF (32 kHz), MVR off 1.7

DDWAIT

WAIT mode current

(all periphs ON)

PCLK = FCLK = 1 MHz 13

DDLPWAIT

LPWAIT mode current

CK_AF (32 kHz), Main VReg off, FLASH in power-down

µA

DDSTOP

STOP mode current

Main VReg off, FLASH in power down, RTC on

Main VReg off, FLASH in power down, RTC off

DDSB

STANDBY mode current

LP VReg on, LVD on, RTC on 10

LP VReg off (ext 1.8V on V18BKP), LVD on, RTC on

LP VReg off (ext1.8V on V18BKP), LVD off, RTC on

LP VReg off (ext 1.8V on V18BKP), LVD off, RTC off

Page 38

Electrical parameters STR71xF

38/74

Figure 11. STOP IDD vs. V

Figure 12. STANDBY IDD vs. V

Figure 13. WFI IDD vs. V

100

3 3.1 3.2 3.3 3.4 3.5 3.6

V33 (V)

IDDSTOP (µA)

TA=-45 t o +25°C

TA=+90°C

3 3.1 3.2 3.3 3.4 3.5 3.6

V33 (V)

IDDSTDBY (µA)

TA= -45°C TA=0°C TA= +25°C TA= +90°C

100

3 3.1 3.2 3.3 3.4 3.5 3.6

V33 (V)

IDDWFI (µA )

TA= -40 to +9 0°C

Page 39

STR71xF Electrical parameters

39/74

On-Chip Peripherals

Notes:

1. Data based on a differential I

measurement between reset configuration and timer counter running at

16MHz. No IC/OC programmed (no I/O pads toggling).

2. Data based on a differential I

measurement between the on-chip peripheral when kept under reset and

not clocked and the on-chip peripheral when clocked and not kept under reset. No I/O pads toggling.

3. Data based on a differential I

measurement between reset configuration and continuous A/D

conversions.

Table 16. Peripheral current consumption

Symbol Parameter Conditions Typ Unit

DD(PLL1)

PLL1 supply current

TA= 25°C

3.42

DD(PLL2)

PLL2 supply current 5.81

DD(TIM)

TIM Timer supply current

TA= 25°C, f

PCLK

=33 MHz

0.88

DD(BSPI)

BSPI supply current

1.1

DD(UART)

UART supply current

1.05

DD(I2C)

I2C supply current

0.45

DD(ADC)

ADC supply current when converting

1.89

DD(HDLC)

HDLC supply current

1.82

DD(USB)

USB supply current

2.08

DD(CAN)

CAN supply current

1.11

Page 40

Electrical parameters STR71xF

40/74

2.3.2 Clock and timing characteristics

External Clock Sources

Subject to general operating conditions for V33, and TA.

Notes:

1. Data based on design simulation and/or technology characteristics, not tested in production.

Figure 14. CK External Clock Source

Table 17. CK External Clock Characteristics

Symbol Parameter Conditions Min Typ Max Unit

External clock source frequency

0 16.5 MHz

CKH

CK input pin high level voltage

0.7xV

CKL

CK input pin low level voltage

0.3xV

w(CK)

CK high or low time

r(CK)

f(CK)

CK rise or fall time

CK Input leakage current

SS≤VIN≤V33

±1 µA

CLK

EXTERNAL

STR710

CLOCK SOURCE

CKL

CKH

r(CK)

f(CK)

w(CKH)

w(CKL)

90%

10%

Page 41

STR71xF Electrical parameters

41/74

Notes:

1. Data based on design simulation and/or technology characteristics, not tested in production.

Table 18. RTCXT1 External Clock Characteristics

Symbol Parameter Conditions Min Typ Max Unit

RTCXT1

External clock source frequency

0 500 kHz

RTCXT1H

RTCXT1 input pin high level voltage

0.7xV

RTCXT1L

RTCXT1 input pin low level voltage

0.3xV

w(RTCXT1)

RTCXT1 high or low time

100

r(RTCXT1)

f(RTCXT1)

RTCXT1 rise or fall time

RTCXT1 Input leakage current

VSS≤VIN≤V

±1 µA

Page 42

Electrical parameters STR71xF

42/74

OSC32K Crystal / Ceramic Resonator Oscillator

The STR7 RTC clock can be supplied with a 32kHz Crystal/Ceramic resonator oscillators. All the information given in this paragraph are based on characterization results with specified typical external components. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and start-up stabilization time. Refer to the crystal resonator manufacturer for more details (frequency, package, accuracy...).

Notes:

1. The oscillator selection can be optimized in terms of supply current using an high quality resonator with small R

value for example MSIV-TIN32.768kHz. Refer to crystal manufacturer for more details

2. t

SU(OSC32KHZ)

is the start-up time measured from the moment it is enabled (by software) to a stabilized 32kHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer

Figure 15. Typical Application with a 32kHz Crystal

Table 19. 32K Oscillator characteristics (f

OSC32K=

32.768kHz)

Symbol Parameter Conditions Typ Unit

Feedback resistor 2.7 MΩ

Recommended load capacitance versus equivalent serial resistance

of the crystal (R

)

RS=40KΩ

12.5 pF

RTCXT2 driving current

=3.3V

VIN=V

3.2 µA

Oscillator Transconductance 8 µA/V

SU(OSC32KHZ)

startup time

is stabilized

RTCXT2

RTCXT1

OSC32K

STR710

32KHz

WHEN RESONATOR WITH INTEGRATED CAPACITORS

RESONATOR

FEEDBACK

LOOP

Page 43

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Figure 16. RTC Crystal Oscillator and Resonator

PLL Electrical Characteristics

V33 = 3.0 to 3.6V, V

33IOPLL

= 3.0 to 3.6V, TA = -40 / 85 °C unless otherwise specified.

RTCXTI

RTCXTO

RTCXTI

RTCXTO

DEVICE

Table 20. PLL1 Characteristics

Symbol Parameter Test Conditions

Val ue

Unit

Min Typ Max

PLLCLK1

PLL multiplier output clock

PLL1

x 24

165 MHz

PLL1

PLL input clock

FREF_RANGE = 0 1.5 3.0 MHz

FREF_RANGE = 1

MX[1:0]=’00’ or ‘01’

3.0 8.25 MHz

FREF_RANGE = 1

MX[1:0]=’10’ or ‘11’

3.0 6 MHz

PLL input clock duty cycle 25 75 %

FREE1

PLL free running frequency

FREF_RANGE = 0

MX[1:0]=’01’ or ‘11’

125 kHz

FREF_RANGE = 0

MX[1:0]=’00’ or ‘10’

250 kHz

FREF_RANGE = 1

MX[1:0]=’01’ or ‘11’

250 kHz

FREF_RANGE = 1

MX[1:0]=’00’ or ‘10’

500 kHz

LOCK1

PLL lock time

FREF_RANGE = 0

Stable Input Clock

Stable V

33IOPLL

, V

300 µs

FREF_RANGE = 1

Stable Input Clock

Stable V

33IOPLL

, V

600 µs

∆t

JITTER1

PLL jitter (peak to peak)

PLL

= 4 MHz, MX[1:0]=’11’ Global Output division = 32 (Output Clock = 2 MHz)

0.7 2 ns

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Table 21. PLL2 Characteristics

Symbol Parameter Test Conditions

Val ue

Unit

Min Typ Max

PLLCLK2

PLL multiplier output clock

PLL

x 28 140 MHz

PLL2

PLL input clock

FREF_RANGE = 0 1.5 3.0 MHz

FREF_RANGE = 1 3.0 5 MHz

LOCK2

PLL lock time

FREF_RANGE = 0 Stable Input Clock Stable V

33IOPLL

, V

300 µs

FREF_RANGE = 1 Stable Input Clock Stable V

33IOPLL

, V

600 µs

∆t

JITTER2

PLL jitter (peak to peak)

PLL

= 4 MHz, MX[1:0]=’11’ Global Output division = 32 (Output Clock = 2 MHz)

0.7 2 ns

Table 22. Low-power Mode Wake-up Timing

Symbol Parameter Typ Unit

WULPWFI

Wake-up from LPWFI mode 26 µs

WUSTOP

Wake-up from STOP mode 131 µs

WUSTBY

Wake-up from STANDBY mode 2 µs

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2.3.3 Memory characteristics

Flash Memory

V33 = 3.0 to 3.6V, TA = -40 to 85 °C unless otherwise specified.

Notes:

1. T

=45°C after 0 cycles. Guaranteed by characterization, not tested in production.

2. Guaranteed by design, not tested in production

2.3.4 EMC characteristics

Susceptibility tests are performed on a sample basis during product characterization.

Table 23. Flash memory characteristics

Symbol Parameter Test Conditions

Val ue

Unit

Min. Typ

Max

Word Program 40 µs

PDW

Double Word Program 60 µs

PB0

Bank 0 Program (256K) Double Word Program 1.6 2.1 s

PB1

Bank 1 Program (16K) Double Word Program 130 170 ms

Sector Erase (64K)

Not preprogrammed Preprogrammed

2.3

1.9

4.0

3.3

Sector Erase (8K)

Not preprogrammed Preprogrammed

0.7

0.6

1.1

1.0

Bank 0 Erase (256K)

Not preprogrammed Preprogrammed

8.0

6.6

13.7

11.2

Bank 1 Erase (16K)

Not preprogrammed Preprogrammed

0.9

0.8

1.5

1.3

RPD

Recovery when disabled 20 µs

PSL

Program Suspend Latency 10 µs

ESL

Erase Suspend Latency 300 µs

END_B0

Endurance (Bank 0 sectors)

10 kcycles

END_B1

Endurance (Bank 1 sectors)

100 kcycles

RET

Data Retention (Bank 0 and Bank 1)

=85° 20 Years

ESR

Erase Suspend Rate

Min time from Erase Resume to next Erase Suspend

20 ms

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Electrical parameters STR71xF

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Functional EMS (Electro Magnetic Susceptibility)

Based on a simple running application on the product (toggling 2 LEDs through I/O ports), the product is stressed by two electro magnetic events until a failure occurs (indicated by the LEDs).

● ESD: Electro-Static Discharge (positive and negative) is applied on all pins of the

device until a functional disturbance occurs. This test conforms with the IEC 1000-4-2 standard.

● FTB: A Burst of Fast Transient voltage (positive and negative) is applied to V

and

through a 100pF capacitor, until a functional disturbance occurs. This test

conforms with the IEC 1000-4-4 standard.

A device reset allows normal operations to be resumed. The test results are given in the table below based on the EMS levels and classes defined in application note AN1709.

Designing hardened software to avoid noise problems

EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular.

Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application.

Software recommendations:

The software flowchart must include the management of runaway conditions such as:

● Corrupted program counter

● Unexpected reset

● Critical Data corruption (control registers...)

Prequalification trials:

Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the RESET pin or the Oscillator pins for 1 second.

To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015).

In the case of an ARM7 CPU, in order to write robust code that can withstand all kinds of stress, such as very strong electromagnetic disturbance, it is mandatory that the Data Abort, Prefetch Abort and Undefined Instruction exceptions are managed by the application software. This will prevent the code going into an undefined state or performing any unexpected operation.

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Electro Magnetic Interference (EMI)

Based on a simple application running on the product (toggling 2 LEDs through the I/O ports), the product is monitored in terms of emission. This emission test is in line with the norm SAE J 1752/3 which specifies the board and the loading of each pin.

Notes:

1. Not tested in production.

2. BGA and LQFP devices have similar EMI characteristics.

Absolute Maximum Ratings (Electrical Sensitivity)

Based on three different tests (ESD, LU and DLU) using specific measurement methods, the product is stressed in order to determine its performance in terms of electrical sensitivity. For more details, refer to the application note AN1181.

Electro-Static Discharge (ESD)

Electro-Static Discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts*(n+1) supply pin). Two models can be simulated: Human Body Model and Machine Model. This test conforms to the JESD22-A114A/A115A standard.

Table 24. EMS data

Symbol Parameter Conditions

Level/ Class

FESD

Voltage limits to be applied on any I/O pin to induce a functional disturbance

=3.3V, TA=+25°C, f

MCLK

=32MHz

conforms to IEC 1000-4-2

EFTB

Fast transient voltage burst limits to be applied through 100pF on V

and V

pins

to induce a functional disturbance

=3.3V, TA=+25°C, f

MCLK

=32MHz

conforms to IEC 1000-4-4

Table 25. EMI data

Symbol Parameter Conditions

Monitored

Frequency Band

Max vs.

OSC4M/fHCLK

]

Unit

16/

48MHz

16/8MHz

EMI

Peak l evel

=3.3V, TA=+25°C,

LQFP64 package conforming to SAE J 1752/3

0.1MHz to 30 MHz 17 19

dBµV30 MHz to 130 MHz 17 16

130 MHz to 1GHz 11 11

SAE EMI Level 4 3 -

Page 48

Electrical parameters STR71xF

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Notes:

1. Data based on characterization results, not tested in production.

Static and Dynamic Latch-Up

● LU: 3 complementary static tests are required on 10 parts to assess the latch-up

performance. A supply overvoltage (applied to each power supply pin) and a current injection (applied to each input, output and configurable I/O pin) are performed on each sample. This test conforms to the EIA/JESD 78 IC latch-up standard. For more details, refer to the application note AN1181.

● DLU: Electro-Static Discharges (one positive then one negative test) are applied to

each pin of 3 samples when the micro is running to assess the latch-up performance in dynamic mode. Power supplies are set to the typical values, the oscillator is connected as near as possible to the pins of the micro and the component is put in reset mode. This test conforms to the IEC1000-4-2 and SAEJ1752/3 standards. For more details, refer to the application note AN1181.

Electrical Sensitivities

Notes:

1. Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the JEDEC specifications, that means when a device belongs to Class A it exceeds the JEDEC standard. B Class strictly covers all the JEDEC criteria (international standard).

Table 26. ESD Absolute Maximum ratings

Symbol Ratings Conditions

Maximum

value

Unit

ESD(HBM)

Electro-static discharge voltage (Human Body Model)

TA=+25°C

2000

ESD(MM)

Electro-static discharge voltage (Machine Model)

200

ESD(CDM)

Electro-static discharge voltage (Charge Device Model)

750 on corner

pins, 500 on

others

Symbol Parameter Conditions

Class

LU Static latch-up class

TA=+25°C TA=+85°C T

=+105°C

A A A

DLU Dynamic latch-up class

=3.3V, f

OSC4M

=4MHz, f

MCLK

=32MHz,

TA=+25°C

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2.3.5 I/O port pin characteristics

General Characteristics

Subject to general operating conditions for V33 and TA unless otherwise specified. All unused pins must be kept at a fixed voltage: using the output mode of the I/O for example or an external pull-up or pull-down resistor.

Notes:

1. Data based on characterization results, not tested in production.

2. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested.

3. When the current limitation is not possible, the V

absolute maximum rating must be respected, otherwise

refer to I

INJ(PIN)

specification. A positive injection is induced by VIN>V33 while a negative injection is

induced by VIN<VSS. Refer to Section 2.2 on page 33 for more details.

4. Leakage could be higher than max. if negative current is injected on adjacent pins.

5. The R

pull-up and RPD pull-down equivalent resistor are based on a resistive transistor (corresponding

and IPD current characteristics described in Figure 18 to Figure 19).

Table 27. I/O static characteristics

Symbol Parameter Conditions Min

Typ

Max Unit

Input low level voltage

CMOS ports

0.3V

Input high level voltage

0.7V

hys

Schmitt trigger voltage hysteresis

0.8 V

Input low level voltage

P0.15 WAKEUP

0.9 0.8 V

Input high level voltage

21.35

hys

Schmitt trigger voltage hysteresis

0.4 V

Input low level voltage

TTL ports

0.8 V

Input high level voltage

2.0

INJ(PIN)

Injected Current on any I/O pin ± 4

ΣI

INJ(PIN)

Total injected current (sum of all

I/O and control pins)

± 25

lkg

Input leakage current

SS≤VIN≤V33

±1 µA

Weak pull-up equivalent

resistor

IN=VSS

110 150 700 kΩ

Weak pull-down equivalent

resistor

IN=V33

110 150 700 kΩ

I/O pin capacitance 5 pF

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Electrical parameters STR71xF

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Figure 17. RPU vs. V33 with VIN=V

Figure 18. IPU vs. V33 with VIN=V

-250.0

-200.0

-150.0

-100.0

-50.0

0.0

3 3.1 3.2 3.3 3.4 3.5 3.6

V33 (V)

RPU (kohm)

TA= -45°C TA=0°C TA=+25°C TA=+90°C

-30

-25

-20

-15

-10

-5

3 3.1 3.2 3.3 3.4 3.5 3.6

V33 (V)

IPU (µA)

TA=-45°C TA=0°C TA=+25°C TA=+90°C

Figure 19. RPD vs. V33 with VIN=V

Figure 20. IPD vs. V33 with VIN=V

0.0

50.0

100.0

150.0

200.0

250.0

300.0

3 3.1 3.2 3.3 3.4 3.5 3.6

V33 (V)

RPD (kohm)

TA=-45°C TA=0°C TA=+25°C TA=+90°C

3 3.1 3.2 3.3 3.4 3.5 3.6

V33 (V)

IPD (µA)

TA= -45°C TA=0°C TA=+25°C TA=+90°C

Page 51

STR71xF Electrical parameters

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Output Driving Current

Subject to general operating conditions for V

and TA unless otherwise specified.

Notes:

1. The I

current sunk must always respect the absolute maximum rating specified in Table 10 and the sum

of I

(I/O ports and control pins) must not exceed I

VSS

2. The I

current sourced must always respect the absolute maximum rating specified in Table 10 and the

sum of IIO (I/O ports and control pins) must not exceed I

V33

Table 28. Output driving current

I/O

Type

Symbol Parameter Conditions Min Max Unit

Standard

Output low level voltage for an I/O pin when 8 pins are sunk at same time (see Figure 21)

=+4mA

0.4

Output high level voltage for an I/O pin when 4 pins are sourced at same time (see Figure 21 and Figure 23)

=-4mA V33-0.8

High Current

Output low level voltage for an I/O pin when 8 pins are sunk at same time (see Figure 21)

=+8mA

0.4

Output high level voltage for an I/O pin when 4 pins are sourced at same time (see Figure 21 and Figure 23)

=-8mA V33-0.8

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Electrical parameters STR71xF

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Figure 21. Typical VOL and V

at V33=3.3V (High current ports)

3.01

3.02

3.03

3.04

3.05

3.06

3.07

3.08

3.09

-4 -8

Iio(mA)

VOH(V)

TA=-45°C TA=0°C TA=+25°C TA=+90°C

0.00

0.02

0.04

0.06

0.08

0.10

0.12

0.14

0.16

-4 -8

Iol (mA)

VOL(V)

TA=-45°C TA=0°C TA=+25°C TA=+90°C

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Figure 22. Typical VOL vs. V33

Figure 23. Typical V

vs. V

0.00

0.02

0.04

0.06

0.08

0.10

0.12

0.14

0.16

3 3.1 3.2 3.3 3.4 3.5 3.6

V33 (V)

VOL (V) I io=4m A

TA=-45°C TA=0°C TA=+25°C TA=+90°C

0.00

0.02

0.04

0.06

0.08

0.10

0.12

0.14

0.16

0.18

3 3.1 3.2 3.3 3.4 3.5 3.6

V33 (V)

VOL(V) I io=8m A

TA=-45°C TA=0°C TA=+25°C TA=+90°C

2.00

2.20

2.40

2.60

2.80

3.00

3.20

3.40

3.60

3 3.1 3.2 3.3 3.4 3.5 3.6

V33 (V)

VOH (V) Iio= 4mA

TA=-45°C TA=0°C TA=+25°C TA=+90°C

2.00

2.20

2.40

2.60

2.80

3.00

3.20

3.40

3.60

3 3.1 3.2 3.3 3.4 3.5 3.6

V33 (V)

VOH(V) Iio=8mA

TA=-45°C TA=0°C TA=+25°C TA=+90°C

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Electrical parameters STR71xF

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RSTIN Pin

The RSTIN pin input driver is CMOS. A permanent pull-up is present which is the same as as R

(seeTable 27 on page 49)

Subject to general operating conditions for V

and TA unless otherwise specified.

Notes:

1. Data based on characterization results, not tested in production.

2) Data guaranteed by design, not tested in production.

Figure 24. Recommended RSTIN pin protection.

Notes:

1. The R

pull-up equivalent resistor is based on a resistive transistor (corresponding I

current

characteristics described in Figure 18).

2. The reset network protects the device against parasitic resets.

3. The user must ensure that the level on the RSTIN

pin can go below the V

IL(RSTINn)

max. level specified in

Table 29. Otherwise the reset will not be taken into account internally.

2.3.6 TIM timer characteristics

Subject to general operating conditions for V33, f

MCLK

, and TA unless otherwise

specified.

Refer to Section 2.3.5: I/O port pin characteristics on page 49 for more details on the input/output alternate function characteristics (output compare, input capture, external clock, PWM output...).

Table 29. RESET pin characteristics

Symbol Parameter Conditions Min

Typ

Max Unit

IL(RSTINn)

RSTIN Input low level voltage

0.8 V

IH(RSTINn)

RSTIN Input high level voltage

F(RSTINn)

RSTIN Input filtered pulse

500 ns

NF(RSTINn)

RSTIN Input not filtered pulse

1.2 µs

0.01µF

EXTERNAL

RESET

CIRCUIT

4.7kΩ

Required

Recommended

STR7X

Filter

INTERNAL RESET

RSTIN

Table 30. TIM characteristics

Symbol Parameter Conditions Min Typ Max Unit

w(ICAP)in

Input capture pulse time 2

CK_TIM

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2.3.7 EMI - Memory Interface

Subject to general operating conditions for VDD, f

HCLK

, and TA unless otherwise specified.

The tables below use a variable which is derived from the EMI_BCONn registers (described in the STR71x Reference Manual) and represents the special characteristics of the programmed memory cycle.

res(TIM)

Timer resolution time

PCLK2

= 30MHz

33.3

EXT

Timer external clock frequency

CK_TIM(MAX)

MCLK

CK_TIM

MHz

CK_TIM

= f

MCLK

60MHz

015MHz

Res

TIM

Timer resolution 16 bit

COUNTER

16-bit Counter clock period when internal clock is selected

1 65536

PCLK

PCLK2

= 30MHz

0.033 2184 µs

MAX_COUNT

Maximum Possible Count

65536x

65536

PCLK

PCLK2

= 30MHz

143.1 s

Table 30. TIM characteristics

Symbol Parameter Conditions Min Typ Max Unit

Table 31. EMI general characteristics

Symbol Parameter Value

MCLK

CPU clock period 1 / f

MCLK

Memory cycle time wait states t

MCLK

x (1 + [C_LENGTH])

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Electrical parameters STR71xF

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See Figure 25, Figure 26, Figure 27 and Figure 28 for related timing diagrams.

1. Data based on characterisation results, not tested in production.

See Figure 29, Figure 30, Figure 31 and Figure 32 for related timing diagrams.

1. Data based on characterisation results, not tested in production.

Table 32. EMI Read Operation

Symbol Parameter Test Conditions

Val ue

Unit

Min

Typ

Max

RCR

Read to CSn Removal Time

MCLK=50 MHz

4 wait states

50 pf load on all pins

19 t

MCLK

Read Pulse Time 98

100 ns

RDS

Read Data Setup Time 22 ns

RDH

Read Data Hold Time 0 ns

RAS

Read Address Setup Time 27

1.5*t

CLK

33 ns

RAH

Read Address Hold Time 0.65 2 ns

RAT

Read Address Turnaround

Time

1.9 3.25 ns

RRT

RDn Turnaround Time 20

MCLK

21 ns

Table 33. EMI Write Operation

Symbol Parameter Test Conditions

Value

Unit

Min

Typ

Max

WCR

WEn to CSn Removal Time

MCLK=50 MHz

3 wait states

50 pf load on all pins

MCLK

22.5 ns

Write Pulse Time 77.5

80 ns

WDS1

Write Data Setup Time 1 97

MCLK

100 ns

WDS2

Write Data Setup Time 2 77

80 ns

WDH

Write Data Hold Time 20

MCLK

23 ns

WAS

Write Address Setup Time 27

1.5*t

MCLK

33 ns

WAH

Write Address Hold Time 0.6 3 ns

WAT

Write Address Turnaround

Time

1.75 4.1 ns

WWT

WEn Turnaround Time 20

MCLK

23 ns

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Figure 25. Read Cycle Timing: 16-bit READ on 16-bit Memory

Figure 26. Read Cycle Timing: 32-bit READ on 16-bit Memory

See Ta bl e 32 for read timing data.

Figure 27. Read Cycle Timing: 16-bit READ on 8-bit Memory

CSn.x

WEn.x

A[23:0]

D[15:0]

RDn

(Input)

Address

Data Input

RDStRDH

RCR

RAS

RAH

CSn.x

WEn.x

A[23:0]

D[15:0]

RDn

(Input)

Address

Data Input

RDStRDH

RCR

RAS

RAH

Data Input

RDStRDH

RRT

RAH

Address

RAT

CSn.x

WEn.x

A[23:0]

D[7:0]

RDn

(Input)

Address

Data Input

RDStRDH

RCR

RAS

RAH

Data Input

RDStRDH

RRT

RAH

Address

RAT

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Electrical parameters STR71xF

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Figure 28. Read Cycle Timing: 32-bit READ on 8-bit Memory

See Ta bl e 32 for read timing data.

Figure 29. Write Cycle Timing: 16-bit WRITE on 16-bit Memory

Figure 30. Write Cycle Timing: 32-bit WRITE on 16-bit Memory

See Ta b le 41 for write timing data.

CSn.x

WEn.x

A[23:0]

D[7:0]

RDn

(Input)

Address

Data Input

RDStRDH

RCR

RAS

RAH

Data Input

RDStRDH

RRT

RAH

Address

RAT

RRT

RAH

Address

RAT

Data Input

RDStRDH

RRT

RAH

Address

RAT

Data Input

RDStRDH

CSn.x

WEn.x

A[23:0]

D[15:0]

RDn

(Output)

Address

Data Output

WDH

WCR

WAS

WDS1

WAH

CSn.x

WEn.x

A[23:0]

D[15:0]

RDn

(Output)

address

Data Output

WDS1tWDH

WCR

WAS

WAH

Data Output

WDS2tWDH

WWT

WAH

address

WAT

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Figure 31. Write Cycle Timing: 16-bit WRITE on 8-bit Memory

Figure 32. Write Cycle Timing: 32-bit WRITE on 8-bit Memory

See Ta bl e 33 for write timing data.

CSn.x

WEn.x

A[23:0]

D[7:0]

RDn

(Output)

address

Data Output

WDS1tWDH

WCR

WAS

WAH

Data Output

WDS2tWDH

WWT

WAH

address

WAT

CSn.x

WEn.x

A[23:0]

D[7:0]

RDn

(Output)

address

Data Output

WDS1tWDH

WCR

WAS

WAH

Data Output

WDS2tWDH

WWT

WAH

address

WAT

WWT

WAH

address

WAT

Data Output

WDS2tWDH

WWT

WAH

address

WAT

Data Output

WDS2tWDH

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2.3.8 Communications interfaces

I2C - Inter IC Control Interface

Subject to general operating conditions for V33,

PCLK1

, and TA unless otherwise specified.

The STR7 I

C interface meets the requirements of the Standard I2C communication

protocol described in the following table with the restriction mentioned below:

Note:

Restriction: The I/O pins which SDA and SCL are mapped to are not “True” Open-Drain: when configured as open-drain, the PMOS connected between the I/O pin and V

disabled, but it is still present. Also, there is a protection diode between

the I/O pin and V

Consequently, when using this I

C in a multi-master network, it is not possible to power off

the STR7X while some another I

C master node remains powered on: otherwise, the

STR7X will be powered by the protection diode.

Refer to I/O port characteristics for more details on the input/output alternate function characteristics (SDA and SCL).

Notes:

1. Data based on standard I

C protocol requirement, not tested in production.

2. The device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the undefined region of the falling edge of SCL.

3. The maximum hold time of the START condition has only to be met if the interface does not stretch the low

Table 34. I2C Characteristics

Symbol Parameter

Standard mode

Fast mode I

2C5)

Unit

Min

Max

Min

Max

w(SCLL)

SCL clock low time 4.7 1.3

µs

w(SCLH)

SCL clock high time 4.0 0.6

su(SDA)

SDA setup time 250 100

h(SDA)

SDA data hold time

900

r(SDA)

r(SCL)

SDA and SCL rise time 1000

20+0.1C

300

f(SDA)

f(SCL)

SDA and SCL fall time 300

20+0.1C

300

h(STA)

START condition hold time 4.0 0.6

µs

su(STA)

Repeated START condition setup time

4.7 0.6

su(STO)

STOP condition setup time 4.0 0.6 µs

w(STO:STA)

STOP to START condition time (bus free)

4.7 1.3 µs

Capacitive load for each bus line 400 400 pF

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period of SCL signal.

4. Measurement points are done at CMOS levels: 0.3xV

and 0.7xVDD.

5. f

PCLK1

, must be at least 8MHz to achieve max fast I2C speed (400kHz).

6. The following table gives the values to be written in the I2CCCR register to obtain the required I

C SCL line

frequency.

Figure 33.

Typical Application with I

C Bus and Timing Diagram

Legend:

= External pull-up resistance

SCL

= I2C speed

NA = Not achievable

Note: For speeds around 200 kHz, achieved speed can have ±5% tolerance

For other speed ranges, achieved speed can have

2% tolerance

The above variations depend on the accuracy of the external components used.

USB Characteristics

The USB interface is USB-IF certified (Low Speed and Full Speed).

Table 35. SCL Frequency Table (

PCLK1

=8 MHz.,V33 = 3.3 V)

SCL

(kHz)

I2CCCR Value

=4.7kΩ

400 83

300 85h

200 8Ah

100 24h

50 4Ch

20 C4h

REPEATED START

START

STOP

START

f(SDA)

r(SDA)

su(SDA)th(SDA)

f(SCK)

r(SCK)

w(SCKL)

w(SCKH)

h(STA)

su(STO)

su(STA)tw(STO:STA)

SDA

SCL

4.7kΩ SDA

STR7

SCL

100Ω

4.7kΩ

I2CBUS

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Electrical parameters STR71xF

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2.3.9 ADC characteristics

Subject to general operating conditions for AVDD, f

PCLK2

, and TA unless otherwise specified.

Notes:

1. Unless otherwise specified, typical data are based on T

=25°C and AVDD-AVSS=3.3V. They are given only

as design guidelines and are not tested.

2. Any added external serial resistor will downgrade the ADC accuracy (especially for resistance greater than 10k

Ω

). Data based on characterization results, not tested in production.

3. Calibration is needed once after each power-up.

Table 36. ADC characteristics

Symbol Parameter Conditions Min

Typ

Max Unit

MOD

Modulator Oversampling frequency

2.1 MHz

AIN

Conversion voltage range

2)3)

02.5V

lkg

Negative input leakage current on analog pins

IN<VSS,

| I

400µA on adjacent analog pin

56µA

PBR Passband Ripple 0.1 dB

SINAD S/N and Distortion 56 63 dB

THD Total Harmonic Distortion 60 74 dB

Input Impedance f

MOD

= 2 MHz 1 MΩ

ADC

Internal sample and hold capacitor 3.2 pF

CONV

Total Conversion time (including sampling time)

4096/

MOD

(max)

ADC

Normal mode

= 27 °C

2.5 3.0 mA

Standby mode

= 27 °C

1 µA

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1. Data based on characterisation, not tested in production. ADC Accuracy vs. Negative Injection Current: Injecting negative current on any of the standard (nonrobust) analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to standard analog pins which may potentially inject negative current. The effect of negative injection current on robust pins is specified in Section 2.3.5. Any positive injection current within the limits specified for I

INJ(PIN)

and ΣI

INJ(PIN)

in Section 2.3.5 does not

affect the ADC accuracy.

Table 37. ADC Accuracy with f

PCLK2

= 20MHz, f

ADC

=10MHz, AVDD=3.3V

Symbol Parameter Conditions Min Typ Max Unit

ADC_DATA(0V)

Converted code when AIN=0V

2370 2565

Dec-

imal

code

ADC_DATA(2.5V)

Converted code when AIN=2.5V

1480 1680

VCM

Center voltage of Sigma-Delta

Modulator

1.23 1.25 1.30 V

TUE Total unadjusted error

In this type of ADC, calibration is necessary to correct gain error and offset errors. Once calibrated, the TUE is limited to the ILE.

Differential linearity error

1.96 2.19 LSB

Integral linearity error

2.36 3.95

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Electrical parameters STR71xF

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Figure 34. ADC Accuracy Characteristics

Analog Power Supply and Reference Pins

The AVDD and AV

pins are the analog power supply of the A/D converter cell. They act as

the high and low reference voltages for the conversion.

Separation of the digital and analog power pins allow board designers to improve A/D performance. Conversion accuracy can be impacted by voltage drops and noise in the event of heavily loaded or badly decoupled power supply lines (see: General PCB Design

Guidelines).

General PCB Design Guidelines

To obtain best results, some general design and layout rules should be followed when designing the application PCB to shield the noise-sensitive, analog physical interface from noise-generating CMOS logic signals.

● Use separate digital and analog planes. The analog ground plane should be connected

to the digital ground plane via a single point on the PCB.

● Filter power to the analog power planes. It is recommended to connect capacitors, with

good high frequency characteristics, between the power and ground lines,

placing

1LSB

IDEAL

1LSB

IDEAL

AVDD AVSS–

4095

------------------------------------------------=

AIN

(LSB

IDEAL

)

(1) Example of an actual transfer cur ve (2) The ideal transfer curve (3) End point correlation line

ED=Differential Linearity Error: maximum deviation between actual steps and the

ideal one.

EL=Integral Linearity Error: maximum deviation between any actual transition and

the end point correlation line.

Digital Result ADC_DATA Register

4095

4094

4093

123

4093 40944095

(1)

(2)

(3)

ADC_DATA(0V)

ADC_DATA(2.5V)

VCM

3100 31013102 3103

Out of range

1633

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STR71xF Electrical parameters

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0.1µF and optionally, if needed 10pF capacitors as close as possible to the STR7 power supply pins and a 1 to 10µF capacitor close to the power source (see Figure 35).

● The analog and digital power supplies should be connected in a star network. Do not

use a resistor, as AV

is used as a reference voltage by the A/D converter and any

resistance would cause a voltage drop and a loss of accuracy.

● Properly place components and route the signal traces on the PCB to shield the analog

inputs. Analog signals paths should run over the analog ground plane and be as short as possible. Isolate analog signals from digital signals that may switch while the analog inputs are being sampled by the A/D converter. Do not toggle digital outputs near the A/D input being converted.

Software Filtering of Spurious Conversion Results

For EMC performance reasons, it is recommended to filter A/D conversion outliers using software filtering techniques.

Figure 35. Power Supply Filtering

0.1µF

STR710

POWER SUPPLY SOURCE

STR7 DIGITAL NOISE FILTERING

EXTERNAL NOISE FILTERING

1 to 10µF

0.1µF

(3.3V)

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Package characteristics STR71xF

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3 Package characteristics

3.1 Package Mechanical Data

Figure 36. 64-Pin Low Profile Quad Flat Package (10x10)

Dim.

mm inches

Min Typ Max Min Typ Max

A 1.60 0.063

A1 0.05 0.15 0.002 0.006

A2 1.35 1.40 1.45 0.053 0.055 0.057

b 0.17 0.22 0.27 0.007 0.009 0.011

c 0.09 0.20 0.004 0.008

D 12.00 0.472

D1 10.00 0.394

E 12.00 0.472

E1 10.00 0.394

e 0.50 0.020

θ 0° 3.5° 7° 0° 3.5° 7°

L 0.45 0.60 0.75 0.018 0.024 0.030

L1 1.00 0.039

Number of Pins

N 64

Recommended footprint (dimensions in mm)

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Figure 37. 144-Pin Low profile Quad Flat Package

Dim.

mm inches

(1)

1.Values in inches are converted from mm and rounded to 3 decimal digits.

Min Typ Max Min Typ Max

A 1.60 0.063

A1 0.05 0.15 0.002 0.006

A2 1.35 1.40 1.45 0.053 0.057

b 0.17 0.22 0.27 0.007 0.011

c 0.09 0.20 0.004 0.008

D 21.80 22.00 22.20 0.858 0.867 0.874

D1 19.80 20.00 20.20 0.780 0.787 0.795

D3 17.50 0.689

E 21.80 22.00 22.20 0.858 0.867 0.874

E1 19.80 20.00 20.20 0.780 0.787 0.795

E3 17.50 0.689

e 0.50 0.020

K 0° 3.5° 7° 0° 3.5° 7°

L 0.45 0.60 0.75 0.018 0.024 0.030

L1 1.00 0.039

Number of Pins

N 144

Jedec Ref. MS-026-BFB

A A2

73108

109

144

Seating Plane

0.08 mm .003 in.

Recommended footprint (dimensions in mm)

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Package characteristics STR71xF

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Figure 38. 64-Low Profile Fine Pitch Ball Grid Array Package

Figure 39. 144-Low Profile Fine Pitch Ball Grid Array Package

Figure 40. Recommended PCB Design rules (0.80/0.75mm pitch BGA)

Dim.

mm inches

Min Typ Max Min Typ Max

A 1.210 1.700 0.048 0.067

A1 0.270 0.011

A2 1.120 0.044

b 0.450 0.500 0.550 0.018 0.020 0.022

D 7.750 8.000 8.150 0.305 0.315 0.321

D1 5.600 0.220

E 7.750 8.000 8.150 0.305 0.315 0.321

E1 5.600 0.220

e 0.720 0.800 0.880 0.028 0.031 0.035

f 1.050 1.200 1.350 0.041 0.047 0.053

ddd 0.120 0.005

Number of Pins

N 64

Dim.

mm inches

Min Typ Max Min Typ Max

A 1.21 1.70 0.048 0.067

A1 0.21 0.008

A2 1.085 0.043

b 0.35 0.40 0.45 0.014 0.016 0.018

D 9.85 10.00 10.15 0.388 0.394 0.400

D1 8.80 0.346

E 9.85 10.00 10.15 0.388 0.394 0.400

E1 8.80 0.346

e 0.80 0.031

F 0.60 0.024

ddd 0.10 0.004

eee 0.15 0.006

fff 0.08 0.003

Number of Pins

N 144

Dpad

Dsm

Dpad 0.37 mm

Dsm

0.52 mm typ. (depends on solder

mask registration tolerance Solder paste 0.37 mm aperture diameter – Non solder mask defined pads are recommended

– 4 to 6 mils screen print

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3.2 Thermal characteristics

The average chip-junction temperature, TJ, in degrees Celsius, may be calculated using the following equation:

= TA + (PD x ΘJA) (1)

Where:

● T

is the Ambient Temperature in °C,

● Θ

is the Package Junction-to-Ambient Thermal Resistance, in °C/W,

● P

is the sum of P

INT

and P

I/O (PD

= P

INT

+ P

I/O

● P

INT

is the product of I

and VDD, expressed in Watts. This is the Chip Internal Power.

I/O

represents the Power Dissipation on Input and Output Pins;

Most of the time for the application P

I/O< PINT

and can be neglected. On the other hand, P

I/O

may be significant if the device is configured to drive continuously external modules and/or memories.

An approximate relationship between P

and TJ (if P

I/O

is neglected) is given by:

= K / (TJ + 273°C) (2)

Therefore (solving equations 1 and 2):

K = P

x (TA + 273°C) + ΘJA x P

(3)

where:

K is a constant for the particular part, which may be determined from equation (3) by measuring P

(at equilibrium) for a known TA. Using this value of K, the values of PD and TJ

may be obtained by solving equations (1) and (2) iteratively for any value of T

Table 38. Thermal characteristics

Symbol Parameter Value Unit

Thermal Resistance Junction-Ambient LQFP 144 - 20 x 20 mm / 0.5 mm pitch

42 °C/W

Thermal Resistance Junction-Ambient LQFP 64 - 10 x 10 mm / 0.5 mm pitch

45 °C/W

Thermal Resistance Junction-Ambient LFBGA 64 - 8 x 8 x 1.7mm

58 °C/W

Thermal Resistance Junction-Ambient LFBGA 144 - 10 x 10 x 1.7mm

50 °C/W

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4 Product history

There are two versions of the STR710F series products. The two versions are functionally identical and differ only with the points listed below.

Version "A" was the first version produced and delivered. The second version, version "Z", is currently being phased into production and will replace version "A".

Version "Z" has lower power consumption in STOP mode.

Marking

The difference between the two versions is visible on the marking of the product, with the version letter on top of the part number. This version letter is visible in Figure 41 shows a TQFP144 "A" STR710 and a TQFP64 "Z" STR712

Figure 41. Version Marking

Table 39. A and Z version differences

Feature A version Z version

ARM7TDMI core device Identification (ID) code register (see ARM7TDMI Technical Reference Manual)

Version bits [31:28] = 0001 Version bits [31:28] = 0010

Low power mode consumption in STOP mode at 25 °C

Not guaranteed Typical 49 µA

50 µA maximum at 25°C. Less than 30 µA at 25 °C for

99.730020% of parts

STR710FZ2T6

2208JVG MLT225571

STR712FR2

2208JVG MLT225571

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STR71xF Order codes

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5 Order codes

Table 40. Order Codes

Partnumber

FLASH Kbytes

RAM

KbytesEMI USB CAN

I/O

Ports

Package

Tem p. Range

STR710FZ1T6 128+16 32

Yes Yes Yes 48 LQFP144 20 x 20

-40 to

+85°C

STR710FZ2T6 256+16 64

STR710RZT6 0 64

STR710FZ1H6 128+16 32

Ye s Ye s Ye s 4 8

LFBGA144 10 x 10

1.7

STR710FZ2H6 256+16 64

STR710RZH6 0 64

STR711FR0H6 64+16 16

Ye s N o 3 0

LFBGA64 8 x 8 1.7STR711FR1H6 128+16 32

STR711FR2H6 256+16 64

STR711FR0T6 64+16 16

LQFP64 10x10STR711FR1T6 128+16 32

STR711FR2T6 256+16 64

STR712FR0H6 64+16 16

Ye s

LFBGA64 8 x 8 1.7STR712FR1H6 128+16 32

STR712FR2H6 256+16 64

STR712FR0T6 64+16 16

LQFP64 10 x10STR712FR1T6 128+16 32

STR712FR2T6 256+16 64

STR715FR0H6 64+16 16

LFBGA64 8 x 8 1.7

STR715FR0T6 64+16 16 LQFP64 10 x 10

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Revision history STR71xF

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6 Revision history

Table 41. Document revision history

Date Revision Changes

17-Mar-2004 1 First Release

05-Apr-2004 2 Updated “Electrical parameters” on page 32

08-Apr-2004 2.1 Corrected STR712F Pinout. Pins 43/42 swapped.

15-Apr-2004 2.2 PDF hyperlinks corrected.

7-Jul-2004 3

Corrected description of STDBY, V18, VSS18 V18BKP VSSBKP pins

Added IDDrun typical data Updated BSPI max. baudrate. Updated “EMI - Memory Interface” on page 55

29-Oct-2004 4

Corrected Flash sector B1F0/F1 address in Figure 6: Memory

Map on page 29

Corrected Table 6 on page 23 LQFP64 TEST pin is 16 instead of 17. Added to TQPFP64 column: pin 7 BOOTEN, pin 17 V

33IO-PLL

Changed description of JTCK from ‘External pull-down required’ to ‘External pull-up or pull down required’.

25-Jan-2005 5

Changed “Product Preview” to “Preliminary Data” on page 1 and 3

Renamed ‘PU/PD’ column to ‘Reset state’ in Table 6 on

page 23

Added reference to STR7 Flash Programming Reference Manual

19-Apr-2005 6

Added STR715F devices and modified RAM size of STR71xF1 devices

Added BGA package in Section 3 Updated ordering information in Section 5. Added PLL duty cycle min and max. in PLL Electrical

Characteristics on page 43

13-Oct-2005 7

Updated feature description on page 1 Update overview Section 1.1 Added OD/PP to P0.12 in Ta bl e 6 Changed name of WFI mode to WAIT mode Changed Memory Map Ta b l e 6 : Ext. Memory changed to 64 MB

and flash register changed to 36 bytes. Added Power Consumption Tab l e 1 4 Modified BGA144 F3, F5, F12 and G12 in Ta b l e 2 and Ta bl e 3 Update EMI Timing Ta bl e 2 5 and Figure 29

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STR71xF Revision history

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22-May-2006 8

Added Flashless device. Changed reset state of pins P1.10 and P1.13 from pu to pd,

P0.15 from pu to floating and removed x in interrupt column for P1.15 and P1.12 in Ta b le 3 and Ta bl e 6

Added notes under Ta b le 3 on EMI pin reset state. Corrected inch value for d3 in Figure 37 Added footprint diagrams in Figure 37 and Figure 39 Updated Section 2: Electrical parameters

1-Aug-2006 9

Flash data retention changed to 20 years at 85° C. Changed note 8 on page 19 Changed note 1 on page 45

Table 41. Document revision history

Date Revision Changes

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