ST STPMS2 User Manual

second-order sigma-delta modulator with embedded PGLNA

Features

STPMS2

Smart sensor II dual-channel 1-bit, 4 MHz,

■ V

■ Two second-order sigma-delta (ΣΔ)

supply range 3.2 V - 5.5 V

CC

modulators

■ Programmable chopper-stabilized low noise

and low offset amplifier

■ Supports 50-60 Hz, EN 50470-1, EN 50470-3,

IEC 62053-21, IEC 62053-22 and IEC 62053­23 standards specs for class 1, class 0.5 and
class 0.2 AC watt meters

■ STPM02H: less than 0.5% error over 1:10000

range

■ STPM02L: less than 0.5% error over 1:5000

range

■ Precision voltage reference: 1.23 V with

programmable TC (STPMS2L only)

■ Internal low drop regulator @ 3 V (typ.)

Applications

■ Power metering

■ Motor control

■ Industrial process control

■ Weight scales

■ Pressure transducers

QFN16 (4 x 4)

or multi-phase energy meters along with the
STPMC1 device, a digital signal processor
designed for energy measurement. This device
can be used in medium and high resolution
measurement applications where single or double
inputs must be monitored at the same time. The
STPMS2 are mixed signal ICs consisting of an
analog and digital section. The analog section
consists of a programmable gain, low noise
choppered amplifier, two second-order ΔΣ
modulator blocks, a band-gap voltage reference,
a low-drop voltage regulator and DC buffers, while
the digital section consists of a clock generator
and output multiplexer.

Description

The STPMS2, also called “smart sensor” devices,
are ASSPs designed for effective measurement in
power line systems utilizing Rogowski coil, current
transformer, Hall or shunt sensors. These devices
are designed as building blocks for single-phase

Table 1. Device summary

Order codes Package Packaging

STPMS2H-PUR QFN16 (4 x 4 mm) 4500 parts per reel

STPMS2L-PUR QFN16 (4 x 4 mm) 4500 parts per reel

October 2011 Doc ID 16525 Rev 3 1/33

www.st.com

33

Contents STPMS2

Contents

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2 Internal block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

3 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

4 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

4.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

5 Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

6 Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

6.1 Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

6.2 Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

7 Typical performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

8 Theory of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

8.1 General operation description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

8.2 Functional description of the analog part . . . . . . . . . . . . . . . . . . . . . . . . . 17

8.3 Functional description of the digital part . . . . . . . . . . . . . . . . . . . . . . . . . . 20

8.3.1 Decoder for different modes of operation . . . . . . . . . . . . . . . . . . . . . . . 21

8.3.2 Generator for clock frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

8.4 Hard mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

8.5 Soft mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

8.5.1 Writing to the configuration register in Soft mode . . . . . . . . . . . . . . . . . 27

9 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

2/33 Doc ID 16525 Rev 3

STPMS2 Introduction

1 Introduction

The STPMS2 is a device designed to measure electrical line parameters (voltage and
current) via analog signals from voltage sensors (current divider) and current sensors
(inductive Rogowski coil, current transformer or shunt resistors). The device is used
together with a digital signal processing circuit to implement an effective measuring system
for multi-phase power meters.

The device consists of two analog measuring channels, consisting of second-order sigma­delta modulators with appropriate non-overlapping control signal generator. The STPMS2
also includes a temperature compensated band-gap reference voltage generator, a low­drop supply voltage stabilizer and minimal digital circuitry that includes BIST (built-in self­test) structures. In a current signal processing channel, a low-noise preamplifier is included
in front of the sigma-delta converter. All reference voltages (band-gap, AGND) are internally
buffered to eliminate channel crosstalk.

The STPMS2 can operate in fast or low-power mode. In fast mode, a nominal clock
frequency of 4.1 or 4.9 MHz is applied to the clock input. In this mode, signal bandwidth is
specified between 0 and 4 kHz. In low-power mode, the nominal clock is four times slower in
order to reduce the power consumption of the circuit. In low-power mode, the quiescent bias
currents of the preamplifier and sigma-delta integrators are lowered and the signal
bandwidth is narrowed to the frequency bandwidth of 0 to 1 kHz.

Doc ID 16525 Rev 3 3/33

Internal block diagram STPMS2

2 Internal block diagram

Figure 1. STPMS2 internal block diagram

VDDav

EINC HPV

VIP

VIN

CIP

CIN

VDDac

VCC

LDR

MUX

BIST D AC

MUX

EINC HPC

EINC HPC,
EINC HPV

GAIN

GAIN

PLNA

TC

VOLTAGE

REFERENCE

2nd ord ΣΔ

modulator

ECHPL FV,

PDV

ECHPHF V

EPRSV

EPRSV

ECHPL FC,
ECHPHFC

2nd ord ΣΔ

modulator

MV, NV

MC, NC

DIGITAL

VRefV

VRefC

FRONT

END

DAT

DATN

MS3

MS2

MS1

MS0

CLK

GND

VDDa

VBG

4/33 Doc ID 16525 Rev 3

AM09892v1

STPMS2 Pin configuration

3 Pin configuration

Figure 2. Pin connections

MS3

CLK

13

MS2

12

MS1

11

VCC

VDDac

DAT

DATn

16

15

14

1

2

GND

10

9

MS0

VDDav

AM09382v1

Table 2. Pin description

VDDa

VBG

3

4

56

CIP

CIN

7

VIN

8

VIP

Pin n° Symbol Description

1 VCC Unregulated supply voltage for pad-ring, bandgap, low-drop and level shifters

2 VDDac Current channel modulator supply input

3 VDDa Output of internal + 3.0 V low drop regulated power supply

4 VBG

Output of internal + 1.23 V bias generator (STPMS2L);
Input of external precision reference voltage (STPMS2H)

5 CIN Current channel -

6 CIP Current channel +

7 VIN Voltage channel -

8 VIP Voltage channel +

9 VDDav Voltage channel modulator supply input

10 MS0 Input for configurator 0

11 MS1 Input for configurator 1

12 MS2 Input for configurator 2

13 MS3 Input for configurator 3

14 CLK Input for external measurement clock

15 DAT

16 DATn

Output of multiplexed ΣΔ signal
Output of current ΣΔ signal

Output of inverted multiplexed ΣΔ signal
Output of voltage ΣΔ signal

Exp PAD GND Ground level for signals and pin protection

Doc ID 16525 Rev 3 5/33

Maximum ratings STPMS2

4 Maximum ratings

Table 3. Absolute maximum ratings

Symbol Parameter Value Unit

V

I

V

V

CC

PIN

ID

IA

DC Input voltage -0.3 to 6 V

Current on any pin (sink/source) ±150 mA

Input voltage at any pin -0.3 to V

+0.3 V

CC

Input voltage at analog pins (VIP, VIN, IIP, IIN) -0.7 to 0.7 V

ESD Human body model (all pins) ±2 kV

T

T

OP

T

J

STG

Operating ambient temperature -40 to 85 °C

Junction temperature -40 to 150 °C

Storage temperature range -55 to 150 °C

Note: Absolute maximum ratings are those values beyond which damage to the device may occur.

Functional operation under these conditions is not implied.

Table 4. Thermal data

Symbol Parameter Value Unit

(1)

R

thJA

1. This value is referred to single-layer PCB, JEDEC standard test board.

Thermal resistance junction-ambient 38.66 °C/W

6/33 Doc ID 16525 Rev 3

STPMS2 Maximum ratings

4.1 General operating conditions

VCC = 5 V, T
between VBG and GND, f

Table 5. General operating conditions

= 25 °C, 1 µF between VCC, VDDa, VDDac, VDDav and GND, 100 nF

AMB

= 4.19 MHZ unless otherwise specified.

CLK

Symbol Parameter Test conditions Min. Typ. Max. Unit

General section

V

I

V

V

I

LATCH

f

Operating supply

CC

voltage

Quiescent current

CC

Power on reset on V

POR

Regulated supply

DD

voltage

LP, 1.229MHz; V

=3.3V; CL=100nF;

CC

no loads

HP, 4.915MHz; V

=3.2V; CL=100nF;

CC

no loads

CC

1.049MHz; VCC=3.2V; CL=100nF; no
loads

3.135 5.25 V

1.2 1.5

45

2.5 V

2.95 3.00 3.05 V

Current injection latch­up immunity

Effective bandwidth Limited by chopper 0 4091 Hz

BW

300 mA

DC measurement accuracy

Resolution 11 16 bit

INL Integral non linearity

DNL Differential linearity

Offset error

Gain error

Result referred to a 16-bit word of CIP­CIN channel, HP mode, f

= 2.047MHz

CLK

Result referred to a 12-bit word of VIP­VIN channel, HP mode, f

=2.047MHz

CLK

Result referred to a 16-bit word of CIP­CIN channel, HP mode, f

=2.047MHz

CLK

Result referred to a 12-bit word of VIP­VIN channel, HP mode, f

=2.047MHz

CLK

Result referred to a 16-bit word of CIP­CIN channel, HP mode, f

=2.047MHz

CLK

Result referred to a 12 bit-word of VIP­VIN channel, HP mode, f

=2.047MHz

CLK

Result referred to a 16-bit word of CIP­CIN channel, HP mode, f

=2.047MHz

CLK

Result referred to a 12-bit word of VIP­VIN channel, HP mode, f

=2.047MHz

CLK

0.04 0.4

3.3

LSB

3.9

0.3

LSB

0.5

0.02

LSB

0.005

LSB/uV

0.003

CIP-CIN channel gain 2x 120

NF Noise floor

VIP-VIN channel 95

mA

dBCIP-CIN channel gain 16x 118

Doc ID 16525 Rev 3 7/33

Maximum ratings STPMS2

Table 5. General operating conditions (continued)

Symbol Parameter Test conditions Min. Typ. Max. Unit

PSRR

Power supply DC

DC

rejection

AC measurement accuracy

SNR Signal to noise ratio

SINAD

Signal to noise ratio +
distortion

THD Total harmonic distortion

SFDR

PSRR

Spurious free dynamic
range

Power supply AC

AC

rejection

Analog inputs (CIP, CIN, VIP, VIN)

Voltage signal: 200 mV
Current signal: 10 mV

=2.048 MHz

f

CLK

rms

rms

/50Hz

/50Hz

VCC=3.3V ±10%, 5V ±10%

CIP-CIN channel – Vin=±230mV @
55Hz gain 2x over 4 kHz bandwidth

VIP-VIN channel – Vin=±230mV @
55Hz over 4 kHz bandwidth

CIP-CIN channel – Vin=±230mV @
55Hz gain 2x over 4 kHz bandwidth

VIP-VIN channel – Vin=±230mV @
55Hz over 4 kHz bandwidth

CIP-CIN channel – Vin=±230mV @
55Hz gain 2x over 4 kHz bandwidth

VIP-VIN channel – Vin=±230mV @
55Hz over 4 kHz bandwidth

CIP-CIN channel – Vin=±230mV @
55Hz gain 2x over 4 kHz bandwidth

VIP-VIN channel – Vin=±230mV @
55Hz over 4 kHz bandwidth

Voltage signal: 200 mV
Current signal: 10 mV

=2.048 MHz

f

CLK

VCC=3.3V+0.2V

=5.0V+0.2V

V

CC

rms

rms

/50Hz

rms

/50Hz

rms

1@100Hz
1@100Hz

90 dB

82

dB

52

82

dB

52

-105

dB

-78

90

dB

68

120 dB

VIP-VIN channel -0.3 +0.3 V

STPMS2L CIP-CIN channel
Gain 2x
Gain 4x
Gain 8x

V

Maximum input signal

MAX

levels

Gain 16x

STPMS2H CIP-CIN channel

f

V

Z

Z

G

A/D sampling frequency f

SPL

Amplifier offset ±20 mV

off

VIP, VIN impedance Over total operating voltage range 100 400 kΩ

IP

CIP, CIN impedance Over total operating voltage range 35 50 kΩ

IN

Gain error of current

ERR

channels

8/33 Doc ID 16525 Rev 3

-0.3

-0.15

-0.075

-0.0375

-V

REF

GAIN

+0.3

+0.15

+0.075

+0.0375

/

+V

REF

GAIN

CLK

±10 %

V

/

Hz

STPMS2 Maximum ratings

Table 5. General operating conditions (continued)

Symbol Parameter Test conditions Min. Typ. Max. Unit

I

Voltage channel leakage

ILV

current

Current channel leakage

I

ILI

current

V

CC

V

CC

V

CC

=5.25V, f

=5.25V, f

=5.25V, f

CLK

CLK

CLK

enabled

Crosstalk between
channels

Digital I/O (CLK, DAT, DATN, MS0, MS1, MS2, MS3)

V

V

V

V

I

t

Input High voltage

IH

Input Low Voltage -0.3

IL

Output high voltage IO=-1mA, CL=50pF, VCC=3.2V VCC-0.4 V

OH

Output low voltage IO=+1mA, CL=50pF, VCC=3.2V 0.4 V

OL

Pull up current 15 µA

UP

Transition time C

TR

t

Latency From 50% of CLK to 50% to DAT 40 ns

L

=50pF 10 ns

LOAD

Clock input

Low precision mode 1.0 1.228

f

Nominal frequencies

CLK

Very high precision mode 4.0 4.915

=4.19MHz -1 1 µA

=4.19MHz -1 1

=4.19MHz input

-10 10

130 dB

0.75V

C

C

5.3 V

0.25V

C

C

MHzHigh precision mode 2.0 2.458

V

On chip reference voltage

V

Z

1. This level may be delivered from external source in STPMS2H.

Reference voltage STPMS2L only

REF

Output impedance 30 200 kΩ

out

I

Maximum load current 0 µA

L

Temperature coefficient After calibration 30 50 ppm/°C

T

C

(1)

Doc ID 16525 Rev 3 9/33

1.21 1.23 1.25 V

Maximum ratings STPMS2

Figure 3. Timing diagram

AM09383v1

CLK - clock signal on CLK pin

CLK

bsV - sigma-delta bit stream of voltage signal

bsC - sigma-delta bit stream of current signal

DATA - multiplexed data of voltage and current signal on DAT pin

- sigma-delta sampling frequency

sample

10/33 Doc ID 16525 Rev 3