STPMS2
Smart sensor II dual-channel 1-bit, 4 MHz, second-order sigma-delta modulator with embedded PGLNA
Features
■VCC supply range 3.2 V - 5.5 V
■Two second-order sigma-delta (ΣΔ) modulators
■Programmable chopper-stabilized low noise and low offset amplifier
■Supports 50-60 Hz, EN 50470-1, EN 50470-3, IEC 62053-21, IEC 62053-22 and IEC 6205323 standards specs for class 1, class 0.5 and class 0.2 AC watt meters
■STPM02H: less than 0.5% error over 1:10000 range
■STPM02L: less than 0.5% error over 1:5000 range
■Precision voltage reference: 1.23 V with programmable TC (STPMS2L only)
■Internal low drop regulator @ 3 V (typ.)
Applications
■Power metering
■Motor control
■Industrial process control
■Weight scales
■Pressure transducers
QFN16 (4 x 4)
or multi-phase energy meters along with the STPMC1 device, a digital signal processor designed for energy measurement. This device can be used in medium and high resolution measurement applications where single or double inputs must be monitored at the same time. The STPMS2 are mixed signal ICs consisting of an analog and digital section. The analog section consists of a programmable gain, low noise choppered amplifier, two second-order ΔΣ modulator blocks, a band-gap voltage reference, a low-drop voltage regulator and DC buffers, while the digital section consists of a clock generator and output multiplexer.
Description
The STPMS2, also called “smart sensor” devices, are ASSPs designed for effective measurement in power line systems utilizing Rogowski coil, current transformer, Hall or shunt sensors. These devices are designed as building blocks for single-phase
Table 1. |
Device summary |
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Order codes |
Package |
Packaging |
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STPMS2H-PUR |
QFN16 (4 x 4 mm) |
4500 parts per reel |
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STPMS2L-PUR |
QFN16 (4 x 4 mm) |
4500 parts per reel |
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October 2011 |
Doc ID 16525 Rev 3 |
1/33 |
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www.st.com |
Contents |
STPMS2 |
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Contents
1 |
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. 3 |
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2 |
Internal block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
6 |
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4.1 |
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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5 |
Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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6.1 Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.2 Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
7 |
Typical performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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8 |
Theory of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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8.1 |
General operation description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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8.2 |
Functional description of the analog part . . . . . . . . . . . . . . . . . . . . . . . . . |
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8.3 |
Functional description of the digital part . . . . . . . . . . . . . . . . . . . . . . . . . . |
20 |
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8.3.1 |
Decoder for different modes of operation . . . . . . . . . . . . . . . . . . . . . . . |
21 |
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8.3.2 |
Generator for clock frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
21 |
8.4 Hard mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 8.5 Soft mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
8.5.1 Writing to the configuration register in Soft mode . . . . . . . . . . . . . . . . . 27
9 |
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
28 |
10 |
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
32 |
2/33 |
Doc ID 16525 Rev 3 |
STPMS2 |
Introduction |
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The STPMS2 is a device designed to measure electrical line parameters (voltage and current) via analog signals from voltage sensors (current divider) and current sensors (inductive Rogowski coil, current transformer or shunt resistors). The device is used together with a digital signal processing circuit to implement an effective measuring system for multi-phase power meters.
The device consists of two analog measuring channels, consisting of second-order sigmadelta modulators with appropriate non-overlapping control signal generator. The STPMS2 also includes a temperature compensated band-gap reference voltage generator, a lowdrop supply voltage stabilizer and minimal digital circuitry that includes BIST (built-in selftest) structures. In a current signal processing channel, a low-noise preamplifier is included in front of the sigma-delta converter. All reference voltages (band-gap, AGND) are internally buffered to eliminate channel crosstalk.
The STPMS2 can operate in fast or low-power mode. In fast mode, a nominal clock frequency of 4.1 or 4.9 MHz is applied to the clock input. In this mode, signal bandwidth is specified between 0 and 4 kHz. In low-power mode, the nominal clock is four times slower in order to reduce the power consumption of the circuit. In low-power mode, the quiescent bias currents of the preamplifier and sigma-delta integrators are lowered and the signal bandwidth is narrowed to the frequency bandwidth of 0 to 1 kHz.
Doc ID 16525 Rev 3 |
3/33 |
Internal block diagram |
STPMS2 |
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VDDav |
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EINCHPV |
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VIP |
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DAT |
VIN |
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MUX |
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2nd ord ΣΔ |
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modulator |
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DATN |
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MV, NV |
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MS3 |
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EINCHPC, |
PDV |
ECHPLFV, |
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EINCHPV |
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ECHPHFV |
DIGITAL |
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BIST DAC |
GAIN |
EPRSV |
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FRONT |
MS2 |
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EPRSV |
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ECHPLFC, |
END |
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ECHPHFC |
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MC, NC |
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GAIN |
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MS1 |
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CIP |
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MUX |
PLNA |
2nd ord ΣΔ |
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modulator |
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MS0 |
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CIN |
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CLK |
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EINCHPC |
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VDDac |
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TC |
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VOLTAGE |
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VRefV |
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VCC |
LDR |
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REFERENCE |
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VRefC |
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GND |
VDDa |
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VBG |
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AM09892v1 |
4/33 |
Doc ID 16525 Rev 3 |
STPMS2 |
Pin configuration |
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DATn |
DAT |
CLK |
MS3 |
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16 |
15 |
14 |
13 |
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VCC |
1 |
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12 |
MS2 |
VDDac |
2 |
GND |
11 |
MS1 |
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VDDa 3
VBG 4
5 |
6 |
7 |
8 |
CIN |
CIP |
VIN |
VIP |
10 MS0
9 VDDav
AM09382v1
Table 2. |
Pin description |
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Pin n° |
Symbol |
Description |
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1 |
VCC |
Unregulated supply voltage for pad-ring, bandgap, low-drop and level shifters |
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2 |
VDDac |
Current channel modulator supply input |
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3 |
VDDa |
Output of internal + 3.0 V low drop regulated power supply |
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4 |
VBG |
Output of internal + 1.23 V bias generator (STPMS2L); |
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Input of external precision reference voltage (STPMS2H) |
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5 |
CIN |
Current channel - |
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6 |
CIP |
Current channel + |
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7 |
VIN |
Voltage channel - |
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8 |
VIP |
Voltage channel + |
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9 |
VDDav |
Voltage channel modulator supply input |
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10 |
MS0 |
Input for configurator 0 |
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11 |
MS1 |
Input for configurator 1 |
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12 |
MS2 |
Input for configurator 2 |
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13 |
MS3 |
Input for configurator 3 |
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14 |
CLK |
Input for external measurement clock |
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15 |
DAT |
Output of multiplexed ΣΔ signal |
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Output of current ΣΔ signal |
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16 |
DATn |
Output of inverted multiplexed ΣΔ signal |
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Output of voltage ΣΔ signal |
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Exp PAD |
GND |
Ground level for signals and pin protection |
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Doc ID 16525 Rev 3 |
5/33 |
Maximum ratings |
STPMS2 |
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Table 3. |
Absolute maximum ratings |
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Symbol |
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Parameter |
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Value |
Unit |
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VCC |
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DC Input voltage |
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-0.3 to 6 |
V |
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IPIN |
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Current on any pin (sink/source) |
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±150 |
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mA |
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VID |
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Input voltage at any pin |
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-0.3 to VCC +0.3 |
V |
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VIA |
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Input voltage at analog pins (VIP, VIN, IIP, IIN) |
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-0.7 to 0.7 |
V |
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ESD |
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Human body model (all pins) |
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±2 |
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kV |
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TOP |
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Operating ambient temperature |
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-40 to 85 |
°C |
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TJ |
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Junction temperature |
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-40 to 150 |
°C |
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TSTG |
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Storage temperature range |
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-55 to 150 |
°C |
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Note: |
Absolute maximum ratings are those values beyond which damage to the device may occur. |
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Functional operation under these conditions is not implied. |
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Table 4. |
Thermal data |
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Value |
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Unit |
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(1) |
Thermal resistance junction-ambient |
38.66 |
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°C/W |
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RthJA |
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1. This value is referred to single-layer PCB, JEDEC standard test board.
6/33 |
Doc ID 16525 Rev 3 |
STPMS2 |
Maximum ratings |
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4.1General operating conditions
VCC = 5 V, TAMB = 25 °C, 1 µF between VCC, VDDa, VDDac, VDDav and GND, 100 nF between VBG and GND, fCLK = 4.19 MHZ unless otherwise specified.
Table 5. |
General operating conditions |
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Symbol |
Parameter |
Test conditions |
Min. |
Typ. |
Max. |
Unit |
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General section |
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VCC |
Operating supply |
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3.135 |
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5.25 |
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voltage |
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LP, 1.229MHz; VCC=3.3V; CL=100nF; |
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1.2 |
1.5 |
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ICC |
Quiescent current |
no loads |
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mA |
HP, 4.915MHz; VCC=3.2V; CL=100nF; |
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4 |
5 |
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no loads |
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VPOR |
Power on reset on VCC |
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2.5 |
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V |
VDD |
Regulated supply |
1.049MHz; VCC=3.2V; CL=100nF; no |
2.95 |
3.00 |
3.05 |
V |
voltage |
loads |
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ILATCH |
Current injection latch- |
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300 |
mA |
up immunity |
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fBW |
Effective bandwidth |
Limited by chopper |
0 |
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4091 |
Hz |
DC measurement accuracy |
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Resolution |
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11 |
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16 |
bit |
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Result referred to a 16-bit word of CIP- |
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3.3 |
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CIN channel, HP mode, fCLK= 2.047MHz |
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INL |
Integral non linearity |
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LSB |
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Result referred to a 12-bit word of VIP- |
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3.9 |
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VIN channel, HP mode, fCLK=2.047MHz |
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Result referred to a 16-bit word of CIP- |
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0.3 |
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CIN channel, HP mode, fCLK=2.047MHz |
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DNL |
Differential linearity |
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LSB |
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Result referred to a 12-bit word of VIP- |
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0.5 |
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VIN channel, HP mode, fCLK=2.047MHz |
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Result referred to a 16-bit word of CIP- |
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0.02 |
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CIN channel, HP mode, fCLK=2.047MHz |
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Offset error |
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LSB |
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Result referred to a 12 bit-word of VIP- |
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0.005 |
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VIN channel, HP mode, fCLK=2.047MHz |
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Result referred to a 16-bit word of CIP- |
0.04 |
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0.4 |
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CIN channel, HP mode, fCLK=2.047MHz |
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Gain error |
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LSB/uV |
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Result referred to a 12-bit word of VIP- |
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0.003 |
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VIN channel, HP mode, fCLK=2.047MHz |
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CIP-CIN channel gain 2x |
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120 |
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NF |
Noise floor |
CIP-CIN channel gain 16x |
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118 |
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dB |
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VIP-VIN channel |
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95 |
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Doc ID 16525 Rev 3 |
7/33 |
Maximum ratings |
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STPMS2 |
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Table 5. |
General operating conditions (continued) |
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Symbol |
Parameter |
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Test conditions |
Min. |
Typ. |
Max. |
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Unit |
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Voltage signal: 200 mVrms/50Hz |
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PSRRDC |
Power supply DC |
Current signal: 10 mVrms/50Hz |
90 |
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dB |
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rejection |
fCLK=2.048 MHz |
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VCC=3.3V ±10%, 5V ±10% |
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AC measurement accuracy |
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CIP-CIN channel – Vin=±230mV @ |
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82 |
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55Hz gain 2x over 4 kHz bandwidth |
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SNR |
Signal to noise ratio |
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dB |
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VIP-VIN channel – Vin=±230mV @ |
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52 |
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55Hz over 4 kHz bandwidth |
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CIP-CIN channel – Vin=±230mV @ |
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82 |
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Signal to noise ratio + |
55Hz gain 2x over 4 kHz bandwidth |
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SINAD |
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dB |
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distortion |
VIP-VIN channel – Vin=±230mV @ |
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52 |
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55Hz over 4 kHz bandwidth |
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CIP-CIN channel – Vin=±230mV @ |
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-105 |
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55Hz gain 2x over 4 kHz bandwidth |
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THD |
Total harmonic distortion |
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dB |
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VIP-VIN channel – Vin=±230mV @ |
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-78 |
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55Hz over 4 kHz bandwidth |
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CIP-CIN channel – Vin=±230mV @ |
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90 |
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Spurious free dynamic |
55Hz gain 2x over 4 kHz bandwidth |
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SFDR |
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dB |
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range |
VIP-VIN channel – Vin=±230mV @ |
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68 |
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55Hz over 4 kHz bandwidth |
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Voltage signal: 200 mVrms/50Hz |
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Power supply AC |
Current signal: 10 mVrms/50Hz |
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PSRRAC |
fCLK=2.048 MHz |
120 |
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dB |
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rejection |
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VCC=3.3V+0.2Vrms1@100Hz |
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VCC=5.0V+0.2Vrms1@100Hz |
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Analog inputs (CIP, CIN, VIP, VIN) |
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VIP-VIN channel |
-0.3 |
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+0.3 |
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V |
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STPMS2L |
CIP-CIN channel |
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Maximum input signal |
Gain 2x |
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-0.3 |
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+0.3 |
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VMAX |
Gain 4x |
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levels |
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-0.15 |
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+0.15 |
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Gain 8x |
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V |
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-0.075 |
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+0.075 |
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Gain 16x |
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-0.0375 |
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+0.0375 |
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STPMS2H |
CIP-CIN channel |
-VREF/ |
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+VREF/ |
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GAIN |
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GAIN |
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fSPL |
A/D sampling frequency |
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fCLK |
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Hz |
Voff |
Amplifier offset |
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±20 |
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mV |
ZIP |
VIP, VIN impedance |
Over total operating voltage range |
100 |
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400 |
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kΩ |
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ZIN |
CIP, CIN impedance |
Over total operating voltage range |
35 |
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50 |
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kΩ |
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GERR |
Gain error of current |
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±10 |
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% |
channels |
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8/33 |
Doc ID 16525 Rev 3 |
STPMS2 |
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Maximum ratings |
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Table 5. |
General operating conditions (continued) |
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Symbol |
Parameter |
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Test conditions |
Min. |
Typ. |
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Max. |
Unit |
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I |
ILV |
Voltage channel leakage |
V |
=5.25V, f |
=4.19MHz |
-1 |
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1 |
µA |
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current |
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CC |
CLK |
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Current channel leakage |
VCC=5.25V, fCLK=4.19MHz |
-1 |
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1 |
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IILI |
VCC=5.25V, fCLK=4.19MHz input |
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current |
-10 |
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10 |
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enabled |
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Crosstalk between |
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130 |
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dB |
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channels |
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Digital I/O (CLK, DAT, DATN, MS0, MS1, MS2, MS3) |
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VIH |
Input High voltage |
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0.75VC |
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5.3 |
V |
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C |
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VIL |
Input Low Voltage |
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-0.3 |
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0.25VC |
V |
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C |
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VOH |
Output high voltage |
IO=-1mA, CL=50pF, VCC=3.2V |
VCC-0.4 |
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V |
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VOL |
Output low voltage |
IO=+1mA, CL=50pF, VCC=3.2V |
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0.4 |
V |
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IUP |
Pull up current |
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15 |
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µA |
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tTR |
Transition time |
CLOAD=50pF |
|
10 |
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ns |
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tL |
Latency |
From 50% of CLK to 50% to DAT |
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40 |
ns |
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Clock input |
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Low precision mode |
1.0 |
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1.228 |
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fCLK |
Nominal frequencies |
High precision mode |
2.0 |
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2.458 |
MHz |
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Very high precision mode |
4.0 |
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4.915 |
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On chip reference voltage |
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VREF |
Reference voltage |
STPMS2L only (1) |
1.21 |
1.23 |
|
1.25 |
V |
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Zout |
Output impedance |
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30 |
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200 |
kΩ |
|
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IL |
Maximum load current |
|
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0 |
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|
µA |
TC |
Temperature coefficient |
After calibration |
|
30 |
|
50 |
ppm/°C |
1. This level may be delivered from external source in STPMS2H.
Doc ID 16525 Rev 3 |
9/33 |
Maximum ratings |
STPMS2 |
|
|
AM09383v1
CLK - clock signal on CLK pin
CLKsample - sigma-delta sampling frequency bsV - sigma-delta bit stream of voltage signal bsC - sigma-delta bit stream of current signal
DATA - multiplexed data of voltage and current signal on DAT pin
10/33 |
Doc ID 16525 Rev 3 |