ST STPMS2 User Manual

STPMS2

Smart sensor II dual-channel 1-bit, 4 MHz, second-order sigma-delta modulator with embedded PGLNA

Features

■VCC supply range 3.2 V - 5.5 V

■Two second-order sigma-delta (ΣΔ) modulators

■Programmable chopper-stabilized low noise and low offset amplifier

■Supports 50-60 Hz, EN 50470-1, EN 50470-3, IEC 62053-21, IEC 62053-22 and IEC 6205323 standards specs for class 1, class 0.5 and class 0.2 AC watt meters

■STPM02H: less than 0.5% error over 1:10000 range

■STPM02L: less than 0.5% error over 1:5000 range

■Precision voltage reference: 1.23 V with programmable TC (STPMS2L only)

■Internal low drop regulator @ 3 V (typ.)

Applications

■Power metering

■Motor control

■Industrial process control

■Weight scales

■Pressure transducers

QFN16 (4 x 4)

or multi-phase energy meters along with the STPMC1 device, a digital signal processor designed for energy measurement. This device can be used in medium and high resolution measurement applications where single or double inputs must be monitored at the same time. The STPMS2 are mixed signal ICs consisting of an analog and digital section. The analog section consists of a programmable gain, low noise choppered amplifier, two second-order ΔΣ modulator blocks, a band-gap voltage reference, a low-drop voltage regulator and DC buffers, while the digital section consists of a clock generator and output multiplexer.

Description

The STPMS2, also called “smart sensor” devices, are ASSPs designed for effective measurement in power line systems utilizing Rogowski coil, current transformer, Hall or shunt sensors. These devices are designed as building blocks for single-phase

Table 1.	Device summary
	Order codes	Package	Packaging
	STPMS2H-PUR	QFN16 (4 x 4 mm)	4500 parts per reel
	STPMS2L-PUR	QFN16 (4 x 4 mm)	4500 parts per reel
October 2011		Doc ID 16525 Rev 3	1/33
			www.st.com

Contents	STPMS2

Contents

1	Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. 3
2	Internal block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. 4
3	Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		5
4	Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		6
	4.1	General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	7
5	Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		11
6	Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		14

6.1 Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

6.2 Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

7	Typical performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .			15
8	Theory of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			17
	8.1	General operation description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		17
	8.2	Functional description of the analog part . . . . . . . . . . . . . . . . . . . . . . . . .		17
	8.3	Functional description of the digital part . . . . . . . . . . . . . . . . . . . . . . . . . .		20
		8.3.1	Decoder for different modes of operation . . . . . . . . . . . . . . . . . . . . . . .	21
		8.3.2	Generator for clock frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	21

8.4 Hard mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 8.5 Soft mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

8.5.1 Writing to the configuration register in Soft mode . . . . . . . . . . . . . . . . . 27

9	Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	28
10	Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	32

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STPMS2	Introduction

1 Introduction

The STPMS2 is a device designed to measure electrical line parameters (voltage and current) via analog signals from voltage sensors (current divider) and current sensors (inductive Rogowski coil, current transformer or shunt resistors). The device is used together with a digital signal processing circuit to implement an effective measuring system for multi-phase power meters.

The device consists of two analog measuring channels, consisting of second-order sigmadelta modulators with appropriate non-overlapping control signal generator. The STPMS2 also includes a temperature compensated band-gap reference voltage generator, a lowdrop supply voltage stabilizer and minimal digital circuitry that includes BIST (built-in selftest) structures. In a current signal processing channel, a low-noise preamplifier is included in front of the sigma-delta converter. All reference voltages (band-gap, AGND) are internally buffered to eliminate channel crosstalk.

The STPMS2 can operate in fast or low-power mode. In fast mode, a nominal clock frequency of 4.1 or 4.9 MHz is applied to the clock input. In this mode, signal bandwidth is specified between 0 and 4 kHz. In low-power mode, the nominal clock is four times slower in order to reduce the power consumption of the circuit. In low-power mode, the quiescent bias currents of the preamplifier and sigma-delta integrators are lowered and the signal bandwidth is narrowed to the frequency bandwidth of 0 to 1 kHz.

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Internal block diagram	STPMS2

2 Internal block diagram

Figure 1. STPMS2 internal block diagram

VDDav
		EINCHPV
VIP							DAT
VIN		MUX		2nd ord ΣΔ
				modulator			DATN
					MV, NV		MS3
			EINCHPC,	PDV	ECHPLFV,
			EINCHPV		ECHPHFV	DIGITAL
	BIST DAC		GAIN	EPRSV
						FRONT	MS2
				EPRSV
					ECHPLFC,	END
					ECHPHFC
					MC, NC
			GAIN				MS1
CIP		MUX	PLNA	2nd ord ΣΔ
				modulator			MS0
CIN							CLK
		EINCHPC
VDDac			TC
			VOLTAGE			VRefV
VCC	LDR
			REFERENCE			VRefC
	GND	VDDa		VBG
							AM09892v1

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STPMS2	Pin configuration

3 Pin configuration

Figure 2. Pin connections

	DATn	DAT	CLK	MS3
	16	15	14	13
VCC	1			12	MS2
VDDac	2	GND		11	MS1

VDDa 3

VBG 4

5	6	7	8
CIN	CIP	VIN	VIP

10 MS0

9 VDDav

AM09382v1

	Table 2.	Pin description
	Pin n°	Symbol	Description
	1	VCC	Unregulated supply voltage for pad-ring, bandgap, low-drop and level shifters
	2	VDDac	Current channel modulator supply input
	3	VDDa	Output of internal + 3.0 V low drop regulated power supply
	4	VBG	Output of internal + 1.23 V bias generator (STPMS2L);
			Input of external precision reference voltage (STPMS2H)
	5	CIN	Current channel -
	6	CIP	Current channel +
	7	VIN	Voltage channel -
	8	VIP	Voltage channel +
	9	VDDav	Voltage channel modulator supply input
	10	MS0	Input for configurator 0
	11	MS1	Input for configurator 1
	12	MS2	Input for configurator 2
	13	MS3	Input for configurator 3
	14	CLK	Input for external measurement clock
	15	DAT	Output of multiplexed ΣΔ signal
			Output of current ΣΔ signal
	16	DATn	Output of inverted multiplexed ΣΔ signal
			Output of voltage ΣΔ signal
	Exp PAD	GND	Ground level for signals and pin protection

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Maximum ratings	STPMS2

4 Maximum ratings

Table 3.	Absolute maximum ratings
Symbol			Parameter		Value		Unit
	VCC		DC Input voltage		-0.3 to 6		V
	IPIN		Current on any pin (sink/source)		±150		mA
	VID		Input voltage at any pin		-0.3 to VCC +0.3		V
	VIA		Input voltage at analog pins (VIP, VIN, IIP, IIN)		-0.7 to 0.7		V
	ESD		Human body model (all pins)		±2		kV
	TOP		Operating ambient temperature		-40 to 85		°C
	TJ		Junction temperature		-40 to 150		°C
	TSTG		Storage temperature range		-55 to 150		°C
Note:	Absolute maximum ratings are those values beyond which damage to the device may occur.
	Functional operation under these conditions is not implied.
Table 4.	Thermal data
Symbol			Parameter		Value		Unit
	(1)	Thermal resistance junction-ambient			38.66		°C/W
RthJA

1. This value is referred to single-layer PCB, JEDEC standard test board.

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STPMS2	Maximum ratings

4.1General operating conditions

VCC = 5 V, TAMB = 25 °C, 1 µF between VCC, VDDa, VDDac, VDDav and GND, 100 nF between VBG and GND, fCLK = 4.19 MHZ unless otherwise specified.

Table 5.	General operating conditions
Symbol	Parameter	Test conditions	Min.	Typ.	Max.	Unit
General section
VCC	Operating supply		3.135		5.25	V
	voltage
		LP, 1.229MHz; VCC=3.3V; CL=100nF;		1.2	1.5
ICC	Quiescent current	no loads				mA
		HP, 4.915MHz; VCC=3.2V; CL=100nF;		4	5
		no loads
VPOR	Power on reset on VCC			2.5		V
VDD	Regulated supply	1.049MHz; VCC=3.2V; CL=100nF; no	2.95	3.00	3.05	V
	voltage	loads
ILATCH	Current injection latch-				300	mA
	up immunity
fBW	Effective bandwidth	Limited by chopper	0		4091	Hz
DC measurement accuracy
	Resolution		11		16	bit
		Result referred to a 16-bit word of CIP-		3.3
		CIN channel, HP mode, fCLK= 2.047MHz
INL	Integral non linearity					LSB
		Result referred to a 12-bit word of VIP-		3.9
		VIN channel, HP mode, fCLK=2.047MHz
		Result referred to a 16-bit word of CIP-		0.3
		CIN channel, HP mode, fCLK=2.047MHz
DNL	Differential linearity					LSB
		Result referred to a 12-bit word of VIP-		0.5
		VIN channel, HP mode, fCLK=2.047MHz
		Result referred to a 16-bit word of CIP-		0.02
		CIN channel, HP mode, fCLK=2.047MHz
	Offset error					LSB
		Result referred to a 12 bit-word of VIP-		0.005
		VIN channel, HP mode, fCLK=2.047MHz
		Result referred to a 16-bit word of CIP-	0.04		0.4
		CIN channel, HP mode, fCLK=2.047MHz
	Gain error					LSB/uV
		Result referred to a 12-bit word of VIP-		0.003
		VIN channel, HP mode, fCLK=2.047MHz
		CIP-CIN channel gain 2x		120
NF	Noise floor	CIP-CIN channel gain 16x		118		dB
		VIP-VIN channel		95

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Maximum ratings							STPMS2
Table 5.	General operating conditions (continued)
Symbol	Parameter		Test conditions	Min.	Typ.	Max.		Unit
		Voltage signal: 200 mVrms/50Hz
PSRRDC	Power supply DC	Current signal: 10 mVrms/50Hz		90				dB
	rejection	fCLK=2.048 MHz
		VCC=3.3V ±10%, 5V ±10%
AC measurement accuracy
		CIP-CIN channel – Vin=±230mV @			82
		55Hz gain 2x over 4 kHz bandwidth
SNR	Signal to noise ratio							dB
		VIP-VIN channel – Vin=±230mV @			52
		55Hz over 4 kHz bandwidth
		CIP-CIN channel – Vin=±230mV @			82
	Signal to noise ratio +	55Hz gain 2x over 4 kHz bandwidth
SINAD								dB
	distortion	VIP-VIN channel – Vin=±230mV @			52
		55Hz over 4 kHz bandwidth
		CIP-CIN channel – Vin=±230mV @			-105
		55Hz gain 2x over 4 kHz bandwidth
THD	Total harmonic distortion							dB
		VIP-VIN channel – Vin=±230mV @			-78
		55Hz over 4 kHz bandwidth
		CIP-CIN channel – Vin=±230mV @			90
	Spurious free dynamic	55Hz gain 2x over 4 kHz bandwidth
SFDR								dB
	range	VIP-VIN channel – Vin=±230mV @			68
		55Hz over 4 kHz bandwidth
		Voltage signal: 200 mVrms/50Hz
	Power supply AC	Current signal: 10 mVrms/50Hz
PSRRAC		fCLK=2.048 MHz		120				dB
	rejection
		VCC=3.3V+0.2Vrms1@100Hz
		VCC=5.0V+0.2Vrms1@100Hz
Analog inputs (CIP, CIN, VIP, VIN)
		VIP-VIN channel		-0.3		+0.3		V
		STPMS2L	CIP-CIN channel
	Maximum input signal	Gain 2x		-0.3		+0.3
VMAX		Gain 4x
	levels			-0.15		+0.15
		Gain 8x						V
				-0.075		+0.075
		Gain 16x
				-0.0375		+0.0375
		STPMS2H	CIP-CIN channel	-VREF/		+VREF/
				GAIN		GAIN
fSPL	A/D sampling frequency				fCLK			Hz
Voff	Amplifier offset					±20		mV
ZIP	VIP, VIN impedance	Over total operating voltage range		100		400		kΩ
ZIN	CIP, CIN impedance	Over total operating voltage range		35		50		kΩ
GERR	Gain error of current				±10			%
	channels

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STPMS2								Maximum ratings
Table 5.		General operating conditions (continued)
Symbol		Parameter		Test conditions		Min.	Typ.		Max.	Unit
I	ILV	Voltage channel leakage	V	=5.25V, f	=4.19MHz	-1			1	µA
		current		CC	CLK
		Current channel leakage	VCC=5.25V, fCLK=4.19MHz			-1			1
IILI			VCC=5.25V, fCLK=4.19MHz input
		current				-10			10
			enabled
		Crosstalk between					130			dB
		channels
Digital I/O (CLK, DAT, DATN, MS0, MS1, MS2, MS3)
VIH		Input High voltage				0.75VC			5.3	V
						C
VIL		Input Low Voltage				-0.3			0.25VC	V
									C
VOH		Output high voltage	IO=-1mA, CL=50pF, VCC=3.2V			VCC-0.4				V
VOL		Output low voltage	IO=+1mA, CL=50pF, VCC=3.2V						0.4	V
IUP		Pull up current					15			µA
tTR		Transition time	CLOAD=50pF				10			ns
	tL	Latency	From 50% of CLK to 50% to DAT						40	ns
Clock input
			Low precision mode			1.0			1.228
fCLK		Nominal frequencies	High precision mode			2.0			2.458	MHz
			Very high precision mode			4.0			4.915
On chip reference voltage
VREF		Reference voltage	STPMS2L only (1)			1.21	1.23		1.25	V
Zout		Output impedance				30			200	kΩ
	IL	Maximum load current					0			µA
TC		Temperature coefficient	After calibration				30		50	ppm/°C

1. This level may be delivered from external source in STPMS2H.

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Maximum ratings	STPMS2

Figure 3. Timing diagram

AM09383v1

CLK - clock signal on CLK pin

CLKsample - sigma-delta sampling frequency bsV - sigma-delta bit stream of voltage signal bsC - sigma-delta bit stream of current signal

DATA - multiplexed data of voltage and current signal on DAT pin

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