ST STPC CLIENT User Manual

查询STPCCLIENT供应商



• POWERFUL X86 PROCESSOR

• 64-BIT 66MHz BUS INTERFACE

• 64-BIT DRAM CONTROLLER

• SVGAGRAPHICS CONTROLLER

• UMA ARCHITECTURE

• VIDEO SCALER

• VIDEO OUTPUT PORT

• VIDEO INPUT PORT

• CRT CONTROLLER

• 135MHz RAMDAC

• 2 OR 3 LINEFLICKER FILTER

• SCAN CONVERTER

• PCI MASTER / SLAVE / ARBITER

• ISA MASTER/SLAVE

• IDE CONTROLLER

• DMA CONTROLLER

• INTERRUPT CONTROLLER

• TIMER / COUNTERS

• POWER MANAGEMENT

STPC CLIENT

PC Compatible Embedded Microprocessor

PBGA388

Figure 1. Logic Diagram

IPC

EID

ISABUS

EIDE

x86

Core

Host I/F

ISA

PCI

STPC CLIENT OVERVIEW

The STPC Client integrates a standard 5th
generation x86 core, a DRAM controller, a
graphics subsystem, a video pipeline, and
support logic including PCI, ISA, and IDE
controllers to provide a single Consumer
orientated PC compatible subsystem on a single
device.
The device is based on a tightly coupled Unified
Memory Architecture (UMA), sharing the same
memory array between the CPU main memory
and the graphics and video frame buffers.
Extra facilities are implemented to handle video
streams. Features include smooth scaling and
colour space conversion of the video input stream
and mixing of the video stream with non-video
data from the frame buffer. The chip also includes
anti-flicker filters to provide a stable, high-quality
Digital TV output.
The STPC Client is packaged in a 388 Plastic Ball
Grid Array (PBGA).

February 8, 2000

PCI

PCIBUS

CCIRInput

VIP

TVOutput

Anti-

Col-

Vid-

2D

CRT

DRAM

Issue 1.7 1/48

Col-

our

Monitor

HW

SYNCOutput

STPC CLIENT

• X86 Processor core

• Fully static 32-bit 5-stage pipeline, x86 proc-

essor with DOS, Windows and UNIX compat­ibility.

• Can access up to 4GB of external memory.

• KBytes unified instruction and data cache

with write back and write through capability.

• Parallelprocessingintegralfloating point unit,
with automatic power down.

• Clock core speeds up to of 75 MHz.

• Fully static design for dynamic clock control.

• Low power and system management modes.

• Optimized design for 3.3V operation.

• DRAM Controller

• Integrated system memory andgraphic frame

memory.

• Supports up to 128 MBytes system memory
in 4 banks and as little as MBytes.

• Supports 4MBytes, 8MBites, 16MBites,
32MBites single-sided and double-sided
DRAM SIMMs.

• Four quad-word write buffers for CPU to
DRAM and PCI to DRAM cycles.

• Four 4-word read buffers for PCI masters.

• Supports Fast Page Mode & EDO DRAMs.

• Programmable timing for DRAM parameters

including CAS pulse width, CAS pre-charge
time, and RAS to CAS delay.

• 60, 70, 80 & 100ns DRAM speeds.

• Memory hole size of 1 MByte to 8 MBytes

supported for PCI/ISA buses.

• Hidden refresh.

To check if your memory device is supported by
the STPC, please refer to Table 7-69 in the
Programming Manual.

• Graphics Controller

• 64-bit windows accelerator.

• Backward compatibility to SVGA standards.

• Hardware acceleration for text, bitblts, trans-

parent blts and fills.

• Up to 64 x 64 bit graphics hardware cursor.

• Up to 4MB long linear frame buffer.

• 8-, 16-, and 24-bit pixels.

• CRT Controller

• Integrated 135MHz triple RAMDACallowing

up to 1024 x 768 x 75Hz display.

• 8-, 16-, 24-bit per pixels.

• Interlaced or non-interlaced output.

• Video Pipeline

• Two-tapinterpolative horizontal filter.

• Two-tapinterpolative vertical filter.

• Colour space conversion (RGB to YUV and

YUV to RGB).

• Programmable window size.

• Chroma and colour keying allowing video

overlay.

• Programmable two tap filter with gamma cor­rection or three tap flicker filter.

• Progressiveto interlaced scan converter.

• Video Input port

• Decodes video inputs in ITU-R 601/656 com-

patible formats.

• Optional 2:1 decimator

• Stores captured video in off setting area of

the onboard frame buffer.

• Video pass through to the onboard PAL/
NTSC encoder for full screen video images.

• HSYNC and B/T generation or lock onto
external video timing source.

• PCI Controller

• Integrated PCI arbitrationinterface able to

directly manage up to 3 PCI masters at a
time.

• Translation of PCI cycles to ISA bus.

• Translation of ISA master initiated cycle to

PCI.

• Support for burst read/write from PCI master.

• The PCI clock runs at a third or half CPU

clock speed.

2/48 Issue 1.7 - February 8, 2000

STPC CLIENT

• ISA master/slave

• The ISA clock generated from either

14.318MHz oscillator clock or PCI clock

• Supports programmable extra wait state for
ISA cycles

• Supports I/O recovery time for back to back I/
O cycles.

• Fast Gate A20 and Fast reset.

• Supports the single ROM that C, D,or E.

blocks shares with F block BIOS ROM.

• Supports flash ROM.

• Buffered DMA & ISA master cycles to reduce

bandwidth utilizationofthe PCI and Host bus.

• IDE Interface

• Supports PIO

• Supports up to Mode 5 Timings

• Supports up to 4 IDE devices

• Individual drive timing for all four IDEdevices

• Concurrent channel operation (PIO modes) -

4 x 32-Bit Buffer FIFO per channel

• Support for PIO mode 3 & 4

• Support for 11.1/16.6 MB/s, I/O Channel

Ready PIO data transfers.

• Supports both legacy & native IDE modes

• Supports hard drives larger than 528MB

• Support for CD-ROM and tape peripherals

• Backward compatibility with IDE (ATA-1).

• Integrated peripheral controller

• 2X8237/AT compatible 7-channel DMA con-

troller.

• 2X8259/AT compatible interrupt Controller.
16 interrupt inputs - ISA and PCI.

• Three 8254 compatible Timer/Counters.

• Power Management

• Four power saving modes: On, Doze, Stand-

by, Suspend.

• Programmable system activity detector

• Supports SMM.

• Supports STOPCLK.

• Supports IO trap & restart.

• Independent peripheral time-out timer to

monitor hard disk, serial & parallel ports.

• Supports RTC, interrupts and DMAs wake-up

Issue 1.7 - February 8, 2000 3/48

STPC CLIENT

4/48 Issue 1.7 - February 8, 2000

UPDATE HISTORY FOR OVERVIEW

UPDATE HISTORY FOR OVERVIEW

The following changes have been made to the Board LayoutChapter on 02/02/2000.

Section Change Text

Added

The following changes have been made to the Board LayoutChapter from Revision 1.0 to Release 1.2.

Section Change Text
N/A Replaced
N/A Replaced “133 MHz” With 75 MHz”
N/A Removed
N/A Removed

N/A Replaced

N/A Replaced

N/A Replaced

N/A Replaced
N/A Removed

N/A Replaced

N/A Replaced

N/A Replaced
N/A Removed
N/A Added “Individual drive timing for all four IDE devices “

N/A Replaced

N/A Removed

To check if your memory device is supported by the STPC, please refer to
Table 7-69 Host Address to MA Bus Mappingin the Programming Manual.

“fully PC compatible” With “with DOS, Windows and UNIX compatibility”

“Drivers for Windows and other operating systems.”

Requires external frequency synthesizer and reference sources.”

“

Chroma and colour keying for integrated video overlay.” With “Chroma and colour

“
keying

allowing video overlay.

“Accepts video inputs in CCIR 601/656 or ITU-R 601/656, and decodes the
stream.” With “Decodes video inputs in ITU-R 601/656 compatible formats.

“Fully compliant with PCI 2.1 specification.
Integrated PCI arbitration interface. Up to 3 masters can connect directly.
External PAL allows for greater than 3 masters.”

With

“Integrated PCI arbitration interface able to directly manage up to 3 PCI
masters at a time.”

“0.33X and 0.5X CPU clock PCI clock.” With “The PCI clock runs at a third or
half CPU clock speed.”

“Supports flash ROM.”
“Supports ISA hidden refresh.” With “Supports flash ROM.”

Buffered DMA & ISA master cycles to reduce bandwidth utilization of the PCI

“

and Host bus. NSP compliant.” With “Buffered DMA & ISA master cycles to
reduce bandwidth utilization of the PCI and Host bus. “

Supports PIO and Bus Master IDE” With “Supports PIO”

“

“Transfer Rates to 22 MBytes/sec”

“Concurrent channel operation (PIO & DMA modes) - 4 x 32-Bit Buffer FIFO
per channel”
With
“Concurrent channel operation (PIO modes) - 4 x 32-Bit Buffer FIFO per
channel”

“Support for DMA mode 1 & 2.”
“Support for 11.1/16.6 MB/s, I/O Channel Ready PIO data transfers.”
“Supports 13.3/16.6 MB/s DMA data transfers”
“Bus Master with scatter/gather capability “
“Multi-word DMA support for fast IDE drives “
“Individual drive timing for all four IDE devices “
“Supports both legacy & native IDE modes”
“Supports hard drives larger than 528MB”
“Support for CD-ROM and tape peripherals”
“Backward compatibility with IDE (ATA-1).”
“Drivers for Windows and other OSes”

Issue 1.7 - February 8, 2000 5/48

UPDATE HISTORY FOR OVERVIEW

Section Change Text

“Support for 11.1/16.6 MB/s, I/O Channel Ready PIO data transfers.”
“Supports both legacy & native IDE modes”

N/A Added

N/A Removed
N/A Replaced “Supports SMM and APM” With “Supports SMM”

N/A Removed

“Supports hard drives larger than 528MB”
“Support for CD-ROM and tape peripherals”
“Backward compatibility with IDE (ATA-1).”

“Co-processor error support logic.”

“Slow system clock down to 8MHz”
“Slow Host clock down to 8Hz”
“Slow graphic clock down to 8Hz”

6/48 Issue 1.7 - February 8, 2000

1.GENERAL DESCRIPTION

GENERAL DESCRIPTION

At the heart of the STPC Client is an advanced
processor block, dubbed the ST X86. The ST X86
includes a powerful x86 processor core along with
a 64-bit DRAM controller, advanced 64bit acceler­ated graphics and video controller, a high speed
PCI local-bus controller and Industry standard PC
chip set functions (Interrupt controller, DMA Con­troller, Interval timer and ISA bus) and EIDE con­troller.

The STPC Client has in addition to the 5ST86 a
Video subsystem and high quality digital Televi­sion output.

The STMicroelectronics x86 processorcore is em­bedded with standard and application specific pe­ripheral modules on the same silicon die. The core
has all the functionality of the ST Microelectronics
standard x86 processor products, including the
low power System Management Mode (SMM).

System Management Mode (SMM) provides an
additional interrupt and address space that can be
used for system power management or software
transparent emulation of peripherals. While run­ning in isolated SMM address space, the SMM in­terrupt routine can execute without interfering with
the operating system or application programs.

Further power management facilities include a
suspend mode that can be initiated from either
hardware orsoftware.Because of the static nature
of the core, no internal data is lost.

The STPC Client makes use of a tightly coupled
Unified Memory Architecture (UMA), where the
same memory array is used for CPU main memo­ry and graphics frame-buffer. This significantly re­duces total system memory with system perform­ances equal to that of a comparable solution with
separate frame buffer and system memory. In ad­dition, memory bandwidth is improved by attach­ing the graphics engine directly to the 64-bit proc­essor host interface running at the speed of the
processor bus rather than the traditional PCI bus.

The 64-bit wide memory array provides the sys­tem with 320MB/s peak bandwidth, double that of
an equivalent system using 32 bits. This allows for
higher screen resolutions and greater colour
depth. The processor bus runs at the speed of the
processor (DX devices) orhalf the speed (DX2 de­vices).

The ‘standard’ PC chipset functions (DMA, inter­rupt controller, timers, power management logic)
are integrated with the x86 processor core.

The PCI bus is the main data communication link
to the STPC Client chip. The STPC Client trans-

lates appropriate host bus I/O and Memory cycles
onto the PCI bus. It also supports the generation
of Configuration cycles on the PCI bus. The STPC
Client, as a PCIbus agent (host bridge class), fully
complies with PCI specification 2.1. The chip-set
also implements the PCI mandatory header regis­ters in Type 0 PCI configuration space for easy
porting of PCI aware system BIOS. The device
contains a PCI arbitration function for three exter­nal PCI devices.

The STPC Client integrates an ISA bus controller.
Peripheral modules such as parallel and serial
communications ports, keyboard controllers and
additional ISA devices can be accessed by the
STPC Client chip set through this bus.

An industry standard EIDE (ATA 2) controller is
built into the STPC Client and connected internally
via the PCI bus.

Graphics functions are controlled by the on-chip
SVGA controller and the monitor display is man­aged by the 2D graphics display engine.

This Graphics Engine is tuned to work with the
host CPU to provide a balanced graphics system
with a low silicon area cost. It performs limited
graphics drawing operations, which include hard­ware acceleration of text, bitblts, transparent blts
and fills. These operations can operate on off­screen or on-screen areas. The frame buffer size
is up to 4 MBytes anywhere in the physical main
memory.

The graphics resolution supported is a maximum
of 1280x1024 in 65536 colours at 75Hz refresh
rate and is VGA and SVGA compatible. Horizontal
timing fields are VGA compatible while the vertical
fields are extended by one bit to accommodate
above display resolution.

STPC Client provides several additional functions
to handle MPEG or similar video streams. The
Video Input Port accepts an encoded digital video
stream in one of a number of industry standard
formats, decodes it, optionally decimates it by a
factor of 2:1, and depositsit into an off screen area
of the frame buffer. An interrupt request can be
generated when an entire field or frame has been
captured.

The video output pipeline incorporates a video­scaler and colour space converter function and
provisions in the CRT controller to display a video
window. While repainting the screen the CRT con­troller fetches both the video as well as the normal
non-video frame buffer in two separate internal
FIFOs (256-Bytes each). The video stream can be
colour-space converted (optionally) and smooth

Issue 1.7 - February 8, 2000 7/48

GENERAL DESCRIPTION

scaled. Smooth interpolative scaling in both hori­zontal andvertical direction are implemented. Col­our and Chroma key functions are also imple­mented to allow mixing video stream with non-vid­eo frame buffer.

The video output passes directly to the RAMDAC
for monitor output or through another optional col­our space converter (RGB to 4:2:2 YCrCb) to the
programmable anti-flicker filter. The flicker filter is
configured as either a two line filter with gamma
correction (primarily designed for DOS type text)
or a 3 line flicker filter (primarily designed for Win­dows type displays). The flicker filter is optional
and can be software disabled for use with large
screen area’s of video.

The Video output pipeline of the STPC Client in­terfaces directly to the external digital TV encoder
(STV0119). It takes a 24 bit RGB non-interlaced
pixel stream and converts to a multiplexed 4:2:2
YCrCb 8 bit output stream, the logic includes a
progressive to interlaced scan converter and logic
to insert appropriate CCIR656 timing reference
codes into the output stream. It facilitates the high
quality display of VGA or full screen video streams
received via the Video input port to standard
NTSC or PAL televisions.

The STPC Client core is compliant with the Ad­vanced Power Management (APM) specification
to provide a standard method by which the BIOS
can control the power used by personal comput­ers. The Power Management Unit module (PMU)
controls the power consumption by providing a
comprehensive set of features that control the
power usage and supports compliance with the
United States Environmental Protection Agency’s
Energy Star Computer Program. The PMU pro­vides following hardware structures to assist the
software in managing the power consumption by
the system.

- System Activity Detection.

- 3 power-down timers detecting system inactivity:

by state.

- Peripheral activity detection.

- Peripheral timer detecting peripheralinactivity

- SUSP# modulation to adjust the system per­formance in various power down states of the sys­tem including full power on state.

- Power control outputs to disable power from dif­ferent planes of the board.

Lack of system activity for progressively longer
period of times is detected by the three power
down timers. These timers can generate SMI in­terrupts to CPU so that the SMM software can put
the system in decreasing states of power con­sumption. Alternatively, system activity in a power
down state can generate SMI interrupt to allow the
software to bring the system back up to full power
on state. The chip-set supports up to three power
down states: Doze state, Stand-by state and Sus­pend mode. These correspond to decreasing lev­els of power savings.

Power down puts the STPC Client into suspend
mode. The processor completes execution of the
current instruction, any pending decoded instruc­tions and associated bus cycles. During the sus­pend mode, internal clocks are stopped. remov­ing power down, the processor resumes instruc­tion fetching and begins execution in the instruc­tion stream at the point it had stopped.

A reference design for the STPC Client is availa­ble including the schematics and layout files, the
design is a PC ATX motherboard design. The de­sign is available as a demonstration board for ap­plication and system development.

The STPC Client is supported by several BIOS
vendors, including the super I/O device used in
the reference design. Drivers for 2D accelerator,
video features and EIDE are available on various
operating systems.

- Doze timer (short durations).

- Stand-by timer (medium durations).

- Suspend timer (long durations).

The STPC Client has been designed using mod­ern reusable modular design techniques, it is pos­sible to add to or remove the standard features of
the STPC Client or other variants of the 5ST86

- House-keeping activity detection.

family. Contact your local STMicroelectonicssales
office for further information.

- House-keeping timer to cope with short bursts

of house-keeping activity while dozing or in stand-

8/48 Issue 1.7 - February 8, 2000

Figure 1-1. Functional description.

x86

Core

GENERAL DESCRIPTION

Host I/F

PCI m/s

VIP

ISA

PCI m/s

IPC

EIDE

ISA BUS

EIDE

PCI BUS

CCIR Input

DRAM

Video

pipeline

2D

SVGA
CRTC

TV Output

Anti-Flicker

Colour

Key

Chroma

HW Cursor

Issue 1.7 - February 8, 2000 9/48

Colour Space

Monitor

SYNC Output

GENERAL DESCRIPTION

Figure 1-2. Pictorial Block Diagram Typical Application

Super I/O

Keyboard / Mouse
Serial Ports
Parallel Port

ISA

MUX

MUX

DMUX

RTC

Flash

IRQ

DMA.REQ

STPC Client

DMA.ACK

Floppy

2x EIDE

DMUX

Monitor

SVGA

TV

S-VHS
RGB
PAL
NTSC

STV0119

PCI

4x 16-bit EDO DRAMs

10/48 Issue 1.7 - February 8, 2000

Video

CCIR601
CCIR656

2.PIN DESCRIPTION

PIN DESCRIPTION

2.1. INTRODUCTION

The STPC Client integrates most of the functional­ities of the PC architecture. As a result, many of
the traditional interconnections between the host
PC microprocessor and the peripheral devices are
totally assimilated to the STPC Client. This offers
improved performance due to the tight coupling of
the processor core and its peripherals. As a result
many of the external pin connections are made di­rectly to the on-chip peripheral functions.

Figure 2-1 shows the STPC Client’s external inter­faces. It defines the main busses and their func­tion. Table 2-1 describes the physical implementa­tion listing signals type and their functionality. Ta­ble 2-2 provides afull pin listing and description of
the pins. Table 2-3 provides a full listing of pin lo­cations of the STPC Client package by physical
connection. Please refer to the pin allocation
drawing for reference.

Figure 2-1. STPC Client External Interfaces

Table 2-1. Signal Description

Group name Qty

Basic Clocks reset & Xtal (SYS) 14
Memory Interface (DRAM) 89
PCI interface (excluding VDD5) 54
ISA / IDE / IPC combined interface 83
Video Input (VIP) 9
TV Output (TV) 10
VGA Monitor interface (VGA) 10
Grounds 69
V

DD

Analog specific V
Reserved/Test/ Misc./ Speaker 10
Total Pin Count 388

CC/VDD

26
14

Note: Several interface pins are multiplexed with
other functions, refer to the Pin Description sec­tion for further details

X86

STPC CLIENT

SOUTHNORTH PCI

DRAM VGA VIP TV SYS ISA/IDE IPC

89 10 9 10 54

14

73 10

Issue 1.7 - February 8, 2000 11/48

PIN DESCRIPTION

Table 2-2. Definition of Signal Pins

Signal Name Dir Description Qty

BASIC CLOCKS RESETS & XTAL

SYSRSTI# I System Reset / Power good 1
SYSRSTO#* O Reset Output to System 1
XTALI I 14.3MHz External Oscillator Input 1
XTALO I/O 14.3MHz External Oscillator Input 1
PCI_CLKI I 33MHz PCI Input Clock 1
PCI_CLKO O 33MHz PCI Output Clock (from internal PLL) 1
ISA_CLK O ISA Clock Output - Multiplexer Select Line For IPC 1
ISA_CLK2X O ISA Clock x 2 Output - Multiplexer Select Line For IPC 1
OSC14M* O ISA bus synchronisation clock 1
HCLK* O Host Clock (Test) 1
DEV_CLK O 24MHz Peripheral Clock (floppy drive) 1
GCLK2X* I/O 80MHz Graphics Clock 1
DCLK* I/O 135MHz Dot Clock 1
DCLK _DIR* I Dot Clock Direction 1
V

_xxx_PLL Power Supply for PLL Clocks

DD

MEMORY INTERFACE

MA[11:0]* I/O Memory Address 12
RAS#[3:0] O Row Address Strobe 4
CAS#[7:0] O Column Address Strobe 8
MWE# O Write Enable 1
MD[63:0]* I/O Memory Data 64

PCI INTERFACE

AD[31:0]* I/O PCI Address / Data 32
CBE[3:0]* I/O Bus Commands / Byte Enables 4
FRAME#* I/O Cycle Frame 1
TRDY#* I/O Target Ready 1
IRDY#* I/O Initiator Ready 1
STOP#* I/O Stop Transaction 1
DEVSEL#* I/O Device Select 1
PAR* I/O Parity Signal Transactions 1
SERR#* O System Error 1
LOCK# I PCI Lock 1
PCI_REQ#[2:0]* I PCI Request 3
PCI_GNT#[2:0]* O PCI Grant 3
PCI_INT[3:0]* I PCI Interrupt Request 4
VDD5 I 5V Power Supply for PCI ESD protection 4

ISA AND IDE COMBINED ADDRESS/DATA

LA[23:22]*/ SCS3#,SCS1# I/O Unlatched Address (ISA) / Secondary Chip Select (IDE) 2
LA[21:20]*/ PCS3#,PCS1# I/O Unlatched Address (ISA) / Primary Chip Select (IDE) 2
LA[19:17]*/ DA[2:0] O Unlatched Address (ISA) / Address (IDE) 3
RMRTCCS#* / DD[15] I/O ROM/RTC Chip Select / Data Bus bit 15 (IDE) 1
KBCS#* / DD[14] I/O Keyboard Chip Select / Data Bus bit 14 (IDE) 1

Note; * denotes theat the pin is V5T(see Section 4. )

12/48 Issue 1.7 - February 8, 2000

PIN DESCRIPTION

Table 2-2. Definition of Signal Pins

Signal Name Dir Descripti on Qty

RTCRW#* / DD[13] I/O RTC Read/Write / Data Bus bit 13 (IDE) 1
RTCDS#* / DD[12] I/O RTC Data Strobe / Data Bus bit 12 (IDE) 1
SA[19:8]* / DD[11:0] I/O Latched Address (ISA) / Data Bus (IDE) 16
SA[7:0] I/O Latched Address (IDE) 4
SD[15:0]* I/O Data Bus (ISA) 16

ISA/IDE COMBINED CONTROL

IOCHRDY* / DIORDY I/O I/O Channel Ready (ISA) - Busy/Ready (IDE) 1

ISA CONTROL

ALE* O Address Latch Enable 1
BHE#* I/O System Bus High Enable 1
MEMR#*, MEMW#* I/O Memory Read and Memory Write 2
SMEMR#*, SMEMW#* O System Memory Read and Memory Write 2
IOR#*, IOW#* I/O I/O Read and Write 2
MASTER#* I Add On Card Owns Bus 1
MCS16#*, IOCS16#* I Memory/IO Chip Select16 2
REF#* O Refresh Cycle. 1
AEN* O Address Enable 1
IOCHCK#* I I/O Channel Check. 1
ISAOE#* O Bidirectional OE Control 1
GPIOCS#* I/O General Purpose Chip Select 1

IDE CONTROL

PIRQ* I Primary Interrupt Request 1
SIRQ* I Secondary Interrupt Request 1
PDRQ* I Primary DMA Request 1
SDRQ* I Secondary DMA Request 1
PDACK#* O Primary DMA Acknowledge 1
SDACK#* O Secondary DMA Acknowledge 1
PIOR#* I/O Primary I/O Read 1
PIOW#* O Primary I/O Write 1
SIOR#* I/O Secondary I/O Read 1
SIOW#* O Secondary I/O Write 1

IPC

IRQ_MUX[3:0]* I Multiplexed Interrupt Request 4
DREQ_MUX[1:0]* I Multiplexed DMA Request 2
DACK_ENC[2:0]* O DMA Acknowledge 3
TC* O ISA Terminal Count 1

MONITOR INTERFACE

RED, GREEN, BLUE O Red, Green, Blue 3
VSYNC* O Vertical Synchronization 1
HSYNC* O Horizontal Synchronization 1
VREF_DAC I DAC Voltage reference 1
RSET I Resistor Set 1
COMP I Compensation 1
SCL / D DC[1]* I/O I C Interfa ce - Clock / Can be used fo r VGA DDC[1] s ignal 1

Note; * denotes theat the pin is V5T(see Section 4. )

Issue 1.7 - February 8, 2000 13/48

PIN DESCRIPTION

Table 2-2. Definition of Signal Pins

Signal Name Dir Descripti on Qty

SDA / DDC[0 ]* I/O I C Interfa ce - Data / Can be used fo r VG A DDC[0] signal 1

VIDEO INPUT

VCLK* I Pixel Clock 1
VIN[7:0 ]* I YUV Video Da ta Input CCIR 601 or 656 8

DIGITAL TV OUTPUT

TV_YUV [7:0] * O Digital Video Output s 8
ODD_EVEN* O Frame Sy nchronisation 1
VCS* O Hor izontal Line Synchronisation 1

MISCEL LANE OUS

ST[6:0] I/O Test/Misc. pins 7
CLKDEL[2:0]* I/O Reserved (Test/Misc pins) 3

Note; * denotes theat the pin is V5T(see Section 4. )

14/48 Issue 1.7 - February 8, 2000

PIN DESCRIPTION

2.2.SIGNAL DESCRIPTIONS

2.2.1. BASIC CLOCKS RESETS & XTAL

PWGD

low when the reset switch is depressed. Other­wise, it reflects the power supply’s power good
signal. PWGD is asynchronous to all clocks, and
acts as a negative active reset. The reset circuit
initiates a hard reset on the rising edge of PWGD.

XTALI
XTALO

pins are the 14.318 MHz external oscillator input;
This clock is used as thereference clock for the in­ternal frequency synthesizer to generate the
HCLK, CLK24M, GCLK2X and DCLK clocks.

HCLK

frequency can vary from 25 to 75 MHz. All host
transactions and PCI transactions are synchro­nized to this clock. This clock drives the DRAM
controller to execute the host transactions. In nor­mal mode, this output clock is generated by the in­ternal PLL.

GCLK2X

Graphics 2X clock, which drives the graphics en­gine and the DRAM controller to execute the
graphics and display cycles.
Normally GCLK2X is generated by the internal fre­quency synthesizer, and this pin is an output. By
setting a bit in Strap Register 2, this pin can be
made an input so that an external clock can re­place the internal frequency synthesizer.

DCLK

which drivesgraphicsdisplay cycles. Its frequency
can go from 8MHz (using internal PLL) up to 135
MHz, and it is required to have a worst case duty
cycle of 60-40.

System Reset/Power good.

This input is

14.3MHz Pull Down (10 kΩ)

14.3MHz External Oscillator Input

Host Clock.

80MHz Graphics Clock.

135MHz Dot Clock.

This is the host 1X clock. Its

This is the

This is the dot clock,

These

these signals can be adjusted by software to
match the timings of most DRAM modules.

MD[63:0]

memory data bus. If only half of a bank is populat­ed, MD63-32 is pulled high, data is on MD31-0.
MD[40-0] are read by the device strap option reg­isters during rising edge of PWGD.

RAS#[3:0]

are 4 active low row address strobe outputs, one
for each bank of the memory. Each bank contains
4 or 8-Bytes of data. The memorycontroller allows
half of a bank (4 Bytes) to be populated to enable
memory upgrade at finer granularity.
The RAS# signals drive the SIMMs directly with­out any external buffering. These pins are always
outputs, but they can also simultaneously be in­puts, to allow the memory controller to monitor the
value of the RAS# signals at the pins.

CAS#[7:0]

are 8 active low column address strobe outputs,
one for each Byte of the memory.
The CAS# signals drive the SIMMs either directly
or through external buffers.
These pins are always outputs, but they can also
simultaneously be inputs, to allow the memory
controller to monitor the value of the CAS# signals
at the pins.

MWE#

fies whether the memory access is a read (MWE#
= H) or a write (MWE# = L). This single write ena­ble controls all DRAMs. It can be externally buff­ered to boost the maximum number of loads
(DRAM chips) supported.
The MWE# signals drive the SIMMs directly with­out any external buffering.

Memory Data I/O.

This is the 64-bit

Row Address Strobe Output.

Column AddressStrobe Output.

Write Enable Output.

Write enable speci-

There

There

2.2.3. VIDEO INPUT

DCLK_DIR

is an input (0) or an output (1).

DEV_CLK

24MHZ signal is provided as a convenience for
the system integration of a floppy disk driver func­tion in an external chip.

Dot ClockDirection.

Specifies if DCLK

24MHz Peripheral Clock Output.

This

2.2.2. MEMORY INTERFACE

MA[11:0]

tiplexed memory address pins support external
DRAM with up to 4K refresh. These include all
16M x N and some 4M x N DRAM modules. The
address signals must be externally buffered to
support more than 16 DRAM chips. The timing of

Memory Address Output.

These 12 mul-

Issue 1.7 - February 8, 2000 15/48

VCLK

Pixel Clock Input.

VIN[7:0]

Time multiplexed 4:2:2 luminance and chromi­nance data as defined in ITU-R Rec601-2 and
Rec656 (except for TTL input levels). This bus in­terfaces with an MPEG video decoder output port
and typically carries a stream ofCb, Y, Cr, Y digit­al video at VCLK frequency, clocked on the rising
edge (by default) of VCLK. A 54-Mbit/s ‘double’
Cb, Y, Cr, Y input multiplex is supported for double
encoding applications (rising and falling edge of
CKREF are operating).

YUV Video Data Input CCIR 601 or 656.

2.2.4. TV OUTPUT

TV_YUV[7:0]

Digital video outputs.

PIN DESCRIPTION

ODD_EVEN
VCS

Horizontal Line Synchronization

Frame Synchronization

.

.

2.2.5. PCI INTERFACE

PCI_CLKI

the PCI bus clock input and should be driven from
the PCI_CLKO pin.

PCI_CLKO

master PCI bus clock output.

AD[31:0]

multiplexed address and data bus. This bus is
driven by the master during the address phase
and data phase of write transactions. It is driven
by the target during data phase of read transac­tions.

CBE#[3:0]

are the multiplexed command and Byte enable
signals of the PCI bus. During the address phase
they define the command and during the data
phase they carry the Byte enable information.
These pins are inputs when a PCI master other
than the STPC Client owns the bus and outputs
when the STPC Client owns the bus.

FRAME#

the PCIbus. It is an input when a PCI master owns
the bus and is an output when STPC Client owns
the PCI bus.

TRDY#

nal of the PCI bus. It is driven as an output when
the STPC Client is the target of the current bus
transaction. It is used as an input when STPC Cli­ent initiates a cycle on the PCI bus.

IRDY#

signal of the PCI bus. It is used as an output when
the STPC Client initiates a bus cycle on the PCI
bus. It is used as an input during the PCI cycles
targeted to theSTPC Client to determine when the
current PCI master is ready to complete the cur­rent transaction.

STOP#

ment the disconnect, retry and abort protocol of
the PCI bus. It is used as an input for the bus cy­cles initiated by the STPC Client and is used as an
output when a PCI master cycle is targeted to the
STPC Client.

DEVSEL#

as an input when the STPC Client initiates a bus

33MHz PCI Input Clock

33MHz PCI Output Clock.

PCI Address/Data.

This isthe 32-bit PCI

Bus Commands/Byte Enables.

Cycle Frame.

Target Ready.

Initiator Ready.

Stop Transaction.

I/O Device Select.

This is the frame signal of

This is the target ready sig-

This is the initiator ready

Stop is used to imple-

This signal is used

This signal is

This is the

These

cycle on the PCI bus to determine if a PCI slave
device has decoded itself to be the target of the
current transaction. It is asserted as an output ei­ther when the STPC Client is the target ofthe cur­rent PCI transaction or when no other device as­serts DEVSEL# prior to the subtractive decode
phase of the current PCI transaction.

PAR

Parity Signal Transactions.

signal of the PCI bus. This signal is used to guar­antee even parity across AD[31:0], CBE#[3:0],
and PAR. This signal is driven by the master dur­ing the address phase and data phase of write
transactions. It is driven by the target during data
phase of read transactions. (Its assertion is identi­cal to that of the AD bus delayed by one PCI clock
cycle)

SERR#

nal of the PCI bus. It may, if enabled, be asserted
for one PCI clock cycle if the target aborts an
STPC Client initiated PCItransaction. Its assertion
by either the STPC Client or by another PCI bus
agent will trigger the assertion of NMI to the host
CPU. This is an open drain output.

LOCK#

bus and is used to implement the exclusive bus
operations when acting as a PCI target agent.

PCI_REQ#[2:0]

three external PCI master request pins. They indi­cate to the PCI arbiter that the external agents re­quire use of the bus.

PCI_GNT#[2:0]

that the PCI bus has been granted master, re­questing it on its PCI_REQ#.

System Error.

PCI Lock.

This is the lock signalof the PCI

PCI Request.

PCI Grant.

This is the system error sig-

This is the parity

These pins are the

These pins indicate

2.2.6. ISA/IDE COMBINED ADDRESS/DATA

LA[23]/SCS3#

ondary Chip Select (IDE).

tions, depending on whether the ISA bus is active
or the IDE bus is active.
When the ISA bus is active, this pins is ISA Bus
unlatched address bit 23 for 16-bit devices. When
ISA bus is accessed by any cycle initiated from
PCI bus, this pin is in output mode. When an ISA
bus master owns the bus, this pins is in input
mode.
When the IDE bus is active, this signals is used as
the active high secondary slave IDE chip select
signal. This signal is to be externally NANDed with
the ISAOE# signal before driving the IDE devices
to guarantee it is active only when ISA bus is idle.

Unlatched Address (ISA) / Sec-

This pin has two func-

16/48 Issue 1.7 - February 8, 2000

PIN DESCRIPTION

LA[22]/SCS1#

ondary Chip Select (IDE)

tions, depending on whether the ISA bus is active
or the IDE bus isactive.
When the ISA bus is active, this pin is ISA bus un­latched address bit 22 for 16-bit devices. When
ISA bus is accessed by any cycle initiated from
PCI bus, this pin is in output mode. When an ISA
bus masterowns the bus, this pin is in input mode.

When the IDE bus is active, this signal is used as
the active high secondary slave IDE chip select
signal. This signal is to be externally ANDed with
the ISAOE# signal before driving the IDE devices
to guarantee it is active only when ISA bus is idle.

LA[21]/PCS3#

Chip Select (IDE).

pending on whether the ISA bus is active or the
IDE bus is active.
When the ISA bus isactive, this pin is ISA Bus un­latched address bit 21 for 16-bit devices. When
ISA bus is accessed by any cycle initiated from
PCI bus, this pin is in output mode. When an ISA
bus masterowns the bus, this pin is in input mode.
When the IDE bus is active, this signas is used as
the active high primary slave IDE chip select sig­nal. This signal is to be externally NANDed with
the ISAOE# signal before driving the IDE devices
to guarantee it is active only when ISA bus is idle.

LA[20]/PCS1#

Chip Select (IDE).

pending on whether the ISA bus is active or the
IDE bus is active.
When the ISA bus isactive, this pin is ISA Bus un­latched address bit 20 for 16-bit devices. When
the ISAbus isaccessed by any cycle initiated from
PCI bus, this pin is in output mode. When an ISA
bus masterowns the bus, this pin is in input mode.

When the IDE bus is active, this signalsis usedas
the active high primary slave IDE chip select sig­nal. This signal is to be externally NANDed with
the ISAOE# signal before driving the IDE devices
to guarantee it is active only when ISA bus is idle.

LA[19:17]/DA[2:0]

dress (IDE).

They are used as the ISA bus unlatched address
bits [19:17] for ISA bus or the three address bits
for the IDE bus devices.
When used by theISA bus,these pins are ISAbus
unlatched address bits 19-17 on 16-bit devices.
When the ISA bus is accessed by any cycle initiat­ed from the PCI bus, these pins are in output
mode. When an ISA bus master owns the bus,
these pins are tristated.

Unlatched Address (ISA) / Sec-

This pin has two func-

Unlatched Address (ISA) / Primary

This pin has two functions, de-

Unlatched Address (ISA) / Primary

This pin has two functions, de-

Unlatched Address (ISA) / Ad-

These pins are multi-function pins.

For IDE devices, these signals are used as the
DA[2:0] and are connected directly or through a
buffer to DA[2:0] of the IDE devices. If the toggling
of signals are to be masked during ISA bus cycles,
they can be externally ORed before being con­nected to the IDE devices.

SA[19:8]/DD[11:0]

Data Bus (IDE).

When the ISA bus is active, they are used as the
ISA bus system address bits 19-8. When the IDE
bus is active, they serve as IDE signals DD[11:0].
These pins are used as an input when an ISA bus
master owns the bus and are outputs at all other
times.
IDE devices are connected to SA[19:8] directly
and the ISA bus is connected to these pins
through two LS245 transceivers. The transceiver
OEs are connected to ISAOE# and the DIR is con­nected to MASTER#. The transceiver bus signals
are connected to the CPC and IDE DD busses
and B bus signals are connected to ISA SA bus.

DD[15:12]

IDE databus are combined with several of the X­bus lines. Refer to the following section for X-bus
pins for further information.

SA[7:0]

8 low bits of the system address bus of ISA on 8­bit slot. These pins are used as an input when an
ISA bus master owns the bus and are outputs at
all other times.

SD[15:0]

external databus to the ISA bus.

Databus (IDE).

ISA Bus address bits [7:0].

I/O Data Bus (ISA).

Unlatched Address (ISA) /

These are multifunction pins.

The high 4 bits of the

These arethe

These pins are the

2.2.7. ISA/IDE COMBINED CONTROL

IOCHRDY/DIORDY

Ready (IDE).

the ISA bus is active, this pin is IOCHRDY. When
the IDE bus is active, this serves as IDE signal DI­ORDY.
IOCHRDY is the I/O channel ready signal of the
ISA bus and is driven as an output in response to
an ISA master cycle targeted to the host bus oran
internal register of the STPC Client. The STPC
Client monitors this signal as an input when per­forming an ISA cycle on behalf of the host CPU,
DMA master or refresh.
ISA masters which do not monitor IOCHRDY are
not guaranteed to workwith the STPC Client since
the access to the system memory can be consid­erably delayed due to CRT refresh or a write back
cycle.

Channel Ready (ISA)/ Busy /

This is a multi-function pin. When

Issue 1.7 - February 8, 2000 17/48

PIN DESCRIPTION

2.2.8. ISA CONTROL

SYSRSTO#

system reset signal and is usedto reset the rest of
the components (not on Host Bus) in the system.
The ISA bus reset is an externally inverted buff­ered version of this outputand the PCI bus reset is
an externally buffered version of this output.

ISA_CLK

lect Line For IPC).

signal for the ISA bus. It is also used with
ISA_CLK2X asthe multiplexor control lines for the
Interrupt Controller Interrupt input lines. This is a
divided down version of either the PCICLK or
OSC14M.

ISA_CLKX2

Select Line For IPC).

twice the frequency of the Clock signal for the ISA
bus. It is also used with ISA_CLK as the multiplex­or control lines for the Interrupt ControllerInterrupt
input lines.

OSC14M

This is the buffered 14.318 Mhz clock to the ISA
bus.

ALE

Address Latch Enable.

latch enable output of the ISA bus and is asserted
by the STPC Client to indicate that LA23-17,
SA19-0, AEN and SBHE# signals are valid. The
ALE is driven high during refresh, DMA master or
ISA master cycles by the STPC Client.
ALE is driven low after reset.

BHE#

asserted, indicates that a dataByte is being trans­ferred on SD15-8 lines. Itisused asan input when
an ISA master owns the bus andis an output at all
other times.

MEMR#

command signal of the ISA bus. It is used as an in­put when an ISA master owns the bus and is an
output at all other times.
The MEMR# signal is active during refresh.

MEMW#

command signal of the ISA bus. It is used as an in­put when an ISA master owns the bus and is an
output at all other times.

SMEMR#

ent generates SMEMR# signal of the ISA bus only
when the address is below 1MByte or the cycle is
a refresh cycle.

Reset Output to System.

This is the

ISA Clock Output (also Multiplexer Se-

This pin produces the Clock

ISA Clock Output (also Multiplexer

This pin produces a signal at

ISA Bus Synchronization Clock Output.

This is the address

System Bus High Enable.

Memory Read.

Memory Write.

This is the memory read

This is the memory write

System Memory Read.

This signal, when

The STPC Cli-

SMEMW#

ent generates SMEMW# signal of the ISA bus
only when the address is below 1MByte.

IOR#

nal of the ISA bus. It is an input when an ISA mas­ter owns the bus and is an output at all other
times.

IOW#

nal of the ISA bus. It is an input when an ISA mas­ter owns the bus and is an output at all other
times.

MASTER#

active when an ISA device has been granted bus
ownership.

MCS16#

code of LA23-17 address pins of the ISA address
bus without any qualification of the command sig­nal lines. MCS16# is always an input. The STPC
Client ignores this signal during I/O and refresh
cycles.

IOCS16#

code of SA15-0 address pins of the ISA address
bus without any qualification of the command sig­nals. The STPC Client does not drive IOCS16#
(similar to PC-AT design). An ISA master access
to an internal register of the STPC Client is exe­cuted as an extended 8-bit I/O cycle.

REF#

signal of the ISA bus. It is driven as an output
when the STPC Client performs a refresh cycle on
the ISA bus. It is used as an input when an ISA
master owns the bus and is used to trigger a re­fresh cycle.
The STPC Client performs a pseudo hidden re­fresh. It requests the host bus for two host clocks
to drive the refresh address and captureit in exter­nal buffers. The host bus is then relinquished
while the refresh cycle continues on the ISA bus.

AEN

when the DMA controller is the bus owner to indi­cate that a DMA transfer will occur. The enabling
of the signal indicates to I/O devices to ignore the
IOR#/IOW# signal during DMA transfers.

IOCHCK#

is enabled by any ISA device to signal an error
condition that can not be corrected.NMIsignal be­comes active upon seeing IOCHCK# active if the
corresponding bit in Port B is enabled.

System Memory Write.

I/O Read.

I/O Write.

This is the I/O read command sig-

This is theI/O writecommand sig-

Add On CardOwns Bus.

Memory Chip Select 16.

I/O Chip Select 16.

Refresh Cycle.

Address Enable.

This is the refresh command

Address Enable is enabled

I/O Channel Check.

The STPC Cli-

This signal is

This is the de-

This signal is thede-

I/O Channel Check

18/48 Issue 1.7 - February 8, 2000

PIN DESCRIPTION

ISAOE#

trols the OE signal of the external transceiver that
connects the IDE DD bus and ISA SA bus.

GPIOCS#

This output signal is used by the external latch on
ISA bus to latch the data on the SD[7:0] bus. The
latch can be used by the PMU unit to control the
external peripheral devices to power down or any
other desired function.
This pin is also serves as a strap input during re­set.

Bidirectional OE Control.

This signal con-

I/O General Purpose Chip Select 1.

2.2.9. IDE CONTROL

PIRQ

Primary Interrupt Request.

from primary IDE channel.

SIRQ

Secondary Interrupt Request.

quest from secondary IDE channel.

PDRQ

primary IDE channel.

SDRQ

from secondary IDE channel.

PDACK#

knowledge to primary IDE channel.

SDACK#

acknowledge to secondary IDE channel.

PIOR#

Active low output.

PIOW#

Active low output.

SIOR#

read. Active low output.

SIOW#

write. Active low output.

Primary DMA Request.

Secondary DMA Request.

Primary DMA Acknowledge.

Secondary DMA Acknowledge.

Primary I/O Read.

Primary I/O Write

. Primary channel write.

Secondary I/O Read

Secondary I/O Write.

Interrupt request

Interrupt re-

DMA request from

DMA request

DMA ac-

DMA

Primary channel read.

. Secondary channel

Secondary channel

2.2.10. X-BUS INTERFACE PINS / IDE DATA

RMRTCCS# / DD[15]

Select.

ISAOE# is active, this signal is used as RM­RTCCS#. This signal is asserted if a ROM access
is decoded during a memory cycle. It should be
combined with MEMR# or MEMW# signals to
properly access the ROM. During an I/O cycle,
this signal is asserted if access to the Real Time
Clock (RTC) is decoded. It should be combined
with IOR#+ or IOW# signals to properly access the
real time clock.
When ISAOE# is inactive, this signal is used as

This pin is a multi-function pin. When

ROM/Real Time Clock Chip

IDE DD[15] signal.
This signal must be ORed externally with ISAOE#
and is then connected to ROM and RTC. An
LS244 or equivalent function canbe used if OE# is
connected to ISAOE# and the output is provided
with a weak pull-up resistor.

KBCS# / DD[14]

is a multi-function pin. When ISAOE# is active,
this signal is used as KBCS#. This signal is assert­ed if a keyboard access is decoded during a I/O
cycle.
When ISAOE# is inactive, this signal is used as
IDE DD[14] signal.
This signal must be ORed externally with ISAOE#
and is then connected to the keyboard. An LS244
or equivalent function can be used if OE# is con­nected to ISAOE# and the output is provided with
a weak pull-up resistor.

RTCRW# / DD[13]

is a multi-function pin. When ISAOE# is active,
this signal is used as RTCRW#. This signal is as­serted for any I/O write to port 71H.
When ISAOE# is inactive, this signal is used as
IDE DD[13] signal.
This signal must be ORed externally with ISAOE#
and then connected to the RTC. An LS244 or
equivalent function can be usedif OE# is connect­ed to ISAOE# and the output is provided with a
weak pull-up resistor.

RTCDS# / DD[12]

a multi-function pin. When ISAOE# is active, this
signal is used as RTCDS. This signal is asserted
for any I/O read to port 71H.
When ISAOE# is inactive, this signal is used as
IDE DD[12] signal.
This signal must be ORed externally with ISAOE#
and is then connected to RTC. An LS244 or equiv­alent function can be used if OE# is connected to
ISAOE# and the output is provided with a weak
pull-up resistor.

Keyboard Chip Select.

Real Time Clock RW.

Real Time Clock DS

. This pin is

This pin

This pin

2.2.11. IPC

IRQ_MUX[3:0]

These are the ISA bus interrupt signals. They are
to be encoded before connection tothe STPC Cli­ent using ISACLK and ISACLKX2 as the input se­lection strobes.
Note that IRQ8B, which by convention is connect­ed to the RTC, is inverted before being sentto the
interrupt controller, so that it may be connected di­rectly to the IRQ pin of the RTC.

PCI_INT[3:0]

the PCI bus interrupt signals. They are to be en­coded before connection to the STPC Client using

Multiplexed Interrupt Request.

PCI Interrupt Request.

These are

Issue 1.7 - February 8, 2000 19/48

PIN DESCRIPTION

ISACLK and ISACLKX2 as the input selection
strobes.

DREQ_MUX[1:0]

quest.

nals. Theyare to be encoded before connectionto
the STPC Client using ISACLK and ISACLKX2 as
the input selection strobes.

DACK_ENC[2:0]

the ISA bus DMA acknowledge signals. They are
encoded by the STPC Client before output and
should be decoded externally using ISACLK and
ISACLKX2 as the control strobes.

TC

output of the DMA controller and is connected to
the TCline of the ISA bus. It isasserted during the
last DMA transfer, when the Byte count expires.

These are the ISA bus DMA request sig-

ISA Terminal Count.

ISA Bus Multiplexed DMA Re-

DMA Acknowledge.

This is the terminal count

These are

2.2.12. MONITOR INTERFACE

RED, GREEN, BLUE

are the 3 analog coloroutputs from the RAMDACs

VSYNC

the vertical synchronization signal from the VGA
controller.

HSYNC

the horizontal synchronization signal from the
VGA controller.

Vertical Synchronization Pulse.

Horizontal Synchronization Pulse.

RGB Video Outputs.

These

This is

This is

RSET

rent input to the RAMDAC is used to set the full­scale output of the RAMDAC.

COMP

pensation pin. Normally, an external capacitor
(typically 10nF) is connected between this pin and
VDDto damp oscillations.

DDC[1:0]

bidirectional pins are connected to CRTC register
3Fh to implement DDC capabilities. They conform
to I2C electrical specifications, they have open­collector output drivers which are internally con­nected to VDDthrough pull-up resistors.

They can instead be used for accessing I C devic­es onboard. DDC1 and DDC0 correspond toSCL
and SDA respectively.

Resistor Current Set.

Compensation.

This reference cur-

This is the RAMDAC com-

Direct Data Channel Serial Link.

These

2.2.13. MISCELLANEOUS

ST[6],
ST[5] This is used for speaker output.
ST[4]
ST[3:0] The pins are for testing the STPC. The

default settings on these pins should be 1111 for
the STPC to function correctly. By setting the
ST[3:0] to 0111, the STPC is tristated.

Reserved.

Reserved.

VREF_DAC

voltage reference is connected to this pin to bias
the DAC.

DAC Voltage reference.

An external

CLKDEL[2:0]

for Test and Miscellaneous functions)

Reserved

. The pins are reserved

20/48 Issue 1.7 - February 8, 2000

PIN DESCRIPTION

Table 2-3. Pinout.

Pin # Pin name

AF3 PWGD
AF15 XTALI
AE16 XTALO
G23 HCLK
F25 DEV_CLK
AC5 GCLK2X
AD5 DCLK
AF5 DCLK_DIR
AD15 MA[0]
AF16 MA[1]
AC15 MA[2]
AE17 MA[3]
AD16 MA[4]
AF17 MA[5]
AC17 MA[6]
AE18 MA[7]
AD17 MA[8]
AF18 MA[9]
AE19 MA[10]
AF19 MA[11]
AD18 RAS#[0]
AE20 RAS#[1]
AC19 RAS#[2]
AF20 RAS#[3]
AE21 CAS#[0]
AC20 CAS#[1]
AF21 CAS#[2]
AD20 CAS#[3]
AE22 CAS#[4]
AF22 CAS#[5]
AD21 CAS#[6]
AE23 CAS#[7]
AC22 MWE#
AF23 MD[0]
AE24 MD[1]
AF24 MD[2]
AD25 MD[3]
AC25 MD[4]
AC26 MD[5]
AB24 MD[6]
AA25 MD[7]
AA24 MD[8]
Y25 MD[9]
Y24 MD[10]
V23 MD[11]
W24 MD[12]
V26 MD[13]
V24 MD[14]

Pin # Pin name

U23 MD[15]
U24 MD[16]
R26 MD[17]
P25 MD[18]
P26 MD[19]
N25 MD[20]
N26 MD[21]
M25 MD[22]
M26 MD[23]
M24 MD[24]
M23 MD[25]
L24 MD[26]
J25 MD[27]
J26 MD[28]
H26 MD[29]
G25 MD[30]
G26 MD[31]
AD22 MD[32]
AD23 MD[33]
AE26 MD[34]
AD26 MD[35]
AC24 MD[36]
AB25 MD[37]
AB26 MD[38]
Y23 MD[39]
AA26 MD[40]
Y26 MD[41]
W25 MD[42]
W26 MD[43]
V25 MD[44]
U25 MD[45]
U26 MD[46]
T25 MD[47]
R25 MD[48]
T24 MD[49]
R23 MD[50]
R24 MD[51]
N23 MD[52]
P24 MD[53]
N24 MD[54]
L25 MD[55]
L26 MD[56]
K25 MD[57]
K26 MD[58]
K24 MD[59]
H25 MD[60]
J24 MD[61]
H23 MD[62]
H24 MD[63]

Pin # Pin name

F24 PCI_CLKI
D25 PCI_CLKO
A20 AD[0]
C20 AD[1]
B19 AD[2]
A19 AD[3]
C19 AD[4]
B18 AD[5]
A18 AD[6]
B17 AD[7]
C18 AD[8]
A17 AD[9]
D17 AD[10]
B16 AD[11]
C17 AD[12]
B15 AD[13]
A15 AD[14]
C16 AD[15]
D15 AD[16]
A14 AD[17]
C15 AD[18]
B13 AD[19]
D13 AD[20]
A13 AD[21]
C14 AD[22]
C13 AD[23]
A12 AD[24]
B11 AD[25]
C12 AD[26]
A11 AD[27]
D12 AD[28]
B10 AD[29]
C11 AD[30]
A10 AD[31]
D10 CBE[0]
C10 CBE[1]
A9 CBE[2]
B8 CBE[3]
A8 FRAME#
B7 TRDY#
D8 IRDY#
A7 STOP#
C8 DEVSEL#
B6 PAR
D7 SERR#
A6 LOCK#
C21 PCI_REQ#[0]
A21 PCI_REQ#[1]
B20 PCI_REQ#[2]

Issue 1.7 - February 8, 2000 21/48

PIN DESCRIPTION

Pin # Pin name

C22 PCI_GNT#[0]
B21 PCI_GNT#[1]
D20 PCI_GNT#[2]
D24 PCI_INT[0]
C26 PCI_INT[1]
A25 PCI_INT[2]
B24 PCI_INT[3]

F2 LA[17]/DA[0]
G4 LA[18]/DA[1]
F3 LA[19]/DA[2]
F1 LA[20]/PCS1#
G2 LA[21]/PCS3#
G3 LA[22]/SCS1#
H2 LA[23]/SCS3#
J4 SA[0]
H1 SA[1]
H3 SA[2]
J2 SA[3]
J1 SA[4]
K2 SA[5]
J3 SA[6]
K1 SA[7]
K4 SA[8]/DD[0]
L2 SA[9]/DD[1]
K3 SA[10]/DD[2]
L1 SA[11]/DD[3]
M2 SA[12] / DD[4]
M1 SA[13] / DD[5]
L3 SA[14] / DD[6]
N2 SA[15] / DD[7]
M4 SA[16] / DD[8]
N1 SA[17] / DD[9]
M3 SA[18] / DD[10]
P4 SA[19] / DD[11]
P3 RTCDS / DD[12]
R2 RTCRW# / DD[13]
N3 KBCS# / DD[14]
P1 RMRTCCS# / DD[15]
R1 SD[0]
T2 SD[1]
R3 SD[2]
T1 SD[3]
R4 SD[4]
U2 SD[5]
T3 SD[6]
U1 SD[7]
U4 SD[8]
V2 SD[9]

Pin # Pin name

U3 SD[10]
V1 SD[11]
W2 SD[12]
W1 SD[13]
V3 SD[14]
Y2 SD[15]
AE4 SYSRSTO#
AD4 ISA_CLK
AE5 ISA_CLK2X
C6 OSC14M
W3 ALE
AA2 BHE#
Y4 MEMR#
AA1 MEMW#
Y3 SMEMR#
AB2 SMEMW#
AA3 IOR#
AC2 IOW#
AB4 MASTER#
AC1 MCS16#
AB3 IOCS16#
AD2 REF#
AC3 AEN
AD1 IOCHCK#
AF2 ISAOE#
AE3 GPIOCS#
Y1 IOCHRDY

B1 PIRQ
C2 SIRQ
C1 PDRQ
D2 SDRQ
D3 PDACK#
D1 SDACK#
E2 PIOR#
E4 PIOW#
E3 SIOR#
E1 SIOW#

E23 IRQ_MUX[0]
D26 IRQ_MUX[1]
E24 IRQ_MUX[2]
C25 IRQ_MUX[3]
A24 DREQ_MUX[0]
B23 DREQ_MUX[1]
C23 DACK_ENC[0]
A23 DACK_ENC[1]
B22 DACK_ENC[2]
D22 TC

Pin # Pin name

AE6 RED
AD6 GREEN
AF6 BLUE
AE9 VSYNC
AF9 HSYNC
AD7 VREF_DAC
AE8 RSET
AC9 COMP
AF8 DDC[1] / SCL
AD8 DDC[0] / SDA

AD14 VCLK
AE13 VIN[0]
AC12 VIN[1]
AD12 VIN[2]
AE14 VIN[3]
AC14 VIN[4]
AF14 VIN[5]
AD13 VIN[6]
AE15 VIN[7]

AF10 VTV_YUV[0]
AC10 VTV_YUV[1]
AE11 VTV_YUV[2]
AD10 VTV_YUV[3]
AF11 VTV_YUV[4]
AE12 VTV_YUV[5]
AF12 VTV_YUV[6]
AD11 VTV_YUV[7]
AE10 VCS
AD9 ODD_EVEN

B4 ST[0]
D5 ST[1]
A4 ST[2]
C5 ST[3]
B3 ST[4]
C4 ST[5]
A3 ST[6]
C7 CLKDEL[0]
B5 CLKDEL[1]
A5 CLKDEL[2]

AC7 VDD_DAC1
AF4 VDD_DAC2
W4 VDD_GCLK_PLL
AB1 VDD_DCLK_PLL
F26 VDD_HCLK_PLL
G24 VDD_DEVCLK_PLL

22/48 Issue 1.7 - February 8, 2000

PIN DESCRIPTION

Pin # Pin name

A16 VDD5
B12 VDD5
B9 VDD5
D18 VDD5
A22 VDD
B14 VDD
C9 VDD
D6 VDD
D11 VDD
D16 VDD
D21 VDD
F4 VDD
F23 VDD
G1 VDD
K23 VDD
L4 VDD
L23 VDD
P2 VDD
T4 VDD
T23 VDD
T26 VDD
AA4 VDD
AA23 VDD
AB23 VDD
AC6 VDD
AC11 VDD
AC16 VDD
AC21 VDD
AD19 VDD
AF13 VDD

Pin # Pin name

M11:16 VSS
N4 VSS
N11:16 VSS
P11:16 VSS
P23 VSS
R11:16 VSS
T11:16 VSS
V4 VSS
W23 VSS
AC4 VSS
AC8 VSS
AC13 VSS
AC18 VSS
AC23 VSS
AD3 VSS
AD24 VSS
AE1:2 VSS
AE25 VSS
AF1 VSS
AF25 VSS
AF26 VSS

AE7 VSS_DAC1
AF7 VSS_DAC2
E25 VSS_DLL
E26 VSS_DLL
A1:2 VSS
A26 VSS
B2 VSS
B25:26 VSS
C3 VSS
C24 VSS
D4 VSS
D9 VSS
D14 VSS
D19 VSS
D23 VSS
H4 VSS
J23 VSS
L11:16 VSS

Issue 1.7 - February 8, 2000 23/48

PIN DESCRIPTION

24/48 Issue 1.7 - February 8, 2000

UPDATE HISTORY FOR PIN DESCRIPTION CHAPTER

2.3 UPDATE HISTORY FOR PIN DESCRIPTION CHAPTER

The following changes have been made to the Pin Description Chapter on 08/02/2000

Section Change Text

2.2.3. Replaced Signals VIDEO_D[7:0] with VIN, VTV_BT# with ODD_EVEN, VTV_SYNCH with VCS.

The following changes have been made to the Pin Description Chapter on 13/01/2000

Section Change Text

2.2.

Added “to a minimum of 8MHz”

DCLK

Dot Clock / Pixel clock.

This clock supplies the display controller, the video pipeline, the ramdac,
and the TV output logic. Its value is dependent on the selected display mode.
Its frequency can be as high as 135 MHz. This signal is either driven by the internal PLL to a minimum of
8MHz or by an external oscillator. The direction can be controlled by a strap option or an internal register
bit.

The following changes have been made to the Pin Description Chapter on 28/09/99

Section Change Text

Table 2-1. Changed Updated signal pin counts and added abbreviations to table.

Figure 2-1.

Table 2-2.

2.2.1. Moved PCI_CLKI and PCI_CLKO moved from 2.2.1. to 2.2.5.

2.2.1. Moved ISA_CLK and ISA_CLKX2 moved from 2.2.1. to 2.2.8.

2.2.3. Replaced “Video Interface” with “Video Input”

Changed Updated External interface pin count
Replaced “PWGD” with “SYSRSTI#”

The following changes have been made to the Pin Description Chapter on 23/09/99

Section Change Text

“Note;

2.2.13. Added

By setting signals ST[3:0] to the following value allows the STPC to be put
Tristate. This means the STPC is switched off and no signals are being driven.“

The following changes have been made to the Pin Description Chapter on 11/08/99

Removed statement; “The direction can be controlled by a strap option or an internal register bit.”

Issue 1.7 - February 8, 2000 25/48

UPDATE HISTORY FOR PIN DESCRIPTION CHAPTER

The following changes have been made to the Pin DescriptionChapter from Revision 1.0 to Release 1.2.

Section Change Text

2.1. Replaced

2.2.1. Replaced

2.2.1. Replaced

2.2.6. Replaced

2.2.6. Replaced

2.2.8. Replaced

2.2.12. Added

2.2.12. Replaced

“internal” With “assimilated “
“The DRAM controller to execute the host transactions is also driven by this

clock”
With
“This clock drives the DRAM controller to execute the host transactions”

“AD[31:0]

PCI Address/Data.

This is the 32-bit multiplexed address and data
bus of the PCI. This bus is driven by the master during the address phase and
data phase of write transactions. It is driven by the target during data phase of
read transactions.”

With

“AD[31:0]

PCI Address/Data.

This is the 32-bit PCI multiplexed address and
data bus. This bus is driven by the master during the address phase and data
phase of write transactions. It is driven by the target during data phase of read
transactions.”

“IDE devices are connected to SA[19:8] directly and ISA bus is connected to
these pins through two LS245 transceivers. The OE of the transceivers are
connected to ISAOE# and the DIR is connected to MASTER#. The A bus sig­nals of the transceivers are connected to CPC and IDE DD bus and the B bus
signals are connected to ISA SA bus.”

With
“IDE devices are connected to SA[19:8] directly and the ISA bus is connected

to these pins through two LS245 transceivers. The transceiver OEs are con­nected to ISAOE# and the DIR is connected to MASTER#. The transceiver bus
signals are connected to the CPC and IDE DD busses and B bus signals are
connected to ISA SA bus.”

“For IDE devices, these signals are used as the DA[2:0] and are connected to
DA[2:0] of IDE devices directly or through a buffer. If the toggling of signals is to
be masked during ISA bus cycles, they can be externally ORed before being
connected to the IDE devices.”

With
“For IDE devices, these signals are used as the DA[2:0] and are connected di-

rectly or through a buffer to DA[2:0] of the IDE devices. If the toggling of signals
are to be masked during ISA bus cycles, they can be externally ORed before
being connected to the IDE devices.”

“IOCS16#

IO Chip Select16.

This signal is the decode of the ISA bus SA15-0
address pins of without any qualification of the command signals. The STPC
Client does not drive IOCS16# (similar to PC-AT design). An ISA master ac­cess to an internal register of the STPC Client is executed as an extended 8-bit
IO cycle.”

With

“IOCS16#

IO Chip Select16.

This signal is the decode of SA15-0 address pins
of the ISA address bus without any qualification of the command signals. The
STPC Client does not drive IOCS16# (similar to PC-AT design). An ISA master
access to an internal register of the STPC Client is executed as an extended 8­bit IO cycle.”

“They can instead be used for accessing I C devices on board. DDC1 and
DDC0 correspond to SCL and S DA respectively.”

Updated table 3

26/48 Issue 1.7 - February 8, 2000

3. STRAP OPTION

This chapter defines the STPC Client Strap Op­tions and their location

STRAP OPTION

Memory

Data

Lines

MD0 - Reserved - - - ­MD1 - Reserved - - - ­MD2 DRAM Bank 1 Speed Index 4A, bit 2 User defined 70 ns 60 ns
MD3 Speed Index 4A, bit 3 Pull up - ­MD4 Type Index 4A, bit 4 User defined EDO FPM
MD5 DRAM Bank 0 Speed Index 4A, bit 5 User defined 70 ns 60 ns
MD6 Speed Index 4A, bit 6 Pull up
MD7 Type Index 4A, bit 7 User defined EDO FPM
MD8 - Reserved Index 4B, bit 0 Pull up - -

MD9 - Reserved Index 4B, bit 1 - - ­MD10 DRAM Bank 3 Speed Index 4B, bit 2 User defined 70 ns 60 ns
MD11 Speed Index 4B, bit 3 Pull up - ­MD12 Type Index 4B, bit 4 User defined EDO FPM
MD13 DRAM Bank 2 Speed Index 4B, bit 5 User defined 70 ns 60 ns
MD14 Speed Index 4B, bit 6 Pull up
MD15 Type Index 4B, bit 7 User defined EDO FPM
MD16 - Reserved Index 4C, bit 0 Pull up - ­MD17 PCI Clock PCI_CLKO Divisor Index 4C, bit 1 User defined HCLK /2 HCLK /3
MD18 - Reserved Index 4C, bit 2- Pull up - ­MD19 ­MD20 - Reserved Index 4C, bit 4 Pull up - ­MD21 - Reserved Index 5F, bit 0 Pull up - ­MD22 - Reserved Index 5F, bit 1 Pull up - ­MD23 - Reserved Index 5F, bit 2 Pull up - ­MD24 HCLK HCLK PLL Speed Index 5F, bit 3 User defined 000 Reserved
MD25 Index 5F, bit 4 User defined 001 Reserved
MD26 Index 5F, bit 5 User defined 010 Reserved

MD27 - Reserved - Pull up - ­MD28 - Reserved - Pull up - ­MD29 - Reserved - Pull up - ­MD30 - Reserved - Pull up - ­MD31 - Reserved - Pull down - ­MD32 - Reserved - Pull up - ­MD33 - Reserved - Pull up - ­MD34 - Reserved - Pull down - ­MD35 - Reserved - Pull up - ­MD36 - Reserved - - - ­MD37 - Reserved - - - -

Refer to Designation Location

Reserved Index 4C, bit 3 Pull up - -

Actual
Settings

User defined 011 25 MHz
User defined 100 50 MHz
User defined 101 60 MHz
User defined 110 66 MHz
User defined 111 75 MHz

Set to ’0’ Set to ’1’

Issue 1.7 - February 8, 2000 27/48

STRAP OPTION

Memory

Data
Lines

MD38 - Reserved - - - ­MD39 - Reserved - - - ­MD40 - Reserved - - - ­MD41 - Reserved - - - ­MD42 - Reserved - - - ­MD43 - Reserved - - - -

Note; Setting of Strap Options MD [15:2] have no

Refer to Designation Location

3.1.2 Strap register 1 Index 4Bh (Strap1)

Actual
Settings

Set to ’0’ Set to ’1’

effect on the DRAM Controller but are purely
meant for software issues. i.e. Readable in a reg­ister.

3.1 Power on strap registers description

Bits 7-0; This register reflect the status of pins
MD[15:8] respectively. They are expected to be
connected on the system board to the SIMM con­figuration pins as follows:

3.1.1 Strap register 0 Index 4Ah (Strap0)

Bits 7-0; This register reflect the status of pins
MD[7:0] respectively. They are expected to be
connected on the system board to the SIMM con­figuration pins as follows:

Bit Sampled Description

Bit 7 SIMM 0 DRAM type

Bits 6-5 SIMM 0 speed

Bit 4 SIMM 1 DRAM type:

Bits 3-2 SIMM 1 speed

Bit 1 Reserved
Bit 0 Reserved

Note that the SIMM speed and type information
read here is meant only for thesoftware and is not
used by the hardware. The software must pro­gram the Host and graphics dram controller con-

Bit Sampled Description

Bit 7 SIMM 2 DRAM type

Bits 6-5 SIMM 2 speed

Bit 4 SIMM 3 dram type

Bits 3-2 SIMM 3 speed

Bit 1 Reserved
Bit 0 Reserved

Note that the SIMM speed and type information
read here is meant only for the software and is not
used by the hardware. The software must pro­gram the Host and graphics dram controller con­figuration registers appropriately based on these
bits.

This register defaults to the values sampled on
MD[15:8] pins after reset.

3.1.3 Strap register 2 Index 4Ch (Strap2)

figuration registers appropriately based on these
bits.

Bits 4-0; This register reflect the status of pins
MD[20:16] respectively.They are use by the chip

This register defaults to the values sampled on

as follows:

MD[7:0] pins after reset.

Bit 4-2; Reserved.
Bit 1; This bit reflects the value sampled on

MD[17] pin and controls the PCI clock output as
follows:

Bit 0; Reserved.
This register defaults to the values sampled on

MD[20:16] pins after reset.

28/48 Issue 1.7 - February 8, 2000

0: PCI clock output = HCLK / 2
1: PCI clock output = HCLK / 3.

STRAP OPTION

3.1.4 HCLK PLL Strap register Index 5Fh
(HCLK_Strap)

Bits 5-0 of this register reflect the status of the
MD[26:21] & are used as follows:

Bit 5-3 These pins reflect the value sampled on
MD[26:24] pins respectively and control the Host
clock frequency synthesizer

Bit 2- 0 Reserved
This register defaults to the values sampled on

above pins after reset.
These pin must not be pulled low for normal sys-

tem operation.
Strap Registers [43:27] are reserved.

Issue 1.7 - February 8, 2000 29/48

ELECTRICAL SPECIFICATIONS

4. ELECTRICAL SPECIFICATIONS

4.1 INTRODUCTION

The electrical specifications in this chapter are val­id for the STPC Client.

4.2 ELECTRICAL CONNECTIONS

4.2.1 POWER/GROUND CONNECTIONS/
DECOUPLING

Due to the high frequency of operation of the
STPC Client, it is necessary to install and test this
device using standard high frequency techniques.
The high clock frequencies used in the STPC Cli­ent and its output buffer circuits can cause tran­sient power surges when several output buffers
switch output levelssimultaneously. These effects
can be minimized by filtering the DC power leads
with low-inductance decoupling capacitors, using
low impedance wiring, and by utilizing all of the
VSS and VDD pins.

4.2.2 UNUSED INPUT PINS

All inputs not used by the designer and not listed
in the table of pin connections in Chapter 3 should
be connected either to VDD or to VSS. Connect
active-high inputs to VDD through a 20 kW
(±10%) pull-down resistor and active-lowinputs to
VSS and connect active-low inputs to VCC

Table 4-1. Absolute Maximum Ratings

through a 20 kW (±10%) pull-up resistor to pre­vent spurious operation.

4.2.3 RESERVED DESIGNATED PINS

Pins designated reserved should be left discon­nected. Connecting a reserved pin to a pull-up re­sistor, pull-down resistor, or an active signal could
cause unexpected results and possible circuit
malfunctions.

4.3 ABSOLUTE MAXIMUM RATINGS

The following table lists the absolute maximum
ratings for the STPC Client device. Stresses be­yond those listed under Table 4-1 limits may
cause permanent damage to the device. These
are stress ratings only and do not imply that oper­ation under any conditions other than those spec­ified in section ”Operating Conditions”.

Exposure to conditions beyond Table 4-1 may (1)
reduce device reliability and (2) result in prema­ture failure even when there is no immediately ap­parent sign of failure. Prolonged exposure to con­ditions at or near the absolute maximum ratings
(Table 4-1) may also result in reduced useful life
and reliability.

Symbol Parameter Minimum Maximum Units

V

DDx

V

I,VO

V

5T

V

ESD

T

STG

T

CASE

P

TOT

Note 1 : -40°C limit of T

range) is given a s a preliminary specification and so as
all the -40°C related data.

30/48 Issue 1.7 - February 8, 2000

DC Supply Voltage -0.3 4.0 V
Digital Input and Output Voltage -0.3 VDD + 0.3 V
5Volt Tolerance 2.5 5 V
ESD Capacity (Human body mode) 1500 V
Storage Temperature -40 +150 °C
Operating Case Temperature (Note 1) -40 +100 °C
Total Power Dissipation 4.8 W

(extended temperature

CASE

ELECTRICAL SPECIFICATIONS

4.4 DC CHARACTERISTICS

Table 4-2. DC Characteristics

Recommended Operating conditions : VDD = 3.3V ±0.3V, Tcase = 0 to 100°C (Commercial Range) or -40 to

100°C (Industrial Range) unless otherwise specified

Symbol Parameter Test conditions Min Typ Max Unit

Operating Voltage 3.0 3.3 3.6 V

V

DD

V

H
V

C

C

5V operating voltage Note 3 4.5 5 5.5 V

DD5

P

Supply Power VDD= 3.3V, H

DD

Internal Clock (Note 1) 75 MHz

CLK

DAC Voltage Reference 1.215 1.235 1.255 V

REF

V

Output Low Voltage I

OL

V

Output High Voltage I

OH

V

Input Low Voltage Except XTALI -0.3 0.8 V

IL

V

Input High Voltage Except XTALI 2.1 VDD+0.3 V

IH

I

Input Leakage Current Input, I/O -5 5 µA

LK

C

Input Capacitance (Note 2) pF

IN

Output Capacitance (Note 2) pF

OUT

Clock Capacitance (Note 2) pF

CLK

=1.5 to 8mA depending of the pin 0.5 V

Load

=-0.5 to -8mA depending of the pin 2.4 V

Load

XTALI -0.3 0.9 V

XTALI 2.35 V

= 66Mhz 3.2 3.9 W

CLK

+0.3 V

DD

Notes:

1. MHz ratings refer to CPU clock frequency.

2. Not 100% tested.

3. Detail of pins refer to Section 2.2.

measurement points identified in Figure 4-1 and
Figure 4-2. The rising clock edge reference level
VREF , and other reference levels are shown in
Table 4-3 below for the STPC Client. Input or out­put signals must cross these levels during testing.

Figure 4-1 shows output delay (A and B) and input
setup and hold times (C and D). Input setup and

4.5 AC CHARACTERISTICS

hold times (C and D) are specified minimums, de­fining the smallest acceptable sampling window a
synchronous input signal must be stable for cor-

Table 4-4 through Table 4-8 list the AC character-

rect operation.
istics including output delays, input setup require­ments, input hold requirements and output float
delays. These measurements are based on the

Table 4-3. Drive Level and Measurement Points for Switching Characteristics

Symbol Value Units

V

V
V

REF

IHD

ILD

1.5 V

3.0 V

0.0 V

Note: Refer to Figure 4-1.

Issue 1.7 - February 8, 2000 31/48

ELECTRICAL SPECIFICATIONS

Figure 4-1 Drive Level and Measurement Points for Switching Characteristics

Tx

CLK:

A

B

MIN

MAX

V

IHD

V

Ref

V

ILD

OUTPUTS:

Valid
Output n

INPUTS:

LEGEND: A - Maximum Output Delay Specification

B - Minimum Output Delay Specification
C - Minimum Input Setup Specification
D - Minimum Input Hold Specification

Figure 4-2 CLK Timing Measurement Points

T1

T2

V

IH (MIN)

V

Ref

V

CLK

IL (MAX)

T5 T4T3

Ref

Valid
Output n+1

V

CD

Valid

Input

V

IHD

V

Ref

V

ILD

32/48 Issue 1.7 - February 8, 2000

ELECTRICAL SPECIFICATIONS

Table 4-4. PCI Bus AC Timing

Name Parameter Min Max Unit

t1 PCI_CLKI to AD[31:0] valid 2 13 ns
t2 PCI_CLKI to FRAME# valid 2 11 ns
t3 PCI_CLKI to CBE#[3:0] valid 2 12 ns
t4 PCI_CLKI to PAR valid 2 12 ns

t5 PCI_CLKI to TRDY# valid 2 13 ns
T6 PCI_CLKI to IRDY# valid 2 11 ns
T7 PCI_CLKI to STOP# valid 2 14 ns
T8 PCI_CLKI to DEVSEL# valid 2 11 ns
T9 PCI_CLKI to PCI_GNT# valid 2 14 ns

t10 AD[31:0] bus setup to PCI_CLKI 7 ns
t11 AD[31:0] bus hold from PCI_CLKI 3 ns
t12 PCI_REQ#[2:0] setup to PCI_CLKI 10 ns
t13 PCI_REQ#[2:0] hold from PCI_CLKI 1 ns
t14 CBE#[3:0] setup to PCI_CLKI 7 ns
t15 CBE#[3:0] hold to PCI_CLKI 5 ns
t16 IRDY# setup to PCI_CLKI 7 ns
t17 IRDY# hold to PCI_CLKI 4 ns
t18 FRAME# setup to PCI_CLKI 7 ns
t19 FRAME# hold from PCI_CLKI 3 ns

Table 4-5. DRAM Bus AC Timing

Name Parameter Min Max Unit

t22 HCLK to RAS#[3:0] valid 17 ns
t23 HCLK to CAS#[7:0] bus valid 17 ns
t24 HCLK to MA[11:0] bus valid 17 ns
t25 HCLK to MWE# valid 17 ns
t26 HCLK to MD[63:0] bus valid 25 ns
t27 MD[63:0] Generic setup 7 ns
t28 GCLK2X to RAS#[3:0] valid 17 ns
t29 GCLK2X to CAS#[7:0] valid 17 ns
t30 GCLK2X to MA[11:0] bus valid 17 ns
t31 GCLK2X to MWE# valid 17 ns
t32 GCLK2X to MD[63:0] bus valid 23 ns
t33 MD[63:0] Generic hold 0 ns

Issue 1.7 - February 8, 2000 33/48

ELECTRICAL SPECIFICATIONS

Table 4-6. Video Input/TV Output AC Timing

Name Parameter Min Max Unit

t34 DCLK to TV_YUV[7:0] bus valid 18 ns
t35 VIN[7:0] setup to VCLK 5 ns
t36 VIN[7:0] hold from VCLK 3 ns
t37 VCLK to ODD_EVEN valid 21 ns
t38 VCLK to VCS valid 21 ns
t39 ODD_EVEN setup to VCLK 10 ns
t40 ODD_EVEN hold from VCLK 5 ns
t41 VCS setup to VCLK 10 ns
t42 VCS hold from VCLK 5 ns

Table 4-7. Graphics Adapter (VGA) AC Timing

Name Parameter Min Max Unit

t43 DCLK to VSYNC valid 45 ns
t44 DCLK to HSYNC valid 45 ns

Table 4-8. ISA Bus AC Timing

Name Parameter Min Max Unit

t45 XTALO to LA[23:17] bus active 60 ns
t46 XTALO to SA[19:0] bus active 60 ns
t47 XTALO to BHE# valid 62 ns
t48 XTALO to SD[15:0] bus active 35 ns
t49 PCI_CLKI to ISAOE# valid 28 ns
t50 XTALO to GPIOCS# valid 60 ns
t51 XTALO to ALE valid 62 ns
t52 XTALO to MEMW# valid 50 ns
t53 XTALO to MEMR# valid 50 ns
t54 XTALO to SMEMW# valid 50 ns
t55 XTALO to SMEMR# valid 50 ns
t56 XTALO to IOR# valid 50 ns
t57 XTALO to IOW# valid 50 ns

34/48 Issue 1.7 - February 8, 2000

5. MECHANICAL DATA

MECHANICAL DATA

5.1 388-Pin Package Dimension

The pin numbering for the STPC 388-pin Plastic
BGA package is shown in Figure 5-1.

Figure 5-1. 388-Pin PBGA Package - Top View

1 3 5 7 9 11 13 15 17 19 21 23 25

2468101214161820222426

A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF

Dimensions are shown in Figure 5-2, Table 5-1
and Figure 5-3, Table 5-2.

A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF

1 3 5 7 9 1113151719212325

2468101214161820222426

Issue 1.7 - February 8, 2000 35/48

MECHANICAL DATA

Figure 5-2. 388-pin PBGA Package - PCB Dimensions

A1 Ball Pad Corner

A

A

B

E
F

Detail

G

C

Table 5-1. 388-pin PBGA Package - PCB Dimensions

Symbols

A 34.95 35.00 35.05 1.375 1.378 1.380
B 1.22 1.27 1.32 0.048 0.050 0.052
C 0.58 0.63 0.68 0.023 0.025 0.027
D 1.57 1.62 1.67 0.062 0.064 0.066
E 0.15 0.20 0.25 0.006 0.008 0.001
F 0.05 0.10 0.15 0.002 0.004 0.006

G 0.75 0.80 0.85 0.030 0.032 0.034

Min Typ Max Min Typ Max

mm inches

D

36/48 Issue 1.7 - February 8, 2000

Figure 5-3. 388-pin PBGA Package - Dimensions

MECHANICAL DATA

A

C

Solderball

F

D

E

Solderball after collapse

B

G

Table 5-2. 388-pin PBGA Package - Dimensions

Symbols

A 0.50 0.56 0.62 0.020 0.022 0.024

B 1.12 1.17 1.22 0.044 0.046 0.048
C 0.60 0.76 0.92 0.024 0.030 0.036
D 0.52 0.53 0.54 0.020 0.021 0.022

E 0.63 0.78 0.93 0.025 0.031 0.037

F 0.60 0.63 0.66 0.024 0.025 0.026
G 30.0 11.8

Min Typ Max Min Typ Max

mm inches

Issue 1.7 - February 8, 2000 37/48

MECHANICAL DATA

5.2 388-Pin Package thermal data

388-pin PBGA package has a Power Dissipation
Capability of 4.5W which increases to 6W when
used with a Heatsink.

Figure 5-4. 388-Pin PBGA structure

Thermal balls

Figure 5-5. Thermal dissipation without heatsink

Structure in shown in Figure 5-4.
Thermal dissipation options are illustrated in Fig-

ure 5-5 and Figure 5-6.

Power & Ground layersSignal layers

Board

Ambient

Rca

Case

Rjc

Junction

Rjb

Board

Rba

Ambient

38/48 Issue 1.7 - February 8, 2000

Board

Junction

66

Case

1258.5

Ambient

Rja = 13 °C/W

Board dimensions:

- 10.2 cm x 12.7 cm

- 4 layers (2 for signals, 1 GND, 1VCC)
The PBGA is centered on board

There are no other devices
1 via pad per ground ball (8-mil wire)
40% copper on signal layers

Copper thickness:

-17

µ

m for internal layers

µ

m for external layers

-34
Airflow = 0

Board temperature taken at the center balls

Figure 5-6. Thermal dissipation with heatsink

Board

MECHANICAL DATA

Ambient

Case

Junction

Board

Ambient

Rca

Rjc

Rjb

Rba

Junction

36

Board

Ambient

Rja = 9.5 °C/W

Case

508.5

Board dimensions:

- 10.2 cm x 12.7 cm

- 4 layers (2 for signals, 1 GND, 1VCC)
The PBGA is centered on board

There are no other devices
1 via pad per ground ball (8-mil wire)
40% copper on signal layers

Copper thickness:

-17

µ

m for internal layers

-34

µ

m for external layers

Airflow = 0
Board temperature taken at the center balls

°

Heat sink is 11.1

C/W

Issue 1.7 - February 8, 2000 39/48

MECHANICAL DATA

40/48 Issue 1.7 - February 8, 2000

6. BOARD LAYOUT

6.1 THERMAL DISSIPATION

BOARD LAYOUT

Thermal dissipation of the STPC depends mainly
on supply voltage. As a result, when the system
does not need to work at 3.3V, it may be to reduce
the voltage to 3.15V for example. This may save
few 100’s of mW.

The second area that can be concidered is un­used interfaces and functions. Depending on the
application, some input signals can be grounded,
and some blocks not powered or shutdown. Clock
speed dynamic adjustment is also a solution that
can be used along with the integrated power man­agement unit.

The standard way to route thermalballs to internal
ground layer implements onlyone via pad for each
ball pad, connected using a 8-mil wire.

Figure 6-1. Ground routing

With such configuration thePlastic BGA 388 pack­agedissipates 90% of the heat through the ground
balls, and especially the central thermal balls
which are directly connected to the die, the re­maining 10% is dissipated through the case. Add­ing a heat sink reduces this value to 85%.

As a result, some basic rules have to be applied
when routing the STPC in order to avoid thermal
problems.

First of all, the whole ground layer acts as a heat
sink and ground balls must be directly connected
to it as illustrated in Figure 6-1.

If one ground layer is not enough, a second
ground plane may be added on the solder side.

Pad for ground ball

T

o

pL

a

y

e

r

:

S

i

g

a

n

a

l

s

y

e

r

y

e

r

a

y

e

r

:

s

i

g

n

a

l

s

+

l

o

c

a

l

g

r

o

u

n

d

l

a

y

e

r

(

i

f

n

e

e

G

r

o

u

n

dl

P

o

w

e

r

l

a

B

o

t

t

o

m

L

Note: For better visibility, ground balls are not all routed.

d

e

d

Thru hole to ground layer

)

Issue 1.7 - February 8, 2000 41/48

BOARD LAYOUT

When considering thermal dissipation, the most
important - and not the more obvious - part of the
layout is the connection between the ground balls
and the ground layer.

A 1-wire connection is shown in Figure 6-2. The
use of a 8-mil wire results in a thermal resistance
of 105°C/W assuming copper is used (418 W/
m.°K). This high value is due to the thickness (34
µm) of the copper on the external side of the PCB.

Considering only the central matrix of 36 thermal
balls and one via for each ball, the global thermal
resistance is 2.9°C/W. This can be easily im­proved byusing four 10 milwires to connect to the
four vias around the ground pad link as in Figure
6-3. This gives a total of 49 vias and a global resis­tance for the 36 thermal balls of 0.6°C/W.

The use of a ground plane like in Figure 6-4 is
even better.

Figure 6-2. Recommended 1-wire ground pad layout

To avoid solder wickingover to the via pads during
soldering, it is important to have a solder mask of
4 mil around the pad (NSMD pad), this gives a di­ameter of 33mil for a 25 mil ground pad.

To obtain the optimum ground layout, place the
vias directly under the ball pads. In this case no lo­cal boar d distortion is tolerated.

The thickness of the copper on PCB layers is typ­ically 34 µm for external layersand17 µm for inter­nal layers. This means thermal dissipation is not
good and temperature of the board is concentrat­ed around the devices and falls quickly with in­creased distance.

When it is possible to place a metal layer inside
the PCB, this improves dramatically the heat
spreading and hence thermal dissipation of the
board.

Pad for ground ball (diameter= 25 mil)

34.5 mil

Figure 6-3. Recommended 4-wire ground pad layout

Solder Mask (4 mil)

Connection Wire (width = 10 mil)

Via (diameter = 24 mil)

Hole to ground layer (diameter = 12 mil)

1 mil = 0.0254 mm

4 via pads for eachground ball

42/48 Issue 1.7 - February 8, 2000

Figure 6-4. Optimum layout for central ground ball

BOARD LAYOUT

Clearance = 6mil
External diameter = 37 mil

Via to Ground layer
hole diameter = 14 mil

Solder mask
diameter = 33 mil

Pad for ground ball
diameter = 25 mil
connections = 10 mil

The PBGA Package also dissipates heat through
peripheral ground balls. When a heat sink is
placed on the device, heat is more uniformely

The more via pads are connected to each ground
ball, the more heat is dissipated . The only limita-

tion is the risk of lossing routing channels.
spread throughout the moulding increasing heat
dissipation through the peripheral ground balls.

Figure 6-5 shows a routing with a good trade off

between thermal dissipation and number of rout-

ing channels.

Figure 6-5. Global ground layout for good thermal dissipation

Via to ground layer

Ground pad

Issue 1.7 - February 8, 2000 43/48

BOARD LAYOUT

Figure 6-6. Bottom side layout and decoupling

Ground plane for thermal dissipation

Via to ground layer

A local ground plane on opposite side of the board
as shown in Figure 6-6 improves thermal dissipa­tion. It is used to connect decoupling capacitances
but can also be used for connection to a heat sink
or to the system’s metal box for better dissipation.

This possibility of using the whole system’s box for

thermal dissipation is very usefull in case of high

temperature inside the system and low tempera-

ture outside. In that case, both sides of the PBGA

should be thermally connected to the metal chas-

sis in order to propagate the heat through the met-

al. Figure 6-7 illustrates such an implementation.

Figure 6-7. Use of metal plate for thermal dissipation

Die

Metal planes Thermal conductor

Board

44/48 Issue 1.7 - February 8, 2000

6.2 HIGH SPEED SIGNALS

BOARD LAYOUT

Some Interfaces of the STPC run at high speed
and have to be carefully routed or even shielded.

Here is the list of these interfaces, in decreasing
speed order:

- Memory Interface.

- Graphics and video interfaces

- PCI bus

- 14MHz oscillator stage

Figure 6-8. Shielding signals

ground pad

All the clocks have to be routed first and shielded

for speeds of 27MHz ormore. The high speed sig-

nals have the same contrainsts as some of the

memory interface control signals.

The next interfaces to be routed are Memory, Vid-

eo/graphics, and PCI.

All the analog noise sensitive signals have to be

routed in a separate area and hence can be rout-

ed indepedently.

ground ring

shielded signal line

ground pad

shielded signal lines

Issue 1.7 - February 8, 2000 45/48

ORDERING DATA

7. ORDERING DATA

7.1 ORDERING CODES

STMicroelectronics

Prefix

Product Family

PC: PC Compatible

Product ID

D01: Client

Core Speed

66: 66MHz
75: 75MHz

ST PC D01 66 BT C 3

Package

BT: 388 Overmoulded BGA

Temperature Range

C: Commercial

Case Temperature (Tcase) = 0°C to +100°C

I: Industrial

Case Temperature (Tcase) = -40°C to +100°C

A: Auatomotive

Case Temperature (Tcase) = -40°C to +115°C

Operating Voltage

3 : 3.3V ± 0.3V

46/48 Issue 1.7 - February 8, 2000

7.2 AVAILABLE PART NUMBERS

ORDERING DATA

Part Number

STPCD0166BTC3 66 DX
STPCD0175BTC3 75 DX
STPCD0166BTI3 66 DX
STPCD0175BTI3 75 DX
STPCD0166BTA3 66 DX -40°C to +115°C

Core Frequency

( MHz )

CPU Mode

(DX/DX2)

Tcase Range

0°C to +100°C

-40°C to +100°C

7.3 CUSTOMER SERVICE

More information is available on the
STMicroelectronics internet site http://

Any specific questions are to be addressed direct-

ly to the local ST Sales Office.
www.ST.com/STPC.

( °C)

Operating Voltage

(V)

3.3V ± 0.3V

Issue 1.7 - February 8, 2000 47/48

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of useof such information nor forany infringement ofpatents or otherrights of third parties which may result from itsuse. No license isgranted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express writtenapproval of STMicroelectronics.

 2000 STMicroelectronics - All Rights Reserved

The ST logo is a registered trademark of STMicroelectronics.

All other names are the property of their respective owners.

STMicroelectronics GROUP OF COMPANIES

Australia - Brazil - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Mexico - Morocco - The Netherlands - Singapore -

Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A.

48

Issue 1.7