The SuperMESH™ s eries is obtained through an
extreme optimization of ST’s well established stripbased PowerMESH™ layout. In addition to pushing
on-resistance significantly down, special careis taken to ensure a very good dv/dt capability for the
most dem anding applications. Such series complements S T full range of high voltage MOSFETs including revolutionary MDmes h™ products.
Avalanche Current, Repetitive or Not-Repetitive
(pulse width limited by T
E
AS
Single Pulse Avalanche Energy
(starting T
max)
j
= 25 °C, ID=IAR,VDD=50V)
j
8A
300mJ
GATE-SOURCE ZENER DIODE
SymbolParameterTest ConditionsMin.Typ.Max.Unit
BV
GSO
Gate-Source Breakdown
Igs=± 1mA (Open Drain)30V
Voltage
PROTECTION FEATURES OF GATE-TO-SOURCE ZENER DIODES
The built-in back-to-back Zener diodes have specifically been designed t o enhance not only the device’s
ESD capability, but also to make them saf ely absorb possible voltage transients that may occasionally be
applied from gate to source. In this respect the Zener voltage is appropriate to achieve an efficient and
cost-effective intervention to protect the device’ s integrity. These integrated Zener diodes thus avoid the
usage of external components.
2/11
STP9NK90Z - S TF9NK9 0Z - STW9NK90Z
ELECTRICAL CHARACTERISTICS (T
=25°C UNLESS OTHERWISE SPECIFIED)
CASE
ON/OFF
SymbolParameterTest ConditionsMin.Typ.Max.Unit
V
(BR)DSS
Drain-source
ID=1mA,VGS= 0900V
Breakdown Voltage
I
DSS
I
GSS
V
GS(th)
R
DS(on)
Zero Gate Voltage
Drain Current (V
GS
=0)
Gate-body Leakage
Current (V
DS
=0)
Gate Threshold Voltage
Static Drain-source On
V
= Max Rating
DS
VDS= Max Rating, TC= 125 °C
V
= ± 20V±10µA
GS
V
DS=VGS,ID
= 100µA
33.754.5V
1
50
VGS=10V,ID= 3.6 A1.11.3Ω
Resistance
DYNAMIC
SymbolParameterTest ConditionsMin.Typ.Max.Unit
(1)Forward TransconductanceVDS=15V,ID= 3.6 A5.75S
g
fs
C
oss eq.
C
iss
C
oss
C
rss
Input Capacitance
Output Capacitance
Reverse Transfer
Capacitance
(3)Equivalent Output
=25V,f=1MHz,VGS= 02115
V
DS
190
40
VGS=0V,VDS= 0V to 720V115pF
Capacitance
SWITCHING ON
SymbolParameterTest ConditionsMin.Typ.Max.Unit
t
d(on)
Q
Q
Q
Turn-on Delay Time
t
r
g
gs
gd
Rise Time
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
VDD=450V,ID=4A
RG= 4.7Ω VGS=10V
(Resistive Load see, Figure 3)
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the
consequences of u se of such inf ormat ion nor for any in fring ement of p aten ts or othe r ri ghts of th ird p arties whic h may resul t f rom
its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications
mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information
previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or
systems without express written approval of STMicroelectronics.
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