ST STP7NK80Z, STP7NK80ZFP, STB7NK80Z, STB7NK80Z-1 User Manual
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1/13August 2002
STP7NK80Z - STP7NK80ZFP
STB7NK80Z - STB7NK80Z-1
N-CHANNEL800V-1.5Ω - 5.2A TO-220/TO-220FP/I
2
PAK/D
2
PAK
Zener-Protected SuperMESH™Power MOSFET
■ TYPICAL R
DS
(on) = 1.5 Ω
■ EXTREMELY HIGH dv/dt CAPABILITY
■ 100% AVALANCHE TESTED
■ GAT E CHARGE MINIMIZED
■ VERY LOW INTRINSIC CAPACITANCES
■ VER Y GO OD MANUFACTURING
REPEATIBILITY
DESCRIPTION
The SuperMESH™ series is obtained through an
extreme optimization of ST’s well established s tri p-
based PowerMESH™ layout. In addition to pushing
on-resistance significantly down, special careis tak-
en t o ensure a very good dv/dt capability for the
most demanding applicat ions. Such series comple-
ments ST full range of high voltage MOSFETs in-
cluding revolutionary MDm es h™ products.
APPLICATIONS
■ HIGH CURRENT,HIGH SPEED SWITCHING
■ SMPS FOR INDUSTRIAL APPLICATION.
■ LIGHT ING (PREHE ATING)
ORDERING INFORMATION
TYPE V
DSS
R
DS(on)
I
D
Pw
STP7NK80Z
STP7NK80ZFP
STB7NK80Z
STB7NK80Z-1
800 V
800 V
800 V
800 V
< 1.8 Ω
< 1.8 Ω
< 1.8 Ω
< 1.8 Ω
5.2 A
5.2 A
5.2 A
5.2 A
125 W
30 W
125 W
125 W
SALES TYPE MARKING PACKAGE PACKAGING
STP7NK80Z P7NK80Z TO-220 TUBE
STP7NK80ZFP P7NK80ZFP TO-220FP TUBE
STB7NK80ZT4 B7NK80Z
D
2
PAK
TAPE & REEL
STB7NK80Z B7NK80Z
D
2
PAK
TUBE
(ONLY UNDER REQUEST)
STB7NK80Z-1 B7NK80Z
I
2
PAK
TUBE
TO-220
TO-220FP
1
2
3
I
2
PAK
1
3
D
2
PAK
1
2
3
INTERNAL SCHEMATIC DIAGRAM
STP7NK80Z - STP7NK80ZFP - STB7NK80Z - STB7NK80Z-1
2/13
ABSOLUTE MAXIMUM RATINGS
(
) Pulse width limited by safe operating area
(1) I
SD
≤5.2A, di/dt ≤200A/µs, V
DD
≤ V
(BR)DSS
,T
j
≤T
JMAX.
(*) Limited only by maximum temperature allowed
THERMAL DATA
AVALANCHE CHARACTERISTICS
GATE-SOURCE ZENER DIODE
PROTECTION FEATURES OF GATE-TO-SOURCE ZENER DIODES
The built-in back-to-back Zener diodes havespecifically been designed to enhance not only the dev ice’s
ESD c apability, but also to make them sa fely absorb pos sible voltage transients that may occasionally be
applied from gate to source. In this respect the Zener voltage is appropriate to achieve an efficient and
cost-effective intervention to protect the device’s integrity. These integrated Zener d iodes thus avoid t he
usage of external components.
Symbol Parameter Value Unit
STP7NK80Z
STB7NK80Z
STB7NK80Z-1
STP7NK80ZFP
V
DS
Drain-source Voltage (V
GS
=0)
800 V
V
DGR
Drain-gate Voltage (R
GS
=20kΩ)
800 V
V
GS
Gate- source Voltage ± 30 V
I
D
Drain Current (continuous) at T
C
= 25°C
5.2 5.2 (*) A
I
D
Drain Current (continuous) at T
C
= 100°C
3.3 3.3 (*) A
I
DM
(
)
Drain Current (pulsed) 20.8 20.8 (*) A
P
TOT
Total Dissipation at T
C
= 25°C
125 30 W
Derating Factor 1 0.24 W/°C
V
ESD(G-S)
Gate source ESD(HBM-C=100pF, R=1.5KΩ) 4000 V
dv/dt (1) Peak Diode Recovery voltage slope 4.5 V/ns
V
ISO
Insulation Withstand Voltage (DC) - 2500 V
T
j
T
stg
Operating Junction Temperature
Storage Temperature
-55 to 150
-55 to 150
°C
°C
TO-220
D
2
PAK
I
2
PAK
TO-220FP
Rthj-case Thermal Resistance Junction-case Max 1 4.2 °C/W
Rthj-amb Thermal Resistance Junction-ambient Max 62.5 50 °C/W
T
l
Maximum Lead Temperature For Soldering Purpose
300 °C
Symbol Parameter Max Value Unit
I
AR
Avalanche Current, Repetitive or Not-Repetitive
(pulse width limited by T
j
max)
5.2 A
E
AS
Single Pulse Avalanche Energy
(starting T
j
= 25 °C, I
D
=I
AR
,V
DD
=50V)
210 mJ
Symbol Parameter Test Conditions Min. Typ. Max. Unit
BV
GSO
Gate-Source Breakdown
Voltage
Igs=± 1mA (Open Drain) 30 V
3/13
STP7NK80Z - STP7NK 80Z FP - STB7NK80Z - STB7NK80Z-1
ELECTRICAL CHARACTERISTICS (TCASE =25°C UNLESS OT HERWISE SPECIFIED)
ON/OFF
DYNAMIC
SWITCHING ON
SWITCHING OFF
SOURCE DRAIN DIODE
Note: 1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %.
2. Pulse width limited by safe operating area.
3. C
oss eq.
is defined as a constant equivalent capacitance giving the same charging time as C
oss
when V
DS
increases from 0 to 80%
V
DSS
.
Symbol Parameter Test Conditions Min. Typ. Max. Unit
V
(BR)DSS
Drain-source
Breakdown Voltage
I
D
=1mA,V
GS
= 0 800 V
I
DSS
Zero Gate Voltage
Drain Current (V
GS
=0)
V
DS
= Max Rating
V
DS
= Max Rating, T
C
= 125 °C
1
50
µA
µA
I
GSS
Gate-body Leakage
Current (V
DS
=0)
V
GS
= ± 20V ±10 µA
V
GS(th)
Gate Threshold Voltage
V
DS
=V
GS
,I
D
= 100µA
3 3.75 4.5 V
R
DS(on)
Static Drain-source On
Resistance
V
GS
=10V,I
D
= 2.6 A 1.5 1.8 Ω
Symbol Parameter Test Conditions Min. Typ. Max. Unit
g
fs
(1) Forward Transconductance V
DS
=15V
,
I
D
= 2.6 A 5 S
C
iss
C
oss
C
rss
Input Capacitance
Output Capacitance
Reverse Transfer
Capacitance
V
DS
=25V,f=1MHz,V
GS
=0 1138
122
25
pF
pF
pF
C
oss eq.
(3) Equivalent Output
Capacitance
V
GS
=0V,V
DS
= 0V to 640V 50 pF
Symbol Parameter Test Conditions Min. Typ. Max. Unit
t
d(on)
t
r
Turn-on Delay Time
Rise Time
V
DD
=400V,I
D
= 2.6 A
R
G
= 4.7Ω V
GS
=10V
(Resistive Load see, Figure 3)
20
12
ns
ns
Q
g
Q
gs
Q
gd
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
V
DD
=640V,I
D
= 5.2 A,
V
GS
=10V
40
7
21
56 nC
nC
nC
Symbol Parameter Test Conditions Min. Typ. Max. Unit
t
d(off)
t
f
Turn-off Delay Time
Fall Time
V
DD
= 400 V, I
D
= 2.6 A
R
G
=4.7ΩV
GS
=10V
(Resistive Load see, Figure 3)
45
22
ns
ns
t
r(Voff)
t
f
t
c
Off-voltage Rise Time
Fall Time
Cross-over Time
V
DD
= 640V, I
D
= 5.2 A,
R
G
=4.7Ω, V
GS
= 10V
(Inductive Load see, Figure 5)
12
10
20
ns
ns
ns
Symbol Parameter Test Conditions Min. Typ. Max. Unit
I
SD
I
SDM
(2)
Source-drain Current
Source-drain Current (pulsed)
5.2
20.8
A
A
V
SD
(1)
Forward On Voltage
I
SD
= 5.2 A, V
GS
=0
1.6 V
t
rr
Q
rr
I
RRM
Reverse Recovery Time
Reverse Recovery Charge
Reverse Recovery Current
I
SD
= 5.2 A, di/dt = 100A/µs
V
DD
=50V,T
j
= 150°C
(see test circuit, Figure 5)
530
3.31
12.5
ns
µC
A
STP7NK80Z - STP7NK80ZF P - STB7NK80Z - STB 7NK80Z -1
4/13
Safe Operating Area For TO-220/D2PAK/I2PAK
Output Characteristics
Thermal Impedan ce For TO-220/D2PAK/I2PAK
Safe Operating Area For TO-220FP
Thermal Impedance For TO-220FP
Transfer Characteristics
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