ST STP7NK40Z, STP7NK40ZFP, STD7NK40Z, STD7NK40Z-1 User Manual
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1/13September 2002
STP7NK40Z - STP7NK40ZFP
STD7NK40Z - STD7NK40Z-1
N-CH A NNEL 400V-0.85Ω-5.4A TO-220/TO-220FP/DPAK/IPAK
Zener-Protected SuperMESH™Power MOSFET
■ TYPICAL R
DS
(on) = 0.85 Ω
■ EXTREMELY HIGH dv /d t C APABILITY
■ 100% AVALANCHE TESTED
■ GATE CHARGE MINIMIZED
■ VERY LOW INTRINSIC CAPAC ITANCES
■ VERY GOOD MANUFACTURING
REPEATIBILITY
DESCRIPTION
The SuperMESH™ series is obtained through an
extreme optimization of ST ’s well established strip-
based PowerMESH™ layout. In addition to pushing
on-resistance significantly down, special care is tak-
en to ensure a very good dv/dt capability for the
most demanding applications. Such series c om pl e-
ments ST full range of high voltage MOSFE Ts in-
cluding revolutionary MDmesh™ products.
APPLICATIONS
■ HIGH CURRENT, HIGH SPEED SWITCHING
■ IDEAL FOR OFF-LIN E POWER SUPPL I ES,
ADAPTORS AND PFC
■ LIGHTING
ORDERING INFORMATION
TYPE V
DSS
R
DS(on)
I
D
Pw
STP7NK40Z
STP7NK40ZFP
STD7NK40Z
STD7NK40Z-1
400 V
400 V
400 V
400 V
< 1 Ω
< 1 Ω
< 1 Ω
< 1 Ω
5.4 A
5.4 A
5.4 A
5.4 A
70 W
25 W
70 W
70 W
SALES TYPE MARKING PACKAGE PACKAGING
STP7NK40Z P7NK40Z TO-220 TUBE
STP7NK40ZFP P7NK40ZFP TO-220FP TUBE
STD7NK40ZT4 D7NK40Z DPAK TAPE & REEL
STD7NK40Z-1 D7NK40Z IPAK TUBE
TO-220 TO-220FP
1
2
3
1
3
DPAK
3
2
1
IPAK
INTERNAL SCHEMATIC DIAGRAM
STP7NK40Z - STP7NK40ZFP - S TD7N K40Z - STD7NK40Z-1
2/13
ABSOLUTE MAXIMUM RATINGS
(
l
) Pulse wi dth limited by safe operating area
(1) I
SD
≤5.4A, di/dt ≤200A/µs, V
DD
≤ V
(BR)DSS
, T
j
≤ T
JMAX.
(*) Limited only by maximum temperature allowed
THERMA L D ATA
AVALANCHE CHARACTERISTICS
GATE-SOURCE ZENER DIODE
PROTECTION FEATURES OF GATE-TO-SOURCE ZENER DIODES
The built-in back-to-back Zener diodes have specifically been designed to enhance not only the device’s
ESD capability, but also to make them safely absorb possible voltage transients that may occasionally be
applied from gate to source. In this respect the Zener voltage is appropriate to achieve an efficient and
cost-effective intervention to protect the device’s integrity. These integrated Zener diodes thus avoid the
usage of external components.
Symbol Parameter Value Unit
STP7NK40Z STP7NK40ZFP
STD7NK40Z
STD7NK40Z-1
V
DS
Drain-source Voltage (V
GS
= 0)
400 V
V
DGR
Drain-gate Voltage (R
GS
= 20 kΩ)
400 V
V
GS
Gate- source Voltage ± 30 V
I
D
Drain Current (continuous) at T
C
= 25°C
5.4 5.4 (*) 5.4 A
I
D
Drain Current (continuous) at T
C
= 100°C
3.4 3.4 (*) 3.4 A
I
DM
(
l
)
Drain Current (pulsed) 21.6 21.6 (*) 21.6 A
P
TOT
Total Dissipation at T
C
= 25°C
70 25 70 W
Derating Factor 0.56 0.2 0.56 W/°C
V
ESD(G-S)
Gate source ESD(HBM-C=100pF, R=1.5KΩ) 3000 V
dv/dt (1) Peak Diode Recovery voltage slope 4.5 V/ns
V
ISO
Insulation Withstand Voltage (DC) - 2500 - V
T
j
T
stg
Operating Junction Temperature
Storage Temperature
-55 to 150
-55 to 150
°C
°C
TO-220 TO-220FP
DPAK
IPAK
Rthj-case Thermal Resistance Junction-case Max 1.78 5 1.78 °C/W
Rthj-amb Thermal Resistance Junction-ambient Max 62.5 100 °C/W
T
l
Maximum Lead Temperature For Soldering Purpose
300 °C
Symbol Parameter Max Value Unit
I
AR
Avalanche Current, Repetitive or Not-Repetitive
(pulse width limited by T
j
max)
5.4 A
E
AS
Single Pulse Avalanche Energy
(starting T
j
= 25 °C, I
D
= I
AR
, V
DD
= 50 V)
130 mJ
Symbol Parameter Test Conditions Min. Typ. Max. Unit
BV
GSO
Gate-Source Breakdown
Voltage
Igs=± 1mA (Open Drain) 30 V
3/13
STP7NK40Z - STP7NK40Z FP - STD7NK40Z - STD7NK40Z-1
ELECTRICAL CHARACTERISTICS (T
CASE
=25°C UNLESS OTHERWISE SPECIFIED)
ON/OFF
DYNAMIC
SWITCHING ON
SWITCHING OFF
SOURCE DRAIN DIODE
Note: 1. Pulsed: Pu l se duration = 300 µs, duty c ycle 1.5 %.
2. Pulse width li mited by safe operating area.
3. C
oss eq.
is defined as a constant equivalent capacitance giving the same charging time as C
oss
when V
DS
increase s fr om 0 to 80%
V
DSS
.
Symbol Parameter Test Conditions Min. Typ. Max. Unit
V
(BR)DSS
Drain-source
Breakdown Voltage
I
D
=1 mA, V
GS
= 0 400 V
I
DSS
Zero Gate Voltage
Drain Current (V
GS
= 0)
V
DS
= Max Rating
V
DS
= Max Rating, T
C
= 125 °C
1
50
µA
µA
I
GSS
Gate-body Leakage
Current (V
DS
= 0)
V
GS
= ± 20V ±10 µA
V
GS(th)
Gate Threshold Voltage
V
DS
= V
GS
, I
D
= 50µA
3 3.75 4.5 V
R
DS(on)
Static Drain-source On
Resistance
V
GS
= 10V, I
D
= 2.7 A 0.85 1 Ω
Symbol Parameter Test Conditions Min. Typ. Max. Unit
g
fs
(1) Forward Transconductance V
DS
=15 V
,
I
D
= 2.7 A 3.5 S
C
iss
C
oss
C
rss
Input Capacitance
Output Capacitance
Reverse Transfer
Capacitance
V
DS
= 25V, f = 1 MHz, V
GS
= 0 535
82
18
pF
pF
pF
C
oss eq.
(3) Equivalent Output
Capacitance
V
GS
= 0V, V
DS
= 0V to 400V 53 pF
Symbol Parameter Test Conditions Min. Typ. Max. Unit
t
d(on)
t
r
Turn-on Delay Time
Rise Time
V
DD
= 200 V, I
D
= 2.7 A
R
G
= 4.7Ω V
GS
= 10 V
(Resistive Load see, Figure 3)
15
15
ns
ns
Q
g
Q
gs
Q
gd
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
V
DD
= 320V, I
D
= 5.4 A,
V
GS
= 10V
19
4
10
26 nC
nC
nC
Symbol Parameter Test Conditions Min. Typ. Max. Unit
t
d(off)
t
f
Turn-off Delay Time
Fall Time
V
DD
= 200 V, I
D
= 2.7A
R
G
=4.7Ω V
GS
= 10 V
(Resistive Load see, Figure 3)
30
12
ns
ns
t
r(Voff)
t
f
t
c
Off-voltage Rise Time
Fall Time
Cross-over Time
V
DD
= 320V, I
D
= 5.4A,
R
G
=4.7Ω, V
GS
= 10V
(Inductive Load see, Figure 5)
12
10
20
ns
ns
ns
Symbol Parameter Test Conditions Min. Typ. Max. Unit
I
SD
I
SDM
(2)
Source-drain Current
Source-drain Current (pulsed)
5.4
21.6
A
A
V
SD
(1)
Forward On Voltage
I
SD
= 5.4 A, V
GS
= 0
1.6 V
t
rr
Q
rr
I
RRM
Reverse Recovery Time
Reverse Recovery Charge
Reverse Recovery Current
I
SD
= 5.4 A, di/dt = 100A/µs
V
DD
= 50V, T
j
= 150°C
(see test circuit, Figure 5)
220
990
9
ns
nC
A
STP7NK40Z - STP7NK40ZFP - S TD7N K40Z - STD7NK40Z-1
4/13
Transfer Characteristics
Output Characteristics
Thermal Impedance For TO-220/DPAK/IPAK
Safe Operating Area For TO-220FPSafe Operating Area For TO-220/DPAK/IPAK
Thermal Impedance For TO-220FP
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