ST STP16DPPS05 User Manual

STP16DPPS05

Low voltage 16-bit constant current

LED sink driver with output error detection and auto power-saving

Features

■ Low voltage power supply down to 3 V

■ 16 constant current output channels

■ Adjustable output current through external

resistor

■ Short and open output error detection

■ Serial data IN/parallel data OUT

■ Auto power-saving

■ 3.3 V MCU-driving capability

■ Output current: 3 to 40 mA

■ 30 MHz clock frequency

■ Available in high thermal efficiency TSSOP

exposed pad

■ ESD protection: 2 kV HBM, 200 V MM

Description

The STP16DPPS05 is a monolithic, low voltage,
low current power 16-bit shift register designed for
LED panel displays. The device features a 16-bit
serial-in, parallel-out shift register that feeds a
16-bit D-type storage register. In the output stage,
sixteen regulated current sources are designed to
provide 3 to 40 mA of constant current to drive the
LEDs. The STP16DPPS05 features open and
short LED detection on the outputs. The detection
circuit checks for 3 different conditions that can
occur on the output line: short to GND, short to V
or open line.

The data detection results are loaded in the shift
registers and shifted out via the serial line output.

Table 1. Device summary

O

QSOP-24

TSSOP24

The detection functionality is implemented without
increasing the pin count, through a secondary
function of the output enable and latch pin (DM1
and DM2 respectively). A dedicated logic
sequence allows the device to enter or exit from
detection mode. The STP16DPPS05 output
current can be adjusted through an external
resistor to control the light intensity of the LEDs.
LED brightness is adjustable from 0% to 100% via
the OE/DM2

pin.

The auto power-shutdown and auto power-ON
feature allows the device to save power with no
external intervention.

The STP16DPPS05 guarantees a 20 V output
driving capability, allowing users to connect more
LEDs in series. The high 30 MHz clock frequency
makes the device suitable for high data rate
transmission. The 3.3 V supply is well suited for
applications which interface a 3.3 V MCU.
Compared to a standard TSSOP package, the
TSSOP with exposed pad increases heat
dissipation capability by a factor of 2.5

SO-24

TSSOP24

(exposed pad)

Order codes Package Packaging

STP16DPPS05MTR SO-24 (tape and reel) 1000 parts per reel

STP16DPPS05TTR TSSOP24 (tape and reel) 2500 parts per reel

STP16DPPS05XTTR

TSSOP24 exposed pad

(tape and reel)

2500 parts per reel

STP16DPPS05PTR QSOP-24 2500 parts per reel

October 2009 Doc ID 15817 Rev 2 1/34

www.st.com

34

Contents STP16DPPS05

Contents

1 Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1.1 Pin connection and description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.3 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

4 Equivalent circuit and outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

5 Timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

6 Typical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

7 Error detection mode functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

7.1 Phase one: entering error detection mode . . . . . . . . . . . . . . . . . . . . . . . . 18

7.2 Phase two: error detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

7.3 Phase three: resuming normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

7.4 Error detection conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

7.5 Auto power-saving . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

8 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

2/34 Doc ID 15817 Rev 2

STP16DPPS05 Summary description

1 Summary description

Table 2. Typical current accuracy

Current accuracy

Output voltage

Between bits Between ICs

≥ 1.3 V ± 1% ± 2% 5 to 40 mA 3.3 V to 5 V 25 °C

1.1 Pin connection and description

Figure 1. Pin connection

Output current

V

DD

Temper atur e

Note: The exposed pad should be electrically connected to a metal land electrically isolated or

connected to ground.

Doc ID 15817 Rev 2 3/34

Summary description STP16DPPS05

Table 3. Pin description

Pin n° Symbol Name and function

1 GND Ground terminal

2 SDI Serial data input terminal

3 CLK Clock input terminal

4 LE/DM1 Latch input terminal - detect mode 1 (see operation principle)

5-20 OUT 0-15

Output terminal

21 OE/DM2

Input terminal of output enable (active low) - detect mode 1
(see operation principle)

22 SDO Serial data out terminal

23 R-EXT

24 V

DD

Input terminal for an external resistor for constant current
programming

Supply voltage terminal

4/34 Doc ID 15817 Rev 2

STP16DPPS05 Electrical ratings

2 Electrical ratings

2.1 Absolute maximum ratings

Stressing the device above the ratings listed in the “absolute maximum ratings” table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other condition above those indicated in the operating sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.

Table 4. Absolute maximum ratings

Symbol Parameter Value Unit

V

DD

V

I

O

V

I

GND

f

CLK

T

1. Such absolute value is based on the thermal shutdown protection.

Supply voltage 0 to 7 V

Output voltage -0.5 to 20 V

O

Output current 50 mA

Input voltage -0.4 to V

I

GND terminal current 800 mA

Clock frequency 50 MHz

Junction temperature range

J

2.2 Thermal data

Table 5. Thermal data

Symbol Parameter Value Unit

T

J-OPR

T

R

T

STG

thJA

Operating free-air temperature range -40 to +125 °C

A

Operating thermal junction temperature range -40 to +150 °C

Storage temperature range -55 to +150 °C

Thermal resistance junction­ambient

(1)

(1)

DD

-40 to +170 °C

SO-24 42.7 °C/W

TSSOP24 55 °C/W

(2)

TSSOP24

Exposed Pad

37.5 °C/W

V

QSOP-24 55 °C/W

1. According with JEDEC standard 51-7B

2. The exposed pad should be soldered directly to the PCB to obtain the thermal benefits.

Doc ID 15817 Rev 2 5/34

Electrical ratings STP16DPPS05

2.3 Recommended operating conditions

Table 6. Recommended operating conditions

Symbol Parameter Test conditions Min. Typ. Max. Unit

V

V

I

I

V

V

t

wLAT

t

wCLK

t

wEN

t

SETUP(D)

t

HOLD(D)

t

SETUP(L)

f

CLK

Supply voltage 3.0 - 5.5 V

DD

Output voltage - 20 V

O

Output current OUTn 3 - 40 mA

I

O

Output current SERIAL-OUT - +1 mA

OH

Output current SERIAL-OUT - -1 mA

OL

Input voltage 0.7 V

IH

Input voltage -0.3 - 0.3 V

IL

LE/DM1 pulse width

DD

20 - ns

-VDDV

CLK pulse width 10 - ns

OE/DM2 pulse width 100 - ns

VDD = 3.0 V to 5.0 V

Setup time for DATA 8 - ns

Hold time for DATA 5 - ns

Setup time for LATCH 8 - ns

Clock frequency Cascade operation

(1)

-30MHz

1. If the device is connected in cascade, it may not be possible achieve the maximum data transfer.
Please consider the timings carefully.

DD

V

6/34 Doc ID 15817 Rev 2

STP16DPPS05 Electrical characteristics

3 Electrical characteristics

VDD = 3.3 V to 5 V, TA = 25 °C, unless otherwise specified.

Table 7. Electrical characteristics

Symbol Parameter Test conditions Min. Typ. Max. Unit

V

V

I

OH

V

V

I

OL1

OL2

I

OL3

ΔI

OL1

OL2

ΔI

OL3

R

SIN(up)

R

SIN(down)

I

DD(OFF1)

Input voltage high level 0.7 V

IH

Input voltage low level GND 0.3 V

IL

DD

Output leakage current VOH = 20 V 1 μA

Output voltage

OL

(serial-OUT)

Output voltage

OH

(serial-OUT)

Output current

Output current error
between bit
(All output ON)

= 1 mA 0.4 V

I

OL

= -1 mA VDD-0.4V V

I

OH

= 0.3 V, R

V

O

VO = 0.3 V, R

VO = 1.3 V, R

VO = 0.3 V, IO = 5 mA

= 4 kΩ

R

EXT

VO = 0.3 V, IO = 20 mA
R

= 980 Ω

EXT

VO = 1.3 V, IO = 40 mA
R

= 490 Ω

EXT

= 4 kΩ 4.75 5 5.25

ext

= 1 kΩ 19 20 21

ext

= 497 Ω 38 40 42

ext

± 1 ± 5

± 0.5 ± 3

± 0.5 ± 3

Pull-up resistor 150 300 600 kΩ

Pull-down resistor 100 200 400 kΩ

R

= 1 kΩ,

EXT

I

= 20 mA,

OUT

5.4 7.5

V

DD

DD

OUT 0 to 15 = OFF

Supply current (OFF)

R

= 497 Ω,

I

DD(OFF2)

EXT

= 40 mA OUT 0 to

I

OUT

8.0 9.5

15 = OFF

R

= 1 kΩ,

I

DD(ON1)

I

OUT

EXT

= 20 mA,

5.5 7.5

OUT 0 to 15 = ON

Supply current (ON)

R

= 497 Ω,

I

DD(ON2)

EXT

I

= 40 mA OUT 0 to

OUT

8.1 9.5

15 = ON

Thermal Thermal protection 170 °C

V

V

mAI

%ΔI

mA

Doc ID 15817 Rev 2 7/34

Electrical characteristics STP16DPPS05

VDD = 3.3 V to 5 V, TA = 25 °C, unless otherwise specified.

Table 8. Switching characteristics

Symbol Parameter Test conditions Min Typ Max Unit

t

PLH1

t

PLH2

t

PLH3

t

PLH

t

PHL1

t

PHL2

t

PHL3

t

PHL

t

ON

Propagation delay time,
CLK-OUTn

, LE/DM1 = H,

OE/DM2 = L

Propagation delay time,
LE/DM1-OUTn

,

OE/DM2 = L

Propagation delay time,
OE/DM2

-OUTn, LE = H

Propagation delay time,
CLK-SDO

Propagation delay time,
CLK-OUTn, LE/DM1 = H,
OE/DM2

= L

Propagation delay time,
LE/DM1-OUTn,
OE/DM2

= L

Propagation delay time,
OE/DM2-OUTn,
LE/DM1 = H

Propagation delay time,
CLK-SDO

Output rise time
10~90% of voltage
waveform

VIH = V

DD

VIL = GND CL = 10 pF
IO = 20 mA VL = 3.0 V

= 1 KΩ RL = 60 Ω

R

EXT

VDD = 3.3 V 53.5 86.5

= 5 V 32 46.5

V

DD

V

= 3.3 V 48 75.5

DD

= 5 V 30 43

V

DD

VDD = 3.3 V 71.5 118

= 5 V 43 62

V

DD

= 3.3 V 15 21 31

V

DD

= 5 V 11 15 21

V

DD

V

= 3.3 V 27.5 39

DD

= 5 V 22 30.5

V

DD

V

= 3.3 V 11.5 17.5

DD

= 5 V 8 11.5

V

DD

VDD = 3.3 V 24 33.5

= 5 V 21 28.5

V

DD

= 3.3 V 17.5 24 36

V

DD

= 5 V 12.5 17 25

V

DD

VDD = 3.3 V 29 54

= 5 V 10 17

V

DD

ns

ns

ns

ns

ns

ns

ns

ns

ns

Output fall time

t

90~10% of voltage

OFF

waveform

CLK rise time

t

r

CLK fall time

t

f

1. In order to achieve high cascade data transfer, please consider tr/tf timings carefully.

(1)

(1)

8/34 Doc ID 15817 Rev 2

VDD = 3.3 V 4.5 6

= 5 V 3.5 5

V

DD

5000 ns

5000 ns

ns

STP16DPPS05 Equivalent circuit and outputs

4 Equivalent circuit and outputs

Figure 2. OE/DM2 terminal

Figure 3. LE/DM1 terminal

Figure 4. CLK, SDI terminal

Doc ID 15817 Rev 2 9/34

Equivalent circuit and outputs STP16DPPS05

Figure 5. SDO terminal

Figure 6. Block diagram

%.

%.&

10/34 Doc ID 15817 Rev 2

STP16DPPS05 Timing diagrams

5 Timing diagrams

Table 9. Truth table

CLOCK LE/DM1 OE/DM2 SERIAL-IN OUT0 ............. OUT7 ................ OUT15 SDO

H L Dn Dn ..... Dn - 7 ..... Dn -15 Dn - 15

L L Dn + 1 No change Dn - 14

H L Dn + 2 Dn + 2 ..... Dn - 5 ..... Dn -13 Dn - 13

X L Dn + 3 Dn + 2 ..... Dn - 5 ..... Dn -13 Dn - 13

X H Dn + 3 OFF Dn - 13

Note: OUTn = ON when Dn = H OUTn = OFF when Dn = L

Figure 7. Timing diagram

Note: 1 Latch and output enable terminals are level-sensitive and are not synchronized with rising or

falling edge of LE/DM1 signal.

2 When LE/DM1 terminal is low level, the latch circuit holds previous set of data.

3 When LE/DM1 terminal is high level, the latch circuit refreshes new set of data from SDI

chain.

4 When OE/DM2

terminal is at low level, the output terminals Out 0 to Out 15 respond to data

in the latch circuits, either ‘1’ for ON or ‘0’ for OFF.

5 When OE/DM2

terminal is at high level, all output terminals are switched OFF.

Doc ID 15817 Rev 2 11/34