ST STP16DPP05 User Manual

LED sink driver with output error detection

Features

■ Low voltage power supply down to 3 V

■ 16 constant current output channels

■ Adjustable output current through external

resistor

■ Short and open output error detection

■ Serial data IN/parallel data OUT

■ 3.3 V MCU-driving capability

■ Output current: 3 to 40 mA

■ 30 MHz clock frequency

■ Available in high thermal efficiency TSSOP

exposed pad

■ ESD protection: 2 kV HBM, 200 V MM

Description

The STP16DPP05 is a monolithic, low voltage,
low current power 16-bit shift register designed for
LED panel displays. The device features a 16-bit
serial-in, parallel-out shift register that feeds a
16-bit D-type storage register. In the output stage,
sixteen regulated current sources are designed to
provide 3 to 40 mA of constant current to drive the
LEDs. The STP16DPP05 features open and short
LED detection on the outputs. The detection
circuit checks for 3 different conditions that can
occur on the output line: short to GND, short to V
or open line.

Table 1. Device summary

O

STP16DPP05

Low voltage 16-bit constant current

QSOP-24

TSSOP24

The data detection results are loaded in the shift
registers and shifted out via the serial line output.

The detection functionality is implemented without
increasing the pin count, through a secondary
function of the output enable and latch pin (DM1
and DM2 respectively). A dedicated logic
sequence allows the device to enter or exit from
detection mode. The STP16DPP05 output current
can be adjusted through an external resistor to
control the light intensity of the LEDs.
LED brightness is adjustable from 0% to 100% via
the OE/DM2

pin.

The STP16DPP05 guarantees a 20 V output
driving capability, allowing users to connect more
LEDs in series. The high 30 MHz clock frequency
makes the device suitable for high data rate
transmission. The 3.3 V supply is well suited for
applications which interface a 3.3 V MCU.
Compared to a standard TSSOP package, the
TSSOP with exposed pad increases heat
dissipation capability by a factor of 2.5

SO-24

TSSOP24

(exposed pad)

Order codes Package Packaging

STP16DPP05MTR SO-24 (tape and reel) 1000 parts per reel

STP16DPP05TTR TSSOP24 (tape and reel) 2500 parts per reel

STP16DPP05XTTR

TSSOP24 exposed pad

(tape and reel)

2500 parts per reel

STP16DPP05PTR QSOP-24 2500 parts per reel

October 2009 Doc ID 16518 Rev 1 1/32

www.st.com

32

Contents STP16DPP05

Contents

1 Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1.1 Pin connection and description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.3 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

4 Equivalent circuit and outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

5 Timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

6 Typical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

7 Error detection mode functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

7.1 Phase one: entering error detection mode . . . . . . . . . . . . . . . . . . . . . . . . 18

7.2 Phase two: error detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

7.3 Phase three: resuming normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

7.4 Error detection conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

8 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

2/32 Doc ID 16518 Rev 1

STP16DPP05 Summary description

1 Summary description

Table 2. Typical current accuracy

Current accuracy

Output voltage

Between bits Between ICs

≥ 1.3 V ± 1% ± 2% 5 to 40 mA 3.3 V to 5 V 25 °C

1.1 Pin connection and description

Figure 1. Pin connection

Output current

V

DD

Temper atur e

Note: The exposed pad should be electrically connected to a metal land electrically isolated or

connected to ground.

Doc ID 16518 Rev 1 3/32

Summary description STP16DPP05

Table 3. Pin description

Pin n° Symbol Name and function

1 GND Ground terminal

2 SDI Serial data input terminal

3 CLK Clock input terminal

4 LE/DM1 Latch input terminal - detect mode 1 (see operation principle)

5-20 OUT 0-15

Output terminal

21 OE/DM2

Input terminal of output enable (active low) - detect mode 1
(see operation principle)

22 SDO Serial data out terminal

23 R-EXT

24 V

DD

Input terminal for an external resistor for constant current
programming

Supply voltage terminal

4/32 Doc ID 16518 Rev 1

STP16DPP05 Electrical ratings

2 Electrical ratings

2.1 Absolute maximum ratings

Stressing the device above the ratings listed in the “absolute maximum ratings” table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other condition above those indicated in the operating sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.

Table 4. Absolute maximum ratings

Symbol Parameter Value Unit

V

DD

V

I

O

V

I

GND

f

CLK

T

1. Such absolute value is based on the thermal shutdown protection.

Supply voltage 0 to 7 V

Output voltage -0.5 to 20 V

O

Output current 50 mA

Input voltage -0.4 to V

I

GND terminal current 800 mA

Clock frequency 50 MHz

Junction temperature range

J

2.2 Thermal data

Table 5. Thermal data

Symbol Parameter Value Unit

T

J-OPR

T

R

T

STG

thJA

Operating free-air temperature range -40 to +125 °C

A

Operating thermal junction temperature range -40 to +150 °C

Storage temperature range -55 to +150 °C

Thermal resistance junction­ambient

(1)

(1)

DD

-40 to +170 °C

SO-24 42.7 °C/W

TSSOP24 55 °C/W

(2)

TSSOP24

Exposed Pad

37.5 °C/W

V

QSOP-24 55 °C/W

1. According with JEDEC standard 51-7B

2. The exposed pad should be soldered directly to the PCB to obtain the thermal benefits.

Doc ID 16518 Rev 1 5/32

Electrical ratings STP16DPP05

2.3 Recommended operating conditions

Table 6. Recommended operating conditions

Symbol Parameter Test conditions Min. Typ. Max. Unit

V

V

I

I

V

V

t

wLAT

t

wCLK

t

wEN

t

SETUP(D)

t

HOLD(D)

t

SETUP(L)

f

CLK

Supply voltage 3.0 5.5 V

DD

Output voltage 20 V

O

Output current OUTn 3 40 mA

I

O

Output current SERIAL-OUT +1 mA

OH

Output current SERIAL-OUT -1 mA

OL

Input voltage 0.7 V

IH

Input voltage -0.3 0.3 V

IL

LE/DM1 pulse width

DD

20 ns

CLK pulse width 10 ns

OE/DM2 pulse width 100 ns

VDD = 3.0 V to 5.0 V

Setup time for DATA 8 ns

Hold time for DATA 5 ns

Setup time for LATCH 8 ns

Clock frequency Cascade operation

(1)

V

DD

30 MHz

1. If the device is connected in cascade, it may not be possible achieve the maximum data transfer.
Please consider the timings carefully.

DD

V

V

6/32 Doc ID 16518 Rev 1

STP16DPP05 Electrical characteristics

3 Electrical characteristics

VDD = 3.3 V to 5 V, TA = 25 °C, unless otherwise specified.

Table 7. Electrical characteristics

Symbol Parameter Test conditions Min. Typ. Max. Unit

V

V

I

OH

V

V

I

OL1

OL2

I

OL3

ΔI

OL1

OL2

ΔI

OL3

R

SIN(up)

R

SIN(down)

I

DD(OFF1)

Input voltage high level 0.7 V

IH

Input voltage low level GND 0.3 V

IL

DD

Output leakage current VOH = 20 V 1 μA

Output voltage

OL

(serial-OUT)

Output voltage

OH

(serial-OUT)

Output current

Output current error
between bit
(All output ON)

= 1 mA 0.4 V

I

OL

= -1 mA VDD-0.4V V

I

OH

= 0.3 V, R

V

O

VO = 0.3 V, R

VO = 1.3 V, R

VO = 0.3 V, IO = 5 mA

= 4 kΩ

R

EXT

VO = 0.3 V, IO = 20 mA
R

= 980 Ω

EXT

VO = 1.3 V, IO = 40 mA
R

= 490 Ω

EXT

= 4 kΩ 4.75 5 5.25

ext

= 1 kΩ 19 20 21

ext

= 497 Ω 38 40 42

ext

± 1 ± 5

± 0.5 ± 3

± 0.5 ± 3

Pull-up resistor 150 300 600 kΩ

Pull-down resistor 100 200 400 kΩ

R

= 1 kΩ,

EXT

I

= 20 mA,

OUT

5.4 7.5

V

DD

DD

OUT 0 to 15 = OFF

Supply current (OFF)

R

= 497 Ω,

I

DD(OFF2)

EXT

= 40 mA OUT 0 to

I

OUT

8.0 9.5

15 = OFF

R

= 1 kΩ,

I

DD(ON1)

I

OUT

EXT

= 20 mA,

5.5 7.5

OUT 0 to 15 = ON

Supply current (ON)

R

= 497 Ω,

I

DD(ON2)

EXT

I

= 40 mA OUT 0 to

OUT

8.1 9.5

15 = ON

Thermal Thermal protection 170 °C

V

V

mAI

%ΔI

mA

Doc ID 16518 Rev 1 7/32

Electrical characteristics STP16DPP05

VDD = 3.3 V to 5 V, TA = 25 °C, unless otherwise specified.

Table 8. Switching characteristics

Symbol Parameter Test conditions Min Typ Max Unit

t

PLH1

t

PLH2

t

PLH3

t

PLH

t

PHL1

t

PHL2

t

PHL3

t

PHL

t

ON

Propagation delay time,
CLK-OUTn

, LE/DM1 = H,

OE/DM2 = L

Propagation delay time,
LE/DM1-OUTn

,

OE/DM2 = L

Propagation delay time,
OE/DM2

-OUTn, LE = H

Propagation delay time,
CLK-SDO

Propagation delay time,
CLK-OUTn, LE/DM1 = H,
OE/DM2

= L

Propagation delay time,
LE/DM1-OUTn,
OE/DM2

= L

Propagation delay time,
OE/DM2-OUTn,
LE/DM1 = H

Propagation delay time,
CLK-SDO

Output rise time
10~90% of voltage
waveform

VIH = V

DD

VIL = GND CL = 10 pF
IO = 20 mA VL = 3.0 V

= 1 KΩ RL = 60 Ω

R

EXT

VDD = 3.3 V 35.5 44.5

= 5 V 18.5 24

V

DD

V

= 3.3 V 41.5 50

DD

= 5 V 23 29

V

DD

VDD = 3.3 V 45 54

= 5 V 25 31

V

DD

= 3.3 V 15 21 31

V

DD

= 5 V 11 15 21

V

DD

V

= 3.3 V 13.7 18

DD

= 5 V 8.8 12.5

V

DD

V

= 3.3 V 17 22

DD

= 5 V 13 17

V

DD

VDD = 3.3 V 12.7 17

= 5 V 9.5 13

V

DD

= 3.3 V 17.5 24 36

V

DD

= 5 V 12.5 17 25

V

DD

VDD = 3.3 V 28 39

= 5 V 17 23

V

DD

ns

ns

ns

ns

ns

ns

ns

ns

ns

Output fall time

t

90~10% of voltage

OFF

waveform

CLK rise time

t

r

CLK fall time

t

f

1. In order to achieve high cascade data transfer, please consider tr/tf timings carefully.

(1)

(1)

8/32 Doc ID 16518 Rev 1

VDD = 3.3 V 4.5 6

= 5 V 3.5 5

V

DD

5000 ns

5000 ns

ns

STP16DPP05 Equivalent circuit and outputs

4 Equivalent circuit and outputs

Figure 2. OE/DM2 terminal

Figure 3. LE/DM1 terminal

Figure 4. CLK, SDI terminal

Doc ID 16518 Rev 1 9/32

Equivalent circuit and outputs STP16DPP05

Figure 5. SDO terminal

Figure 6. Block diagram

%.

%.&

10/32 Doc ID 16518 Rev 1