The STP16DP05 is a monolithic, low voltage, low
current power 16-bit shift register designed for
LED panel displays. The device contains a 16-bit
serial-in, parallel-out shift register that feeds a
16-bit D-type storage register. In the output stage,
sixteen regulated current sources were designed
to provide 5-100 mA constant current to drive the
LEDs.
The STP16DP05 features open and short LED
detections on the outputs.The STP16DP05 is
backward compatible with STP16C/L596.The
detection circuit checks 3 different conditions that
can occur on the output line: short to GND, short
to V
or open line.
O
Table 1.Device summary
STP16DP05
Low voltage 16-bit constant current
QSOP-24
TSSOP24
The data detection results are loaded in the shift
register and shifted out via the serial line output.
The detection functionality is implemented without
increasing the pin count number, through a
secondary function of the output enable and latch
pin (DM1 and DM2 respectively), a dedicated
logic sequence allows the device to enter or leave
from detection mode. Through an external
resistor, users can adjust the STP16DP05 output
current, controlling in this way the light intensity of
LEDs, in addition, user can adjust LED’s
brightness intensity from 0% to 100% via
pin.
The STP16DP05 guarantees a 20 V output
driving capability, allowing users to connect more
LEDs in series. The high clock frequency,
30 MHz, makes the device suitable for high data
rate transmission. The 3.3 V voltage supply is well
useful for applications that interface any 3.3V
micro. Compared with a standard TSSOP
package, the TSSOP exposed pad increases heat
dissipation capability by a 2.5 factor.
SO-24
TSSOP24
(exposed pad)
OE/DM2
Order codesPackagePackaging
STP16DP05MTR SO-24 (tape and reel)1000 parts per reel
STP16DP05TTRTSSOP24 (tape and reel)2500 parts per reel
Note:The exposed pad should be electrically connected to a metal land electrically isolated or
connected to ground
Table 3.Pin description
Pin n°SymbolName and function
1GNDGround terminal
2SDISerial data input terminal
3CLKClock input terminal
4LE-DM1Latch input terminal - detect mode 1 (see operation principle)
5-20OUT 0-15Output terminal
21OE-DM2
22SDOSerial data out terminal
23R-EXTInput terminal of an external resistor for constant current programing
24V
DD
Input terminal of output enable (active low) - detect mode 1
(see operation principle)
Supply voltage terminal
Doc ID 13093 Rev 63/31
Electrical ratingsSTP16DP05
2 Electrical ratings
2.1 Absolute maximum ratings
Stressing the device above the rating listed in the “absolute maximum ratings” table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the operating sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Table 4.Absolute maximum ratings
SymbolParameterValueUnit
V
V
I
V
I
GND
f
CLK
DD
O
Supply voltage0 to 7V
Output voltage -0.5 to 20V
O
Output current100mA
Input voltage-0.4 to V
I
GND terminal current1600mA
Clock frequency50MHz
2.2 Thermal data
Table 5.Thermal data
SymbolParameterValueUnit
T
OPR
T
STG
R
thJC
1. The exposed pad should be soldered directly to the PCB to realize the thermal benefits.
Operating temperature range-40 to +125°C
Storage temperature range-55 to +150°C
Thermal resistance junction-case
DD
SO-2442.7°C/W
TSSOP2455°C/W
(1)
TSSOP24
exposed pad
37.5°C/W
QSOP-2455°C/W
V
4/31 Doc ID 13093 Rev 6
STP16DP05Electrical ratings
2.3 Recommended operating conditions
Table 6.Recommended operating conditions
SymbolParameterTest conditionsMin.Typ.Max.Unit
V
V
I
I
V
V
t
wLAT
t
wCLK
t
wEN
t
SETUP(D)
t
HOLD(D)
t
SETUP(L)
f
CLK
Supply voltage3.0-5.5V
DD
Output voltage-20V
O
Output currentOUTn5-100mA
I
O
Output currentSERIAL-OUT-+1mA
OH
Output currentSERIAL-OUT--1mA
OL
Input voltage0.7V
IH
Input voltage-0.3-0.3V
IL
LE\DM1 pulse width
DD
6-ns
-VDD+0.3V
CLK pulse width8-ns
OE\DM2 pulse width100-ns
VDD = 3.0 V to 5.0 V
Setup time for DATA10-ns
Hold time for DATA5-ns
Setup time for LATCH10-ns
Clock frequencyCascade operation
(1)
-30MHz
1. If the device is connected in cascade, it may not be possible achieve the maximum data transfer.
Please consider the timings carefully.
DD
V
Doc ID 13093 Rev 65/31
Electrical characteristicsSTP16DP05
3 Electrical characteristics
VDD = 3.3 V to 5 V, T = 25 °C, unless otherwise specified
Table 7.Electrical characteristics
SymbolParameterTest conditionsMin.Typ.Max.Unit
V
V
I
OH
V
OL
V
OH
I
OL1
OL2
I
OL3
ΔI
OL1
OL2
ΔI
OL3
R
SIN(up)
R
SIN(down)
I
DD(OFF1)
Input voltage high level0.7V
IH
Input voltage low levelGND0.3V
IL
Output leakage currentVOH = 20 V1μA
Output voltage
(Serial-OUT)
Output voltage
(Serial-OUT)
Output current
I
= 1 mA0.4V
OL
= -1 mAVOH -VDD = -0.4 VV
I
OH
= 0.3 V, R
V
O
VO = 0.3 V, R
VO = 1.3 V, R
V
= 0.3 VR
Output current error
between bit
(all output ON)
O
VO = 0.3 VR
VO = 1.3 VR
Pull-up resistor150300600KΩ
Pull-down resistor100200400KΩ
R
= 970
EXT
OUT 0 to 15 = OFF
Supply current (OFF)
R
= 240
I
DD(OFF2)
I
DD(ON1)
EXT
OUT 0 to 15 = OFF
R
= 970
EXT
OUT 0 to 15 = ON
Supply current (ON)
R
= 240
I
DD(ON2)
ThermalThermal protection
1. Guaranteed by design (not tested)
The thermal protection switches OFF only the outputs current
(1)
EXT
OUT 0 to 15 = ON
DD
= 3.9 kΩ4.2555.75
ext
= 970 Ω192021
ext
= 190 Ω96100104
ext
= 3.9 kΩ± 5± 8
EXT
= 970 Ω± 1.5± 3
EXT
=190 Ω± 1.2± 3
EXT
56
1314
67
13.514.5
170°C
V
DD
DD
V
V
mAI
%ΔI
mA
6/31 Doc ID 13093 Rev 6
STP16DP05Electrical characteristics
V
= 5 V, T = 25 °C, unless otherwise specified
DD
Table 8.Switching characteristics
SymbolParameterTest conditionsMin.Typ.Max. Unit
Propagation delay time,
t
PLH1
CLK-OUTn
, LE\DM1 = H,
OE\DM2 = L
Propagation delay time,
t
PLH2
LE\DM1 -OUTn
,
OE\DM2 = L
Propagation delay time,
t
PLH3
OE\DM2
-OUTn,
LE\DM1 = H
t
Propagation delay time,
PLH
CLK-SDO
Propagation delay time,
t
PHL1
t
PHL2
CLK-OUTn
, LE\DM1 = H,
OE\DM2 = L
Propagation delay time,
LE\DM1 -OUTn
,
VIH = V
DD
VIL = GND CL = 10 pF
= 20 mA VL = 3.0 V
I
O
= 1 KΩRL = 60 Ω
R
EXT
OE\DM2 = L
Propagation delay time,
t
PHL3
OE\DM2
-OUTn,
LE\DM1 = H
t
Propagation delay time,
PHL
CLK-SDO
Output rise time
10~90% of voltage
t
ON
waveform
Output fall time
t
90~10% of voltage
OFF
waveform
CLK rise time
t
r
CLK fall time
t
f
1. In order to achieve high cascade data transfer, please consider tr/tf timings carefully.
Note:1Latch and output enable are level sensitive and ARE NOT synchronized with rising-or-falling
edge of CALK signal.
2When LE terminal is low level, the latch circuits hold previous set of data
3When LE terminal is at high level, the latch circuits refresh new set of data from SDI chain.
4When OE terminal is at low level, the output terminals - Out0 to Out15 respond to data in the
latch circuits, either '1' for ON or '0' for OFF
5When OE terminal is at high level, all output terminals will be switched OFF.
10/31 Doc ID 13093 Rev 6
STP16DP05Timing diagrams
Figure 8.Clock, serial-in, serial-out
Doc ID 13093 Rev 611/31
Timing diagramsSTP16DP05
Figure 9.Clock, serial-in, latch, enable, outputs
LE\DM1
OE\DM2
Figure 10. Outputs
12/31 Doc ID 13093 Rev 6
STP16DP05Typical characteristics
6 Typical characteristics
Figure 11. Output current-R
Table 10.Output current-R
EXT
EXT
resistor
resistor
Rext (Ω)Output current (mA)
97620
78025
65230
56035
48840
43345
38950
35455
32560
30065
27870
25975
24180
22985
21590
Doc ID 13093 Rev 613/31
Typical characteristicsSTP16DP05
Conditions:
Temperature = 25 °C, V
= 3.3 V; 5.0 V, I
DD
= 3 mA; 5 mA; 10 mA; 20 mA; 50 mA; 80 mA.
SET
Figure 12. I
Table 11.I
Iout (mA)Avg @ 3.0 VAvg @ 5.0 V
vs drop out voltage (V
SET
drop
)
800
700
600
500
400
300
Vdrop (mV)
200
Avg @ 3.0V
Avg @ 5.0V
100
0
0 20406080
Iset mA )
vs drop out voltage (V
SET
drop
)
319.3322.66
536.6740.33
1077.3380
20158.67157.33
50406406
80692668
14/31 Doc ID 13093 Rev 6
STP16DP05Typical characteristics
Figure 13. I
ON\OFF
DD
14
12
10
8
6
Idd (mA)
4
2
0
0 102030405060708090
Ise t ( mA)
Figure 14. Power dissipation vs temperature package
IddON Avg @ 5.5V
IddON Avg @ 3.6V
IddOFF Avg @ 5.5V
IddOFF Avg @ 3.6V
Note:The exposed pad should be soldered to the PBC to realize the thermal benefits.
Doc ID 13093 Rev 615/31
Detection mode functionalitySTP16DP05
7 Detection mode functionality
7.1 Phase one: “entering in detection mode“
From the “normal mode” condition the device can switch to the “error mode” by a logic
sequence on the OE\DM2
Table 12.Entering in detection truth table
CLK1°2°3°4°5°
and LE/DM1 pins as showed in the following table and diagram:
OE/DM2
HLHHH
LE/DM1LLLHL
Figure 15. Entering in detection timing diagram
After these five CLK cycles the device goes into the “error detection mode” and at the 6th
rise front of CLK the SDI data are ready for the sampling.
16/31 Doc ID 13093 Rev 6
STP16DP05Detection mode functionality
7.2 Phase two: “error detection”
The 16 data bits must be set “1” in order to set ON all the outputs during the detection. The
data are latched by LE/DM1 and after that the outputs are ready for the detection process.
When the micro controller switches the OE\DM2
order to analyze if an OPEN or SHORT condition has occurred.
Figure 16. Detection diagram
to LOW, the device drives the LEDs in
The LEDs status will be detected at least in 1 microsecond and after this time the
microcontroller sets OE\DM2
in HIGH state and the output data detection result will go to
the microprocessor via SDO.
Detection mode and normal mode use both the same format data. As soon as all the
detection data bits are available on the serial line, the device may go back to normal mode
of operation. To re-detect the status the device must go back in normal mode and reentering in error detection mode.
Doc ID 13093 Rev 617/31
Detection mode functionalitySTP16DP05
Figure 17. Timing example for open and/or short detection
18/31 Doc ID 13093 Rev 6
STP16DP05Detection mode functionality
7.3 Phase three: “resuming to normal mode”
The sequence for re-entering in normal mode is showed in the following table and diagram:
Figure 18. Resuming to normal mode timing diagram
CLK1°2°3°4°5°
OE/DM2
HLHHH
LE/DM1LLLLL
Note:For proper device operation the “Entering in detection” sequence must be follow by a
“resume mode” sequence, it is not possible to insert consecutive equal sequence.
7.4 Error detection conditions
VDD = 3.3 to 5 V temperature range -40 to 125 °C
Table 13.Detection conditions
SW-1 or
SW-3b
SW-2 or
SW-3a
Note:Where: IO = the output current programmed by the R
current in detection mode
Open line or output
short to GND detected
Short on LED or short
to V-LED detected
==> I
==> V
ODEC
≥ 2.4 V
O
≤ 0.5 x I
No error detected
O
No error detected
, I
EXT
ODEC
ODEC
≥ 0.5 x I
==> I
==> VO ≤ 2.2 V
= the detected output
O
Doc ID 13093 Rev 619/31
Detection mode functionalitySTP16DP05
Figure 19. Detection circuit
16
STP16DP05
20/31 Doc ID 13093 Rev 6
STP16DP05Detection mode functionality
Figure 20. Error detection sequence
During the error
During the error
dete ctio n are
16 CLK pulse are required to
16 CLK pulse are required to
load the data setting 1 into
load the data setting 1 into
shift re gister
shift re gister
dete ctio n are
necessary at least
necessary at least
2 CLK si gnal plus
2 CLK si gnal plus
oneat the end
oneat the end
Every C LK pulse shows the re sults of
Every C LK pulse shows the re sults of
single O utput resu lts:Out 15;14; 13 etc. etc
single O utput resu lts:Out 15;14; 13 etc. etc
The OE Pulse put
The LE pulse
LE and OE Key
LE and OE Key
Sequence
Sequence
necessary to Enter
necessary to Enter
in EDM
in EDM
The LE pulse
latch the data
latch the data
loaded during the
loaded during the
previous state
previous state
After OE signal turn High the
After OE signal turn High the
SDO pin sh ow the resul ts of
SDO pin sh ow the resul ts of
Error Detection (Open or
Error Detection (Open or
Short in this case)
Short in this case)
The OE Pulse put
the device from
the device from
EDM to Normal
EDM to Normal
Mode
Mode
Doc ID 13093 Rev 621/31
Package mechanical dataSTP16DP05
8 Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK
®
packages, depending on their level of environmental compliance. ECOPACK®
®
is an ST trademark
.
Table 14.QSOP-24 mechanical data
mm. inch
Dim.
Min.Typ.Max. Min.Typ.Max.
A 1.541.621.730.0610.0640.068
A1 0.10.150.250.0040.0060.010
A2 1.470.058
b 0.310.2 0.0120.008
c 0.2540.17 0.0100.007
D 8.568.668.760.3370.3410.345
E 5.8 6 6.20.2280.2360.244
E1 3.83.914.010.1500.1540.158
e 0.6350.025
L 0.40.6350.890.0160.0250.035
h 0.250.330.410.0100.0130.016
< 8° 0°
22/31 Doc ID 13093 Rev 6
STP16DP05Package mechanical data
Figure 21. QSOP-24 package dimensions
Doc ID 13093 Rev 623/31
Package mechanical dataSTP16DP05
Table 15.QSOP-24 tape and reel
mm. inch
Dim.
MinTypMaxMinTypMax
R112.81313.55.0395.1185.315
R2330129.921
R310039.37
eint16.46.457
e11.522.50.5910.7870.984
Table 16.QSOP-24 tape and reel dimensions
0.3+/-0.05
0.3+/-0.05
1
1
0
0
.
.
3
3
+
+
/
/
-
0
0
.
.
1
1
2.1 +/-0.1
2.1 +/-0.1
6
6
.
.
5
5
+
+
/
/
-
-
24/31 Doc ID 13093 Rev 6
1.5+1/0
1.5+1/0
0
0
.
.
1
1
2.0+/-0.1
2.0+/-0.1
8 +/-0.1
8 +/-0.1
4.0+/-0.1
4.0+/-0.1
1.75+/-0.1
1.75+/-0.1
1.6 +1/-0.1
1.6 +1/-0.1
7.5+/-0.1
7.5+/-0.1
16 +/-0.3
16 +/-0.3
7217811_C
STP16DP05Package mechanical data
Table 17.TSSOP24 mechanical data
mm. inch
Dim.
Min.Typ.Max.Min.Typ.Max.
A 1.1 0.043
A1 0.05 0.15 0.002 0.006
A2 0.9 0.035
b 0.19 0.30 0.0075 0.0118
c 0.09 0.20 0.0035 0.0079
D 7.7 7.9 0.303 0.311
E 4.3 4.5 0.169 0.177
e 0.65 BSC 0.0256 BSC
H 6.25 6.5 0.246 0.256
K 0° 8° 0° 8°
L 0.50 0.70 0.020 0.028
Figure 22. TSSOP24 package dimensions
Doc ID 13093 Rev 625/31
Package mechanical dataSTP16DP05
Table 18.Tape and reel TSSOP24
mm. inch
Dim.
Min.Typ.Max.Min.Typ.Max.
A 330 12.992
C 12.8 13.2 0.504 0.519
D 20.2 0.795
N 60 2.362
T 22.4 0.882
Ao 6.8 7 0.268 0.276
Bo 8.2 8.4 0.323 0.331
Ko 1.7 1.9 0.067 0.075
Po 3.9 4.1 0.153 0.161
P 11.9 12.1 0.468 0.476
Figure 23. Reel dimensions
26/31 Doc ID 13093 Rev 6
STP16DP05Package mechanical data
Table 19.SO-24 mechanical data
mm. inch
Dim.
Min.Typ.Max.Min.Typ.Max.
A 2.65 0.104
a1 0.1 0.2 0.004 0.008
a2 2.45 0.096
b 0.35 0.49 0.014 0.019
b1 0.23 0.32 0.009 0.012
C 0.5 0.020
c1 45°(typ.)
D 15.20 15.60 0.598 0.614
E 10.00 10.65 0.393 0.419
e 1.27 0.050
e3 13.97 0.550
F 7.40 7.60 0.291 0.300
L 0.50 1.27 0.020 0.050
S °(max.) 8
Figure 24. SO-24 package dimensions
Doc ID 13093 Rev 627/31
Package mechanical dataSTP16DP05
Table 20.Tape and reel SO-24
mm. inch
Dim.
Min.Typ.Max.Min.Typ.Max.
A 330 12.992
C 12.8 13.2 0.504 0.519
D 20.2 0.795
N 60 2.362
T 30.4 1.197
Ao 10.8 11.0 0.425 0.433
Bo 15.7 15.9 0.618 0.626
Ko 2.9 3.1 0.114 0.122
Po 3.9 4.1 0.153 0.161
P 11.9 12.1 0.468 0.476
Figure 25. Reel dimensions
28/31 Doc ID 13093 Rev 6
STP16DP05Package mechanical data
Table 21.TSSOP24 exposed pad
mm inch
Dim.
Min.Typ.Max.Min.Typ.Max.
A 1.2 0.047
A1 0.15 0.004 0.006
A2 0.8 1 1.05 0.031 0.039 0.041
b 0.19 0.30 0.007 0.012
c 0.09 0.20 0.004 0.0089
D 7.7 7.8 7.9 0.303 0.307 0.311
D1 4.7 5.05.30.1850.1970.209
E 6.2 6.4 6.6 0.244 0.252 0.260
E1 4.3 4.4 4.5 0.169 0.173 0.177
E2 2.93.23.50.1140.1260.138
e 0.65 0.0256
K 0° 8° 0° 8°
L 0.45 0.60 0.75 0.018 0.024 0.030
Figure 26. TSSOP24 dimensions
Doc ID 13093 Rev 629/31
Revision historySTP16DP05
9 Revision history
Table 22.Document revision history
DateRevisionChanges
9-Jan-20071First release
21-May-20072Updated Table 7 on page 6
10-Jul-20073Updated Table 9: Truth table on page 10
Updated Table 15: TSSOP24 exposed-pad on page 23
28-Feb-20084
23-Oct-20095Updated Figure 7 on page 10, Chapter 3 on page 6
20-Jan-20106Updated Table 5 on page 4
Added QSOP-24 package information Ta bl e 1 4 and Figure 21
on page 23
30/31 Doc ID 13093 Rev 6
STP16DP05
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