ST STP16DP05 User Manual
LED sink driver with outputs error detection
Features
■ Low voltage power supply down to 3 V
■ 16 constant current output channels
■ Adjustable output current through external
resistor
■ Short and open output error detection
■ Serial data IN/Parallel data OUT
■ 3.3 V micro driver-able
■ Output current: 5-100 mA
■ 30 MHz clock frequency
■ Available in high thermal efficiency TSSOP
exposed pad
■ ESD protection 2.5 kV HBM, 200 V MM
Description
The STP16DP05 is a monolithic, low voltage, low
current power 16-bit shift register designed for
LED panel displays. The device contains a 16-bit
serial-in, parallel-out shift register that feeds a
16-bit D-type storage register. In the output stage,
sixteen regulated current sources were designed
to provide 5-100 mA constant current to drive the
LEDs.
The STP16DP05 features open and short LED
detections on the outputs.The STP16DP05 is
backward compatible with STP16C/L596.The
detection circuit checks 3 different conditions that
can occur on the output line: short to GND, short
to V
or open line.
O
Table 1. Device summary
STP16DP05
Low voltage 16-bit constant current
QSOP-24
TSSOP24
The data detection results are loaded in the shift
register and shifted out via the serial line output.
The detection functionality is implemented without
increasing the pin count number, through a
secondary function of the output enable and latch
pin (DM1 and DM2 respectively), a dedicated
logic sequence allows the device to enter or leave
from detection mode. Through an external
resistor, users can adjust the STP16DP05 output
current, controlling in this way the light intensity of
LEDs, in addition, user can adjust LED’s
brightness intensity from 0% to 100% via
pin.
The STP16DP05 guarantees a 20 V output
driving capability, allowing users to connect more
LEDs in series. The high clock frequency,
30 MHz, makes the device suitable for high data
rate transmission. The 3.3 V voltage supply is well
useful for applications that interface any 3.3V
micro. Compared with a standard TSSOP
package, the TSSOP exposed pad increases heat
dissipation capability by a 2.5 factor.
SO-24
TSSOP24
(exposed pad)
OE/DM2
Order codes Package Packaging
STP16DP05MTR SO-24 (tape and reel) 1000 parts per reel
STP16DP05TTR TSSOP24 (tape and reel) 2500 parts per reel
STP16DP05XTTR
TSSOP24 exposed pad
(tape and reel)
2500 parts per reel
STP16DP05PTR QSOP-24 2500 parts per reel
January 2010 Doc ID 13093 Rev 6 1/31
www.st.com
31
Contents STP16DP05
Contents
1 Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1 Pin connection and description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.3 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4 Equivalent circuit and outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
5 Timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
6 Typical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
7 Detection mode functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
7.1 Phase one: “entering in detection mode“ . . . . . . . . . . . . . . . . . . . . . . . . . 16
7.2 Phase two: “error detection” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
7.3 Phase three: “resuming to normal mode” . . . . . . . . . . . . . . . . . . . . . . . . . 19
7.4 Error detection conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
8 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
2/31 Doc ID 13093 Rev 6
STP16DP05 Summary description
1 Summary description
Table 2. Typical current accuracy
Output voltage
Current accuracy
Between bits Between ICs
≥ 1.3 V ±1.5% ±5% 20 to 100 mA 3.3 V to 5 V 25 °C
1.1 Pin connection and description
Figure 1. Pin connection
Output current
V
DD
Temper atur e
Note: The exposed pad should be electrically connected to a metal land electrically isolated or
connected to ground
Table 3. Pin description
Pin n° Symbol Name and function
1 GND Ground terminal
2 SDI Serial data input terminal
3 CLK Clock input terminal
4 LE-DM1 Latch input terminal - detect mode 1 (see operation principle)
5-20 OUT 0-15 Output terminal
21 OE-DM2
22 SDO Serial data out terminal
23 R-EXT Input terminal of an external resistor for constant current programing
24 V
DD
Input terminal of output enable (active low) - detect mode 1
(see operation principle)
Supply voltage terminal
Doc ID 13093 Rev 6 3/31
Electrical ratings STP16DP05
2 Electrical ratings
2.1 Absolute maximum ratings
Stressing the device above the rating listed in the “absolute maximum ratings” table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the operating sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Table 4. Absolute maximum ratings
Symbol Parameter Value Unit
V
V
I
V
I
GND
f
CLK
DD
O
Supply voltage 0 to 7 V
Output voltage -0.5 to 20 V
O
Output current 100 mA
Input voltage -0.4 to V
I
GND terminal current 1600 mA
Clock frequency 50 MHz
2.2 Thermal data
Table 5. Thermal data
Symbol Parameter Value Unit
T
OPR
T
STG
R
thJC
1. The exposed pad should be soldered directly to the PCB to realize the thermal benefits.
Operating temperature range -40 to +125 °C
Storage temperature range -55 to +150 °C
Thermal resistance junction-case
DD
SO-24 42.7 °C/W
TSSOP24 55 °C/W
(1)
TSSOP24
exposed pad
37.5 °C/W
QSOP-24 55 °C/W
V
4/31 Doc ID 13093 Rev 6
STP16DP05 Electrical ratings
2.3 Recommended operating conditions
Table 6. Recommended operating conditions
Symbol Parameter Test conditions Min. Typ. Max. Unit
V
V
I
I
V
V
t
wLAT
t
wCLK
t
wEN
t
SETUP(D)
t
HOLD(D)
t
SETUP(L)
f
CLK
Supply voltage 3.0 - 5.5 V
DD
Output voltage - 20 V
O
Output current OUTn 5 - 100 mA
I
O
Output current SERIAL-OUT - +1 mA
OH
Output current SERIAL-OUT - -1 mA
OL
Input voltage 0.7V
IH
Input voltage -0.3 - 0.3V
IL
LE\DM1 pulse width
DD
6- ns
-VDD+0.3 V
CLK pulse width 8 - ns
OE\DM2 pulse width 100 - ns
VDD = 3.0 V to 5.0 V
Setup time for DATA 10 - ns
Hold time for DATA 5 - ns
Setup time for LATCH 10 - ns
Clock frequency Cascade operation
(1)
-30MHz
1. If the device is connected in cascade, it may not be possible achieve the maximum data transfer.
Please consider the timings carefully.
DD
V
Doc ID 13093 Rev 6 5/31
Electrical characteristics STP16DP05
3 Electrical characteristics
VDD = 3.3 V to 5 V, T = 25 °C, unless otherwise specified
Table 7. Electrical characteristics
Symbol Parameter Test conditions Min. Typ. Max. Unit
V
V
I
OH
V
OL
V
OH
I
OL1
OL2
I
OL3
ΔI
OL1
OL2
ΔI
OL3
R
SIN(up)
R
SIN(down)
I
DD(OFF1)
Input voltage high level 0.7V
IH
Input voltage low level GND 0.3V
IL
Output leakage current VOH = 20 V 1 μA
Output voltage
(Serial-OUT)
Output voltage
(Serial-OUT)
Output current
I
= 1 mA 0.4 V
OL
= -1 mA VOH -VDD = -0.4 V V
I
OH
= 0.3 V, R
V
O
VO = 0.3 V, R
VO = 1.3 V, R
V
= 0.3 VR
Output current error
between bit
(all output ON)
O
VO = 0.3 VR
VO = 1.3 VR
Pull-up resistor 150 300 600 KΩ
Pull-down resistor 100 200 400 KΩ
R
= 970
EXT
OUT 0 to 15 = OFF
Supply current (OFF)
R
= 240
I
DD(OFF2)
I
DD(ON1)
EXT
OUT 0 to 15 = OFF
R
= 970
EXT
OUT 0 to 15 = ON
Supply current (ON)
R
= 240
I
DD(ON2)
Thermal Thermal protection
1. Guaranteed by design (not tested)
The thermal protection switches OFF only the outputs current
(1)
EXT
OUT 0 to 15 = ON
DD
= 3.9 kΩ 4.25 5 5.75
ext
= 970 Ω 19 20 21
ext
= 190 Ω 96 100 104
ext
= 3.9 kΩ ± 5 ± 8
EXT
= 970 Ω ± 1.5 ± 3
EXT
=190 Ω ± 1.2 ± 3
EXT
56
13 14
67
13.5 14.5
170 °C
V
DD
DD
V
V
mAI
%ΔI
mA
6/31 Doc ID 13093 Rev 6
STP16DP05 Electrical characteristics
V
= 5 V, T = 25 °C, unless otherwise specified
DD
Table 8. Switching characteristics
Symbol Parameter Test conditions Min. Typ. Max. Unit
Propagation delay time,
t
PLH1
CLK-OUTn
, LE\DM1 = H,
OE\DM2 = L
Propagation delay time,
t
PLH2
LE\DM1 -OUTn
,
OE\DM2 = L
Propagation delay time,
t
PLH3
OE\DM2
-OUTn,
LE\DM1 = H
t
Propagation delay time,
PLH
CLK-SDO
Propagation delay time,
t
PHL1
t
PHL2
CLK-OUTn
, LE\DM1 = H,
OE\DM2 = L
Propagation delay time,
LE\DM1 -OUTn
,
VIH = V
DD
VIL = GND CL = 10 pF
= 20 mA VL = 3.0 V
I
O
= 1 KΩ RL = 60 Ω
R
EXT
OE\DM2 = L
Propagation delay time,
t
PHL3
OE\DM2
-OUTn,
LE\DM1 = H
t
Propagation delay time,
PHL
CLK-SDO
Output rise time
10~90% of voltage
t
ON
waveform
Output fall time
t
90~10% of voltage
OFF
waveform
CLK rise time
t
r
CLK fall time
t
f
1. In order to achieve high cascade data transfer, please consider tr/tf timings carefully.
(1)
(1)
VDD = 3.3 V - 40 65
= 5 V - 20 30
V
DD
V
= 3.3 V - 51 77
DD
= 5 V - 32 47
V
DD
V
= 3.3 V - 49 77
DD
= 5 V - 27 41
V
DD
= 3.3 V - 21.5 32
V
DD
= 5 V - 14.5 21.5
V
DD
V
= 3.3 V - 15 25
DD
= 5 V - 11 14.5
V
DD
V
= 3.3 V - 13 20
DD
= 5 V - 9 12.5
V
DD
V
= 3.3 V - 11.5 18
DD
= 5 V - 8.5 12
V
DD
= 3.3 V - 25.5 38
V
DD
= 5 V - 17.5 25
V
DD
VDD = 3.3 V - 34 53.5
= 5 V - 12.5 18.5
V
DD
VDD = 3.3 V - 5.5 8.5
= 5 V - 4.5 6.5
V
DD
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
- 5000 ns
- 5000 ns
Doc ID 13093 Rev 6 7/31
Equivalent circuit and outputs STP16DP05
4 Equivalent circuit and outputs
Figure 2. OE\DM2 terminal
Figure 3. LE\DM1 terminal
Figure 4. CLK, SDI terminal
8/31 Doc ID 13093 Rev 6
STP16DP05 Equivalent circuit and outputs
Figure 5. SDO terminal
Figure 6. Block diagram
Doc ID 13093 Rev 6 9/31
Timing diagrams STP16DP05
5 Timing diagrams
Table 9. Truth table
CLOCK LE\DM1 OE\DM2 SERIAL-IN OUT0 ............. OUT7 ................ OUT15 SDO
H L Dn Dn ..... Dn - 7 ..... Dn -15 Dn - 15
L L Dn + 1 No change Dn - 14
H L Dn + 2 Dn + 2 ..... Dn - 5 ..... Dn -13 Dn - 13
X L Dn + 3 Dn + 2 ..... Dn - 5 ..... Dn -13 Dn - 13
X H Dn + 3 OFF Dn - 13
Note: OUTn = ON when Dn = H OUTn = OFF when Dn = L
Figure 7. Timing diagram
Note: 1 Latch and output enable are level sensitive and ARE NOT synchronized with rising-or-falling
edge of CALK signal.
2 When LE terminal is low level, the latch circuits hold previous set of data
3 When LE terminal is at high level, the latch circuits refresh new set of data from SDI chain.
4 When OE terminal is at low level, the output terminals - Out0 to Out15 respond to data in the
latch circuits, either '1' for ON or '0' for OFF
5 When OE terminal is at high level, all output terminals will be switched OFF.
10/31 Doc ID 13093 Rev 6
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