The STP16CPPS05 is a monolithic, low voltage,
low current power 16-bit shift register designed for
LED panel displays. The device features a 16-bit
serial-in, parallel-out shift register that feeds a
16-bit D-type storage register. In the output stage,
sixteen regulated current sources are designed to
provide 3 to 40 mA of constant current to drive the
LEDs.
Table 1.Device summary
STP16CPPS05
Low voltage 16-bit constant current
Preliminary data
QSOP-24
TSSOP24
The STP16CPPS05 output current can be
adjusted through an external resistor to control
the light intensity of the LEDs.
LED brightness is adjustable from 0% to 100% via
the
OE pin.
The auto power-shutdown and auto power-ON
feature allows the device to save power with no
external intervention.
The STP16CPPS05 guarantees a 20 V output
driving capability, allowing users to connect more
LEDs in series. The high 30 MHz clock frequency
makes the device suitable for high data rate
transmission. The 3.3 V supply is well suited for
applications which interface a 3.3 V MCU.
Compared to a standard TSSOP package, the
TSSOP with exposed pad increases heat
dissipation capability by a factor of 2.5
SO-24
TSSOP24
(exposed pad)
Order codesPackagePackaging
STP16CPPS05MTR SO-24 1000 parts per reel
STP16CPPS05TTRTSSOP24 2500 parts per reel
STP16CPPS05XTTRTSSOP24 exposed pad2500 parts per reel
STP16CPPS05PTRQSOP-242500 parts per reel
October 2009Doc ID 16536 Rev 11/29
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to
change without notice.
Note:The exposed pad should be electrically connected to a metal land electrically isolated or
connected to ground.
Doc ID 16536 Rev 13/29
Summary descriptionSTP16CPPS05
Table 3.Pin description
Pin n°SymbolName and function
1GNDGround terminal
2SDISerial data input terminal
3CLKClock input terminal
4LELatch input terminal - detect mode 1 (see operation principle)
5-20OUT 0-15
Output terminal
21OE
Input terminal of output enable (active low) - detect mode 1
(see operation principle)
22SDOSerial data out terminal
23R-EXT
24V
DD
Input terminal for an external resistor for constant current
programming
Supply voltage terminal
4/29 Doc ID 16536 Rev 1
STP16CPPS05Electrical ratings
2 Electrical ratings
2.1 Absolute maximum ratings
Stressing the device above the ratings listed in the “absolute maximum ratings” table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other condition above those indicated in the operating sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
Table 4.Absolute maximum ratings
SymbolParameterValueUnit
V
DD
V
I
O
V
I
GND
f
CLK
T
1. Such absolute value is based on the thermal shutdown protection.
Supply voltage0 to 7V
Output voltage -0.5 to 20V
O
Output current50mA
Input voltage-0.4 to V
I
GND terminal current800mA
Clock frequency50MHz
Junction temperature range
J
2.2 Thermal data
Table 5.Thermal data
SymbolParameterValueUnit
T
J-OPR
T
R
T
STG
thJA
Operating free-air temperature range-40 to +125°C
A
Operating thermal junction temperature range-40 to +150°C
Storage temperature range -55 to +150°C
Thermal resistance junctionambient
(1)
(1)
DD
-40 to +170°C
SO-2442.7°C/W
TSSOP2455°C/W
(2)
TSSOP24
Exposed Pad
37.5°C/W
V
QSOP-2455°C/W
1. According with JEDEC standard 51-7B
2. The exposed pad should be soldered directly to the PCB to obtain the thermal benefits.
Doc ID 16536 Rev 15/29
Electrical ratingsSTP16CPPS05
2.3 Recommended operating conditions
Table 6.Recommended operating conditions
SymbolParameterTest conditionsMin.Typ.Max.Unit
V
V
I
I
V
V
t
wLAT
t
wCLK
t
wEN
t
SETUP(D)
t
HOLD(D)
t
SETUP(L)
f
CLK
Supply voltage3.05.5V
DD
Output voltage20V
O
Output currentOUTn340mA
I
O
Output currentSERIAL-OUT+1mA
OH
Output currentSERIAL-OUT-1mA
OL
Input voltage0.7 V
IH
Input voltage-0.30.3 V
IL
LE pulse width
DD
20ns
CLK pulse width10ns
OE pulse width100ns
VDD = 3.0 V to 5.0 V
Setup time for DATA8ns
Hold time for DATA5ns
Setup time for LATCH8ns
Clock frequencyCascade operation
(1)
V
DD
30MHz
1. If the device is connected in cascade, it may not be possible achieve the maximum data transfer.
Please consider the timings carefully.
DD
V
V
6/29 Doc ID 16536 Rev 1
STP16CPPS05Electrical characteristics
3 Electrical characteristics
VDD = 3.3 V to 5 V, TA = 25 °C, unless otherwise specified.
Table 7.Electrical characteristics
SymbolParameterTest conditionsMin.Typ.Max.Unit
V
V
I
OH
V
V
I
OL1
OL2
I
OL3
ΔI
OL1
OL2
ΔI
OL3
R
SIN(up)
R
SIN(down)
I
DD(OFF1)
Input voltage high level0.7 V
IH
Input voltage low levelGND0.3 V
IL
DD
Output leakage currentVOH = 20 V1μA
Output voltage
OL
(serial-OUT)
Output voltage
OH
(serial-OUT)
Output current
Output current error
between bit
(All output ON)
= 1 mA0.4V
I
OL
= -1 mAVDD-0.4VV
I
OH
= 0.3 V, R
V
O
VO = 0.3 V, R
VO = 1.3 V, R
VO = 0.3 V, IO = 5 mA
= 4 kΩ
R
EXT
VO = 0.3 V, IO = 20 mA
R
= 980 Ω
EXT
VO = 1.3 V, IO = 40 mA
R
= 490 Ω
EXT
= 4 kΩ4.7555.25
ext
= 1 kΩ192021
ext
= 497 Ω384042
ext
± 1± 5
± 0.5± 3
± 0.5± 3
Pull-up resistor150300600kΩ
Pull-down resistor100200400kΩ
R
= 1 kΩ,
EXT
I
= 20 mA,
OUT
5.47.5
V
DD
DD
V
V
mAI
%ΔI
OUT 0 to 15 = OFF
Supply current (OFF)
R
= 497 Ω,
I
DD(OFF2)
EXT
= 40 mA OUT 0 to
I
OUT
8.09.5
15 = OFF
mA
R
= 1 kΩ,
I
DD(ON1)
I
OUT
EXT
= 20 mA,
5.57.5
OUT 0 to 15 = ON
Supply current (ON)
R
= 497 Ω,
I
DD(ON2)
EXT
I
= 40 mA OUT 0 to
OUT
8.19.5
15 = ON
I
DD(SH)
ThermalThermal protection170°C
Shut-down current all
latched data = L
VDD = 3.3V160200µA
VDD = 5V190240µA
Doc ID 16536 Rev 17/29
Electrical characteristicsSTP16CPPS05
VDD = 3.3 V to 5 V, TA = 25 °C, unless otherwise specified.
Table 8.Switching characteristics
SymbolParameterTest conditionsMinTypMaxUnit
t
PLH1
Propagation delay time,
CLK-OUTn
, LE = H, OE = L
Propagation delay time,
t
PLH2
t
PLH3
t
LE-OUTn,
= L
OE
Propagation delay time,
OE-OUTn, LE = H
Propagation delay time,
PLH
CLK-SDO
Propagation delay time,
t
PHL1
t
PHL2
CLK-OUTn
OE = L
Propagation delay time,
LE-OUTn,
OE = L
, LE = H,
= V
V
IH
DD
VIL = GND CL = 10 pF
= 20 mAVL = 3.0 V
I
O
R
= 1 KΩRL = 60 Ω
EXT
Propagation delay time,
t
PHL3
OE-OUTn,
LE = H
t
Propagation delay time,
PHL
CLK-SDO
Output rise time
t
10~90% of voltage
ON
waveform
Output fall time
t
90~10% of voltage
OFF
waveform
CLK rise time
t
r
t
CLK fall time
f
1. In order to achieve high cascade data transfer, please consider tr/tf timings carefully.
(1)
(1)
VDD = 3.3 V53.586.5
= 5 V 3246.5
V
DD
V
= 3.3 V4875.5
DD
= 5 V3043
V
DD
= 3.3 V71.5118
V
DD
= 5 V4362
V
DD
= 3.3 V152131
V
DD
= 5 V111521
V
DD
V
= 3.3 V27.539
DD
= 5 V2230.5
V
DD
VDD = 3.3 V11.517.5
= 5 V811.5
V
DD
VDD = 3.3 V2433.5
= 5 V2128.5
V
DD
= 3.3 V17.52436
V
DD
= 5 V12.51725
V
DD
VDD = 3.3 V2954
= 5 V1017
V
DD
VDD = 3.3 V4.56
= 5 V3.55
V
DD
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5000ns
5000ns
8/29 Doc ID 16536 Rev 1
STP16CPPS05Equivalent circuit and outputs
4 Equivalent circuit and outputs
Figure 2.OE terminal
Figure 3.LE terminal
Figure 4.CLK, SDI terminal
Doc ID 16536 Rev 19/29
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