ST STP14NK60Z, STP14NK60ZFP, STB14NK60Z, STB14NK60Z-1, STW14NK60Z User Manual

STB14NK60

STP14NK60Z - STP14NK60ZFP STB14NK60Z/-1 - STW14NK60Z

N-CHANNEL 600V - 0.45Ω - 13.5A TO-220/FP-D²/I²PAK-TO-247 Zener-Protected SuperMESH™ MOSFET

Table 1: General Features

TYPE	VDSS	RDS(on)	ID	Pw
STP14NK60Z	600 V	< 0.5 Ω	13.5 A	160 W
STP14NK60ZFP	600 V	< 0.5 Ω	13.5 A	40 W
STB14NK60Z	600 V	< 0.5 Ω	13.5 A	160 W
STB14NK60Z-1	600 V	< 0.5 Ω	13.5 A	160 W
STW14NK60Z	600 V	< 0.5 Ω	13.5 A	160 W

■TYPICAL RDS(on) = 0.45 Ω

■EXTREMELY HIGH dv/dt CAPABILITY

■100% AVALANCHE TESTED

■GATE CHARGE MINIMIZED

■VERY LOW INTRINSIC CAPACITANCES

■VERY GOOD MANUFACTURING REPEATIBILITY

DESCRIPTION

The SuperMESH™ series is obtained through an extreme optimization of ST’s well established strip-based PowerMESH™ layout. In addition to pushing on-resistance significantly down, special care is taken to ensure a very good dv/dt capability for the most demanding applications. Such series complements ST full range of high voltage MOSFETs including revolutionary MDmesh™ products.

APPLICATIONS

■HIGH CURRENT, HIGH SPEED SWITCHING

■IDEAL FOR OFF-LINE POWER SUPPLIES, ADAPTORS AND PFC

■LIGHTING

Table 2: Order Codes

Figure 1: Package

	3	3
	2	2
	1	1
	TO-220	TO-220P
		3
		2
		1
		TO-247
	3	1 2 3
	1	I²PAK
	D²PAK
	Figure 2: Internal Schematic Diagram

Part Number	Marking	Package	Packaging
STP14NK60Z	P14NK60Z	TO-220	TUBE
STP14NK60ZFP	P14NK60ZFP	TO-220FP	TUBE
STB14NK60ZT4	B14NK60Z	D²PAK	TAPE & REEL
STB14NK60Z-1	B14NK60Z	I²PAK	TUBE
STW14NK60Z	W14NK60Z	TO-247	TUBE
			Rev. 4
September 2005			1/17

STP14NK60Z - STP14NK60ZFP - STB14NK60Z - STB14NK60Z-1 - STW14NK60Z

Table 3: Absolute Maximum ratings

Symbol	Parameter	Value			Unit
		TO-220/D²PAK/I²PAK		TO-220FP
		TO-247
VDS	Drain-source Voltage (VGS = 0)	600			V
VDGR	Drain-gate Voltage (RGS = 20 kΩ)	600			V
VGS	Gate-source Voltage	± 30			V
ID	Drain Current (continuous) at TC = 25°C	13.5		13.5 (*)	A
ID	Drain Current (continuous) at TC = 100°C	8.5		8.5 (*)	A
IDM ( )	Drain Current (pulsed)	54		54 (*)	A
PTOT	Total Dissipation at TC = 25°C	160		40	W
	Derating Factor	1.28		0.32	W/°C
VESD(G-S)	Gate source ESD (HBM-C= 100pF, R= 1.5kΩ)	4000			V
dv/dt (1)	Peak Diode Recovery voltage slope	4.5			V/ns
VISO	Insulation Winthstand Voltage (DC)	--		2500	V
Tj	Operating Junction Temperature	-55 to 150			°C
Tstg	Storage Temperature

( ) Pulse width limited by safe operating area

(1) ISD ≤ 13.5A, di/dt ≤ 200 A/µs, VDD ≤ V(BR)DSS, Tj ≤ TJMAX.

(*) Limited only by maximum temperature allowed

Table 4: Thermal Data

		TO-220/D²PAK/I²PAK		TO-220FP	Unit
		TO-247
Rthj-case	Thermal Resistance Junction-case Max	0.78		3.1	°C/W
Rthj-amb	Thermal Resistance Junction-ambient Max	62.5		50	°C/W
Tl	Maximum Lead Temperature For Soldering Purpose	300			°C

Table 5: Avalanche Characteristics

Symbol	Parameter	Max Value	Unit
IAR	Avalanche Current, Repetitive or Not-Repetitive	12	A
	(pulse width limited by Tj max)
EAS	Single Pulse Avalanche Energy	300	mJ
	(starting Tj = 25 °C, ID = IAR, VDD = 50 V)

Table 6: Gate-Source Zener Diode

Symbol	Parameter	Test Conditions	Min.	Typ.	Max.	Unit
BVGSO	Gate source Breakdown	Igs= ± 1 mA (Open Drain)	30			V
	Voltage

PROTECTION FEATURES OF GATE-TO-SOURCE ZENER DIODES

The built-in back-to-back Zener diodes have specifically been designed to enhance not only the device’s ESD capability, but also to make them safely absorb possible voltage transients that may occasionally be applied from gate to source. In this respect the Zener voltage is appropriate to achieve an efficient and cost-effective intervention to protect the device’s integrity. These integrated Zener diodes thus avoid the usage of external components.

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ELECTRICAL CHARACTERISTICS (TCASE =25°C UNLESS OTHERWISE SPECIFIED)

Table 7: On/Off

Symbol	Parameter	Test Conditions	Min.	Typ.	Max.	Unit
V(BR)DSS	Drain-source	ID = 1mA, VGS = 0	600			V
	Breakdown Voltage
IDSS	Zero Gate Voltage	VDS = Max Rating			1	µA
	Drain Current (VGS = 0)	VDS = Max Rating, TC = 125 °C			50	µA
IGSS	Gate-body Leakage	VGS = ± 30V			±10	µA
	Current (VDS = 0)
VGS(th)	Gate Threshold Voltage	VDS = VGS, ID = 100 µA	3	3.75	4.5	V
RDS(on)	Static Drain-source On	VGS = 10V, ID = 6 A		0.45	0.5	Ω
	Resistance

Table 8: Dynamic

Symbol	Parameter	Test Conditions	Min.	Typ.	Max.	Unit
gfs (1)	Forward Transconductance	VDS = 15 V, ID= 6 A		11		S
Ciss	Input Capacitance	VDS = 25V, f = 1 MHz, VGS = 0		2220		pF
Coss	Output Capacitance			240		pF
Crss	Reverse Transfer Capacitance			57		pF
Coss eq. (3)	Equivalent Output Capacitance	VGS = 0V, VDS = 0V to 480V		122		pF
td(on)	Turn-on Delay Time	VDD = 300 V, ID = 6 A,		26		ns
tr	Rise Time	RG= 4.7 Ω, VGS = 10 V		18		ns
td(off)	Turn-off Delay Time	(Resistive Load see, Figure 21)		62		ns
tf	Fall Time			13		ns
Qg	Total Gate Charge	VDD = 480V, ID = 12 A,		75		nC
Qgs	Gate-Source Charge	VGS = 10V		13.2		nC
Qgd	Gate-Drain Charge	(see, Figure 24)		38.6		nC

Table 9: Source Drain Diode

Symbol	Parameter	Test Conditions		Min.	Typ.	Max.	Unit
ISD	Source-drain Current					12	A
ISDM (2)	Source-drain Current (pulsed)					48	A
VSD (1)	Forward On Voltage	ISD = 12	A, VGS = 0			1.6	V
trr	Reverse Recovery Time	ISD = 12	A, di/dt = 100 A/µs		490		ns
Qrr	Reverse Recovery Charge	VDD = 50 V, Tj = 25°C			4.7		µC
IRRM	Reverse Recovery Current	(see test circuit, Figure 22)			19.3		A
trr	Reverse Recovery Time	ISD = 12	A, di/dt = 100 A/µs		664		ns
Qrr	Reverse Recovery Charge	VDD = 50 V, Tj = 150°C			6.8		µC
IRRM	Reverse Recovery Current	(see test circuit, Figure 22)			20.5		A

(1)Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %.

(2)Pulse width limited by safe operating area.

(3)Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS

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Figure 3: .Safe Operating Area For TO-220/

Figure 6: Thermal Impedance For TO-220/

D²PAK/I²PAK

D²PAK/I²PAK

Figure 4: Safe Operating Area For TO-220FP

Figure 7: Thermal Impedance For TO-220FP

Figure 5: Safe Operating Area For TO-247

Figure 8: Thermal Impedance For TO-247

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Figure 9: Output Characteristics		Figure 12: Transfer Characteristics

Figure 10: Transconductance		Figure 13: Static Drain-source On Resistance

Figure 11: Gate Charge vs Gate-source Voltage

Figure 14: Capacitance Variations

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Figure 15: Normalized Gate Thereshold Voltage vs Temperature

Figure 16: Source-Drain Forward Characteristics

Figure 17: Maximum Avalanche Energy vs Temperature

Figure 18: Normalized On Resistance vs Temperature

Figure 19: Normalized BVDSS vs Temperature

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