ST STP12NK30Z User Manual

ST STP12NK30Z User Manual

STP12NK30Z

STP12NK30Z

N-CHANNEL 300V - 0.36Ω - 9A - TO-220

Zener-Protected SuperMESH™Power MOSFET

TYPE

VDSS

RDS(on)

ID (1)

Pw (1)

STP12NK30Z

300 V

< 0.4 Ω

9 A

90 W

 

 

 

 

 

TYPICAL RDS(on) = 0.36 Ω

EXTREMELY HIGH dv/dt CAPABILITY

IMPROVED ESD CAPABILITY

100% AVALANCHE RATED

GATE CHARGE MINIMIZED

VERY LOW INTRINSIC CAPACITANCES

VERY GOOD MANUFACTURING REPEATIBILITY

DESCRIPTION

The SuperMESH™ series is obtained through an extreme optimization of ST’s well established stripbased PowerMESH™ layout. In addition to pushing on-resistance significantly down, special care is taken to ensure a very good dv/dt capability for the most demanding applications. Such series complements ST full range of high voltage MOSFETs including revolutionary MDmesh™ products.

APPLICATIONS

LIGHTING

IDEAL FOR OFF-LINE POWER SUPPLIES, ADAPTORS AND PFC

HIGH CURRENT, HIGH SPEED SWITCHING

3

2

1

TO-220

INTERNAL SCHEMATIC DIAGRAM

ORDERING INFORMATION

SALES TYPE

MARKING

PACKAGE

PACKAGING

 

 

 

 

STP12NK30Z

P12NK30Z

TO-220

TUBE

 

 

 

 

December 2002

1/8

STP12NK30Z

ABSOLUTE MAXIMUM RATINGS

Symbol

Parameter

Value

Unit

 

 

 

 

VDS

Drain-source Voltage (VGS = 0)

300

V

VDGR

Drain-gate Voltage (RGS = 20 kΩ)

300

V

VGS

Gatesource Voltage

± 30

V

 

 

 

 

ID

Drain Current (continuous) at TC = 25°C

9

A

 

Drain Current (continuous) at TC = 100°C

5.6

A

IDM (1)

Drain Current (pulsed)

36

A

PTOT

Total Dissipation at TC = 25°C

90

W

 

Derating Factor

0.72

W/°C

 

 

 

 

VESD(G-S)

Gate source ESD(HBM-C=100pF, R=1.5KΩ)

3000

V/ns

dv/dt (2)

Peak Diode Recovery voltage slope

4.5

V/ns

 

 

 

 

Tstg

Storage Temperature

–55 to 150

°C

Tj

Max. Operating Junction Temperature

 

 

THERMAL DATA

Rthj-case

Thermal Resistance Junction-case

Max

1.38

°C/W

 

 

 

 

 

Rthj-amb

Thermal Resistance Junction-ambient

Max

62.5

°C/W

Tl

 

Maximum Lead Temperature For Soldering Purpose

300

°C

 

 

 

 

 

 

Note: 1.

Pulse width limited by safe operating area

 

 

 

2.

ISD< 9A, di/dt<300A/µs, VDD<V(BR)DSS, TJ<TJMAX

 

 

 

AVALANCHE CHARACTERISTICS

Symbol

Parameter

Max Value

Unit

 

 

 

 

IAR

Avalanche Current, Repetitive or Not-Repetitive

9

A

 

(pulse width limited by Tj max)

 

 

EAS

Single Pulse Avalanche Energy

155

mJ

 

(starting Tj = 25 °C, I D = IAR, VDD = 50 V)

 

 

GATE-SOURCE ZENER DIODE

Symbol

Parameter

Test Conditions

Min.

Typ.

Max.

Unit

 

 

 

 

 

 

 

BVGSO

Gate-Source Breakdown

Igs=± 1mA (Open Drain)

30

 

 

V

 

Voltage

 

 

 

 

 

 

 

 

 

 

 

 

PROTECTION FEATURES OF GATE-TO-SOURCE ZENER DIODES

The built-in back-to-back Zener diodes have specifically been designed to enhance not only the device’s ESD capability, but also to make them safely absorb possible voltage transients that may occasionally be applied from gate to source. In this respect the Zener voltage is appropriate to achieve an efficient and cost-effective intervention to protect the device’s integrity. These integrated Zener diodes thus avoid the usage of external components.

2/8

STP12NK30Z

ELECTRICAL CHARACTERISTICS (TCASE =25°C UNLESS OTHERWISE SPECIFIED) ON/OFF

Symbol

Parameter

Test Conditions

Min.

Typ.

Max.

Unit

 

 

 

 

 

 

 

V(BR)DSS

Drain-source

ID = 1 mA, VGS = 0

300

 

 

V

 

Breakdown Voltage

 

 

 

 

 

 

 

 

 

 

 

 

IDSS

Zero Gate Voltage

VDS = Max Rating

 

 

1

µA

 

Drain Current (VGS = 0)

VDS = Max Rating, TC = 125 °C

 

 

50

µA

IGSS

Gate-body Leakage

VGS = ± 20V

 

 

±10

µA

 

Current (VDS = 0)

 

 

 

 

 

VGS(th)

Gate Threshold Voltage

VDS = VGS, ID = 50µA

3

3.75

4.5

V

RDS(on)

Static Drain-source On

VGS = 10V, ID = 4.5 A

 

0.36

0.4

Ω

 

Resistance

 

 

 

 

 

 

 

 

 

 

 

 

DYNAMIC

Symbol

 

Parameter

Test Conditions

Min.

Typ.

Max.

Unit

 

 

 

 

 

 

 

 

gfs (1)

 

Forward Transconductance

VDS = 10 V, ID = 4.5 A

 

5.4

 

S

Ciss

 

Input Capacitance

VDS = 25V, f = 1 MHz, VGS = 0

 

670

 

pF

Coss

 

Output Capacitance

 

 

125

 

pF

Crss

 

Reverse Transfer

 

 

28

 

pF

 

 

Capacitance

 

 

 

 

 

 

 

 

 

 

 

 

 

Coss eq. (3)

 

Equivalent Output

VGS = 0V, VDS = 0V to 440 V

 

70

 

pF

 

 

Capacitance

 

 

 

 

 

 

 

 

 

 

 

 

 

RG

 

Gate Input Resistance

f=1 MHz Gate DC Bias = 0

 

3.6

 

Ω

 

 

 

Test Signal Level = 20mV

 

 

 

 

 

 

 

Open Drain

 

 

 

 

 

 

 

 

 

 

 

 

SWITCHING

 

 

 

 

 

 

 

 

 

 

 

 

 

Symbol

 

Parameter

Test Conditions

Min.

Typ.

Max.

Unit

 

 

 

 

 

 

 

 

td(on)

 

Turn-on Delay Time

VDD = 150 V, ID = 4.5 A

 

16

 

ns

tr

 

Rise time

RG = 4.7Ω VGS = 10 V

 

20

 

ns

td(off)

 

Turn-off Delay Time

(Resistive Load see, Figure 3)

 

36

 

ns

tf

 

Fall Time

 

 

10

 

ns

Qg

 

Total Gate Charge

VDD = 240V, ID = 9 A,

 

25

35

nC

Qgs

 

Gate-Source Charge

VGS = 10V

 

5.5

 

nC

Qgd

 

Gate-Drain Charge

 

 

13.4

 

nC

SOURCE DRAIN DIODE

 

 

 

 

 

 

 

 

 

 

 

 

Symbol

 

Parameter

Test Conditions

Min.

Typ.

Max.

Unit

 

 

 

 

 

 

 

 

ISD

 

Source-drain Current

 

 

 

9

A

ISDM (2)

 

Source-drain Current (pulsed)

 

 

 

36

A

VSD (1)

 

Forward On Voltage

ISD = 9 A, VGS = 0

 

 

1.6

V

trr

 

Reverse Recovery Time

ISD = 9 A, di/dt = 100A/µs

 

165

 

ns

Qrr

 

Reverse Recovery Charge

VDD = 40V, Tj = 150°C

 

0.9

 

µC

IRRM

 

Reverse Recovery Current

(see test circuit, Figure 5)

 

11.2

 

A

Note: 1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %.

2.Pulse width limited by safe operating area.

3.Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS.

3/8

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