ST STP08CDC596 User Manual
查询STP08CDC596TTR供应商
LED SINK DRIVER WITH FULL OUTPUT DETECTION
STP08CDC596
8-BIT CONSTANT CURRENT
■ 8 CONSTANT CURRENT OUTPUT
CHANNELS
■ ADJUST ABLE OUTPUT CURRENT
THROUGH ONE EXTERNAL RESISTOR
■ OPEN AND SHORT LINE, SHORT TO GND,
SHORT TO V-LED SUPPLY ERROR
DETECTION
■ SERIAL DATA IN/PARALLEL DATA OUT
■ SERIAL OUT CHANGE STATE ON THE
FALLING EDGES OF CL OCK
■ OUTPUT CURRENT: 20-120 mA
■ 25 MHz CLOCK FREQ.
DESCRIPTION
The STP08CDC596 is a monolithic,
medium-voltage, low current power 8-bit shift
register designed for LED panel display. The
STP08CDC596 contains a 8-bit serial-in,
parallel-out shift register that feeds a 8-bitD-type
storage register. In the output stage, eight
regulated current sources were designed to
provide 15-120mA constant current to drive the
LEDs.
The STP08CDC596 contains the built-IN error
detection feature. The device performs this
additional function wi thout any in crea se of t he pi n
number and any change of the pin function, if
compared to the standard device without error
detection. Consequently, choosing this device
does not mean to change the footprint on the
board. To perform this functionality mode, the
device needs a digital key coming from the
Microprocessor. The STP08CDC596 is able to
detect: open and sho rt on the LED line, short to
SO-16DIP-16
TSSOP16
GND, short to Led voltage supply. The data
mapping of output channels status detection is
provided by a feedbac k from the serial output to
the Microprocessor.
Trough an external resistor, users m ay adjust the
STP08CDC596 output current, controlling the light
intensity of LEDs.
The STP08CDC596 guarantees 16V output
driving capability, allowing users to connect more
LEDs in series. The high clock frequency, 25 MHz,
also satisfies the system requirement of high
volume data transmission.
The device is offered in DIP-16, SO-16 and
TSSOP -16 packages.
The STP08CDC596 is well suitable for traffic
display signs where the detection feature is
strongly required.
Table 1: Order Codes
Type Temp. Range Package Comments
STP08CDC596B1 -40°C to 125°C DIP-16 25 part per tube
STP08CDC596M -40°C to 125°C SO-16 (Tube) 50 parts per tube
STP08CDC596MTR -40°C to 125°C SO-16 (Tape & Reel) 2500 parts per reel
STP08CDC596TTR -40°C to 125°C TSSOP16 (Tape & Reel) 2500 parts per reel
Rev. 2
1/20October 2005
STP08CDC596
Table 2: Current Accuracy
Output Voltage
≥ 0.7V TYP. ± 3% ± 10% 20 to 120 mA
Figure 1: Pin Connec t ion
Table 3: Pin Description
Current accuracy
Output Current
Between bits Between ICs
PIN N° Symbol Name and Function
1 GND Ground Terminal
2 SDI Serial data input terminal
3 CLK Clock input terminal
4 LE/DM1 Latch input terminal
5-12 OUT 0-7 Output terminal
13 OE/DM2 Output enable input terminal (active low)
14 SDO Serial data out terminal
15 R-EXT Constant Current programming
16 V
DD
5V Supply voltage terminal
Table 4: Absolute Maximum Ratings
Symbol Parameter Value Unit
V
I
f
T
T
V
I
V
GND
CLK
OPR
STG
Supply Voltage
DD
Output Voltage
O
Output Current
O
Input Voltage -0.4 to VDD+0.4
I
GND Termin al Current
Clock Frequency
Operating Temperature Range
Storage Temperature Range
0 to 7 V
-0.5 to 16 V
120 mA
980 mA
25 MHz
-40 to +125 °C
-55 to +150 °C
V
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition is
not implied.
2/20
STP08CDC596
Table 5: Thermal Data
Symbol Parameter DIP-16 SO-16 TSSOP16 Unit
R
thj-amb
Table 6: Recommended Operating Conditions
Symbol Parameter Test Conditions Min. Typ. Max. Unit
V
DD
V
O
I
O
I
OH
I
OL
V
IH
V
IL
t
wLAT
t
wCLK
t
wEN
t
SETUP(D)
t
HOLD(D)
t
SETUP(L)
f
CLK
(1) If the device is connected in cascade, it may not be possible achieve the maximum data transfer. Please considered the timings carefully.
(2) In norm al mode the OE/DM2 must rem ai n l ow at least two c l ock cycles.
Table 7: Electrical Characteristics (VDD=5V, T = 25°C, unless otherwise specified.)
Thermal Resistance Junction-ambient
90 125 140 °C/W
Supply Voltage 3.3 5.5 V
Output Voltage 16.0 V
Output Current OUTn 15 120 mA
Output Current SERIAL-OUT +1 mA
Output Current SERIAL-OUT -1 mA
Input Voltage 0.7V
DD
Input Voltage -0.3 0.3V
VDD+0.3 V
DD
V
LE/DM1 Pulse Width VDD = 3.0 to 3.6V 10 20 ns
CLK Pulse Width 10 20 ns
OE/DM2 Pulse Width (1) 120 400 ns
Setup Time for DATA 5 20 ns
Hold Time for DATA 4 15 ns
Setup Time for LATCH 8 15 ns
Clock Frequency (2) 25 MHz
Symbol Parameter Test Conditions Min. Typ. Max. Unit
V
V
I
V
V
I
OL1
I
OL2
∆I
∆I
R
SIN(up)
R
SIN(down)
I
DD(OFF1)
I
DD(OFF2)
I
DD(OFF3)
I
DD(ON1)
I
DD(ON2)
Input Voltage High Level 0.7V
IH
Input Voltage Low Level GND 0.3V
IL
Output Leakage Current VOH = 16 V 10 µA
OH
Output Voltage (Serial-OUT) IOL = 1mA 0.4 V
OL
Output Voltage (Serial-OUT) IOH = -1mA VDD-0.4V V
OH
Output Current VO = 0.7V R
Output Current Error
OL1
between bit (All Output ON)
OL2
VO = 0.7V R
VO = 0.7V R
VO = 0.7V R
= 910 Ω 18.8 20.9 24.00 mA
EXT
= 360 Ω 46.00 51.5 56.5 mA
EXT
= 910 Ω ± 2 ± 5 %
EXT
= 360 Ω ± 1 ± 4 %
EXT
DD
Pull-up Resistor 150 300 600 KΩ
Pull-down Resistor 100 200 400 KΩ
Supply Current (OFF) R
Supply Current (ON) R
= OPEN OUT 0 to 7 = OFF 0.45 0.7 mA
EXT
R
= 910 Ω OUT 0 to 7 = OFF 3.0 6.0
EXT
R
= 360 Ω OUT 0 to 7 = OFF 8.2 12.0
EXT
= 910 Ω OUT 0 to 7 = ON 3.1 6.2
EXT
R
= 360 Ω OUT 0 to 7 = ON 8.4 12.8
EXT
V
DD
DD
V
V
3/20
STP08CDC596
Table 8: Switching Characteristics (VDD=3.3 to 5.5V, T = 25°C, unless otherwise specified.)
Symbol Parameter Test Conditions Min. Typ. Max. Unit
t
PLH1
t
PLH2
t
PLH3
t
PLH
t
PHL1
t
PHL2
t
PHL3
t
PHL
Propagation Delay Time,
OUTn, LE/DM1 = H,
CLKOE/DM2 = L
Propagation Delay Time,
LE/DM1-OUTn, OE/DM2 = L
Propagation Delay Time,
VDD = 3 V VIH = V
DD
VIL = GND CL = 13pF
IO = 40mA VL = 3 V
R
= 470 Ω RL = 65 Ω
EXT
180 280 ns
150 280 ns
140 280 ns
OE/DM2-OUTn, LE/DM1 = H
Propagation Delay Time,
25 35 ns
CLK-SDO
Propagation Delay Time,
OUTn, LE/DM1 = H,
CLK-
30 60 ns
OE/DM2 = L
Propagation Delay Time,
30 50 ns
LE/DM1-OUTn, OE/DM2 = L
Propagation Delay Time,
35 70 ns
OE/DM2-OUTn, LE/DM1 = H
Propagation Delay Time,
30 40 ns
CLK-SDO
t
Output Rise Time 220 ns
r
t
Output Fall Time 20 ns
f
EQUIVALENT CIRCUIT OF INPUTS AND OUTPUTS
Figure 2: OE/DM2 Terminal
4/20
Figure 3: LE/DM1 Ter m i nal
Figure 4: CLK, SDI Terminal
STP08CDC596
Figure 5: SDO Termi nal
5/20
STP08CDC596
Figure 6: Block Diagram
Figure 7: Timing Dia gram
In norma l mode the OE/DM2 must remain low at least two clock cycles.
6/20
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