This datasheet contains the description of the device features, pinout, electrical characteristics,
mechanical data and ordering information.
For complete information on the STM8S microcontroller memory, registers and peripherals,
•
please refer to the STM8S microcontroller family reference manual (RM0016).
For information on programming, erasing and protection of the internal Flash memory
•
please refer to the STM8S Flash programming manual (PM0051).
For information on the debug and SWIM (single wire interface module) refer to the STM8
•
SWIM communication protocol and debug module user manual (UM0470).
For information on the STM8 core, please refer to the STM8 CPU programming manual
•
(PM0044).
7/103DocID022186 Rev 3
STM8S005K6 STM8S005C6Description
Description2
The STM8S005xx value line 8-bit microcontrollers offer 32 Kbytes of Flash program memory,
plus 128 bytes of data EEPROM. They are referred to as medium-density devices in the
STM8S microcontroller family reference manual (RM0016). All devices of the STM8S005xx
value line provide the following benefits: performance, robustness, reduced system cost, and
short develoment cycles.
Device performance and robustness are ensured by true data EEPROM supporting up to 100
000 write/erase cycles, advanced core and peripherals made in a state-of-the art technology,
a 16 MHz clock frequency, robust I/Os, independent watchdogs with separate clock source,
and a clock security system.
The system cost is reduced thanks to high system integration level with internal clock
oscillators, watchdog and brown-out reset.
Common family product architecture with compatible pinout, memory map and modular
peripherals allow application scalability and reduced development cycles.
All products operate from a 2.95 to 5.5 V supply voltage.
Full documentation is offered as well as a wide choice of development tools.
Table 1: STM8S005xx value line features
STM8S005K6STM8S005C6Device
3248Pin count
(bytes)
Peripheral set
2538Maximum number of GPIOs
2335Ext. Interrupt pins
89Timer CAPCOM channels
33Timer complementary outputs
710A/D Converter channels
1216High sink I/Os
32K32KMedium density Flash Program memory
128128Data EEPROM (bytes)
2K2KRAM (bytes)
Advanced control timer (TIM1), General-purpose timers (TIM2 and TIM3), Basic
timer (TIM4) SPI, I2C, UART, Window WDG, Independent WDG, ADC
DocID022186 Rev 38/103
XTAL 1-16 MHz
RC int. 16 MHz
RC int. 128 kHz
STM8 core
Debug/SWIM
I2C
SPI
UART2
16-bit general purpose
AWU timer
Reset block
Reset
POR/
PDR
BOR
Clock controller
Detector
Clock to peripherals and core
8 Mbit/s
Address and data bus
Window WDG
Independent WDG
32 Kbytes
128 bytes
2 Kbytes
Boot ROM
ADC1
Reset
400 Kbit/s
Single wire
debug interf.
program Flash
16-bit advanced control
timer (TIM1)
timers (TIM2, TIM3)
8-bit basic timer
(TIM4)
data EEPROM
RAM
Master/slave
autosynchro
LIN master
SPI emul.
Beeper
1/2/4 kHz
beep
5 CAPCOM
channels
Up to
4 CAPCOM
channels +3
Up to
complementary
outputs
Block diagramSTM8S005K6 STM8S005C6
Block diagram3
Figure 1: STM8S005xx value line block diagram
9/103DocID022186 Rev 3
STM8S005K6 STM8S005C6Product overview
Product overview4
The following section intends to give an overview of the basic features of the device functional
modules and peripherals.
For more detailed information please refer to the corresponding family reference manual
(RM0016).
Central processing unit STM84.1
The 8-bit STM8 core is designed for code efficiency and performance.
It contains 6 internal registers which are directly addressable in each execution context, 20
addressing modes including indexed indirect and relative addressing and 80 instructions.
Architecture and registers
Harvard architecture
•
3-stage pipeline
•
32-bit wide program memory bus - single cycle fetching for most instructions
•
X and Y 16-bit index registers - enabling indexed addressing modes with or without offset
•
and read-modify-write type data manipulations
8-bit accumulator
•
24-bit program counter - 16-Mbyte linear memory space
•
16-bit stack pointer - access to a 64 K-level stack
•
8-bit condition code register - 7 condition flags for the result of the last instruction
•
Addressing
20 addressing modes
•
Indexed indirect addressing mode for look-up tables located anywhere in the address
•
space
Stack pointer relative addressing mode for local variables and parameter passing
•
Instruction set
80 instructions with 2-byte average instruction size
•
Standard data movement and logic/arithmetic functions
•
8-bit by 8-bit multiplication
•
16-bit by 8-bit and 16-bit by 16-bit division
•
Bit manipulation
•
Data transfer between stack and accumulator (push/pop) with direct stack access
•
Data transfer using the X and Y registers or direct memory-to-memory transfers
•
Single wire interface module (SWIM) and debug module (DM)4.2
The single wire interface module and debug module permits non-intrusive, real-time in-circuit
debugging and fast memory programming.
DocID022186 Rev 310/103
Product overviewSTM8S005K6 STM8S005C6
SWIM
Single wire interface module for direct access to the debug module and memory programming.
The interface can be activated in all device operation modes. The maximum data transmission
speed is 145 bytes/ms.
Debug module
The non-intrusive debugging module features a performance close to a full-featured emulator.
Beside memory and peripherals, also CPU operation can be monitored in real-time by means
of shadow registers.
R/W to RAM and peripheral registers in real-time
•
R/W access to all resources by stalling the CPU
•
Breakpoints on all program-memory instructions (software breakpoints)
•
Two advanced breakpoints, 23 predefined configurations
•
Interrupt controller4.3
Nested interrupts with three software priority levels
•
32 interrupt vectors with hardware priority
•
Up to 37 external interrupts on 6 vectors including TLI
•
Trap and reset interrupts
•
Flash program and data EEPROM memory4.4
32 Kbytes of Flash program single voltage Flash memory
•
128 bytes true data EEPROM
•
Read while write: Writing in data memory possible while executing code in program memory
•
User option byte area
•
Write protection (WP)
Write protection of Flash program memory and data EEPROM is provided to avoid unintentional
overwriting of memory that could result from a user software malfunction.
There are two levels of write protection. The first level is known as MASS (memory access
security system). MASS is always enabled and protects the main Flash program memory,
data EEPROM and option bytes.
To perform in-application programming (IAP), this write protection can be removed by writing
a MASS key sequence in a control register. This allows the application to write to data
EEPROM, modify the contents of main program memory or the device option bytes.
A second level of write protection, can be enabled to further protect a specific area of memory
known as UBC (user boot code). Refer to the figure below.
The size of the UBC is programmable through the UBC option byte, in increments of 1 page
(512 bytes) by programming the UBC option byte in ICP mode.
This divides the program memory into two areas:
Main program memory: 32 Kbytes minus UBC
•
User-specific boot code (UBC): Configurable up to 32 Kbytes
•
11/103DocID022186 Rev 3
Programmable area
Data
Program memory area
Data memory area ( 128 bytes)
EEPROM
UBC area
Remains write protected during IAP
memory
Write access possible for IAP
(1 page steps)
Option bytes
(2 first pages) up to
Medium density
Flash program memory
(32 Kbytes)
from 1 Kbyte
32 Kbytes
STM8S005K6 STM8S005C6Product overview
The UBC area remains write-protected during in-application programming. This means that
the MASS keys do not unlock the UBC area. It protects the memory used to store the boot
program, specific code libraries, reset and interrupt vectors, the reset routine and usually the
IAP and communication routines.
Figure 2: Flash memory organization
Read-out protection (ROP)
The read-out protection blocks reading and writing the Flash program memory and data
EEPROM memory in ICP mode (and debug mode). Once the read-out protection is activated,
any attempt to toggle its status triggers a global erase of the program and data memory. Even
if no protection can be considered as totally unbreakable, the feature provides a very high
level of protection for a general purpose microcontroller.
Clock controller4.5
The clock controller distributes the system clock (f
to the core and the peripherals. It also manages clock gating for low power modes and ensures
clock robustness.
Features
Clock prescaler: To get the best compromise between speed and current consumption
•
the clock frequency to the CPU and peripherals can be adjusted by a programmable
prescaler.
Safe clock switching: Clock sources can be changed safely on the fly in run mode
•
through a configuration register. The clock signal is not switched until the new clock source
is ready. The design guarantees glitch-free switching.
Clock management: To reduce power consumption, the clock controller can stop the
•
clock to the core, individual peripherals or memory.
Master clock sources: Four different clock sources can be used to drive the master
•
clock:
1-16 MHz high-speed external crystal (HSE)
-
Up to 16 MHz high-speed user-external clock (HSE user-ext)
-
MASTER
) coming from different oscillators
DocID022186 Rev 312/103
Product overviewSTM8S005K6 STM8S005C6
16 MHz high-speed internal RC oscillator (HSI)
-
128 kHz low-speed internal RC (LSI)
-
Startup clock: After reset, the microcontroller restarts by default with an internal 2 MHz
•
clock (HSI/8). The prescaler ratio and clock source can be changed by the application
program as soon as the code execution starts.
Clock security system (CSS): This feature can be enabled by software. If an HSE clock
•
failure occurs, the internal RC (16 MHz/8) is automatically selected by the CSS and an
interrupt can optionally be generated.
Configurable main clock output (CCO): This outputs an external clock for use by the
•
application.
Table 2: Peripheral clock gating bit assignments in CLK_PCKENR1/2 registers
For efficent power management, the application can be put in one of four different low-power
modes. You can configure each mode to obtain the best compromise between lowest power
consumption, fastest start-up time and available wakeup sources.
Wait mode: In this mode, the CPU is stopped, but peripherals are kept running. The
•
wakeup is performed by an internal or external interrupt or reset.
Active halt mode with regulator on: In this mode, the CPU and peripheral clocks are
•
stopped. An internal wakeup is generated at programmable intervals by the auto wake up
unit (AWU). The main voltage regulator is kept powered on, so current consumption is
higher than in active halt mode with regulator off, but the wakeup time is faster. Wakeup
is triggered by the internal AWU interrupt, external interrupt or reset.
Active halt mode with regulator off: This mode is the same as active halt with regulator
•
on, except that the main voltage regulator is powered off, so the wake up time is slower.
Halt mode: In this mode the microcontroller uses the least power. The CPU and peripheral
•
clocks are stopped, the main voltage regulator is powered off. Wakeup is triggered by
external event or reset.
13/103DocID022186 Rev 3
STM8S005K6 STM8S005C6Product overview
Watchdog timers4.7
The watchdog system is based on two independent timers providing maximum security to
the applications.
Activation of the watchdog timers is controlled by option bytes or by software. Once activated,
the watchdogs cannot be disabled by the user program without performing a reset.
Window watchdog timer
The window watchdog is used to detect the occurrence of a software fault, usually generated
by external interferences or by unexpected logical conditions, which cause the application
program to abandon its normal sequence.
The window function can be used to trim the watchdog behavior to match the application
perfectly.
The application software must refresh the counter before time-out and during a limited time
window.
A reset is generated in two situations:
1. Timeout: At 16 MHz CPU clock the time-out period can be adjusted between 75 µs up to
64 ms.
2. Refresh out of window: The downcounter is refreshed before its value is lower than the
one stored in the window register.
Independent watchdog timer
The independent watchdog peripheral can be used to resolve processor malfunctions due to
hardware or software failures.
It is clocked by the 128 kHZ LSI internal RC clock source, and thus stays active even in case
of a CPU clock failure
The IWDG time base spans from 60 µs to 1 s.
Auto wakeup counter4.8
Used for auto wakeup from active halt mode
•
Clock source: Internal 128 kHz internal low frequency RC oscillator or external clock
•
LSI clock can be internally connected to TIM3 input capture channel 1 for calibration
•
Beeper4.9
The beeper function outputs a signal on the BEEP pin for sound generation. The signal is in
the range of 1, 2 or 4 kHz.
The beeper output port is only available through the alternate function remap option bit AFR7.
DocID022186 Rev 314/103
Product overviewSTM8S005K6 STM8S005C6
TIM1 - 16-bit advanced control timer4.10
This is a high-end timer designed for a wide range of control applications. With its
complementary outputs, dead-time control and center-aligned PWM capability, the field of
applications is extended to motor control, lighting and half-bridge driver
16-bit up, down and up/down autoreload counter with 16-bit prescaler
•
Four independent capture/compare channels (CAPCOM) configurable as input capture,
•
output compare, PWM generation (edge and center aligned mode) and single pulse mode
output
Synchronization module to control the timer with external signals
•
Break input to force the timer outputs into a defined state
•
Three complementary outputs with adjustable dead time
•
Encoder mode
•
Interrupt sources: 3 x input capture/output compare, 1 x overflow/update, 1 x break
•
TIM2, TIM3 - 16-bit general purpose timers4.11
16-bit autoreload (AR) up-counter
•
15-bit prescaler adjustable to fixed power of 2 ratios 1…32768
•
Timers with 3 or 2 individually configurable capture/compare channels
•
PWM mode
•
Interrupt sources: 2 or 3 x input capture/output compare, 1 x overflow/update
•
Timer
size
(bits)
16TIM1
16TIM2
16TIM3
TIM4 - 8-bit basic timer4.12
8-bit autoreload, adjustable prescaler ratio to any power of 2 from 1 to 128
•
Clock source: CPU clock
•
Interrupt source: 1 x overflow/update
•
Table 3: TIM timer features
PrescalerCounter
Any integer from 1 to
65536
1 to 32768
1 to 32768
Counting
mode
down
CAPCOM
channels
Complem.
outputs
Ext.
trigger
No03UpAny power of 2 from
No02UpAny power of 2 from
Timer
synchronization/
chaining
NoYes34Up/
15/103DocID022186 Rev 3
STM8S005K6 STM8S005C6Product overview
Timer
Timer
synchronization/
chaining
size
(bits)
8TIM4
PrescalerCounter
1 to 128
Counting
mode
CAPCOM
channels
Complem.
outputs
Ext.
trigger
No00UpAny power of 2 from
Analog-to-digital converter (ADC1)4.13
The STM8S105xx products contain a 10-bit successive approximation A/D converter (ADC1)
with up to 10 multiplexed input channels and the following main features:
Input voltage range: 0 to V
•
Conversion time: 14 clock cycles
•
Single and continuous and buffered continuous conversion modes
•
Buffer size (n x 10 bits) where n = number of input channels
•
Scan mode for single and continuous conversion of a sequence of channels
•
Analog watchdog capability with programmable upper and lower thresholds
•
Analog watchdog interrupt
•
External trigger input
•
Trigger from TIM1 TRGO
•
End of conversion (EOC) interrupt
•
DDA
Note: Additional AIN12 analog input is not selectable in ADC scan mode or with analog
watchdog. Values converted from AIN12 are stored only into the ADC_DRH/ADC_DRL
registers.
Communication interfaces4.14
The following communication interfaces are implemented:
2. [ ] alternate function remapping option (If the same alternate function is shown twice, it
indicates an exclusive choice not a duplication of the function).
Table 5: Pin description for STM8S005 microcontrollers
Default alternate
function
Resonator/Port A1XXO1XXI/OPA1/ OSC
crystal in
Resonator/Port A2XXO1XXXI/OPA2/ OSC
crystal out
IN
OUT
SSIO_1
SS
wpufloatingLQFP32LQFP48
Ext.
interrupt
OutputInputTypePin namePin number
sink
PPODSpeedHigh
Main function
(after reset)
ResetXI/ONRST11
I/O groundSV
Digital groundSV
Alternate
function after
remap [option
bit]
21/103DocID022186 Rev 3
STM8S005K6 STM8S005C6Pinout and pin description
(2)
Alternate
function after
remap [option
bit]
TIM3_ CH1
[AFR1]
Default alternate
function
Timer 2 -
channel 3
Analog input 12
PPODSpeedHigh
Main function
(after reset)
1.8 V regulator capacitorSVCAP56
Digital power supplySV
I/O power supplySV
Port A3XXO1XXXI/OPA3/ TIM2
Port A4XXO3HSXXXI/OPA4-10
Port A5XXO3HSXXXI/OPA5-11
Port A6XXO3HSXXXI/OPA6-12
Port F4XXO1XXI/OPF4/
Analog power supplySV
Analog groundSV
OutputInputTypePin namePin number
Ext.
wpufloatingLQFP32LQFP48
interrupt
67
78
-9
8-
913
1014
DD
DDIO_1
_CH3
[TIM3
_CH1]
AIN12
DDA
SSA
(1)
sink
Analog input 7Port B7XXO1XXXI/OPB7/ AIN7-15
Analog input 6Port B6XXO1XXXI/OPB6/ AIN6-16
1117
1218
1319
1420
1521
1622
[I2C_
SDA]
[I2C_
SCL]
[TIM1_
ETR]
[TIM1_
CH3N]
[TIM1_
CH2N]
[TIM1_
CH1N]
Analog input 5Port B5XXO1XXXI/OPB5/ AIN5
Analog input 4Port B4XXO1XXXI/OPB4/ AIN4
Analog input 3Port B3XXO1XXXI/OPB3/ AIN3
Analog input 2Port B2XXO1XXXI/OPB2/ AIN2
Analog input 1Port B1XXO1XXXI/OPB1/ AIN1
Analog input 0Port B0XXO1XXXI/OPB0/ AIN0
Analog input 8Port E7XXO1XXXI/OPE7/ AIN8-23
I2C_SDA
[AFR6]
I2C_SCL
[AFR6]
TIM1_ ETR
[AFR5]
TIM1_ CH3N
[AFR5]
TIM1_ CH2N
[AFR5]
TIM1_ CH1N
[AFR5]
Analog input 9Port E6XXO1XXXI/OPE6/ AIN9-24
DocID022186 Rev 322/103
Pinout and pin descriptionSTM8S005K6 STM8S005C6
Default alternate
function
SPI master/slave
select
Timer 1 -Port C1XXO3HSXXXI/OPC1/
channel 1/ UART2
synchronous clock
Timer 1-Port C2XXO3HSXXXI/OPC2/
channel 2
Timer 1 -Port C3XXO3HSXXXI/OPC3/
channel 3
Timer 1 -Port C4XXO3HSXXXI/OPC4/
channel 4
SPI clockPort C5XXO3HSXXXI/OPC5/ SPI_
PPODSpeedHigh
Main function
(after reset)
Port E5XXO1XXXI/OPE5/SPI_
I/O groundSV
I/O power supplySV
OutputInputTypePin namePin number
Ext.
wpufloatingLQFP32LQFP48
interrupt
1725
1826
1927
2028
2129
2230
-31
-32
NSS
TIM1_
CH1/
UART2_CK
TIM1_
CH2
TIM1_
CH3
TIM1_
CH4
SCK
SSIO_2
DDIO_2
sink
Alternate
function after
remap [option
bit]
2333
2434
-37
-38
-39
-40
2541
MOSI
MISO
TIM1_
BKIN
SDA
SCL
CLK_
CCO
TIM3_
CH2
[TIM1_
BKIN]
[CLK_
CCO]
(3)
O1XXI/OPE2/ I2C_
T
(3)
O1XXI/OPE1/ I2C_
T
Port C6XXO3HSXXXI/OPC6/ SPI_
Port C7XXO3HSXXXI/OPC7/ SPI_
Port G0XXO1XXI/OPG0-35
Port G1XXO1XXI/OPG1-36
Port E0XXO3HSXXXI/OPE0/
Port D0XXO3HSXXXI/OPD0/
SPI master out/slave
in
SPI master in/ slave
out
Timer 1 - break inputPort E3XXO1XXXI/OPE3/
I2C dataPort E2
I2C clockPort E1
Configurable clock
output
Timer 3 -
channel 2
TIM1_ BKIN
[AFR3]/ CLK_
CCO [AFR2]
23/103DocID022186 Rev 3
STM8S005K6 STM8S005C6Pinout and pin description
Default alternate
function
SWIM data interfacePort D1XXO4HSXXXI/OPD1/
Timer 3 -
channel 1
Timer 2 -
channel 2
Timer 2 -
channel 1
UART2 data transmitPort D5XXO1XXXI/OPD5/
UART2 data receivePort D6XXO1XXXI/OPD6/
PPODSpeedHigh
Main function
(after reset)
Port D2XXO3HSXXXI/OPD2/
Port D3XXO3HSXXXI/OPD3/
Port D4XXO3HSXXXI/OPD4/
OutputInputTypePin namePin number
Ext.
wpufloatingLQFP32LQFP48
interrupt
2642
2743
2844
2945
3046
3147
SWIM
TIM3_
CH1
[TIM2_
CH3]
TIM2_
CH2
[ADC_
ETR]
TIM2_
CH1
[BEEP]
UART2_
TX
UART2_
RX
(4)
sink
Alternate
function after
remap [option
bit]
TIM2_CH3
[AFR1]
ADC_ ETR
[AFR0]
BEEP output
[AFR7]
3248
(1)
A pull-up is applied to PF4 during the reset phase. This pin is input floating after reset release.
(2)
AIN12 is not selectable in ADC scan mode or with analog watchdog.
(3)
In the open-drain output column, ‘T’ defines a true open-drain I/O (P-buffer, weak pull-up, and protection diode to VDDare not implemented).
(4)
The PD1 pin is in input pull-up during the reset phase and after internal reset release.
[TIM1_
CH4]
Top level interruptPort D7XXO1XXXI/OPD7/ TLI
Alternate function remapping5.1.1
As shown in the rightmost column of the pin description table, some alternate functions can
be remapped at different I/O ports by programming one of eight AFR (alternate function
remap) option bits. When the remapping option is active, the default alternate function is no
longer available.
To use an alternate function, the corresponding peripheral must be enabled in the peripheral
registers.
Alternate function remapping does not effect GPIO capabilities of the I/O ports (see the GPIO
section of the family reference manual, RM0016).
TIM1_ CH4
[AFR4]
DocID022186 Rev 324/103
0x00 FFFF
Flash program memory
(32 Kbytes)
0x00 8000
Reserved
0x01 0000
0x02 7FFF
0x00 0000
RAM
0x00 07FF
(2 Kbytes)
0x00 4000
0x00 407F
128-byte data EEPROM
Reserved
Reserved
0x00 4080
0x00 47FF
32 interrupt vectors
0x00 807F
GPIO and periph. reg.
0x00 5000
0x00 57FF
0x00 5800
0x00 7FFF
0x00 4900
0x00 4FFF
2 Kbytes boot ROM
0x00 6000
0x00 67FF
0x00 6800
0x00 7EFF
CPU/SWIM/debug/ITC
registers
0x00 7F00
0x00 5FFF
Reserved
Reserved
Reserved
Option bytes
0x00 4800
0x00 487F
512 bytes stack
Memory and register mapSTM8S005K6 STM8S005C6
Memory and register map6
Memory map6.1
Figure 5: Memory map
The following table lists the boundary addresses for each memory size. The top of the stack
is at the RAM end address in each case.
25/103DocID022186 Rev 3
STM8S005K6 STM8S005C6Memory and register map
Table 6: Flash, Data EEPROM and RAM boundary addresses
End addressStart addressSize (bytes)Memory area
0x00 FFFF0x00 800032KFlash program memory
0x00 07FF0x00 00002KRAM
0x00 407F0x00 4000128Data EEPROM
Register map6.2
I/O port hardware register map6.2.1
Table 7: I/O port hardware register map
Register nameRegister labelBlockAddress
Port A input pin value registerPA_IDR0x00 5001
Port B input pin value registerPB_IDR0x00 5006
Reset
status
0x00Port A data output latch registerPA_ODRPort A0x00 5000
0xXX
0x00Port A data direction registerPA_DDR0x00 5002
0x00Port A control register 1PA_CR10x00 5003
0x00Port A control register 2PA_CR20x00 5004
0x00Port B data output latch registerPB_ODRPort B0x00 5005
0xXX
0x00Port B data direction registerPB_DDR0x00 5007
0x00Port B control register 1PB_CR10x00 5008
(1)
(1)
0x00Port B control register 2PB_CR20x00 5009
0x00Port C data output latch registerPC_ODRPort C0x00 500A
DocID022186 Rev 326/103
Memory and register mapSTM8S005K6 STM8S005C6
Register nameRegister labelBlockAddress
Reset
status
(1)
Port C input pin value registerPC_IDR0x00 500B
0xXX
0x00Port C data direction registerPC_DDR0x00 500C
0x00Port C control register 1PC_CR10x00 500D
0x00Port C control register 2PC_CR20x00 500E
0x00Port D data output latch registerPD_ODRPort D0x00 500F
(1)
Port D input pin value registerPD_IDR0x00 5010
0xXX
0x00Port D data direction registerPD_DDR0x00 5011
0x02Port D control register 1PD_CR10x00 5012
0x00Port D control register 2PD_CR20x00 5013
0x00Port E data output latch registerPE_ODRPort E0x00 5014
(1)
Port E input pin value registerPE_IDR0x00 5015
0xXX
0x00Port E data direction registerPE_DDR0x00 5016
0x00Port E control register 1PE_CR10x00 5017
0x00Port E control register 2PE_CR20x00 5018
0x00Port F data output latch registerPF_ODRPort F0x00 5019
(1)
Port F input pin value registerPF_IDR0x00 501A
0xXX
0x00Port F data direction registerPF_DDR0x00 501B
0x00Port F control register 1PF_CR10x00 501C
0x00Port F control register 2PF_CR20x00 501D
27/103DocID022186 Rev 3
STM8S005K6 STM8S005C6Memory and register map
Register nameRegister labelBlockAddress
Reset
status
0x00Port G data output latch registerPG_ODRPort G0x00 501E
(1)
Port G input pin value registerPG_IDR0x00 501F
0xXX
0x00Port G data direction registerPG_DDR0x00 5020
0x00Port G control register 1PG_CR10x00 5021
0x00Port G control register 2PG_CR20x00 5022
0x00Port H data output latch registerPH_ODRPort H0x00 5023
(1)
Port H input pin value registerPH_IDR0x00 5024
0xXX
0x00Port H data direction registerPH_DDR0x00 5025
0x00Port H control register 1PH_CR10x00 5026
(1)
Depends on the external circuitry.
0x00Port H control register 2PH_CR20x00 5027
0x00Port I data output latch registerPI_ODRPort I0x00 5028
0x00DM debug module control register 1DM_CR10x00 7F96
DM_CSR10x00 7F98
DM_CSR20x00 7F99
Reserved area (5 bytes)0x00 7F9B to
0x00 7F9F
(1)
Accessible by debug module only
0x00DM debug module control register 2DM_CR20x00 7F97
0x10DM debug module control/status
register 1
0x00DM debug module control/status
register 2
0xFFDM enable function registerDM_ENFCTR0x00 7F9A
41/103DocID022186 Rev 3
STM8S005K6 STM8S005C6Interrupt vector mapping
Interrupt vector mapping7
Table 10: Interrupt mapping
IRQ
no.
block
DescriptionSource
Port A external interruptsEXTI03
Wakeup
from halt
mode
(1)
Yes
Wakeup from
active-halt
mode
(1)
Vector
address
0x00 8000YesYesResetRESET
0x00 8004--Software interruptTRAP
0x00 8008--External top level interruptTLI0
0x00 800CYes-Auto wake up from haltAWU1
0x00 8010--Clock controllerCLK2
0x00 8014Yes
0x00 8018YesYesPort B external interruptsEXTI14
0x00 801CYesYesPort C external interruptsEXTI25
0x00 8020YesYesPort D external interruptsEXTI36
0x00 8024YesYesPort E external interruptsEXTI47
0x00 80288
0x00 802C--Reserved9
0x00 8030YesYesEnd of transferSPI10
TIM111
underflow/ trigger/ break
0x00 8034--TIM1 update/ overflow/
0x00 8038--TIM1 capture/ compareTIM112
0x00 803C--TIM update/ overflowTIM13
0x00 8040--TIM capture/ compareTIM14
DocID022186 Rev 342/103
Interrupt vector mappingSTM8S005K6 STM8S005C6
IRQ
no.
block
UART221
ADC122
DescriptionSource
FULL
analog watchdog interrupt
Wakeup
from halt
mode
Wakeup from
active-halt
mode
Vector
address
0x00 8044--Update/ overflowTIM315
0x00 8048--Capture/ compareTIM316
0x00 804C--Reserved17
0x00 8050--Reserved18
0x00 8054YesYesI2C interruptI2C19
0x00 8058--Tx completeUART220
0x00 805C--Receive register DATA
0x00 8060--ADC1 end of conversion/
Reserved
(1)
Except PA1
0x00 8064--TIM update/ overflowTIM23
0x00 8068--EOP/ WR_PG_DISFlash24
0x00 806C
to 0x00
807C
43/103DocID022186 Rev 3
STM8S005K6 STM8S005C6Option bytes
Option bytes8
Option bytes contain configurations for device hardware features as well as the memory
protection of the device. They are stored in a dedicated block of the memory. Except for the
ROP (read-out protection) byte, each option byte has to be stored twice, in a regular form
(OPTx) and a complemented one (NOPTx) for redundancy.
Option bytes can be modified in ICP mode (via SWIM) by accessing the EEPROM address
shown in the table below.
Option bytes can also be modified ‘on the fly’ by the application in IAP mode, except the ROP
option that can only be modified in ICP mode (via SWIM).
Refer to the STM8S Flash programming manual (PM0051) and STM8 SWIM communication
protocol and debug module user manual (UM0470) for information on SWIM programming
procedures.
For STM8S products, this option is checked by the boot ROM code
after reset. Depending on the content of addresses 0x487E, 0x487F,
and 0x8000 (reset vector), the CPU jumps to the bootloader or to
the reset vector. Refer to the UM0560 (STM8L/S bootloader manual)
for more details.
For STM8L products, the bootloader option bytes are on addresses
0xXXXX and 0xXXXX+1 (2 bytes). These option bytes control
whether the bootloader is active or not. For more details, refer to the
UM0560 (STM8L/S bootloader manual) for more details.
Table 13: Description of alternate function remapping bits [7:0] of OPT2
Option byte no.
Description
(1)
AFR7 Alternate function remapping option 7OPT2
0: AFR7 remapping option inactive: Default alternate function
1: Port B3 alternate function = TIM1_ETR; port B2 alternate function
= TIM1_NCC3; port B1 alternate function = TIM1_CH2N; port B0
alternate function = TIM1_CH1N.
AFR4 Alternate function remapping option 4
0: AFR4 remapping option inactive: Default alternate function
(2)
.
1: Port D7 alternate function = TIM1_CH4.
AFR3 Alternate function remapping option 3
0: AFR3 remapping option inactive: Default alternate function
(2)
.
.
.
1: Port D0 alternate function = TIM1_BKIN.
AFR2 Alternate function remapping option 2
47/103DocID022186 Rev 3
STM8S005K6 STM8S005C6Option bytes
Option byte no.
Description
(1)
0: AFR2 remapping option inactive: Default alternate function
1: Port D0 alternate function = CLK_CCO.Note: AFR2 option has
priority over AFR3 if both are activated.
1: Port A3 alternate function = TIM3_CH1; port D2 alternate function
TIM2_CH3.
AFR0 Alternate function remapping option 0
0: AFR0 remapping option inactive: Default alternate function
1: Port D3 alternate function = ADC_ETR.
(1)
Do not use more than one remapping option in the same port.
(2)
Refer to pinout description.
(2)
(2)
(2)
.
.
.
DocID022186 Rev 348/103
5 V or 3.3 V
A
V
V
V
V
V
V
DD
DDA
DDIO
SS
SSA
SSIO
Electrical characteristicsSTM8S005K6 STM8S005C6
Electrical characteristics9
Parameter conditions9.1
Unless otherwise specified, all voltages are referred to VSS.
Minimum and maximum values9.1.1
Unless otherwise specified the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100 % of the devices with an ambient temperature at TA= 25 °C and TA= T
the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production. Based on characterization,
the minimum and maximum values refer to sample tests and represent the mean value plus
or minus three times the standard deviation (mean ± 3 Σ).
Typical values9.1.2
Unless otherwise specified, typical data are based on TA= 25 °C, VDD= 5 V. They are given
only as design guidelines and are not tested.
Amax
(given by
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated (mean ± 2 Σ).
Typical curves9.1.3
Unless otherwise specified, all typical curves are given only as design guidelines and are not
tested.
Typical current consumption9.1.4
For typical current consumption measurements, VDD, V
in the configuration shown in the following figure.
Figure 6: Supply current measurement conditions
DDIO
and V
are connected together
DDA
49/103DocID022186 Rev 3
STM8 PIN
50 pF
STM8 PIN
V
IN
STM8S005K6 STM8S005C6Electrical characteristics
Loading capacitor9.1.5
The loading conditions used for pin parameter measurement are shown in the following figure.
Figure 7: Pin loading conditions
Pin input voltage9.1.6
The input voltage measurement on a pin of the device is described in the following figure.
Figure 8: Pin input voltage
Absolute maximum ratings9.2
Stresses above those listed as ‘absolute maximum ratings’ may cause permanent damage
to the device. This is a stress rating only and functional operation of the device under these
conditions is not implied. Exposure to maximum rating conditions for extended periods may
affect device reliability.
Table 14: Voltage characteristics
UnitMaxMinRatingsSymbol
(1)
V
- V
DDx
SS
V
IN
PE2)
(2)
DocID022186 Rev 350/103
DDA andVDDIO
)
6.5VSS- 0.3Input voltage on true open drain pins (PE1,
V6.5-0.3Supply voltage (including V
Electrical characteristicsSTM8S005K6 STM8S005C6
UnitMaxMinRatingsSymbol
DDx
(2)
-
VDD+ 0.3VSS- 0.3Input voltage on any other pin
mV50Variations between different power pins|V
VDD|
SSx
ESD
- VSS|
Electrostatic discharge voltageV
see Absolute maximum
50Variations between all the different ground pins|V
ratings (electrical sensitivity)
(1)
All power (VDD, V
DDIO
, V
) and ground (VSS, V
DDA
SSIO
, V
) pins must always be
SSA
connected to the external power supply
(2)
I
INJ(PIN)
must never be exceeded. This is implicitly insured if VINmaximum is respected.
If VINmaximum cannot be respected, the injection current must be limited externally to the
I
INJ(PIN)
value. A positive injection is induced by VIN>VDDwhile a negative injection is induced
by VIN<VSS. For true open-drain pads, there is no positive injection current, and the
corresponding VINmaximum must always be respected
Table 15: Current characteristics
(1)
RatingsSymbol
UnitMax.
I
VDD
I
VSS
IO
ΣI
(2)
(2)
60Total current out of VSSground lines (sink)
mA60Total current into VDDpower lines (source)
20Output current sunk by any I/O and control pinI
20Output current source by any I/Os and control pin
IO
pins) for devices with two V
pins) for devices with one V
pins) for devices with two V
pins) for devices with one V
DDIO
DDIO
SSIO
SSIO
pins
pin
pins
pin
(3)
(3)
(3)
(3)
200Total output current sourced (sum of all I/O and control
100Total output current sourced (sum of all I/O and control
160Total output current sunk (sum of all I/O and control
80Total output current sunk (sum of all I/O and control
51/103DocID022186 Rev 3
STM8S005K6 STM8S005C6Electrical characteristics
(1)
RatingsSymbol
UnitMax.
INJ(PIN)
(4) (5)
±4Injected current on NRST pinI
±4Injected current on OSCIN pin
(6)
ΣI
INJ(PIN)
(1)
(2)
(4)
Data based on characterization results, not tested in production.
All power (VDD, V
DDIO
, V
) and ground (VSS, V
DDA
SSIO
, V
SSA
) pins must always be
(6)
±4Injected current on any other pin
±20Total injected current (sum of all I/O and control pins)
connected to the external supply.
(3)
I/O pins used simultaneously for high current source/sink must be uniformly spaced
around the package between the V
(4)
I
INJ(PIN)
must never be exceeded. This is implicitly insured if VINmaximum is respected.
DDIO/VSSIO
pins.
If VINmaximum cannot be respected, the injection current must be limited externally to the
I
INJ(PIN)
value. A positive injection is induced by VIN>VDDwhile a negative injection is induced
by VIN<VSS. For true open-drain pads, there is no positive injection current, and the
corresponding VINmaximum must always be respected
(5)
Negative injection disturbs the analog performance of the device. See note in I2C interface
characteristics.
(6)
When several inputs are submitted to a current injection, the maximum ΣI
INJ(PIN)
is the
absolute sum of the positive and negative injected currents (instantaneous values). These
results are based on characterization with ΣI
INJ(PIN)
maximum current injection on four I/O
port pins of the device.
Table 16: Thermal characteristics
UnitValueRatingsSymbol
STG
J
150Maximum junction temperatureT
°C-65 to 150Storage temperature rangeT
Operating conditions9.3
The device must be used in operating conditions that respect the parameters in the table
below. In addition, full account must be taken of all physical capacitor characteristics and
tolerances.
DocID022186 Rev 352/103
Table 17: General operating conditions
Electrical characteristicsSTM8S005K6 STM8S005C6
UnitMaxMinConditionsParameterSymbol
f
CPU
VDD/ V
VCAP
(2)
P
D
DD_IO
(1)
frequency
voltage
: capacitance of
EXT
external capacitor
ESR of external
capacitor
capacitor
Power dissipation at
TA = 85 °C for suffix 6
(4)
output on eight standard
ports, two high sink ports
and two open drain ports
simultaneously
(3)
output on eight standard
ports and two high sink
ports simultaneously
(3)
MHz160Internal CPU clock
V5.52.95Standard operating
nF3300470C
Ohm0.3at 1 MHz
nH15ESL of external
mW44348-pin devices, with
36032-pin package, with
T
A
T
J
Ambient temperature
for 6 suffix version
dissipation
105-406 suffix versionJunction temperature
°C85-40Maximum power
range
(1)
Care should be taken when selecting the capacitor, due to its tolerance, as well as the
parameter dependency on temperature, DC bias and frequency in addition to other factors.
The parameter maximum value must be respected for the full application range.
(2)
To calculate P
Dmax(TA
characteristics ) with the value for T
), use the formula P
given in the current table and the value for Θ
Jmax
Dmax
= (T
- TA)/ΘJA(see Thermal
Jmax
JA
given in Thermal characteristics.
(3)
Refer to Thermal characteristics.
(4)
This frequency of 1 MHz as a condition for V
parameters is given by design of the
CAP
internal regulator.
53/103DocID022186 Rev 3
16
12
8
4
0
2.95
4.0
5.0
5.5
f
CPU
(MHz)
Functionality guaranteed
@TA-40 to 85 °C
Supply voltage
Functionality
not
guaranteed
in this area
STM8S005K6 STM8S005C6Electrical characteristics
VDD
Figure 9: f
CPUmax
versus V
DD
Table 18: Operating conditions at power-up/power-down
VDDrise time ratet
VDDfall time rate
(1)
(1)
UnitMaxTypMinConditionsParameterSymbol
µs/V∞2.0
∞2.0
TEMP
V
IT+
VDDrisingReset releasedelayt
threshold
V
IT-
2.882.72.58Brown-out reset
threshold
V
HYS(BOR)
hysteresis
(1)
Guaranteed by design, not tested in production.
VCAP external capacitor9.3.1
Stabilization for the main regulator is achieved connecting an external capacitor C
V
pin. C
CAP
the series inductance to less than 15 nH.
is specified in the Operating conditions section. Care should be taken to limit
EXT
(1)
EXT
ms1.7
V2.952.82.65Power-on reset
mV70Brown-out reset
to the
DocID022186 Rev 354/103
ESR
R
Leak
ESL
C
Electrical characteristicsSTM8S005K6 STM8S005C6
Figure 10: External capacitor C
EXT
1. ESR is the equivalent series resistance and ESL is the equivalent inductance.
Supply current characteristics9.3.2
The current consumption is measured as described in Pin input voltage.
Total current consumption in run mode9.3.2.1
Table 19: Total current consumption with code execution in run mode at VDD= 5 V
TypConditionsParameterSymbol
(1)
UnitMax
I
DD(RUN)
f
Supply
current in run
mode, code
= f
CPU
MASTER
= 16 MHz
(16 MHz)
executed
from RAM3.22.6HSE user ext. clock
(16 MHz)
(16 MHz)
f
= f
CPU
125 kHz
MASTER
/128 =
(16 MHz)
(16 MHz)
f
= f
CPU
MASTER
15.625 kHz
f
= f
CPU
= 128 kHz
/128 =
(16 MH3z/8)
MASTER
(128 kHz)
mA3.2HSE crystal osc.
3.22.5HSI RC osc.
2.21.6HSE user ext. clock
2.01.3HSI RC osc.
0.75HSI RC osc.
0.55LSI RC osc.
55/103DocID022186 Rev 3
I
DD(RUN)
STM8S005K6 STM8S005C6Electrical characteristics
f
Supply
current in run
mode, code
= f
CPU
MASTER
= 16 MHz
(16 MHz)
executed
fromFlash8.07.0HSE user ext. clock
(16 MHz)
(16 MHz)
(1)
TypConditionsParameterSymbol
UnitMax
7.7HSE crystal osc.
8.07.0HSI RC osc.
f
= f
CPU
= 2 MHz
f
CPU
125 kHz
f
CPU
15.625 kHz
f
CPU
= 128 kHz
(1)
Data based on characterization results, not tested in production.
(2)
Default clock configuration measured with all peripherals off.
MASTER
= f
MASTER
= f
MASTER
= f
MASTER
/128 =
/128 =
(16 MHz/8)
(16 MHz)
(16 MHz/8)
(128 kHz)
(2)
1.5HSI RC osc.
2.01.35HSI RC osc.
0.75HSI RC osc.
0.6LSI RC osc.
Table 20: Total current consumption with code execution in run mode at VDD= 3.3 V
(1)
TypConditionsParameterSymbol
UnitMax
I
DD(RUN)
current
in run
mode,
code
executed
from
RAM
f
CPU
= f
MASTER
DocID022186 Rev 356/103
= 16 MHzSupply
mA2.8HSE crystal osc.
(16 MHz)
3.22.6HSE user ext. clock
(16 MHz)
3.22.5HSI RC osc.
(16 MHz)
Electrical characteristicsSTM8S005K6 STM8S005C6
(1)
TypConditionsParameterSymbol
UnitMax
current
in run
mode,
code
executed
from
Flash
f
= f
CPU
MASTER
= 125 kHz
= f
CPU
MASTER
15.625 kHz
f
= f
CPU
f
CPU
= f
MASTER
MASTER
/128
/128 =
= 128 kHz
= 16 MHzSupply
2.21.6HSE user ext. clock
(16 MHz)
2.01.3HSI RC osc.
(16 MHz)
0.75HSI RC osc. (16 MHz/8)f
0.55LSI RC osc.
(128 kHz)
7.3HSE crystal osc.
(16 MHz)
8.07.0HSE user ext. clock
(16 MHz)
8.07.0HSI RC osc.
(16 MHz)
f
= f
CPU
f
CPU
= f
MASTER
MASTER
= 125 kHz
f
= f
CPU
MASTER
15.625 kHz
f
= f
CPU
MASTER
= 2 MHz
/128
/128 =
= 128 kHz
(16 MHz/8)
(16 MHz)
(16 MHz/8)
(2)
(128 kHz)
(1)
Data based on characterization results, not tested in production.
(2)
Default clock configuration measured with all peripherals off.
1.5HSI RC osc.
2.01.35HSI RC osc.
0.75HSI RC osc.
0.6LSI RC osc.
57/103DocID022186 Rev 3
STM8S005K6 STM8S005C6Electrical characteristics
Total current consumption in wait mode9.3.2.2
Table 21: Total current consumption in wait mode at VDD= 5 V
(1)
TypConditionsParameterSymbol
UnitMax
I
DD(WFI)
Supply
current in
wait mode
CPU
MHz
= f
MASTER
= 16
(16 MHz)
f
(16 MHz)
(16 MHz)
f
= f
CPU
MASTER
= 125 kHz
f
= f
CPU
MASTER
= 15.625 kHz
f
= f
CPU
MASTER
kHz
(1)
Data based on characterization results, not tested in production.
(2)
Default clock configuration measured with all peripherals off.
/128
/128
= 128
(16 MHz)
(16 MHz/8)
(128 kHz)
(2)
mA2.15HSE crystal osc.
2.01.55HSE user ext. clock
1.91.5HSI RC osc.
1.3HSI RC osc.
0.7HSI RC osc.
0.5LSI RC osc.
I
DD(WFI)
Table 22: Total current consumption in wait mode at VDD= 3.3 V
TypConditionsParameterSymbol
Supply
current in
wait mode
CPU
MHz
= f
MASTER
= 16
(16 MHz)
f
(16 MHz)
(16 MHz)
DocID022186 Rev 358/103
(1)
UnitMax
mA1.75HSE crystal osc.
2.01.55HSE user ext. clock
1.91.5HSI RC osc.
Electrical characteristicsSTM8S005K6 STM8S005C6
(1)
TypConditionsParameterSymbol
UnitMax
f
= f
CPU
MASTER
= 125 kHz
f
= f
CPU
MASTER
= 15.625 kHz
f
= f
CPU
MASTER
128 kHz
(1)
Data based on characterization results, not tested in production.
(2)
Default clock configuration measured with all peripherals off.
/128
/128
=
(16 MHz)
(16 MHz/8)
(128 kHz)
(2)
Total current consumption in active halt mode9.3.2.3
Table 23: Total current consumption in active halt mode at VDD= 5 V
(3)
Main
voltage
regulator
(MVR)
(2)
Clock sourceFlash mode
1.3HSI RC osc.
0.7HSI RC osc.
0.5LSI RC osc.
TypConditionsParameterSymbol
85
°C
UnitMax at
(1)
I
DD(AH)
current in
active halt
mode
Operating modeOnSupply
Power-down
mode
µA1080HSE crystal
osc.
(16 MHz)
320200LSI RC osc.
(128 kHz)
1030HSE crystal
osc.
(16 MHz)
270140LSI RC osc.
(128 kHz)
59/103DocID022186 Rev 3
STM8S005K6 STM8S005C6Electrical characteristics
(3)
Main
Clock sourceFlash mode
voltage
regulator
(MVR)
(2)
Operating modeOff
(128 kHz)
mode
(1)
Data based on characterization results, not tested in production.
(2)
Configured by the REGAH bit in the CLK_ICKR register.
(3)
Configured by the AHALT bit in the FLASH_CR1 register.
Table 24: Total current consumption in active halt mode at VDD= 3.3 V
(3)
Main
Clock sourceFlash mode
voltage
regulator
(2)
(MVR)
TypConditionsParameterSymbol
85
°C
UnitMax at
(1)
12068LSI RC osc.
6012Power-down
TypConditionsParameterSymbol
85
°C
UnitMax at
(1)
I
DD(AH)
current in
active halt
mode
OnSupply
Off
Operating
mode
Power-down
mode
Operating
mode
mode
µA680HSE crystal osc.
(16 MHz)
320200LSI RC osc.
(128 kHz)
630HSE crystal osc.
(16 MHz)
270140LSI RC osc.
(128 kHz)
12066LSI RC osc.
(128 kHz)
6010Power-down
DocID022186 Rev 360/103
(1)
Data based on characterization results, not tested in production.
(2)
Configured by the REGAH bit in the CLK_ICKR register.
(3)
Configured by the AHALT bit in the FLASH_CR1 register.
Total current consumption in halt mode9.3.2.4
Table 25: Total current consumption in halt mode at VDD= 5 V
Electrical characteristicsSTM8S005K6 STM8S005C6
I
DD(H)
Supply current in
halt mode
clock after wakeup
clock after wakeup
(1)
Data based on characterization results, not tested in production.
Table 26: Total current consumption in halt mode at VDD= 3.3 V
I
DD(H)
Supply current in
halt mode
clock after wakeup
clock after wakeup
TypConditionsParameterSymbol
85 °C
(1)
UnitMax at
µA9062Flash in operating mode, HSI
256.5Flash in powerdown mode, HSI
TypConditionsParameterSymbol
85 °C
(1)
UnitMax at
µA9060Flash in operating mode, HSI
204.5Flash in powerdown mode, HSI
t
WU(WFI)
(1)
Data based on characterization results, not tested in production.
Low power mode wakeup times9.3.2.5
Table 27: Wakeup times
Wakeup time from
wait mode to run
(3)
0 to 16 MHz
= f
CPU
MASTER
= 16 MHzmode
(1)
TypConditionsParameterSymbol
Max
See
note
Unit
(2)
μs
0.56f
61/103DocID022186 Rev 3
STM8S005K6 STM8S005C6Electrical characteristics
(1)
TypConditionsParameterSymbol
Max
Unit
t
WU(AH)
t
WU(H)
Wakeup time active
halt mode to run
(3)
mode
Wakeup time active
halt mode to run
(3)
mode
Wakeup time active
halt mode to run
(3)
mode
Wakeup time active
halt mode to run
(3)
mode
Wakeup time from
halt mode to run
(3)
mode
MVR voltage
regulator
(4)
on
MVR voltage
regulator
(4)
on
MVR voltage
regulator
(4)
off
MVR voltage
regulator
(4)
off
Flash in operating
(5)
mode
Flash in
power-down
(5)
Flash in operating
(5)
mode
Flash in
power-down
(5)
(5)
(5)
HSI
(after
wakeup)
HSI
(after
wakeup)mode
HSI
(after
wakeup)
HSI
(after
wakeup)mode
1
3
48
50
52Flash in operating mode
54Flash in power-down mode
(6)
(6)
(6)
(6)
(6)
2
(1)
Data guaranteed by design, not tested in production.
(2)
t
WU(WFI)
(3)
Measured from interrupt event to interrupt vector fetch.
(4)
Configured by the REGAH bit in the CLK_ICKR register.
(5)
Configured by the AHALT bit in the FLASH_CR1 register.
(6)
Plus 1 LSI clock depending on synchronization.
= 2 x 1/f
master
+ x 1/f
CPU.
Total current consumption and timing in forced reset state9.3.2.6
Table 28: Total current consumption and timing in forced reset state
I
DD(R)
state
(2)
(1)
TypConditionsParameterSymbol
UnitMax
500VDD= 5 VSupply current in reset
μA
400VDD= 3.3 V
DocID022186 Rev 362/103
Electrical characteristicsSTM8S005K6 STM8S005C6
(1)
TypConditionsParameterSymbol
UnitMax
t
RESETBL
Reset pin release to
vector fetch
(1)
Data guaranteed by design, not tested in production.
(2)
Characterized with all I/Os tied to VSS.
Current consumption of on-chip peripherals9.3.2.7
Subject to general operating conditions for VDDand TA.
HSI internal RC/f
I
DD(TIM1)
I
DD(TIM2)
I
DD(TIM3)
CPU
= f
MASTER
= 16 MHz.
Table 29: Peripheral current consumption
(1)
(1)
(1)
μs150
UnitTyp.ParameterSymbol
230TIM1 supply current
115TIM2 supply current
90TIM3 timer supply current
I
DD(TIM4)
(1)
30TIM4 timer supply current
µA
I
DD(UART2)
I
DD(SPI)
I
DD(I2C)
I
DD(ADC1)
(1)
Data based on a differential IDDmeasurement between reset configuration and timer
(2)
(2)
(2)
(3)
110UART2 supply current
45SPI supply current
65I2C supply current
955ADC1 supply current when converting
counter running at 16 MHz. No IC/OC programmed (no I/O pads toggling). Not tested in
production.
(2)
Data based on a differential IDDmeasurement between the on-chip peripheral when kept
under reset and not clocked and the on-chip peripheral when clocked and not kept under
reset. No I/O pads toggling. Not tested in production.
(3)
Data based on a differential IDDmeasurement between reset configuration and continuous
A/D conversions. Not tested in production.
63/103DocID022186 Rev 3
2.5
2.55
2.6
2.65
2.7
2.75
2.8
2.85
2.9
2.95
3
2.533.544.555.56
I
DD(RUN)HSE
[mA]
VDD[V]
-40°C
25°C
85°C
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
051015202530
I
DD(RUN)HSE
[mA]
fcpu[MHz]
-40°C
25°C
85°C
STM8S005K6 STM8S005C6Electrical characteristics
Current consumption curves9.3.2.8
The following figures show typical current consumption measured with code executing in
RAM.
Figure 11: Typ. I
DD(RUN)
vs. V
HSE user external clock, f
DD ,
= 16 MHz
CPU
Figure 12: Typ. I
DD(RUN)
vs. f
HSE user external clock, VDD= 5 V
CPU ,
DocID022186 Rev 364/103
2
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
3
2.533.544.555.56
I
DD(RUN)HSI
[mA]
VDD[V]
-40°C
25°C
85°C
1
1.2
1.4
1.6
1.8
2
2.2
2.4
2.533.544.555.56
I
DD(WFI)HSE
[mA]
VDD[V]
-40°C
25°C
85°C
0
0.5
1
1.5
2
2.5
3
051015202530
I
DD(WFI)HSE
[mA]
fcpu[MHz]
-40°C
25°C
85°C
Electrical characteristicsSTM8S005K6 STM8S005C6
Figure 13: Typ. I
Figure 14: Typ. I
DD(WFI)
DD(RUN)
vs. V
vs. V
HSE user external clock, f
DD ,
HSI RC osc, f
DD ,
= 16 MHz
CPU
CPU
= 16 MHz
Figure 15: Typ. I
DD(WFI)
vs. f
, HSE user external clock VDD= 5 V
CPU
65/103DocID022186 Rev 3
1
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2
2.533.544.555.56
I
DD(WFI)HSI
[mA]
VDD[V]
-40°C
25°C
85°C
STM8S005K6 STM8S005C6Electrical characteristics
Figure 16: Typ. I
DD(WFI)
vs. VDD, HSI RC osc, f
External clock sources and timing characteristics9.3.3
HSE user external clock
Subject to general operating conditions for VDDand TA.
Table 30: HSE user external clock characteristics
CPU
= 16 MHz
UnitMaxMinConditionsParameterSymbol
f
HSE_ext
User external clock source
frequency
V
HSEH
(1)
OSCIN input pin high level
voltage
V
HSEL
(1)
OSCIN input pin low level
voltage
LEAK_HSE
(1)
Data based on characterization results, not tested in production.
OSCIN input leakage currentI
VSS< VIN< V
DD
MHz160
DD
VDD+ 0.3 V0.7 x V
V
V
SS
0.3 x V
DD
μA+1-1
DocID022186 Rev 366/103
V
HSEH
V
HSEL
External clock
source
OSCIN
f
HSE
STM8
Electrical characteristicsSTM8S005K6 STM8S005C6
Figure 17: HSE external clocksource
HSE crystal/ceramic resonator oscillator
The HSE clock can be supplied with a 1 to 16 MHz crystal/ceramic resonator oscillator. All
the information given in this paragraph is based on characterization results with specified
typical external components. In the application, the resonator and the load capacitors have
to be placed as close as possible to the oscillator pins in order to minimize output distortion
and start-up stabilization time. Refer to the crystal resonator manufacturer for more details
(frequency, package, accuracy...).
f
HSE
F
(1)
C
I
DD(HSE)
g
m
SU(HSE)
External high speed
oscillator frequency
Feedback resistorR
Recommended load
capacitance
HSE oscillator power
consumption
Oscillator
transconductance
(4)
Table 31: HSE oscillator characteristics
(2)
C = 20 pF,
f
= 16 MHz
OSC
C = 10 pF,
f
=16 MHz
OSC
VDDis stabilizedStartup timet
6 (startup)
1.6 (stabilized)
6 (startup)
1.2 (stabilized)
UnitMaxTypMinConditionsParameterSymbol
MHz161
kΩ220
pF20
(3)
mA
(3)
mA/V5
ms1
(1)
C is approximately equivalent to 2 x crystal Cload.
67/103DocID022186 Rev 3
OSCOUT
OSCIN
f
HSE
to core
C
L1
C
L2
R
F
STM8
Resonator
Consumption
control
g
m
R
m
C
m
L
m
C
O
Resonator
STM8S005K6 STM8S005C6Electrical characteristics
(2)
The oscillator selection can be optimized in terms of supply current using a high quality resonator with
small Rmvalue. Refer to crystal manufacturer for more details
(3)
Data based on characterization results, not tested in production.
(4)
t
SU(HSE)
is the start-up time measured from the moment it is enabled (by software) to a stabilized 16
MHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary
significantly with the crystal manufacturer.
Figure 18: HSE oscillator circuit diagram
HSE oscillator critical gmequation
g
mcrit
= (2 × Π × f
)2× Rm(2Co + C)
HSE
2
Rm: Notional resistance (see crystal specification)
Lm: Notional inductance (see crystal specification)
Cm: Notional capacitance (see crystal specification)
Co: Shunt capacitance (see crystal specification)
CL1= CL2= C: Grounded external capacitance
gm>> g
mcrit
Internal clock sources and timing characteristics9.3.4
Subject to general operating conditions for VDDand TA.
High speed internal RC oscillator (HSI)
Table 32: HSI oscillator characteristics
UnitMaxTypMinConditionsParameterSymbol
HSI
DocID022186 Rev 368/103
MHz16Frequencyf
ACC
15.5
15.6
15.7
15.8
15.9
16
16.1
16.2
16.3
16.4
16.5
2.533.544.555.56
HSIfrequency[MHz]
VDD[V]
-40°C
25°C
85°C
Accuracy of HSI
HSI
oscillator
User-trimmed with
CLK_HSITRIMR register
for given VDDand T
conditions
(1)
A
Electrical characteristicsSTM8S005K6 STM8S005C6
UnitMaxTypMinConditionsParameterSymbol
(2)
%1.0
Accuracy of HSI
(3)
oscillator (factory
calibrated)5.0-5.0
VDD= 5 V,
-40 °C ≤ TA≤ 85 °C
t
su(HSI)
HSI oscillator
wakeup time
including calibration
I
DD(HSI)
consumption
(1)
Refer to application note.
(2)
Guaranteed by design, not tested in production.
(3)
Data based on characterization results, not tested in production.
Figure 19: Typical HSI frequency variation vs VDD@ 3 temperatures
5.0VDD= 5 V, TA= 25°C
(2)
µs1.0
(3)
170HSI oscillator power
µA250
Low speed internal RC oscillator (LSI)
Subject to general operating conditions for VDDand TA.
69/103DocID022186 Rev 3
100
105
110
115
120
125
130
135
140
145
150
2.533.544.555.56
LSIfrequency[MHz]
VDD[V]
-40°C
25°C
85°C
STM8S005K6 STM8S005C6Electrical characteristics
Table 33: LSI oscillator characteristics
UnitMaxTypMinParameterSymbol
LSI
su(LSI)
DD(LSI)
(1)
Guaranteeed by design, not tested in production.
LSI oscillator wakeup timet
Figure 20: Typical LSI frequency variation vs VDD@ 3 temperatures
(1)
kHz128Frequencyf
µs7
µA5LSI oscillator power consumptionI
Memory characteristics9.3.5
RAM and hardware registers
V
RM
(1)
Minimum supply voltage without losing data stored in RAM (in halt mode or under reset)
or in hardware registers (only in halt mode). Guaranteed by design, not tested in production.
refer to Operating conditions for the value of V
(2)
Refer to the Operating conditions section for the value of V
Flash program memory/data EEPROM memory
General conditions: TA= -40 to 85°C.
Table 34: RAM and hardware registers
(1)
DocID022186 Rev 370/103
Halt mode (or reset)Data retention mode
IT-max
IT-max
IT-max
(2)
UnitMinConditionsParameterSymbol
VV
Electrical characteristicsSTM8S005K6 STM8S005C6
Table 35: Flash program memory/data EEPROM memory
V
DD
t
prog
erase
N
RW
t
RET
execution/write/erase)
(including erase) for
byte/word/block (1 byte/4
bytes/128 bytes)
(128 bytes)
(2)
(program
memory)
after 100 erase/write cycles at T
= 85 °C
(2)
ConditionsParameterSymbol
CPU
(1)
≤ 16 MHzOperating voltage (all modes,
UnitMaxTypMin
V5.52.95f
ms6.66.0Standard programming time
ms3.33.0Fast programming time for 1 block
ms3.33.0Erase time for 1 block (128 bytes)t
cycles100TA= 85 °CErase/write cycles
100 kTA= 85 ° CErase/write cycles(data memory)
= 55° CData retention (program memory)
RET
A
years20T
20Data retention (data memory) after
10 k erase/write cycles at TA= 85
°C
RET
= 85° CData retention (data memory) after
1T
100 k erase/write cyclesat TA= 85
°C
I
DD
programming or erasing for 1 to
128 bytes)
(1)
Data based on characterization results, not tested in production.
(2)
The physical granularity of the memory is 4 bytes, so cycling is performed on 4 bytes
even when a write/erase operation addresses a single byte.
mA2.0Supply current (Flash
71/103DocID022186 Rev 3
STM8S005K6 STM8S005C6Electrical characteristics
I/O port pin characteristics9.3.6
General characteristics
Subject to general operating conditions for VDDand TAunless otherwise specified. All unused
pins must be kept at a fixed voltage: using the output mode of the I/O for example or an
external pull-up or pull-down resistor.
Table 36: I/O static characteristics
UnitMaxTypMinConditionsParameterSymbol
V
IL
V
IH
V
hys
pu
tR, t
I
lkg
I
lkg ana
voltage
Input high level
voltage
Pull-up resistorR
F
time(10 % - 90 %)
Input leakage
current, analog
and digital
Analog input
leakage current
(1)
SS
Fast I/Os load = 50 pFRise and fall
Standard and high sink
I/OsLoad = 50 pF
VSS≤ VIN≤ V
VSS≤ VIN≤ V
DD
DD
-0.3VDD= 5 VInput low level
0.7 x
V
DD
V0.3 x V
DD
VVDD+ 0.3
V
mV700Hysteresis
kΩ805530VDD= 5 V, VIN= V
(3)
(3)
(2)
(2)
ns35
ns125
µA±1.0
nA±250
I
lkg(inj)
adjacent I/O
(1)
Hysteresis voltage between Schmitt trigger switching levels. Based on characterization
(2)
Injection current ±4 mALeakage current in
(2)
results, not tested in production.
(2)
Data based on characterization results, not tested in production.
(3)
Data guaranteed by design, not tested in production.
Figure 35: Typical NRST pull-up resistance vs VDD@ 3 temperatures
Figure 36: Typical NRST pull-up current vs VDD@ 3 temperatures
DocID022186 Rev 380/103
External
reset
circuit
(optional)
0.1 μF
NRST
VDD
RPU
Filter
Internal reset
STM8
Electrical characteristicsSTM8S005K6 STM8S005C6
The reset network shown in the following figure protects the device against parasitic resets.
The user must ensure that the level on the NRST pin can go below V
IL(NRST)
max. (see Table
40: NRST pin characteristics ), otherwise the reset is not taken into account internally.
For power consumption sensitive applications, the external reset capacitor value can be
reduced to limit the charge/discharge current. If NRST signal is used to reset external circuitry,
attention must be taken to the charge/discharge time of the external capacitor to fulfill the
external devices reset timing conditions. Minimum recommended capacity is 100 nF.
Figure 37: Recommended reset pin protection
SPI serial peripheral interface9.3.9
Unless otherwise specified, the parameters given in the following table are derived from tests
performed under ambient temperature, f
t
MASTER
= 1/f
MASTER
.
MASTER
Refer to I/O port characteristics for more details on the input/output alternate function
characteristics (NSS, SCK, MOSI, MISO).
Table 41: SPI characteristics
f
1
SCK
t
c(SCK)
t
r(SCK)
t
f(SCK)
su(NSS)
(1)
frequency
and fall time
Slave modeNSS setup timet
frequency and VDDsupply voltage conditions.
UnitMaxMinConditionsParameterSymbol
MHz80Master modeSPI clock
60Slave mode
25Capacitive load: C = 30 pFSPI clock rise
ns
4 x
t
MASTER
ns
h(NSS)
(1)
ns70Slave modeNSS hold timet
81/103DocID022186 Rev 3
STM8S005K6 STM8S005C6Electrical characteristics
UnitMaxMinConditionsParameterSymbol
t
w(SCKH)
t
w(SCKL)
t
su(MI)
t
su(SI)
t
h(MI)
t
h(SI)
t
a(SO)
t
dis(SO)
(1)
(1)
(1)
(1)
(1) (2)
(1) (3)
(1)
(1)
low time
setup time
setup time
time
time
access time
disable time
t
t
Master modeSCK high and
SCK
/2 -
15
5Master modeData input
5Slave modeData input
7Master modeData input hold
10Slave modeData input hold
Slave modeData output
25Slave modeData output
/2 +
SCK
15
3 x
t
MASTER
ns
ns
ns
ns
ns
ns
ns
t
v(SO)
t
v(MO)
t
h(SO)
t
h(MO)
(1)
(1)
(1)
(1)
Data output
valid time
Data output
valid time
Data output
hold time
(after enable edge)
(after enable edge)
28Slave mode
(after enable edge)
12Master mode
73Slave mode
36Master mode
(after enable edge)
(1)
Values based on design simulation and/or characterization results, and not tested in
production.
(2)
Min time is for the minimum time to drive the output and the max time is for the maximum
time to validate the data.
(3)
Min time is for the minimum time to invalidate the output and the max time is for the
1. Measurement points are made at CMOS levels: 0.3 VDDand 0.7 VDD.
(1)
83/103DocID022186 Rev 3
ai14136b
SCK intput
CPHA=0
MOSI
OUTUT
MISO
INPUT
CPHA=0
MSBIN
MSB OUT
BIT6 IN
LSB OUT
LSB IN
CPOL=0
CPOL=1
BIT1 OUT
NSSinput
t
c(SCK)
t
w(SCKH)
t
w(SCKL)
t
r(SCK)
t
f(SCK)
t
h(MI)
High
SCK output
CPHA=1
CPHA=1
CPOL=0
CPOL=1
t
su(MI)
t
v(MO)
t
h(MO)
STM8S005K6 STM8S005C6Electrical characteristics
Figure 40: SPI timing diagram - master mode
(1)
1. Measurement points are made at CMOS levels: 0.3 VDDand 0.7 VDD.
w(SCLL)
w(SCLH)
su(SDA)
h(SDA)
t
r(SDA)
t
r(SCL)
t
f(SDA)
t
f(SCL)
I2C interface characteristics9.3.10
SDA data hold timet
Table 42: I2C characteristics
Standard mode I2CParameterSymbol
Min
(3)
0
(2)
Max
(2)
Min
(4)
0
(2)
Max
(1)
(2)
(3)
UnitFast mode I2C
μs1.34.7SCL clock low timet
μs0.64.0SCL clock high timet
ns100250SDA setup timet
ns900
ns3001000SDA and SCL rise time
ns300300SDA and SCL fall time
DocID022186 Rev 384/103
ai15385b
START
SDA
I²C bus
V
DD
V
DD
STM8Sx05xx
SDA
SCL
t
f(SDA)
t
r(SDA)
SCL
t
h(STA)
t
w(SCLH)
t
w(SCLL)
t
su(SDA)
t
r(SCL)
t
f(SCL)
t
h(SDA)
START REPEATED
START
t
su(STA)
t
su(STO)
STOP
t
su(STA:STO)
Electrical characteristicsSTM8S005K6 STM8S005C6
(1)
Standard mode I2CParameterSymbol
UnitFast mode I2C
Max
(2)
μs0.64.0START condition hold timet
μs0.64.7
h(STA)
t
su(STA)
Repeated START condition
Min
(2)
Max
(2)
Min
(2)
setup time
su(STO)
t
w(STO:STA)
STOP to START condition time
μs0.64.0STOP condition setup timet
μs1.34.7
(bus free)
b
(1)
f
MASTER
(2)
Data based on standard I2C protocol requirement, not tested in production.
(3)
The maximum hold time of the start condition has only to be met if the interface does not stretch the
, must be at least 8 MHz to achieve max fast I2C speed (400kHz).
pF400400Capacitive load for each bus lineC
low time.
(4)
The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge
the undefined region of the falling edge of SCL.
Figure 41: Typical application with I2C bus and timing diagram
1. Measurement points are made at CMOS levels: 0.3 x VDDand 0.7 x V
(1)
DD
85/103DocID022186 Rev 3
STM8S005K6 STM8S005C6Electrical characteristics
10-bit ADC characteristics9.3.11
Subject to general operating conditions for V
Table 43: ADC characteristics
ADC
DDA
Positive reference voltageV
Negative reference voltageV
Conversion voltage range
(2)
V
REF+
REF-
AIN
Devices with
external
V
, f
DDA
MASTER
=2.95 to 5.5 VADC clock frequencyf
DDA
=4.5 to 5.5 V
DDA
REF+/VREF-
, and TAunless otherwise specified.
UnitMaxTypMinConditionsParameterSymbol
6.01.0V
(1)
2.75
V SSA
V
REF-
DDA
(1)
V DDAV SSA
REF+
pins
MHz4.01.0V
V5.53.0Analog supplyV
VV
V0.5
V
VV
C
ADC
pF3.0Internal sample and hold
capacitor
(2)
S
STAB
t
CONV
ADC
ADC
ADC
= 4 MHzSampling timet
= 6 MHz
= 4 MHzTotal conversion time
0.5f
µs0.75f
µs7.0Wakeup time from standbyt
µs3.5f
(including sampling time,
10-bit resolution)
(1)
Data guaranteed by design, not tested in production..
(2)
During the sample time the input capacitance C
ADC
= 6 MHz
AIN
14
(3 pF max) can be charged/discharged
µs2.33f
1/f
by the external source. The internal resistance of the analog source must allow the
capacitance to reach its final voltage level within tS.After the end of the sample time tS,
ADC
DocID022186 Rev 386/103
Electrical characteristicsSTM8S005K6 STM8S005C6
changes of the analog input voltage have no effect on the conversion result. Values for the
sample clock tSdepend on programming.
|ET|
|EO|
|EG|
Table 44: ADC accuracy with R
(2)
(2)
(2)
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
= 2 MHzTotal unadjusted error
= 4 MHz
= 6 MHz
= 2 MHzOffset error
= 4 MHz
= 6 MHz
= 2 MHzGain error
= 4 MHz
< 10 kΩ , V
AIN
DDA
TypConditionsParameterSymbol
= 5 V
(1)
UnitMax
LSB2.51.0f
3.01.4f
3.51.6f
2.00.6f
2.51.1f
2.51.2f
2.00.2f
2.50.6f
= 6 MHz
ADC
|ED|
|EL|
(1)
Data based on characterisation results, not tested in production.
(2)
ADC accuracy vs. negative injection current: Injecting negative current on any of the
(2)
(2)
ADC
ADC
ADC
ADC
ADC
ADC
= 2 MHzDifferential linearity error
= 4 MHz
= 6 MHz
= 2 MHzIntegral linearity error
= 4 MHz
= 6 MHz
2.50.8f
1.50.7f
1.50.7f
1.50.8f
1.50.6f
1.50.6f
1.50.6f
analog input pins should be avoided as this significantly reduces the accuracy of the
conversion being performed on another analog input. It is recommended to add a Schottky
diode (pin to ground) to standard analog pins which may potentially inject negative current.
87/103DocID022186 Rev 3
STM8S005K6 STM8S005C6Electrical characteristics
Any positive injection current within the limits specified for I
INJ(PIN)
port pin characteristics section does not affect the ADC accuracy.
|ET|
|EO|
|EG|
|ED|
Table 45: ADC accuracy with R
(2)
(2)
(2)
(2)
ADC
ADC
ADC
ADC
ADC
ADC
ADC
< 10 kΩ R
AIN
= 2 MHzTotal unadjusted error
= 4 MHz
= 2 MHzOffset error
= 4 MHz
= 2 MHzGain error
= 4 MHz
= 2 MHzDifferential linearity error
AIN
, V
and ΣI
DDA
TypConditionsParameterSymbol
INJ(PIN)
= 3.3 V
2.51.6f
1.50.7f
2.01.3f
1.50.2f
2.00.5f
1.00.7f
in the I/O
(1)
UnitMax
LSB2.01.1f
= 4 MHz
ADC
|EL|
(1)
Data based on characterisation results, not tested in production.
(2)
ADC accuracy vs. negative injection current: Injecting negative current on any of the
(2)
ADC
ADC
= 2 MHzIntegral linearity error
= 4 MHz
1.00.7f
1.50.6f
1.50.6f
analog input pins should be avoided as this significantly reduces the accuracy of the
conversion being performed on another analog input. It is recommended to add a Schottky
diode (pin to ground) to standard analog pins which may potentially inject negative current.
Any positive injection current within the limits specified for I
INJ(PIN)
and ΣI
INJ(PIN)
in I/O port
pin characteristics does not affect the ADC accuracy.
DocID022186 Rev 388/103
Figure 42: ADC accuracy characteristics
STM8
10-bit A/D
conversion
R
AIN
C
AIN
V
AIN
AINx
V
DD
V
T
0.6 V
V
T
0.6 V
I
L
± 1 µA
C
ADC
1. Example of an actual transfer curve.
2. The ideal transfer curve
3. End point correlation line
Electrical characteristicsSTM8S005K6 STM8S005C6
ET= Total unadjusted error: maximum deviation between the actual and the ideal transfer
curves.
EO= Offset error: deviation between the first actual transition and the first ideal one.
EG= Gain error: deviation between the last ideal transition and the last actual one.
ED= Differential linearity error: maximum deviation between actual steps and the ideal
one.
EL= Integral linearity error: maximum deviation between any actual transition and the end
point correlation line.
Figure 43: Typical application with ADC
EMC characteristics9.3.12
Susceptibility tests are performed on a sample basis during product characterization.
While executing a simple application (toggling 2 LEDs through I/O ports), the product is
stressed by two electromagnetic events until a failure occurs (indicated by the LEDs).
FESD: Functional electrostatic discharge (positive and negative) is applied on all pins of
•
the device until a functional disturbance occurs. This test conforms with the IEC 61000-4-2
standard.
FTB: A burst of fast transient voltage (positive and negative) is applied to VDDand V
•
through a 100 pF capacitor, until a functional disturbance occurs. This test conforms with
the IEC 61000-4-4 standard.
A device reset allows normal operations to be resumed. The test results are given in the table
below based on the EMS levels and classes defined in application note AN1709 (EMC design
guide for STMicrocontrollers).
SS
Designing hardened software to avoid noise problems9.3.12.2
EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
V
FESD
V
EFTB
Software recommendations
The software flowchart must include the management of runaway conditions such as:
Corrupted program counter
•
Unexpected reset
•
Critical data corruption (control registers...)
•
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
recovered by applying a low state on the NRST pin or the oscillator pins for 1 second.
To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring. See application note AN1015 (Software techniques
for improving microcontroller EMC performance).
Table 46: EMS data
Level/ classConditionsParameterSymbol
Voltage limits to be applied on
any I/O pin to induce a
functional disturbance
Fast transient voltage burst
limits to be applied through 100
pF on VDDand VSSpins to
induce a functional disturbance
VDD= 5 V, TA= 25 °C, f
conforming to IEC 1000-4-2
VDD= 5 V, TA= 25 °C ,f
to IEC 1000-4-4
MASTER
MASTER
= 16 MHz,
= 16 MHz,conforming
2/B
4/A
(1)
(1)
DocID022186 Rev 390/103
Electrical characteristicsSTM8S005K6 STM8S005C6
(1)
Data obtained with HSI clock configuration, after applying HW recommendations described in AN2860 (EMC
guidelines for STM8S microcontrollers).
Electromagnetic interference (EMI)9.3.12.3
Emission tests conform to the IEC61967-2 standard for test software, board layout and pin
loading.
Table 47: EMI data
UnitConditionsParameterSymbol
General
conditions
Monitored
frequency
band
Max f
8 MHz/ 8
MHz
EMI
Peak levelS
VDD= 5 V,
TA= +25 °C,
30 MHz
LQFP48
package
conforming to
130 MHz
IEC61967-2
GHz
level
(1)
Data based on characterization results, not tested in production.
Absolute maximum ratings (electrical sensitivity)9.3.12.4
HSE/fCPU
(1)
8 MHz/ 16
MHz
dBµV14130.1 MHz to
192330 MHz to
-4.0-4.0130 MHz to 1
—1.52.0SAE EMI
Based on two different tests (ESD and LU) using specific measurement methods, the product
is stressed in order to determine its performance in terms of electrical sensitivity. For more
details, refer to the application note AN1181.
Electrostatic discharge (ESD)9.3.12.5
Electrostatic discharges (3 positive then 3 negative pulses separated by 1 second) are applied
to the pins of each sample according to each pin combination. The sample size depends on
the number of supply pins in the device (3 parts*(n+1) supply pin). This test conforms to the
JESD22-A114A/A115A standard. For more details, refer to the application note AN1181.
91/103DocID022186 Rev 3
STM8S005K6 STM8S005C6Electrical characteristics
Table 48: ESD absolute maximum ratings
(1)
UnitMaximum
V2000ATA= +25°C,
V1000IVTA=+25°C, conforming
V
ESD(HBM)
V
ESD(CDM)
(1)
Data based on characterization results, not tested in production
Electrostatic discharge
voltage (Human body model)
Electrostatic discharge
voltage (Charge device
model)
conforming to
JESD22-A114
to JESD22-C101
ClassConditionsRatingsSymbol
value
Static latch-up9.3.12.6
Two complementary static tests are required on 10 parts to assess the latch-up performance:
A supply overvoltage (applied to each power supply pin)
•
A current injection (applied to each input, output and configurable I/O pin) are performed
•
on each sample.
This test conforms to the EIA/JESD 78 IC latch-up standard. For more details, refer to the
application note AN1181.
Table 49: Electrical sensitivities
(1)
ConditionsParameterSymbol
(1)
Class description: A Class is an STMicroelectronics internal specification. All its limits
are higher than the JEDEC specifications, that means when a device belongs to class A it
exceeds the JEDEC standard. B class strictly covers all the JEDEC criteria (international
standard).
Class
ATA= +25 °CStatic latch-up classLU
ATA= +85 °C
DocID022186 Rev 392/103
5B_ME
L
A1K
L1
c
A
A2
ccc
C
D
D1
D3
E3
E1 E
24
25
36
37
b
48
1
Pin 1
identification
12
13
Package informationSTM8S005K6 STM8S005C6
Package information10
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK®packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com. ECOPACK
is an ST trademark.
Table 51: 32-pin low profile quad flat package mechanical data
mmDim.
inches
(1)
MaxTypMinMaxTypMin
0.06301.600A
0.00590.00200.1500.050A1
0.05710.05510.05311.4501.4001.350A2
0.01770.01460.01180.4500.3700.300b
0.00790.00350.2000.090c
0.36220.35430.34659.2009.0008.800D
0.22055.600D3
0.28350.27560.26777.2007.0006.800D1
0.36220.35430.34659.2009.0008.800E
0.28350.27560.26777.2007.0006.800E1
95/103DocID022186 Rev 3
STM8S005K6 STM8S005C6Package information
mmDim.
inches
(1)
0.22055.600E3
0.03150.800e
0.03941.000L1
(1)
Values in inches are converted from mm and rounded to 4 decimal digits
MaxTypMinMaxTypMin
0.02950.02360.01770.7500.6000.450L
7.0°3.5°0°7.0°3.5°0°k
0.00390.100ccc
DocID022186 Rev 396/103
Thermal characteristicsSTM8S005K6 STM8S005C6
Thermal characteristics11
The maximum chip junction temperature (T
Operating conditions
The maximum chip-junction temperature, T
the following equation:
T
= T
Jmax
Where:
T
Amax
•
ΘJAis the package junction-to-ambient thermal resistance in ° C/W
•
P
Dmax
•
P
INTmax
•
power.
P
I/Omax
•
+ Σ((VDD-V
and high level in the application.
Θ
JA
+ (P
Amax
is the maximum ambient temperature in °C
is the sum of P
is the product of IDDandVDD, expressed in Watts. This is the maximum chip internal
represents the maximum power dissipation on output pinsWhere:P
OH)*IOH
LQFP 48 - 7 x 7 mm
x ΘJA)
Dmax
and P
INTmax
), taking into account the actual VOL/I
Table 52: Thermal characteristics
I/Omax(PDmax
) must never exceed the values given in
J max
, in degrees Celsius, may be calculated using
Jmax
= P
+ P
INTmax
OL andVOH/IOH
I/Omax
(1)
)
=Σ (VOL*IOL)
I/Omax
of the I/Os at low
UnitValueParameterSymbol
°C/W57Thermal resistance junction-ambient
Θ
JA
LQFP 32 - 7 x 7 mm
1. Thermal resistances are based on JEDEC JESD51-2 with 4-layer PCB in a natural
convection environment.
°C/W60Thermal resistance junction-ambient
Reference document11.1
JESD51-2 integrated circuits thermal test method environment conditions - natural convection
(still air). Available from www.jedec.org.
Selecting the product temperature range11.2
When ordering the microcontroller, the temperature range is specified in the order code.
The following example shows how to calculate the temperature range needed for a given
application.
Assuming the following application conditions:
Maximum ambient temperature T
•
I
•
= 15 mA, VDD= 5.5 V
DDmax
= 82 °C (measured according to JESD51-2)
Amaz
97/103DocID022186 Rev 3
STM8S005K6 STM8S005C6Thermal characteristics
Maximum 8 standard I/Os used at the same time in output at low level with IOL= 10 mA,
•
VOL= 2 V
Maximum 4 high sink I/Os used at the same time in output at low level with IOL= 20 mA,
•
VOL= 1.5 V
Maximum 2 true open drain I/Os used at the same time in output at low level with IOL=
•
20 mA, VOL= 2 V
P
P
This gives: P
P
Thus: P
T
Jmax
T
Jmax
This is within the range of the suffix 6 version parts (-40 < TJ< 106° C). In this case, parts
must be ordered at least with the temperature range suffix 6.
= 15 mA x 5.5 V = 82.5 mW
INTmax
= (10 mA x 2 V x 8 )+(20 mA x 2 V x 2)+(20 mA x 1.5 V x 4) = 360 mW
IOmax
= 82.5 mW and P
INTmax
= 82.5 mW + 360 mW
Dmax
= 443 mW
Dmax
for LQFP32 can be calculated as follows, using the thermal resistance ΘJA:
= 75° C + (59° C/W x 464 mW) = 75°C + 27°C = 102° C
IOmax
360 mW:
DocID022186 Rev 398/103
Product class
Pin count
K = 32 pins
C = 48 pins
Package type
T = LQFP
Example:
Sub-family type
005 = Value line STM8S005x
Family type
S = Standard
Temperature range
6 = -40 °C to 85 °C
Program memory size
6 = 32 Kbytes
Package pitch
No character = 0.5 mm
C = 0.8 mm
Packing
No character = Tray or tube
TR = Tapeand reel
STM8
S
005
K6T
6
C
TR
Ordering informationSTM8S005K6 STM8S005C6
Ordering information12
Figure 46: STM8S005xx value line ordering information scheme
1. For a list of available options (e.g. memory size, package) and orderable part numbers or
for further information on any aspect of this device, please go to www.st.com or contact
the ST sales office nearest to you.
99/103DocID022186 Rev 3
STM8S005K6 STM8S005C6STM8 development tools
STM8 development tools13
Development tools for the STM8 microcontrollers include the full-featured STice emulation
system supported by a complete software tool package including C compiler, assembler and
integrated development environment with high-level language debugger. In addition, the
STM8 is to be supported by a complete range of tools including starter kits, evaluation boards
and a low-cost in-circuit debugger/programmer.
Emulation and in-circuit debugging tools13.1
The STice emulation system offers a complete range of emulation and in-circuit debugging
features on a platform that is designed for versatility and cost-effectiveness. In addition, STM8
application development is supported by a low-cost in-circuit debugger/programmer.
The STice is the fourth generation of full featured emulators from STMicroelectronics. It offers
new advanced debugging capabilities including profiling and coverage to help detect and
eliminate bottlenecks in application execution and dead code when fine tuning an application.
In addition, STice offers in-circuit debugging and programming of STM8 microcontrollers via
the STM8 single wire interface module (SWIM), which allows non-intrusive debugging of an
application while it runs on the target microcontroller.
For improved cost effectiveness, STice is based on a modular design that allows you to order
exactly what you need to meet your development requirements and to adapt your emulation
system to support existing and future ST microcontrollers.
STice key features
Occurrence and time profiling and code coverage (new features)
•
Advanced breakpoints with up to 4 levels of conditions
•
Data breakpoints
•
Program and data trace recording up to 128 KB records
•
Read/write on the fly of memory during emulation
•
In-circuit debugging/programming via SWIM protocol
•
8-bit probe analyzer
•
1 input and 2 output triggers
•
Power supply follower managing application voltages between 1.62 to 5.5 V
•
Modularity that allows you to specify the components you need to meet your development
•
requirements and adapt to future requirements
Supported by free software tools that include integrated development environment (IDE),
•
programming software interface and assembler for STM8.
Software tools13.2
STM8 development tools are supported by a complete, free software package from
STMicroelectronics that includes ST Visual Develop (STVD) IDE and the ST Visual
Programmer (STVP) software interface. STVD provides seamless integration of the Cosmic
and Raisonance C compilers for STM8, which are available in a free version that outputs up
to 16 Kbytes of code.
DocID022186 Rev 3100/103
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