ST STM8S005K6, STM8S005C6 User Manual

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Value line, 16 MHz STM8S 8-bit MCU, 32 Kbytes Flash, data

LQFP48 7x7

LQFP32 7x7

EEPROM,10-bit ADC, timers, UART, SPI, I²C

Features

Core

16 MHz advanced STM8 core with Harvard

•

architecture and 3-stage pipeline

Extended instruction set

•

Memories

Medium-density Flash/EEPROM:

•

Program memory: 32 Kbytes of Flash

memory; data retention 20 years at 55°C after 100 cycles

Data memory: 128 bytes of true data

EEPROM; endurance up to 100 k write/erase cycles

STM8S005K6 STM8S005C6

Permanently active, low consumption power-on

•

and power-down reset

Interrupt management

Nested interrupt controller with 32 interrupts

•

Up to 37 external interrupts on 6 vectors

•

Timers

2x 16-bit general purpose timers, with 2+3

•

CAPCOM channels (IC, OC or PWM)

Advanced control timer: 16-bit, 4 CAPCOM

•

channels, 3 complementary outputs, dead-time insertion and flexible synchronization

8-bit basic timer with 8-bit prescaler

•

Auto wake-up timer

•

Window and independent watchdog timers

•

Communications interfaces

UART with clock output for synchronous

•

operation, Smartcard, IrDA, LIN

SPI interface up to 8 Mbit/s

•

I2C interface up to 400 Kbit/s

•

Analog-to-digital converter (ADC)

10-bit, ±1 LSB ADC with up to 10 multiplexed

•

channels, scan mode and analog watchdog

RAM: 2 Kbytes

•

Clock, reset and supply management

2.95 V to 5.5 V operating voltage

•

Flexible clock control, 4 master clock sources:

•

Low power crystal resonator oscillator

External clock input

Internal, user-trimmable 16 MHz RC

Internal low power 128 kHz RC

Clock security system with clock monitor

•

Power management:

•

Low power modes (wait, active-halt, halt)

Switch-off peripheral clocks individually

June 2012

I/Os

Up to 38 I/Os on a 48-pin package including 16

•

high sink outputs

Highly robust I/O design, immune against current

•

injection

Development support

Embedded single wire interface module (SWIM)

•

for fast on-chip programming and non intrusive debugging

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www.st.com

STM8S005K6 STM8S005C6Contents

1 Introduction ..............................................................................................................7

2 Description ...............................................................................................................8

3 Block diagram ..........................................................................................................9

4 Product overview ...................................................................................................10

4.1 Central processing unit STM8 .....................................................................................10

4.2 Single wire interface module (SWIM) and debug module (DM) ..................................10

4.3 Interrupt controller .......................................................................................................11

4.4 Flash program and data EEPROM memory ................................................................11

4.5 Clock controller ............................................................................................................12

4.6 Power management ....................................................................................................13

4.7 Watchdog timers ..........................................................................................................14

4.8 Auto wakeup counter ...................................................................................................14

4.9 Beeper ........................................................................................................................14

4.10 TIM1 - 16-bit advanced control timer .........................................................................15

4.11 TIM2, TIM3 - 16-bit general purpose timers ..............................................................15

4.12 TIM4 - 8-bit basic timer ..............................................................................................15

4.13 Analog-to-digital converter (ADC1) ............................................................................16

4.14 Communication interfaces .........................................................................................16

4.14.1 UART2 ...............................................................................................16

4.14.2 SPI .....................................................................................................17

4.14.3 I²C ......................................................................................................18

5 Pinout and pin description ...................................................................................19

5.1 STM8S005 pinouts and pin description .......................................................................20

5.1.1 Alternate function remapping ...............................................................24

6 Memory and register map .....................................................................................25

6.1 Memory map ................................................................................................................25

6.2 Register map ...............................................................................................................26

6.2.1 I/O port hardware register map ............................................................26

6.2.2 General hardware register map ...........................................................29

6.2.3 CPU/SWIM/debug module/interrupt controller registers ......................39

7 Interrupt vector mapping ......................................................................................42

8 Option bytes ...........................................................................................................44

9 Electrical characteristics ......................................................................................49

9.1 Parameter conditions ...................................................................................................49

9.1.1 Minimum and maximum values ...........................................................49

9.1.2 Typical values .......................................................................................49

9.1.3 Typical curves ......................................................................................49

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ContentsSTM8S005K6 STM8S005C6

9.1.4 Typical current consumption ................................................................49

9.1.5 Loading capacitor .................................................................................50

9.1.6 Pin input voltage ...................................................................................50

9.2 Absolute maximum ratings ..........................................................................................50

9.3 Operating conditions ...................................................................................................52

9.3.1 VCAP external capacitor ......................................................................54

9.3.2 Supply current characteristics ..............................................................55

9.3.3 External clock sources and timing characteristics ...............................66

9.3.4 Internal clock sources and timing characteristics .................................68

9.3.5 Memory characteristics ........................................................................70

9.3.6 I/O port pin characteristics ...................................................................72

9.3.7 Typical output level curves ...................................................................75

9.3.8 Reset pin characteristics ......................................................................79

9.3.9 SPI serial peripheral interface ..............................................................81

9.3.10 I2C interface characteristics ...............................................................84

9.3.11 10-bit ADC characteristics ..................................................................86

9.3.12 EMC characteristics ...........................................................................89

10 Package information ...........................................................................................93

10.1 48-pin LQFP package mechanical data ....................................................................93

10.2 32-pin LQFP package mechanical data ....................................................................95

11 Thermal characteristics .......................................................................................97

11.1 Reference document .................................................................................................97

11.2 Selecting the product temperature range ..................................................................97

12 Ordering information ...........................................................................................99

13 STM8 development tools ..................................................................................100

13.1 Emulation and in-circuit debugging tools .................................................................100

13.2 Software tools ..........................................................................................................100

13.2.1 STM8 toolset ....................................................................................101

13.2.2 C and assembly toolchains ..............................................................101

13.3 Programming tools ..................................................................................................101

14 Revision history .................................................................................................102

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STM8S005K6 STM8S005C6List of tables

List of tables

Table 1. STM8S005xx value line features ................................................................................................8

Table 2. Peripheral clock gating bit assignments in CLK_PCKENR1/2 registers ..................................13

Table 3. TIM timer features ...................................................................................................................15

Table 4. Legend/abbreviations for pinout tables ...................................................................................19

Table 5. Pin description for STM8S005 microcontrollers .......................................................................21

Table 6. Flash, Data EEPROM and RAM boundary addresses ............................................................26

Table 7. I/O port hardware register map ................................................................................................26

Table 8. General hardware register map ................................................................................................29

Table 9. CPU/SWIM/debug module/interrupt controller registers ..........................................................39

Table 10. Interrupt mapping ...................................................................................................................42

Table 11. Option bytes ...........................................................................................................................44

Table 12. Option byte description ...........................................................................................................45

Table 13. Description of alternate function remapping bits [7:0] of OPT2 ..............................................47

Table 14. Voltage characteristics ...........................................................................................................50

Table 15. Current characteristics ...........................................................................................................51

Table 16. Thermal characteristics ..........................................................................................................52

Table 17. General operating conditions .................................................................................................53

Table 18. Operating conditions at power-up/power-down ......................................................................54

Table 19. Total current consumption with code execution in run mode at VDD= 5 V .............................55

Table 20. Total current consumption with code execution in run mode at VDD= 3.3 V ..........................66

Table 21. Total current consumption in wait mode at VDD= 5 V ............................................................58

Table 22. Total current consumption in wait mode at VDD= 3.3 V .........................................................58

Table 23. Total current consumption in active halt mode at VDD= 5 V ..................................................59

Table 24. Total current consumption in active halt mode at VDD= 3.3 V ...............................................60

Table 25. Total current consumption in halt mode at VDD= 5 V .............................................................61

Table 26. Total current consumption in halt mode at VDD= 3.3 V ..........................................................61

Table 27. Wakeup times .........................................................................................................................61

Table 28. Total current consumption and timing in forced reset state ....................................................92

Table 29. Peripheral current consumption .............................................................................................63

Table 30. HSE user external clock characteristics .................................................................................66

Table 31. HSE oscillator characteristics .................................................................................................67

Table 32. HSI oscillator characteristics ..................................................................................................68

Table 33. LSI oscillator characteristics ...................................................................................................70

Table 34. RAM and hardware registers ..................................................................................................70

Table 35. Flash program memory/data EEPROM memory ....................................................................71

Table 36. I/O static characteristics .........................................................................................................72

Table 37. Output driving current (standard ports) ..................................................................................74

Table 38. Output driving current (true open drain ports) ........................................................................74

Table 39. Output driving current (high sink ports) ..................................................................................74

Table 40. NRST pin characteristics ........................................................................................................79

Table 41. SPI characteristics ..................................................................................................................81

Table 42. I2C characteristics ..................................................................................................................84

Table 43. ADC characteristics ................................................................................................................86

Table 44. ADC accuracy with R Table 45. ADC accuracy with R

Table 46. EMS data ................................................................................................................................90

Table 47. EMI data .................................................................................................................................91

< 10 kΩ , V

AIN

< 10 kΩ R

AIN

= 5 V .......................................................................87

DDA

AIN

, V

= 3.3 V ............................................................88

DDA

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List of tablesSTM8S005K6 STM8S005C6

Table 48. ESD absolute maximum ratings .............................................................................................92

Table 49. Electrical sensitivities .............................................................................................................92

Table 50. 48-pin low profile quad flat package mechanical data ............................................................93

Table 51. 32-pin low profile quad flat package mechanical data .........................................................102

Table 52. Thermal characteristics

(1)

......................................................................................................97

Table 53. Document revision history ...................................................................................................102

5/103DocID022186 Rev 3

STM8S005K6 STM8S005C6List of figures

List of figures

Figure 1. STM8S005xx value line block diagram .....................................................................................9

Figure 2. Flash memory organization ....................................................................................................12

Figure 3. LQFP 48-pin pinout .................................................................................................................20

Figure 4. LQFP 32-pin pinout ................................................................................................................21

Figure 5. Memory map ...........................................................................................................................25

Figure 6. Supply current measurement conditions ................................................................................49

Figure 7. Pin loading conditions .............................................................................................................50

Figure 8. Pin input voltage .....................................................................................................................50

Figure 9. f

CPUmax

Figure 10. External capacitor C Figure 11. Typ. I Figure 12. Typ. I Figure 13. Typ. I Figure 14. Typ. I Figure 15. Typ. I Figure 16. Typ. I

Figure 17. HSE external clocksource .....................................................................................................67

Figure 18. HSE oscillator circuit diagram ...............................................................................................68

Figure 19. Typical HSI frequency variation vs VDD@ 3 temperatures ..................................................69

Figure 20. Typical LSI frequency variation vs VDD@ 3 temperatures ...................................................70

Figure 21. Typical VILand VIHvs VDD@ 3 temperatures ......................................................................73

Figure 22. Typical pull-up resistance vs VDD@ 3 temperatures ............................................................73

Figure 23. Typical pull-up current vs VDD@ 3 temperatures .................................................................73

Figure 24. Typ. VOL@ VDD= 5 V (standard ports) ................................................................................75

Figure 25. Typ. VOL@ VDD= 3.3 V (standard ports) .............................................................................76

Figure 26. Typ. VOL@ VDD= 5 V (true open drain ports) ......................................................................76

Figure 27. Typ. VOL@ VDD= 3.3 V (true open drain ports) ...................................................................76

Figure 28. Typ. VOL@ VDD= 5 V (high sink ports) ................................................................................77

Figure 29. Typ. VOL@ VDD= 3.3 V (high sink ports) .............................................................................77

Figure 30. Typ. VDD- VOH@ VDD= 5 V (standard ports) .......................................................................77

Figure 31. Typ. VDD- VOH@ VDD= 3.3 V (standard ports) ....................................................................78

Figure 32. Typ. VDD- VOH@ VDD= 5 V (high sink ports) ......................................................................78

Figure 33. Typ. VDD- VOH@ VDD= 3.3 V (high sink ports) ...................................................................78

Figure 34. Typical NRST VILand VIHvs VDD@ 3 temperatures ...........................................................80

Figure 35. Typical NRST pull-up resistance vs VDD@ 3 temperatures .................................................80

Figure 36. Typical NRST pull-up current vs VDD@ 3 temperatures ......................................................80

Figure 37. Recommended reset pin protection ......................................................................................81

Figure 38. SPI timing diagram - slave mode and CPHA = 0 ..................................................................83

Figure 39. SPI timing diagram - slave mode and CPHA = 1 Figure 40. SPI timing diagram - master mode Figure 41. Typical application with I2C bus and timing diagram

Figure 42. ADC accuracy characteristics ...............................................................................................89

Figure 43. Typical application with ADC ................................................................................................89

Figure 44. 48-pin low profile quad flat package (7 x 7) ..........................................................................93

Figure 45. 32-pin low profile quad flat package (7 x 7) ..........................................................................95

Figure 46. STM8S005xx value line ordering information scheme .........................................................99

versus V

DD(RUN)

DD(WFI)

................................................................................................................54

vs. V

vs. f

vs. V vs. V vs. f

DD ,

CPU ,

DD ,

CPU

.......................................................................................................55

EXT

HSE user external clock, f

HSE user external clock, VDD= 5 V ..................................................64

HSI RC osc, f

HSE user external clock, f

, HSE user external clock VDD= 5 V ....................................................65

vs. VDD, HSI RC osc, f

= 16 MHz ...........................................64

CPU

= 16 MHz ..............................................................65

CPU

= 16 MHz ................................................................66

CPU

(1)

...................................................................................84

= 16 MHz ............................................65

CPU

(1)

.............................................................83

(1)

.......................................................85

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IntroductionSTM8S005K6 STM8S005C6

Introduction1

This datasheet contains the description of the device features, pinout, electrical characteristics, mechanical data and ordering information.

For complete information on the STM8S microcontroller memory, registers and peripherals,

•

please refer to the STM8S microcontroller family reference manual (RM0016).

For information on programming, erasing and protection of the internal Flash memory

•

please refer to the STM8S Flash programming manual (PM0051).

For information on the debug and SWIM (single wire interface module) refer to the STM8

•

SWIM communication protocol and debug module user manual (UM0470).

For information on the STM8 core, please refer to the STM8 CPU programming manual

•

(PM0044).

7/103DocID022186 Rev 3

STM8S005K6 STM8S005C6Description

Description2

The STM8S005xx value line 8-bit microcontrollers offer 32 Kbytes of Flash program memory, plus 128 bytes of data EEPROM. They are referred to as medium-density devices in the STM8S microcontroller family reference manual (RM0016). All devices of the STM8S005xx value line provide the following benefits: performance, robustness, reduced system cost, and short develoment cycles.

Device performance and robustness are ensured by true data EEPROM supporting up to 100 000 write/erase cycles, advanced core and peripherals made in a state-of-the art technology, a 16 MHz clock frequency, robust I/Os, independent watchdogs with separate clock source, and a clock security system.

The system cost is reduced thanks to high system integration level with internal clock oscillators, watchdog and brown-out reset.

Common family product architecture with compatible pinout, memory map and modular peripherals allow application scalability and reduced development cycles.

All products operate from a 2.95 to 5.5 V supply voltage.

Full documentation is offered as well as a wide choice of development tools.

Table 1: STM8S005xx value line features

STM8S005K6STM8S005C6Device

3248Pin count

(bytes)

Peripheral set

2538Maximum number of GPIOs

2335Ext. Interrupt pins

89Timer CAPCOM channels

33Timer complementary outputs

710A/D Converter channels

1216High sink I/Os

32K32KMedium density Flash Program memory

128128Data EEPROM (bytes)

2K2KRAM (bytes)

Advanced control timer (TIM1), General-purpose timers (TIM2 and TIM3), Basic timer (TIM4) SPI, I2C, UART, Window WDG, Independent WDG, ADC

DocID022186 Rev 38/103

XTAL 1-16 MHz

RC int. 16 MHz

RC int. 128 kHz

STM8 core

Debug/SWIM

I2C

SPI

UART2

16-bit general purpose

AWU timer

Reset block

Reset

POR/ PDR

BOR

Clock controller

Detector

Clock to peripherals and core

8 Mbit/s

Address and data bus

Window WDG

Independent WDG

32 Kbytes

128 bytes

2 Kbytes

Boot ROM

ADC1

Reset

400 Kbit/s

Single wire debug interf.

program Flash

16-bit advanced control

timer (TIM1)

timers (TIM2, TIM3)

8-bit basic timer

(TIM4)

data EEPROM

RAM

Master/slave autosynchro LIN master SPI emul.

Beeper

1/2/4 kHz beep

5 CAPCOM channels

Up to

4 CAPCOM channels +3

Up to

complementary outputs

Block diagramSTM8S005K6 STM8S005C6

Block diagram3

Figure 1: STM8S005xx value line block diagram

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STM8S005K6 STM8S005C6Product overview

Product overview4

The following section intends to give an overview of the basic features of the device functional modules and peripherals.

For more detailed information please refer to the corresponding family reference manual (RM0016).

Central processing unit STM84.1

The 8-bit STM8 core is designed for code efficiency and performance.

It contains 6 internal registers which are directly addressable in each execution context, 20 addressing modes including indexed indirect and relative addressing and 80 instructions.

Architecture and registers

Harvard architecture

•

3-stage pipeline

•

32-bit wide program memory bus - single cycle fetching for most instructions

•

X and Y 16-bit index registers - enabling indexed addressing modes with or without offset

•

and read-modify-write type data manipulations

8-bit accumulator

•

24-bit program counter - 16-Mbyte linear memory space

•

16-bit stack pointer - access to a 64 K-level stack

•

8-bit condition code register - 7 condition flags for the result of the last instruction

•

Addressing

20 addressing modes

•

Indexed indirect addressing mode for look-up tables located anywhere in the address

•

space

Stack pointer relative addressing mode for local variables and parameter passing

•

Instruction set

80 instructions with 2-byte average instruction size

•

Standard data movement and logic/arithmetic functions

•

8-bit by 8-bit multiplication

•

16-bit by 8-bit and 16-bit by 16-bit division

•

Bit manipulation

•

Data transfer between stack and accumulator (push/pop) with direct stack access

•

Data transfer using the X and Y registers or direct memory-to-memory transfers

•

Single wire interface module (SWIM) and debug module (DM)4.2

The single wire interface module and debug module permits non-intrusive, real-time in-circuit debugging and fast memory programming.

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Product overviewSTM8S005K6 STM8S005C6

SWIM

Single wire interface module for direct access to the debug module and memory programming. The interface can be activated in all device operation modes. The maximum data transmission speed is 145 bytes/ms.

Debug module

The non-intrusive debugging module features a performance close to a full-featured emulator. Beside memory and peripherals, also CPU operation can be monitored in real-time by means of shadow registers.

R/W to RAM and peripheral registers in real-time

•

R/W access to all resources by stalling the CPU

•

Breakpoints on all program-memory instructions (software breakpoints)

•

Two advanced breakpoints, 23 predefined configurations

•

Interrupt controller4.3

Nested interrupts with three software priority levels

•

32 interrupt vectors with hardware priority

•

Up to 37 external interrupts on 6 vectors including TLI

•

Trap and reset interrupts

•

Flash program and data EEPROM memory4.4

32 Kbytes of Flash program single voltage Flash memory

•

128 bytes true data EEPROM

•

Read while write: Writing in data memory possible while executing code in program memory

•

User option byte area

•

Write protection (WP)

Write protection of Flash program memory and data EEPROM is provided to avoid unintentional overwriting of memory that could result from a user software malfunction.

There are two levels of write protection. The first level is known as MASS (memory access security system). MASS is always enabled and protects the main Flash program memory, data EEPROM and option bytes.

To perform in-application programming (IAP), this write protection can be removed by writing a MASS key sequence in a control register. This allows the application to write to data EEPROM, modify the contents of main program memory or the device option bytes.

A second level of write protection, can be enabled to further protect a specific area of memory known as UBC (user boot code). Refer to the figure below.

The size of the UBC is programmable through the UBC option byte, in increments of 1 page (512 bytes) by programming the UBC option byte in ICP mode.

This divides the program memory into two areas:

Main program memory: 32 Kbytes minus UBC

•

User-specific boot code (UBC): Configurable up to 32 Kbytes

•

11/103DocID022186 Rev 3

Programmable area

Data

Program memory area

Data memory area ( 128 bytes)

EEPROM

UBC area

Remains write protected during IAP

memory

Write access possible for IAP

(1 page steps)

Option bytes

(2 first pages) up to

Medium density Flash program memory (32 Kbytes)

from 1 Kbyte 32 Kbytes

STM8S005K6 STM8S005C6Product overview

The UBC area remains write-protected during in-application programming. This means that the MASS keys do not unlock the UBC area. It protects the memory used to store the boot program, specific code libraries, reset and interrupt vectors, the reset routine and usually the IAP and communication routines.

Figure 2: Flash memory organization

Read-out protection (ROP)

The read-out protection blocks reading and writing the Flash program memory and data EEPROM memory in ICP mode (and debug mode). Once the read-out protection is activated, any attempt to toggle its status triggers a global erase of the program and data memory. Even if no protection can be considered as totally unbreakable, the feature provides a very high level of protection for a general purpose microcontroller.

Clock controller4.5

The clock controller distributes the system clock (f to the core and the peripherals. It also manages clock gating for low power modes and ensures clock robustness.

Features

Clock prescaler: To get the best compromise between speed and current consumption

•

the clock frequency to the CPU and peripherals can be adjusted by a programmable prescaler.

Safe clock switching: Clock sources can be changed safely on the fly in run mode

•

through a configuration register. The clock signal is not switched until the new clock source is ready. The design guarantees glitch-free switching.

Clock management: To reduce power consumption, the clock controller can stop the

•

clock to the core, individual peripherals or memory.

Master clock sources: Four different clock sources can be used to drive the master

•

clock:

1-16 MHz high-speed external crystal (HSE)

Up to 16 MHz high-speed user-external clock (HSE user-ext)

MASTER

) coming from different oscillators

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Product overviewSTM8S005K6 STM8S005C6

16 MHz high-speed internal RC oscillator (HSI)

128 kHz low-speed internal RC (LSI)

Startup clock: After reset, the microcontroller restarts by default with an internal 2 MHz

•

clock (HSI/8). The prescaler ratio and clock source can be changed by the application program as soon as the code execution starts.

Clock security system (CSS): This feature can be enabled by software. If an HSE clock

•

failure occurs, the internal RC (16 MHz/8) is automatically selected by the CSS and an interrupt can optionally be generated.

Configurable main clock output (CCO): This outputs an external clock for use by the

•

application.

Table 2: Peripheral clock gating bit assignments in CLK_PCKENR1/2 registers

Bit

Peripheral clock

ADCPCKEN2 3ReservedPCKEN2 7UART2PCKEN1 3TIM1PCKEN1 7

AWUPCKEN2 2ReservedPCKEN2 6ReservedPCKEN1 2TIM3PCKEN1 6

ReservedPCKEN2 1ReservedPCKEN2 5SPIPCKEN1 1TIM2PCKEN1 5

ReservedPCKEN2 0ReservedPCKEN2 4I2CPCKEN1 0TIM4PCKEN1 4

clock

BitPeripheral

clock

BitPeripheral

clock

BitPeripheral

Power management4.6

For efficent power management, the application can be put in one of four different low-power modes. You can configure each mode to obtain the best compromise between lowest power consumption, fastest start-up time and available wakeup sources.

Wait mode: In this mode, the CPU is stopped, but peripherals are kept running. The

•

wakeup is performed by an internal or external interrupt or reset.

Active halt mode with regulator on: In this mode, the CPU and peripheral clocks are

•

stopped. An internal wakeup is generated at programmable intervals by the auto wake up unit (AWU). The main voltage regulator is kept powered on, so current consumption is higher than in active halt mode with regulator off, but the wakeup time is faster. Wakeup is triggered by the internal AWU interrupt, external interrupt or reset.

Active halt mode with regulator off: This mode is the same as active halt with regulator

•

on, except that the main voltage regulator is powered off, so the wake up time is slower.

Halt mode: In this mode the microcontroller uses the least power. The CPU and peripheral

•

clocks are stopped, the main voltage regulator is powered off. Wakeup is triggered by external event or reset.

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STM8S005K6 STM8S005C6Product overview

Watchdog timers4.7

The watchdog system is based on two independent timers providing maximum security to the applications.

Activation of the watchdog timers is controlled by option bytes or by software. Once activated, the watchdogs cannot be disabled by the user program without performing a reset.

Window watchdog timer

The window watchdog is used to detect the occurrence of a software fault, usually generated by external interferences or by unexpected logical conditions, which cause the application program to abandon its normal sequence.

The window function can be used to trim the watchdog behavior to match the application perfectly.

The application software must refresh the counter before time-out and during a limited time window.

A reset is generated in two situations:

1. Timeout: At 16 MHz CPU clock the time-out period can be adjusted between 75 µs up to 64 ms.

2. Refresh out of window: The downcounter is refreshed before its value is lower than the one stored in the window register.

Independent watchdog timer

The independent watchdog peripheral can be used to resolve processor malfunctions due to hardware or software failures.

It is clocked by the 128 kHZ LSI internal RC clock source, and thus stays active even in case of a CPU clock failure

The IWDG time base spans from 60 µs to 1 s.

Auto wakeup counter4.8

Used for auto wakeup from active halt mode

•

Clock source: Internal 128 kHz internal low frequency RC oscillator or external clock

•

LSI clock can be internally connected to TIM3 input capture channel 1 for calibration

•

Beeper4.9

The beeper function outputs a signal on the BEEP pin for sound generation. The signal is in the range of 1, 2 or 4 kHz.

The beeper output port is only available through the alternate function remap option bit AFR7.

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Product overviewSTM8S005K6 STM8S005C6

TIM1 - 16-bit advanced control timer4.10

This is a high-end timer designed for a wide range of control applications. With its complementary outputs, dead-time control and center-aligned PWM capability, the field of applications is extended to motor control, lighting and half-bridge driver

16-bit up, down and up/down autoreload counter with 16-bit prescaler

•

Four independent capture/compare channels (CAPCOM) configurable as input capture,

•

output compare, PWM generation (edge and center aligned mode) and single pulse mode output

Synchronization module to control the timer with external signals

•

Break input to force the timer outputs into a defined state

•

Three complementary outputs with adjustable dead time

•

Encoder mode

•

Interrupt sources: 3 x input capture/output compare, 1 x overflow/update, 1 x break

•

TIM2, TIM3 - 16-bit general purpose timers4.11

16-bit autoreload (AR) up-counter

•

15-bit prescaler adjustable to fixed power of 2 ratios 1…32768

•

Timers with 3 or 2 individually configurable capture/compare channels

•

PWM mode

•

Interrupt sources: 2 or 3 x input capture/output compare, 1 x overflow/update

•

Timer

size (bits)

16TIM1

16TIM2

16TIM3

TIM4 - 8-bit basic timer4.12

8-bit autoreload, adjustable prescaler ratio to any power of 2 from 1 to 128

•

Clock source: CPU clock

•

Interrupt source: 1 x overflow/update

•

Table 3: TIM timer features

PrescalerCounter

Any integer from 1 to 65536

1 to 32768

Counting mode

down

CAPCOM channels

Complem. outputs

Ext. trigger

No03UpAny power of 2 from

No02UpAny power of 2 from

Timer synchronization/ chaining

NoYes34Up/

15/103DocID022186 Rev 3

STM8S005K6 STM8S005C6Product overview

Timer

Timer synchronization/ chaining

size (bits)

8TIM4

PrescalerCounter

1 to 128

Counting mode

CAPCOM channels

Complem. outputs

Ext. trigger

No00UpAny power of 2 from

Analog-to-digital converter (ADC1)4.13

The STM8S105xx products contain a 10-bit successive approximation A/D converter (ADC1) with up to 10 multiplexed input channels and the following main features:

Input voltage range: 0 to V

•

Conversion time: 14 clock cycles

•

Single and continuous and buffered continuous conversion modes

•

Buffer size (n x 10 bits) where n = number of input channels

•

Scan mode for single and continuous conversion of a sequence of channels

•

Analog watchdog capability with programmable upper and lower thresholds

•

Analog watchdog interrupt

•

External trigger input

•

Trigger from TIM1 TRGO

•

End of conversion (EOC) interrupt

•

DDA

Note: Additional AIN12 analog input is not selectable in ADC scan mode or with analog watchdog. Values converted from AIN12 are stored only into the ADC_DRH/ADC_DRL registers.

Communication interfaces4.14

The following communication interfaces are implemented:

UART2: Full feature UART, synchronous mode, SPI master mode, Smartcard mode, IrDA

•

mode, LIN2.1 master/slave capability

SPI : Full and half-duplex, 8 Mbit/s

•

I²C: Up to 400 Kbit/s

•

UART24.14.1

Main features

One Mbit/s full duplex SCI

•

SPI emulation

•

High precision baud rate generator

•

Smartcard emulation

•

IrDA SIR encoder decoder

•

DocID022186 Rev 316/103

LIN master mode

•

LIN slave mode

•

Asynchronous communication (UART mode)

Full duplex communication - NRZ standard format (mark/space)

•

Programmable transmit and receive baud rates up to 1 Mbit/s (f

•

following any standard baud rate regardless of the input frequency

Separate enable bits for transmitter and receiver

•

Two receiver wakeup modes:

•

Address bit (MSB)

Idle line (interrupt)

Transmission error detection with interrupt generation

•

Parity control

•

Synchronous communication

Full duplex synchronous transfers

•

SPI master operation

•

8-bit data communication

•

Maximum speed: 1 Mbit/s at 16 MHz (f

•

CPU

/16)

Product overviewSTM8S005K6 STM8S005C6

/16) and capable of

CPU

LIN master mode

Emission: Generates 13-bit synch break frame

•

Reception: Detects 11-bit break frame

•

LIN slave mode

Autonomous header handling - one single interrupt per valid message header

•

Automatic baud rate synchronization - maximum tolerated initial clock deviation ±15 %

•

Synch delimiter checking

•

11-bit LIN synch break detection - break detection always active

•

Parity check on the LIN identifier field

•

LIN error management

•

Hot plugging support

•

SPI4.14.2

Maximum speed: 8 Mbit/s (f

•

Full duplex synchronous transfers

•

Simplex synchronous transfers on two lines with a possible bidirectional data line

•

Master or slave operation - selectable by hardware or software

•

CRC calculation

•

1 byte Tx and Rx buffer

•

Slave/master selection input pin

•

MASTER

/2) both for master and slave

17/103DocID022186 Rev 3

STM8S005K6 STM8S005C6Product overview

I²C4.14.3

I²C master features:

•

Clock generation

Start and stop generation

I²C slave features:

•

Programmable I2C address detection

Stop bit detection

Generation and detection of 7-bit/10-bit addressing and general call

•

Supports different communication speeds:

•

Standard speed (up to 100 kHz)

Fast speed (up to 400 kHz)

DocID022186 Rev 318/103

Pinout and pin descriptionSTM8S005K6 STM8S005C6

Pinout and pin description5

Table 4: Legend/abbreviations for pinout tables

I= Input, O = Output, S = Power supplyType

Output speed

configuration

Reset state

InputLevel

O1 = Slow (up to 2 MHz)

O2 = Fast (up to 10 MHz)

O3 = Fast/slow programmability with slow as default state after reset

O4 = Fast/slow programmability with fast as default state after reset

Output

Bold X (pin state after internal reset release).

Unless otherwise specified, the pin state is the same during the reset phase and after the internal reset release.

CM = CMOS

HS = High sinkOutput

float = floating, wpu = weak pull-upInputPort and control

T = True open drain, OD = Open drain, PP = Push pull

19/103DocID022186 Rev 3

44 43 42 41 40 39 38 37

36 35 34 33 32 31 30 29 28 27 26 25

13 14 15 16 17 18

19 20 21 22

1 2 3 4 5 6 7 8 9 10 11

48 47 46 45

(HS) PA6

AIN8/PE7

PC1 (HS)/TIM1_CH1/UART2_CK

PE5/SPI_NSS

PG1

AIN9/PE6

PD3 (HS)/TIM2_CH2 [ADC_ETR]

PD2 (HS)/TIM3_CH1 [TIM2_CH3]

PE0 (HS)/CLK_CCO

PE1 (T)/I

C_SCL

PE2 (T)/I

C_SDA

PE3/TIM1_BKIN

PD7/TLI [TIM1_CH4]

PD6/UART2_RX

PD5/UART2_TX

PD4 (HS)/TIM2_CH1 [BEEP]

PD1 (HS)/SWIM

PD0 (HS)/TIM3_CH2 [TIM1_BKIN] [CLK_CCO]

SSIO_2

PC5 (HS)/SPI_SCK PC4 (HS)/TIM1_CH4 PC3 (HS)/TIM1_CH3

PC2 (HS)/TIM1_CH2

PG0

PC7 (HS)/SPI_MISO PC6 (HS)/SPI_MOSI V

DDIO_2

AIN7/PB7

AIN6/PB6

C_SDA] AIN5/PB5

C_SCL] AIN4/PB4

[TIM1_ETR/AIN3/PB3

[TIM1_CH3N] AIN2/PB2

[TIM1_CH2N] AIN1/PB1

[TIM1_CH1N] AIN0/PB0

DDA

SSA

VCAP

DDIO_1

[TIM3_CH1] TIM2_CH3/PA3

(HS) PA4

(HS) PA5

NRST

OSCIN/PA1

OSCOUT/PA2

SSIO_1

STM8S005K6 STM8S005C6Pinout and pin description

STM8S005 pinouts and pin description5.1

Figure 3: LQFP 48-pin pinout

1. (HS) high sink capability.

2. (T) True open drain (P-buffer and protection diode to VDDnot implemented).

3. [ ] alternate function remapping option (If the same alternate function is shown twice, it

indicates an exclusive choice not a duplication of the function).

DocID022186 Rev 320/103

Figure 4: LQFP 32-pin pinout

C_SCL] AIN4/PB4

[TIM1_ETR] AIN3/PB3

[TIM1_CH3N] AIN2/PB2

[TIM1_CH2N] AIN1/PB1

[TIM1_CH1N] AIN0/PB0

DDA

SSA

C_SDA] AIN5/PB5

32 31 30 29 28 27 26 25

24 23 22 21 20 19 18 17

9 10 11 12 13 14 15

1 2 3 4 5 6 7 8

VCAP

DDIO

AIN12/PF4

NRST

OSCIN/PA1

OSCOUT/PA2

PC3 (HS)/TIM1_CH3 PC2 (HS)/TIM1_CH2

PC1 (HS)/TIM1_CH1/UART2_CK PE5/SPI_NSS

PC7 (HS)/SPI_MISO PC6 (HS)/SPI_MOSI PC5 (HS)/SPI_SCK PC4 (HS)/TIM1_CH4

PD3 (HS)/TIM2_CH2 [ADC_ETR]

PD2 (HS)/TIM3_CH1[TIM2_CH3]

PD1 (HS)/SWIM

PD0 (HS)/TIM3_CH2 [TIM1_BKIN][CLK_CCO]

PD7/TLI [TIM1_CH4]

PD6/UART2_RX

PD5/UART2_TX

PD4 (HS)/TIM2_CH1 [BEEP]

Pinout and pin descriptionSTM8S005K6 STM8S005C6

-4

1. (HS) high sink capability.

2. [ ] alternate function remapping option (If the same alternate function is shown twice, it

indicates an exclusive choice not a duplication of the function).

Table 5: Pin description for STM8S005 microcontrollers

Default alternate function

Resonator/Port A1XXO1XXI/OPA1/ OSC

crystal in

Resonator/Port A2XXO1XXXI/OPA2/ OSC

crystal out

OUT

SSIO_1

wpufloatingLQFP32LQFP48

Ext. interrupt

OutputInputTypePin namePin number

sink

PPODSpeedHigh

Main function (after reset)

ResetXI/ONRST11

I/O groundSV

Digital groundSV

Alternate function after remap [option bit]

21/103DocID022186 Rev 3

STM8S005K6 STM8S005C6Pinout and pin description

(2)

Alternate function after remap [option bit]

TIM3_ CH1 [AFR1]

Default alternate function

Timer 2 -

channel 3

Analog input 12

PPODSpeedHigh

Main function (after reset)

1.8 V regulator capacitorSVCAP56

Digital power supplySV

I/O power supplySV

Port A3XXO1XXXI/OPA3/ TIM2

Port A4XXO3HSXXXI/OPA4-10

Port A5XXO3HSXXXI/OPA5-11

Port A6XXO3HSXXXI/OPA6-12

Port F4XXO1XXI/OPF4/

Analog power supplySV

Analog groundSV

OutputInputTypePin namePin number

Ext.

wpufloatingLQFP32LQFP48

interrupt

-9

913

1014

DDIO_1

_CH3 [TIM3 _CH1]

AIN12

DDA

SSA

(1)

sink

Analog input 7Port B7XXO1XXXI/OPB7/ AIN7-15

Analog input 6Port B6XXO1XXXI/OPB6/ AIN6-16

1117

1218

1319

1420

1521

1622

[I2C_ SDA]

[I2C_ SCL]

[TIM1_ ETR]

[TIM1_ CH3N]

[TIM1_ CH2N]

[TIM1_ CH1N]

Analog input 5Port B5XXO1XXXI/OPB5/ AIN5

Analog input 4Port B4XXO1XXXI/OPB4/ AIN4

Analog input 3Port B3XXO1XXXI/OPB3/ AIN3

Analog input 2Port B2XXO1XXXI/OPB2/ AIN2

Analog input 1Port B1XXO1XXXI/OPB1/ AIN1

Analog input 0Port B0XXO1XXXI/OPB0/ AIN0

Analog input 8Port E7XXO1XXXI/OPE7/ AIN8-23

I2C_SDA [AFR6]

I2C_SCL [AFR6]

TIM1_ ETR [AFR5]

TIM1_ CH3N [AFR5]

TIM1_ CH2N [AFR5]

TIM1_ CH1N [AFR5]

Analog input 9Port E6XXO1XXXI/OPE6/ AIN9-24

DocID022186 Rev 322/103

Pinout and pin descriptionSTM8S005K6 STM8S005C6

Default alternate function

SPI master/slave select

Timer 1 -Port C1XXO3HSXXXI/OPC1/

channel 1/ UART2 synchronous clock

Timer 1-Port C2XXO3HSXXXI/OPC2/

channel 2

Timer 1 -Port C3XXO3HSXXXI/OPC3/

channel 3

Timer 1 -Port C4XXO3HSXXXI/OPC4/

channel 4

SPI clockPort C5XXO3HSXXXI/OPC5/ SPI_

PPODSpeedHigh

Main function (after reset)

Port E5XXO1XXXI/OPE5/SPI_

I/O groundSV

I/O power supplySV

OutputInputTypePin namePin number

Ext.

wpufloatingLQFP32LQFP48

interrupt

1725

1826

1927

2028

2129

2230

-31

-32

NSS

TIM1_ CH1/ UART2_CK

TIM1_ CH2

TIM1_ CH3

TIM1_ CH4

SCK

SSIO_2

DDIO_2

sink

Alternate function after remap [option bit]

2333

2434

-37

-38

-39

-40

2541

MOSI

MISO

TIM1_ BKIN

SDA

SCL

CLK_ CCO

TIM3_ CH2 [TIM1_ BKIN] [CLK_ CCO]

(3)

O1XXI/OPE2/ I2C_

(3)

O1XXI/OPE1/ I2C_

Port C6XXO3HSXXXI/OPC6/ SPI_

Port C7XXO3HSXXXI/OPC7/ SPI_

Port G0XXO1XXI/OPG0-35

Port G1XXO1XXI/OPG1-36

Port E0XXO3HSXXXI/OPE0/

Port D0XXO3HSXXXI/OPD0/

SPI master out/slave in

SPI master in/ slave out

Timer 1 - break inputPort E3XXO1XXXI/OPE3/

I2C dataPort E2

I2C clockPort E1

Configurable clock output

Timer 3 -

channel 2

TIM1_ BKIN [AFR3]/ CLK_ CCO [AFR2]

23/103DocID022186 Rev 3

STM8S005K6 STM8S005C6Pinout and pin description

Default alternate function

SWIM data interfacePort D1XXO4HSXXXI/OPD1/

Timer 3 -

channel 1

Timer 2 -

channel 2

Timer 2 -

channel 1

UART2 data transmitPort D5XXO1XXXI/OPD5/

UART2 data receivePort D6XXO1XXXI/OPD6/

PPODSpeedHigh

Main function (after reset)

Port D2XXO3HSXXXI/OPD2/

Port D3XXO3HSXXXI/OPD3/

Port D4XXO3HSXXXI/OPD4/

OutputInputTypePin namePin number

Ext.

wpufloatingLQFP32LQFP48

interrupt

2642

2743

2844

2945

3046

3147

SWIM

TIM3_ CH1 [TIM2_ CH3]

TIM2_ CH2 [ADC_ ETR]

TIM2_ CH1 [BEEP]

UART2_ TX

UART2_ RX

(4)

sink

Alternate function after remap [option bit]

TIM2_CH3 [AFR1]

ADC_ ETR [AFR0]

BEEP output [AFR7]

3248

(1)

A pull-up is applied to PF4 during the reset phase. This pin is input floating after reset release.

(2)

AIN12 is not selectable in ADC scan mode or with analog watchdog.

(3)

In the open-drain output column, ‘T’ defines a true open-drain I/O (P-buffer, weak pull-up, and protection diode to VDDare not implemented).

(4)

The PD1 pin is in input pull-up during the reset phase and after internal reset release.

[TIM1_ CH4]

Top level interruptPort D7XXO1XXXI/OPD7/ TLI

Alternate function remapping5.1.1

As shown in the rightmost column of the pin description table, some alternate functions can be remapped at different I/O ports by programming one of eight AFR (alternate function remap) option bits. When the remapping option is active, the default alternate function is no longer available.

To use an alternate function, the corresponding peripheral must be enabled in the peripheral registers.

Alternate function remapping does not effect GPIO capabilities of the I/O ports (see the GPIO section of the family reference manual, RM0016).

TIM1_ CH4 [AFR4]

DocID022186 Rev 324/103

0x00 FFFF

Flash program memory

(32 Kbytes)

0x00 8000

Reserved

0x01 0000

0x02 7FFF

0x00 0000

RAM

0x00 07FF

(2 Kbytes)

0x00 4000

0x00 407F

128-byte data EEPROM

Reserved

0x00 4080

0x00 47FF

32 interrupt vectors

0x00 807F

GPIO and periph. reg.

0x00 5000

0x00 57FF

0x00 5800

0x00 7FFF

0x00 4900

0x00 4FFF

2 Kbytes boot ROM

0x00 6000

0x00 67FF

0x00 6800

0x00 7EFF

CPU/SWIM/debug/ITC

registers

0x00 7F00

0x00 5FFF

Reserved

Option bytes

0x00 4800

0x00 487F

512 bytes stack

Memory and register mapSTM8S005K6 STM8S005C6

Memory and register map6

Memory map6.1

Figure 5: Memory map

The following table lists the boundary addresses for each memory size. The top of the stack is at the RAM end address in each case.

25/103DocID022186 Rev 3

STM8S005K6 STM8S005C6Memory and register map

Table 6: Flash, Data EEPROM and RAM boundary addresses

End addressStart addressSize (bytes)Memory area

0x00 FFFF0x00 800032KFlash program memory

0x00 07FF0x00 00002KRAM

0x00 407F0x00 4000128Data EEPROM

Register map6.2

I/O port hardware register map6.2.1

Table 7: I/O port hardware register map

Port A input pin value registerPA_IDR0x00 5001

Port B input pin value registerPB_IDR0x00 5006

Reset status

0x00Port A data output latch registerPA_ODRPort A0x00 5000

0xXX

0x00Port A data direction registerPA_DDR0x00 5002

0x00Port A control register 1PA_CR10x00 5003

0x00Port A control register 2PA_CR20x00 5004

0x00Port B data output latch registerPB_ODRPort B0x00 5005

0xXX

0x00Port B data direction registerPB_DDR0x00 5007

0x00Port B control register 1PB_CR10x00 5008

(1)

0x00Port B control register 2PB_CR20x00 5009

0x00Port C data output latch registerPC_ODRPort C0x00 500A

DocID022186 Rev 326/103

Memory and register mapSTM8S005K6 STM8S005C6

Reset status

(1)

Port C input pin value registerPC_IDR0x00 500B

0xXX

0x00Port C data direction registerPC_DDR0x00 500C

0x00Port C control register 1PC_CR10x00 500D

0x00Port C control register 2PC_CR20x00 500E

0x00Port D data output latch registerPD_ODRPort D0x00 500F

(1)

Port D input pin value registerPD_IDR0x00 5010

0xXX

0x00Port D data direction registerPD_DDR0x00 5011

0x02Port D control register 1PD_CR10x00 5012

0x00Port D control register 2PD_CR20x00 5013

0x00Port E data output latch registerPE_ODRPort E0x00 5014

(1)

Port E input pin value registerPE_IDR0x00 5015

0xXX

0x00Port E data direction registerPE_DDR0x00 5016

0x00Port E control register 1PE_CR10x00 5017

0x00Port E control register 2PE_CR20x00 5018

0x00Port F data output latch registerPF_ODRPort F0x00 5019

(1)

Port F input pin value registerPF_IDR0x00 501A

0xXX

0x00Port F data direction registerPF_DDR0x00 501B

0x00Port F control register 1PF_CR10x00 501C

0x00Port F control register 2PF_CR20x00 501D

27/103DocID022186 Rev 3

STM8S005K6 STM8S005C6Memory and register map

Reset status

0x00Port G data output latch registerPG_ODRPort G0x00 501E

(1)

Port G input pin value registerPG_IDR0x00 501F

0xXX

0x00Port G data direction registerPG_DDR0x00 5020

0x00Port G control register 1PG_CR10x00 5021

0x00Port G control register 2PG_CR20x00 5022

0x00Port H data output latch registerPH_ODRPort H0x00 5023

(1)

Port H input pin value registerPH_IDR0x00 5024

0xXX

0x00Port H data direction registerPH_DDR0x00 5025

0x00Port H control register 1PH_CR10x00 5026

(1)

Depends on the external circuitry.

0x00Port H control register 2PH_CR20x00 5027

0x00Port I data output latch registerPI_ODRPort I0x00 5028

(1)

Port I input pin value registerPI_IDR0x00 5029

0xXX

0x00Port I data direction registerPI_DDR0x00 502A

0x00Port I control register 1PI_CR10x00 502B

0x00Port I control register 2PI_CR20x00 502C

DocID022186 Rev 328/103

0x00 5059

Memory and register mapSTM8S005K6 STM8S005C6

General hardware register map6.2.2

Table 8: General hardware register map

Reset statusRegister nameRegister labelBlockAddress

Reserved area (10 bytes)0x00 5050 to

0x00 5061

Flash0x00 505A

FLASH_NCR20x00 505C

FLASH _IAPSR0x00 505F

Reserved area (2 bytes)0x00 5060 to

FLASH _PUKRFlash0x00 5062

0x00Flash control register 1FLASH_CR1

0x00Flash control register 2FLASH_CR20x00 505B

0xFFFlash complementary control

0x00Flash protection registerFLASH _FPR0x00 505D

0xFFFlash complementary protection registerFLASH _NFPR0x00 505E

0x00Flash in-application programming status

0x00Flash program memory unprotection

0x00 509F

0x00 50B2

Reserved area (1 byte)0x00 5063

0x00Data EEPROM unprotection registerFLASH _DUKRFlash0x00 5064

Reserved area (59 bytes)0x00 5065 to

0x00External interrupt control register 1EXTI_CR1ITC0x00 50A0

0x00External interrupt control register 2EXTI_CR20x00 50A1

Reserved area (17 bytes)0x00 50A2 to

29/103DocID022186 Rev 3

0x00 50BF

STM8S005K6 STM8S005C6Memory and register map

Reset statusRegister nameRegister labelBlockAddress

(1)

Reset status registerRST_SRRST0x00 50B3

0xXX

Reserved area (12 bytes)0x00 50B4 to

0x01Internal clock control registerCLK_ICKRCLK0x00 50C0

0x00External clock control registerCLK_ECKR0x00 50C1

Reserved area (1 byte)0x00 50C2

0xE1Clock master status registerCLK_CMSRCLK0x00 50C3

0xE1Clock master switch registerCLK_SWR0x00 50C4

0x00 50D0

0xXXClock switch control registerCLK_SWCR0x00 50C5

0x18Clock divider registerCLK_CKDIVR0x00 50C6

0xFFPeripheral clock gating register 1CLK_PCKENR10x00 50C7

0x00Clock security system registerCLK_CSSR0x00 50C8

0x00Configurable clock control registerCLK_CCOR0x00 50C9

0xFFPeripheral clock gating register 2CLK_PCKENR20x00 50CA

0x00HSI clock calibration trimming registerCLK_HSITRIMR0x00 50CC

SWIM clock control registerCLK_SWIMCCR0x00 50CD

0bXXXX XXX0

Reserved area (3 bytes)0x00 50CE to

0x7FWWDG control registerWWDG_CRWWDG0x00 50D1

0x7FWWDR window registerWWDG_WR0x00 50D2

DocID022186 Rev 330/103

0x00 50DF

0x00 50EF

Memory and register mapSTM8S005K6 STM8S005C6

Reset statusRegister nameRegister labelBlockAddress

Reserved area (13 bytes)0x00 50D3 to

(2)

IWDG key registerIWDG_KRIWDG0x00 50E0

0xXX

0x00IWDG prescaler registerIWDG_PR0x00 50E1

0xFFIWDG reload registerIWDG_RLR0x00 50E2

Reserved area (13 bytes)0x00 50E3 to

0x00AWU control/ status register 1AWU_CSR1AWU0x00 50F0

0x00 50FF

AWU_APR0x00 50F1

0x3FAWU asynchronous prescaler buffer

0x00AWU timebase selection registerAWU_TBR0x00 50F2

0x1FBEEP control/ status registerBEEP_CSRBEEP0x00 50F3

Reserved area (12 bytes)0x00 50F4 to

0x00SPI control register 1SPI_CR1SPI0x00 5200

0x00SPI control register 2SPI_CR20x00 5201

0x00SPI interrupt control registerSPI_ICR0x00 5202

0x02SPI status registerSPI_SR0x00 5203

0x00SPI data registerSPI_DR0x00 5204

0x07SPI CRC polynomial registerSPI_CRCPR0x00 5205

0xFFSPI Rx CRC registerSPI_RXCRCR0x00 5206

0xFFSPI Tx CRC registerSPI_TXCRCR0x00 5207

31/103DocID022186 Rev 3

0x00 520F

STM8S005K6 STM8S005C6Memory and register map

Reset statusRegister nameRegister labelBlockAddress

Reserved area (8 bytes)0x00 5208 to

0x00I2C control register 1I2C_CR1I2C0x00 5210

0x00I2C control register 2I2C_CR20x00 5211

0x00I2C frequency registerI2C_FREQR0x00 5212

0x00I2C Own address register lowI2C_OARL0x00 5213

0x00I2C own address register highI2C_OARH0x00 5214

Reserved0x00 5215

0x00 522F

0x00I2C data registerI2C_DR0x00 5216

0x00I2C status register 1I2C_SR10x00 5217

0x00I2C status register 2I2C_SR20x00 5218

0x00I2C status register 3I2C_SR30x00 5219

0x00I2C interrupt control registerI2C_ITR0x00 521A

0x00I2C clock control register lowI2C_CCRL0x00 521B

0x00I2C clock control register highI2C_CCRH0x00 521C

0x02I2C TRISE registerI2C_TRISER0x00 521D

0x00I2C packet error checking registerI2C_PECR0x00 521E

Reserved area (17 bytes)0x00 521F to

0x00 523F

Reserved area (6 bytes)0x00 5230 to

DocID022186 Rev 332/103

Memory and register mapSTM8S005K6 STM8S005C6

Reset statusRegister nameRegister labelBlockAddress

0xC0UART2 status registerUART2_SRUART20x00 5240

0xXXUART2 data registerUART2_DR0x00 5241

0x00UART2 baud rate register 1UART2_BRR10x00 5242

0x00UART2 baud rate register 2UART2_BRR20x00 5243

0x00UART2 control register 1UART2_CR10x00 5244

0x00UART2 control register 2UART2_CR20x00 5245

0x00UART2 control register 3UART2_CR30x00 5246

0x00UART2 control register 4UART2_CR40x00 5247

0x00 524F

0x00UART2 control register 5UART2_CR50x00 5248

0x00UART2 control register 6UART2_CR60x00 5249

0x00UART2 guard time registerUART2_GTR0x00 524A

0x00UART2 prescaler registerUART2_PSCR0x00 524B

Reserved area (4 bytes)0x00 524C to

0x00TIM1 control register 1TIM1_CR1TIM10x00 5250

0x00TIM1 control register 2TIM1_CR20x00 5251

0x00TIM1 slave mode control registerTIM1_SMCR0x00 5252

0x00TIM1 external trigger registerTIM1_ETR0x00 5253

0x00TIM1 interrupt enable registerTIM1_IER0x00 5254

0x00TIM1 status register 1TIM1_SR10x00 5255

33/103DocID022186 Rev 3

STM8S005K6 STM8S005C6Memory and register map

Reset statusRegister nameRegister labelBlockAddress

0x00TIM1 status register 2TIM1_SR20x00 5256

0x00TIM1 event generation registerTIM1_EGR0x00 5257

TIM1_CCMR10x00 5258

0x00TIM1 capture/ compare mode

TIM1_CCMR20x00 5259

0x00TIM1 capture/compare mode

TIM1_CCMR30x00 525A

0x00TIM1 capture/ compare mode

TIM1_CCMR40x00 525B

0x00TIM1 capture/compare mode

TIM1_CCER10x00 525C

0x00TIM1 capture/ compare enable

TIM1_CCER20x00 525D

0x00TIM1 capture/compare enable

0x00TIM1 counter highTIM1_CNTRH0x00 525E

0x00TIM1 counter lowTIM1_CNTRL0x00 525F

0x00TIM1 prescaler register highTIM1_PSCRH0x00 5260

0x00TIM1 prescaler register lowTIM1_PSCRL0x00 5261

0xFFTIM1 auto-reload register highTIM1_ARRH0x00 5262

0xFFTIM1 auto-reload register lowTIM1_ARRL0x00 5263

0x00TIM1 repetition counter registerTIM1_RCR0x00 5264

0x00TIM1 capture/ compare register 1 highTIM1_CCR1H0x00 5265

DocID022186 Rev 334/103

Memory and register mapSTM8S005K6 STM8S005C6

Reset statusRegister nameRegister labelBlockAddress

0x00TIM1 capture/ compare register 1 lowTIM1_CCR1L0x00 5266

0x00TIM1 capture/ compare register 2 highTIM1_CCR2H0x00 5267

0x00TIM1 capture/ compare register 2 lowTIM1_CCR2L0x00 5268

0x00TIM1 capture/ compare register 3 highTIM1_CCR3H0x00 5269

0x00TIM1 capture/ compare register 3 lowTIM1_CCR3L0x00 526A

0x00TIM1 capture/ compare register 4 highTIM1_CCR4H0x00 526B

0x00TIM1 capture/ compare register 4 lowTIM1_CCR4L0x00 526C

0x00TIM1 break registerTIM1_BKR0x00 526D

0x00 52FF

0x00TIM1 dead-time registerTIM1_DTR0x00 526E

0x00TIM1 output idle state registerTIM1_OISR0x00 526F

Reserved area (147 bytes)0x00 5270 to

0x00TIM2 control register 1TIM2_CR1TIM20x00 5300

0x00TIM2 interrupt enable registerTIM2_IER0x00 5301

0x00TIM2 status register 1TIM2_SR10x00 5302

0x00TIM2 status register 2TIM2_SR20x00 5303

0x00TIM2 event generation registerTIM2_EGR0x00 5304

TIM2_CCMR10x00 5305

0x00TIM2 capture/ compare mode

TIM2_CCMR20x00 5306

0x00TIM2 capture/ compare mode

35/103DocID022186 Rev 3

STM8S005K6 STM8S005C6Memory and register map

Reset statusRegister nameRegister labelBlockAddress

TIM2_CCMR30x00 5307

0x00TIM2 capture/ compare mode

TIM2_CCER10x00 5308

0x00TIM2 capture/ compare enable register

TIM2_CCER20x00 5309

0x00TIM2 capture/ compare enable register

0x00TIM2 counter highTIM2_CNTRH0x00 530A

0x00TIM2 counter lowTIM2_CNTRL0x00 530B

0x00TIM2 prescaler registerTIM2_PSCR0x00 530C

0xFFTIM2 auto-reload register highTIM2_ARRH0x00 530D

0xFFTIM2 auto-reload register lowTIM2_ARRL0x00 530E

0x00TIM2 capture/ compare register 1 highTIM2_CCR1H0x00 530F

0x00 531F

0x00TIM2 capture/ compare register 1 lowTIM2_CCR1L0x00 5310

0x00TIM2 capture/ compare reg. 2 highTIM2_CCR2H0x00 5311

0x00TIM2 capture/ compare register 2 lowTIM2_CCR2L0x00 5312

0x00TIM2 capture/ compare register 3 highTIM2_CCR3H0x00 5313

0x00TIM2 capture/ compare register 3 lowTIM2_CCR3L0x00 5314

Reserved area (11 bytes)0x00 5315 to

0x00TIM3 control register 1TIM3_CR1TIM30x00 5320

0x00TIM3 interrupt enable registerTIM3_IER0x00 5321

0x00TIM3 status register 1TIM3_SR10x00 5322

DocID022186 Rev 336/103

Memory and register mapSTM8S005K6 STM8S005C6

Reset statusRegister nameRegister labelBlockAddress

0x00TIM3 status register 2TIM3_SR20x00 5323

0x00TIM3 event generation registerTIM3_EGR0x00 5324

TIM3_CCMR10x00 5325

0x00TIM3 capture/ compare mode

TIM3_CCMR20x00 5326

0x00TIM3 capture/ compare mode

TIM3_CCER10x00 5327

0x00TIM3 capture/ compare enable register

0x00TIM3 counter highTIM3_CNTRH0x00 5328

0x00TIM3 counter lowTIM3_CNTRL0x00 5329

0x00TIM3 prescaler registerTIM3_PSCR0x00 532A

0xFFTIM3 auto-reload register highTIM3_ARRH0x00 532B

0xFFTIM3 auto-reload register lowTIM3_ARRL0x00 532C

0x00TIM3 capture/ compare register 1 highTIM3_CCR1H0x00 532D

0x00 533F

0x00TIM3 capture/ compare register 1 lowTIM3_CCR1L0x00 532E

0x00TIM3 capture/ compare register 2 highTIM3_CCR2H0x00 532F

0x00TIM3 capture/ compare register 2 lowTIM3_CCR2L0x00 5330

Reserved area (15 bytes)0x00 5331 to

0x00TIM4 control register 1TIM4_CR1TIM40x00 5340

0x00TIM4 interrupt enable registerTIM4_IER0x00 5341

0x00TIM4 status registerTIM4_SR0x00 5342

37/103DocID022186 Rev 3

0x00 53DF

0x00 53F3

0x00 53FF

STM8S005K6 STM8S005C6Memory and register map

Reset statusRegister nameRegister labelBlockAddress

0x00TIM4 event generation registerTIM4_EGR0x00 5343

0x00TIM4 counterTIM4_CNTR0x00 5344

0x00TIM4 prescaler registerTIM4_PSCR0x00 5345

0xFFTIM4 auto-reload registerTIM4_ARR0x00 5346

Reserved area (153 bytes)0x00 5347 to

0x00ADC data buffer registersADC _DBxRADC10x00 53E0 to

Reserved area (12 bytes)0x00 53F4 to

0x00ADC control/ status registerADC _CSRADC10x00 5400

0x00ADC configuration register 1ADC_CR10x00 5401

0x00ADC configuration register 2ADC_CR20x00 5402

0x00ADC configuration register 3ADC_CR30x00 5403

0xXXADC data register highADC_DRH0x00 5404

0xXXADC data register lowADC_DRL0x00 5405

ADC_TDRH0x00 5406

0x00ADC Schmitt trigger disable

ADC_TDRL0x00 5407

0x00ADC Schmitt trigger disable

0x03ADC high threshold register highADC_HTRH0x00 5408

0xFFADC high threshold register lowADC_HTRL0x00 5409

DocID022186 Rev 338/103

Memory and register mapSTM8S005K6 STM8S005C6

Reset statusRegister nameRegister labelBlockAddress

0x00ADC low threshold register highADC_LTRH0x00 540A

0x00ADC low threshold register lowADC_LTRL0x00 540B

ADC_AWSRH0x00 540C

ADC_AWSRL0x00 540D

ADC _AWCRH0x00 540E

ADC_AWCRL0x00 540F

Reserved area (1008 bytes)0x00 5410 to

0x00 57FF

(1)

Depends on the previous reset source.

(2)

Write only register.

0x00ADC analog watchdog status

0x00ADC analog watchdog control

CPU/SWIM/debug module/interrupt controller registers6.2.3

0x00 7F00

Table 9: CPU/SWIM/debug module/interrupt controller registers

(1)

Reset status

0x00AccumulatorACPU

0x00Program counter extendedPCE0x00 7F01

0x00Program counter highPCH0x00 7F02

0x00Program counter lowPCL0x00 7F03

0x00X index register highXH0x00 7F04

39/103DocID022186 Rev 3

STM8S005K6 STM8S005C6Memory and register map

0x00 7F5F

Reset status

0x00X index register lowXL0x00 7F05

0x00Y index register highYH0x00 7F06

0x00Y index register lowYL0x00 7F07

0x07Stack pointer highSPH0x00 7F08

0xFFStack pointer lowSPL0x00 7F09

0x28Condition code registerCCR0x00 7F0A

Reserved area (85 bytes)0x00 7F0B to

0x00Global configuration registerCFG_GCRCPU0x00 7F60

0x00 7F79

0xFFInterrupt software priority register 1ITC_SPR1ITC0x00 7F70

0xFFInterrupt software priority register 2ITC_SPR20x00 7F71

0xFFInterrupt software priority register 3ITC_SPR30x00 7F72

0xFFInterrupt software priority register 4ITC_SPR40x00 7F73

0xFFInterrupt software priority register 5ITC_SPR50x00 7F74

0xFFInterrupt software priority register 6ITC_SPR60x00 7F75

0xFFInterrupt software priority register 7ITC_SPR70x00 7F76

0xFFInterrupt software priority register 8ITC_SPR80x00 7F77

Reserved area (2 bytes)0x00 7F78 to

0x00SWIM control status registerSWIM_CSRSWIM0x00 7F80

DocID022186 Rev 340/103

Memory and register mapSTM8S005K6 STM8S005C6

0x00 7F8F

Reset status

Reserved area (15 bytes)0x00 7F81 to

DM_BK1REDM0x00 7F90

0xFFDM breakpoint 1 register extended

byte

0xFFDM breakpoint 1 register high byteDM_BK1RH0x00 7F91

0xFFDM breakpoint 1 register low byteDM_BK1RL0x00 7F92

DM_BK2RE0x00 7F93

0xFFDM breakpoint 2 register extended

byte

0xFFDM breakpoint 2 register high byteDM_BK2RH0x00 7F94

0xFFDM breakpoint 2 register low byteDM_BK2RL0x00 7F95

0x00DM debug module control register 1DM_CR10x00 7F96

DM_CSR10x00 7F98

DM_CSR20x00 7F99

Reserved area (5 bytes)0x00 7F9B to

0x00 7F9F

(1)

Accessible by debug module only

0x00DM debug module control register 2DM_CR20x00 7F97

0x10DM debug module control/status

0x00DM debug module control/status

0xFFDM enable function registerDM_ENFCTR0x00 7F9A

41/103DocID022186 Rev 3

STM8S005K6 STM8S005C6Interrupt vector mapping

Interrupt vector mapping7

Table 10: Interrupt mapping

IRQ no.

block

DescriptionSource

Port A external interruptsEXTI03

Wakeup from halt mode

(1)

Yes

Wakeup from active-halt mode

(1)

Vector address

0x00 8000YesYesResetRESET

0x00 8004--Software interruptTRAP

0x00 8008--External top level interruptTLI0

0x00 800CYes-Auto wake up from haltAWU1

0x00 8010--Clock controllerCLK2

0x00 8014Yes

0x00 8018YesYesPort B external interruptsEXTI14

0x00 801CYesYesPort C external interruptsEXTI25

0x00 8020YesYesPort D external interruptsEXTI36

0x00 8024YesYesPort E external interruptsEXTI47

0x00 80288

0x00 802C--Reserved9

0x00 8030YesYesEnd of transferSPI10

TIM111

underflow/ trigger/ break

0x00 8034--TIM1 update/ overflow/

0x00 8038--TIM1 capture/ compareTIM112

0x00 803C--TIM update/ overflowTIM13

0x00 8040--TIM capture/ compareTIM14

DocID022186 Rev 342/103

Interrupt vector mappingSTM8S005K6 STM8S005C6

IRQ no.

block

UART221

ADC122

DescriptionSource

FULL

analog watchdog interrupt

Wakeup from halt mode

Wakeup from active-halt mode

Vector address

0x00 8044--Update/ overflowTIM315

0x00 8048--Capture/ compareTIM316

0x00 804C--Reserved17

0x00 8050--Reserved18

0x00 8054YesYesI2C interruptI2C19

0x00 8058--Tx completeUART220

0x00 805C--Receive register DATA

0x00 8060--ADC1 end of conversion/

Reserved

(1)

Except PA1

0x00 8064--TIM update/ overflowTIM23

0x00 8068--EOP/ WR_PG_DISFlash24

0x00 806C to 0x00 807C

43/103DocID022186 Rev 3

STM8S005K6 STM8S005C6Option bytes

Option bytes8

Option bytes contain configurations for device hardware features as well as the memory protection of the device. They are stored in a dedicated block of the memory. Except for the ROP (read-out protection) byte, each option byte has to be stored twice, in a regular form (OPTx) and a complemented one (NOPTx) for redundancy.

Option bytes can be modified in ICP mode (via SWIM) by accessing the EEPROM address shown in the table below.

Option bytes can also be modified ‘on the fly’ by the application in IAP mode, except the ROP option that can only be modified in ICP mode (via SWIM).

Refer to the STM8S Flash programming manual (PM0051) and STM8 SWIM communication protocol and debug module user manual (UM0470) for information on SWIM programming procedures.

Table 11: Option bytes

Addr.

0x4800

0x4801

0x4803

0x4805h

0x4807

Option name

protection (ROP)

code(UBC)

function remapping (AFR)

option

byte no.

Option bitsOption

01234567

AFR6AFR7OPT2Alternate

ReservedOPT3Miscell.

ReservedNOPT30x4806

TRIM

NHSI TRIM

LSI_ ENHSI

NLSI_ EN

EXT CLKReservedOPT4Clock

IWDG _HW

NIWDG _HW

SEL

WWDG _HW

NWWDG _HW

_HALT

G_HALT

Factory default setting

00hROP [7:0]OPT0Read-out

00hUBC [7:0]OPT1User boot

FFhNUBC [7:0]NOPT10x4802

00hAFR0AFR1AFR2AFR3AFR4AFR5

FFhNAFR0NAFR1NAFR2NAFR3NAFR4NAFR5NAFR6NAFR7NOPT20x4804

00hWWDG

FFhNWW

00hPRS C0PRS C1CKAWU

0x4809

startup

Reserved0x480B

OPT6

ReservedNOPT40x4808

NEXT CLK

WUSEL

NPRSC1NCKA

SC0

FFhNPR

00hHSECNT [7:0]OPT5HSE clock

FFhNHSECNT [7:0]NOPT50x480A

00hReserved

DocID022186 Rev 344/103

Option bytesSTM8S005K6 STM8S005C6

Addr.

0x480C

0x480E

0x487F

Option name

Reserved0x480D

Bootloader0x487E

byte no.

NOPT6

OPT7

NOPT7

OPTBL

NOPTBL

Option bitsOption

01234567

Factory default setting

FFhReserved

00hReserved

FFhReserved

00hBL[7:0]

FFhNBL[7:0]

Table 12: Option byte description

DescriptionOption byte no.

ROP[7:0] Memory readout protection (ROP)OPT0

AAh: Enable readout protection (write access via SWIM protocol)

Note: Refer to the family reference manual (RM0016) section on Flash/EEPROM memory readout protection for details.

UBC[7:0] User boot code areaOPT1

0x00: no UBC, no write-protection

0x01: Page 0 to 1 defined as UBC, memory write-protected

0x02: Page 0 to 3 defined as UBC, memory write-protected

0x03: Page 0 to 4 defined as UBC, memory write-protected

...

0x3E: Pages 0 to 63 defined as UBC, memory write-protected

Other values: Reserved

Note: Refer to the family reference manual (RM0016) section on Flash write protection for more details.

AFR[7:0]OPT2

Refer to following table for the alternate function remapping decriptions of bits [7:2].

HSITRIM:High speed internal clock trimming register sizeOPT3

0: 3-bit trimming supported in CLK_HSITRIMR register

1: 4-bit trimming supported in CLK_HSITRIMR register

45/103DocID022186 Rev 3

STM8S005K6 STM8S005C6Option bytes

DescriptionOption byte no.

LSI_EN:Low speed internal clock enable

0: LSI clock is not available as CPU clock source

1: LSI clock is available as CPU clock source

IWDG_HW: Independent watchdog

0: IWDG Independent watchdog activated by software

1: IWDG Independent watchdog activated by hardware

WWDG_HW: Window watchdog activation

0: WWDG window watchdog activated by software

1: WWDG window watchdog activated by hardware

WWDG_HALT: Window watchdog reset on halt

0: No reset generated on halt if WWDG active

1: Reset generated on halt if WWDG active

EXTCLK: External clock selectionOPT4

0: External crystal connected to OSCIN/OSCOUT

1: External clock signal on OSCIN

CKAWUSEL:Auto wake-up unit/clock

0: LSI clock source selected for AWU

1: HSE clock with prescaler selected as clock source for for AWU

PRSC[1:0] AWU clock prescaler

0x: 16 MHz to 128 kHz prescaler

10: 8 MHz to 128 kHz prescaler

11: 4 MHz to 128 kHz prescaler

HSECNT[7:0]:HSE crystal oscillator stabilization timeOPT5

0x00: 2048 HSE cycles

0xB4: 128 HSE cycles

0xD2: 8 HSE cycles

0xE1: 0.5 HSE cycles

DocID022186 Rev 346/103

Option bytesSTM8S005K6 STM8S005C6

DescriptionOption byte no.

ReservedOPT6

ReservedOPT7

BL[7:0] Bootloader option byteOPTBL

For STM8S products, this option is checked by the boot ROM code after reset. Depending on the content of addresses 0x487E, 0x487F, and 0x8000 (reset vector), the CPU jumps to the bootloader or to the reset vector. Refer to the UM0560 (STM8L/S bootloader manual) for more details.

For STM8L products, the bootloader option bytes are on addresses 0xXXXX and 0xXXXX+1 (2 bytes). These option bytes control whether the bootloader is active or not. For more details, refer to the UM0560 (STM8L/S bootloader manual) for more details.

Table 13: Description of alternate function remapping bits [7:0] of OPT2

Option byte no.

Description

(1)

AFR7 Alternate function remapping option 7OPT2

0: AFR7 remapping option inactive: Default alternate function

(2)

1: Port D4 alternate function = BEEP.

AFR6 Alternate function remapping option 6

0: AFR6 remapping option inactive: Default alternate functions

(2)

1: Port B5 alternate function = I2C_SDA; port B4 alternate function = I2C_SCL.

AFR5 Alternate function remapping option 5

0: AFR5 remapping option inactive: Default alternate functions

(2)

1: Port B3 alternate function = TIM1_ETR; port B2 alternate function = TIM1_NCC3; port B1 alternate function = TIM1_CH2N; port B0 alternate function = TIM1_CH1N.

AFR4 Alternate function remapping option 4

0: AFR4 remapping option inactive: Default alternate function

(2)

1: Port D7 alternate function = TIM1_CH4.

AFR3 Alternate function remapping option 3

0: AFR3 remapping option inactive: Default alternate function

(2)

1: Port D0 alternate function = TIM1_BKIN.

AFR2 Alternate function remapping option 2

47/103DocID022186 Rev 3

STM8S005K6 STM8S005C6Option bytes

Option byte no.

Description

(1)

0: AFR2 remapping option inactive: Default alternate function

1: Port D0 alternate function = CLK_CCO.Note: AFR2 option has priority over AFR3 if both are activated.

AFR1 Alternate function remapping option 1

0: AFR1 remapping option inactive: Default alternate functions

1: Port A3 alternate function = TIM3_CH1; port D2 alternate function TIM2_CH3.

AFR0 Alternate function remapping option 0

0: AFR0 remapping option inactive: Default alternate function

1: Port D3 alternate function = ADC_ETR.

(1)

Do not use more than one remapping option in the same port.

(2)

Refer to pinout description.

(2)

DocID022186 Rev 348/103

5 V or 3.3 V

V V

V V V V

DD DDA

DDIO SS

SSA

SSIO

Electrical characteristicsSTM8S005K6 STM8S005C6

Electrical characteristics9

Parameter conditions9.1

Unless otherwise specified, all voltages are referred to VSS.

Minimum and maximum values9.1.1

Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100 % of the devices with an ambient temperature at TA= 25 °C and TA= T the selected temperature range).

Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean ± 3 Σ).

Typical values9.1.2

Unless otherwise specified, typical data are based on TA= 25 °C, VDD= 5 V. They are given only as design guidelines and are not tested.

Amax

(given by

Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean ± 2 Σ).

Typical curves9.1.3

Unless otherwise specified, all typical curves are given only as design guidelines and are not tested.

Typical current consumption9.1.4

For typical current consumption measurements, VDD, V in the configuration shown in the following figure.

Figure 6: Supply current measurement conditions

DDIO

and V

are connected together

DDA

49/103DocID022186 Rev 3

STM8 PIN

50 pF

STM8 PIN

STM8S005K6 STM8S005C6Electrical characteristics

Loading capacitor9.1.5

The loading conditions used for pin parameter measurement are shown in the following figure.

Figure 7: Pin loading conditions

Pin input voltage9.1.6

The input voltage measurement on a pin of the device is described in the following figure.

Figure 8: Pin input voltage

Absolute maximum ratings9.2

Stresses above those listed as ‘absolute maximum ratings’ may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

Table 14: Voltage characteristics

UnitMaxMinRatingsSymbol

(1)

- V

DDx

PE2)

(2)

DocID022186 Rev 350/103

DDA andVDDIO

)

6.5VSS- 0.3Input voltage on true open drain pins (PE1,

V6.5-0.3Supply voltage (including V

Electrical characteristicsSTM8S005K6 STM8S005C6

UnitMaxMinRatingsSymbol

DDx

(2)

VDD+ 0.3VSS- 0.3Input voltage on any other pin

mV50Variations between different power pins|V

VDD|

SSx

ESD

- VSS|

Electrostatic discharge voltageV

see Absolute maximum

50Variations between all the different ground pins|V

ratings (electrical sensitivity)

(1)

All power (VDD, V

DDIO

, V

) and ground (VSS, V

DDA

SSIO

, V

) pins must always be

SSA

connected to the external power supply

(2)

INJ(PIN)

must never be exceeded. This is implicitly insured if VINmaximum is respected. If VINmaximum cannot be respected, the injection current must be limited externally to the I

INJ(PIN)

value. A positive injection is induced by VIN>VDDwhile a negative injection is induced by VIN<VSS. For true open-drain pads, there is no positive injection current, and the corresponding VINmaximum must always be respected

Table 15: Current characteristics

(1)

RatingsSymbol

UnitMax.

VDD

VSS

ΣI

(2)

60Total current out of VSSground lines (sink)

mA60Total current into VDDpower lines (source)

20Output current sunk by any I/O and control pinI

20Output current source by any I/Os and control pin

pins) for devices with two V

pins) for devices with one V

pins) for devices with two V

pins) for devices with one V

DDIO

SSIO

pins

(3)

200Total output current sourced (sum of all I/O and control

100Total output current sourced (sum of all I/O and control

160Total output current sunk (sum of all I/O and control

80Total output current sunk (sum of all I/O and control

51/103DocID022186 Rev 3

STM8S005K6 STM8S005C6Electrical characteristics

(1)

RatingsSymbol

UnitMax.

INJ(PIN)

(4) (5)

±4Injected current on NRST pinI

±4Injected current on OSCIN pin

(6)

ΣI

INJ(PIN)

(1)

(2)

(4)

Data based on characterization results, not tested in production.

All power (VDD, V

DDIO

, V

) and ground (VSS, V

DDA

SSIO

, V

SSA

) pins must always be

(6)

±4Injected current on any other pin

±20Total injected current (sum of all I/O and control pins)

connected to the external supply.

(3)

I/O pins used simultaneously for high current source/sink must be uniformly spaced

around the package between the V

(4)

INJ(PIN)

must never be exceeded. This is implicitly insured if VINmaximum is respected.

DDIO/VSSIO

pins.

If VINmaximum cannot be respected, the injection current must be limited externally to the I

INJ(PIN)

(5)

Negative injection disturbs the analog performance of the device. See note in I2C interface

characteristics.

(6)

When several inputs are submitted to a current injection, the maximum ΣI

INJ(PIN)

is the absolute sum of the positive and negative injected currents (instantaneous values). These results are based on characterization with ΣI

INJ(PIN)

maximum current injection on four I/O

port pins of the device.

Table 16: Thermal characteristics

UnitValueRatingsSymbol

STG

150Maximum junction temperatureT

°C-65 to 150Storage temperature rangeT

Operating conditions9.3

The device must be used in operating conditions that respect the parameters in the table below. In addition, full account must be taken of all physical capacitor characteristics and tolerances.

DocID022186 Rev 352/103

Table 17: General operating conditions

Electrical characteristicsSTM8S005K6 STM8S005C6

UnitMaxMinConditionsParameterSymbol

CPU

VDD/ V

VCAP

(2)

DD_IO

(1)

frequency

voltage

: capacitance of

EXT

external capacitor

ESR of external capacitor

capacitor

Power dissipation at TA = 85 °C for suffix 6

(4)

output on eight standard ports, two high sink ports and two open drain ports simultaneously

(3)

output on eight standard ports and two high sink ports simultaneously

(3)

MHz160Internal CPU clock

V5.52.95Standard operating

nF3300470C

Ohm0.3at 1 MHz

nH15ESL of external

mW44348-pin devices, with

36032-pin package, with

Ambient temperature for 6 suffix version

dissipation

105-406 suffix versionJunction temperature

°C85-40Maximum power

range

(1)

Care should be taken when selecting the capacitor, due to its tolerance, as well as the parameter dependency on temperature, DC bias and frequency in addition to other factors. The parameter maximum value must be respected for the full application range.

(2)

To calculate P

Dmax(TA

characteristics ) with the value for T

), use the formula P

given in the current table and the value for Θ

Jmax

Dmax

= (T

- TA)/ΘJA(see Thermal

Jmax

given in Thermal characteristics.

(3)

Refer to Thermal characteristics.

(4)

This frequency of 1 MHz as a condition for V

parameters is given by design of the

CAP

internal regulator.

53/103DocID022186 Rev 3

8 4

2.95

4.0

5.0

5.5

CPU

(MHz)

Functionality guaranteed

@TA-40 to 85 °C

Supply voltage

Functionality not guaranteed in this area

STM8S005K6 STM8S005C6Electrical characteristics

VDD

Figure 9: f

CPUmax

versus V

Table 18: Operating conditions at power-up/power-down

VDDrise time ratet

VDDfall time rate

(1)

UnitMaxTypMinConditionsParameterSymbol

µs/V∞2.0

∞2.0

TEMP

IT+

VDDrisingReset releasedelayt

threshold

IT-

2.882.72.58Brown-out reset

threshold

HYS(BOR)

hysteresis

(1)

Guaranteed by design, not tested in production.

VCAP external capacitor9.3.1

Stabilization for the main regulator is achieved connecting an external capacitor C V

pin. C

CAP

the series inductance to less than 15 nH.

is specified in the Operating conditions section. Care should be taken to limit

EXT

(1)

EXT

ms1.7

V2.952.82.65Power-on reset

mV70Brown-out reset

to the

DocID022186 Rev 354/103

ESR

Leak

ESL

Electrical characteristicsSTM8S005K6 STM8S005C6

Figure 10: External capacitor C

EXT

1. ESR is the equivalent series resistance and ESL is the equivalent inductance.

Supply current characteristics9.3.2

The current consumption is measured as described in Pin input voltage.

Total current consumption in run mode9.3.2.1

Table 19: Total current consumption with code execution in run mode at VDD= 5 V

TypConditionsParameterSymbol

(1)

UnitMax

DD(RUN)

Supply current in run mode, code

= f

CPU

MASTER

= 16 MHz

(16 MHz)

executed from RAM 3.22.6HSE user ext. clock

(16 MHz)

= f

CPU

125 kHz

MASTER

/128 =

(16 MHz)

= f

CPU

MASTER

15.625 kHz

= f

CPU

= 128 kHz

/128 =

(16 MH3z/8)

MASTER

(128 kHz)

mA3.2HSE crystal osc.

3.22.5HSI RC osc.

2.21.6HSE user ext. clock

2.01.3HSI RC osc.

0.75HSI RC osc.

0.55LSI RC osc.

55/103DocID022186 Rev 3

DD(RUN)

STM8S005K6 STM8S005C6Electrical characteristics

Supply current in run mode, code

= f

CPU

MASTER

= 16 MHz

(16 MHz)

executed fromFlash 8.07.0HSE user ext. clock

(16 MHz)

(1)

TypConditionsParameterSymbol

UnitMax

7.7HSE crystal osc.

8.07.0HSI RC osc.

= f

CPU

= 2 MHz

CPU

125 kHz

CPU

15.625 kHz

CPU

= 128 kHz

(1)

Data based on characterization results, not tested in production.

(2)

Default clock configuration measured with all peripherals off.

MASTER

= f

MASTER

= f

MASTER

= f

MASTER

/128 =

(16 MHz/8)

(16 MHz)

(16 MHz/8)

(128 kHz)

(2)

1.5HSI RC osc.

2.01.35HSI RC osc.

0.75HSI RC osc.

0.6LSI RC osc.

Table 20: Total current consumption with code execution in run mode at VDD= 3.3 V

(1)

TypConditionsParameterSymbol

UnitMax

DD(RUN)

current in run mode, code executed from RAM

CPU

= f

MASTER

DocID022186 Rev 356/103

= 16 MHzSupply

mA2.8HSE crystal osc.

(16 MHz)

3.22.6HSE user ext. clock

(16 MHz)

3.22.5HSI RC osc.

(16 MHz)

Electrical characteristicsSTM8S005K6 STM8S005C6

(1)

TypConditionsParameterSymbol

UnitMax

current in run mode, code executed from Flash

= f

CPU

MASTER

= 125 kHz

= f

CPU

MASTER

15.625 kHz

= f

CPU

= f

MASTER

/128

/128 =

= 128 kHz

= 16 MHzSupply

2.21.6HSE user ext. clock

(16 MHz)

2.01.3HSI RC osc.

(16 MHz)

0.75HSI RC osc. (16 MHz/8)f

0.55LSI RC osc.

(128 kHz)

7.3HSE crystal osc.

(16 MHz)

8.07.0HSE user ext. clock

(16 MHz)

8.07.0HSI RC osc.

(16 MHz)

= f

CPU

= f

MASTER

= 125 kHz

= f

CPU

MASTER

15.625 kHz

= f

CPU

MASTER

= 2 MHz

/128

/128 =

= 128 kHz

(16 MHz/8)

(16 MHz)

(16 MHz/8)

(2)

(128 kHz)

(1)

Data based on characterization results, not tested in production.

(2)

Default clock configuration measured with all peripherals off.

1.5HSI RC osc.

2.01.35HSI RC osc.

0.75HSI RC osc.

0.6LSI RC osc.

57/103DocID022186 Rev 3

STM8S005K6 STM8S005C6Electrical characteristics

Total current consumption in wait mode9.3.2.2

Table 21: Total current consumption in wait mode at VDD= 5 V

(1)

TypConditionsParameterSymbol

UnitMax

DD(WFI)

Supply current in wait mode

CPU

MHz

= f

MASTER

= 16

(16 MHz)

= f

CPU

MASTER

= 125 kHz

= f

CPU

MASTER

= 15.625 kHz

= f

CPU

MASTER

kHz

(1)

Data based on characterization results, not tested in production.

(2)

Default clock configuration measured with all peripherals off.

/128

= 128

(16 MHz)

(16 MHz/8)

(128 kHz)

(2)

mA2.15HSE crystal osc.

2.01.55HSE user ext. clock

1.91.5HSI RC osc.

1.3HSI RC osc.

0.7HSI RC osc.

0.5LSI RC osc.

DD(WFI)

Table 22: Total current consumption in wait mode at VDD= 3.3 V

TypConditionsParameterSymbol

Supply current in wait mode

CPU

MHz

= f

MASTER

= 16

(16 MHz)

DocID022186 Rev 358/103

(1)

UnitMax

mA1.75HSE crystal osc.

2.01.55HSE user ext. clock

1.91.5HSI RC osc.

Electrical characteristicsSTM8S005K6 STM8S005C6

(1)

TypConditionsParameterSymbol

UnitMax

= f

CPU

MASTER

= 125 kHz

= f

CPU

MASTER

= 15.625 kHz

= f

CPU

MASTER

128 kHz

(1)

Data based on characterization results, not tested in production.

(2)

Default clock configuration measured with all peripherals off.

/128

(16 MHz)

(16 MHz/8)

(128 kHz)

(2)

Total current consumption in active halt mode9.3.2.3

Table 23: Total current consumption in active halt mode at VDD= 5 V

(3)

Main voltage regulator (MVR)

(2)

Clock sourceFlash mode

1.3HSI RC osc.

0.7HSI RC osc.

0.5LSI RC osc.

TypConditionsParameterSymbol

85 °C

UnitMax at

(1)

DD(AH)

current in active halt mode

Operating modeOnSupply

Power-down mode

µA1080HSE crystal

osc.

(16 MHz)

320200LSI RC osc.

(128 kHz)

1030HSE crystal

osc.

(16 MHz)

270140LSI RC osc.

(128 kHz)

59/103DocID022186 Rev 3

STM8S005K6 STM8S005C6Electrical characteristics

(3)

Main

Clock sourceFlash mode voltage regulator (MVR)

(2)

Operating modeOff

(128 kHz)

mode

(1)

Data based on characterization results, not tested in production.

(2)

Configured by the REGAH bit in the CLK_ICKR register.

(3)

Configured by the AHALT bit in the FLASH_CR1 register.

Table 24: Total current consumption in active halt mode at VDD= 3.3 V

(3)

Main

Clock sourceFlash mode

voltage regulator

(2)

(MVR)

TypConditionsParameterSymbol

85 °C

UnitMax at

(1)

12068LSI RC osc.

6012Power-down

TypConditionsParameterSymbol

85 °C

UnitMax at

(1)

DD(AH)

current in active halt mode

OnSupply

Off

Operating mode

Power-down mode

Operating mode

mode

µA680HSE crystal osc.

(16 MHz)

320200LSI RC osc.

(128 kHz)

630HSE crystal osc.

(16 MHz)

270140LSI RC osc.

(128 kHz)

12066LSI RC osc.

(128 kHz)

6010Power-down

DocID022186 Rev 360/103

(1)

Data based on characterization results, not tested in production.

(2)

Configured by the REGAH bit in the CLK_ICKR register.

(3)

Configured by the AHALT bit in the FLASH_CR1 register.

Total current consumption in halt mode9.3.2.4

Table 25: Total current consumption in halt mode at VDD= 5 V

Electrical characteristicsSTM8S005K6 STM8S005C6

DD(H)

Supply current in halt mode

clock after wakeup

(1)

Data based on characterization results, not tested in production.

Table 26: Total current consumption in halt mode at VDD= 3.3 V

DD(H)

Supply current in halt mode

clock after wakeup

TypConditionsParameterSymbol

85 °C

(1)

UnitMax at

µA9062Flash in operating mode, HSI

256.5Flash in powerdown mode, HSI

TypConditionsParameterSymbol

85 °C

(1)

UnitMax at

µA9060Flash in operating mode, HSI

204.5Flash in powerdown mode, HSI

WU(WFI)

(1)

Data based on characterization results, not tested in production.

Low power mode wakeup times9.3.2.5

Table 27: Wakeup times

Wakeup time from

wait mode to run

(3)

0 to 16 MHz

= f

CPU

MASTER

= 16 MHzmode

(1)

TypConditionsParameterSymbol

Max

See note

Unit

(2)

μs

0.56f

61/103DocID022186 Rev 3

STM8S005K6 STM8S005C6Electrical characteristics

(1)

TypConditionsParameterSymbol

Max

Unit

WU(AH)

WU(H)

Wakeup time active

halt mode to run

(3)

mode

Wakeup time active

halt mode to run

(3)

mode

Wakeup time active

halt mode to run

(3)

mode

Wakeup time active

halt mode to run

(3)

mode

Wakeup time from

halt mode to run

(3)

mode

MVR voltage

regulator

(4)

MVR voltage

regulator

(4)

MVR voltage

regulator

(4)

off

MVR voltage

regulator

(4)

off

Flash in operating

(5)

mode

Flash in

power-down

(5)

Flash in operating

(5)

mode

Flash in

power-down

(5)

HSI

(after

wakeup)

HSI

(after

wakeup)mode

HSI

(after

wakeup)

HSI

(after

wakeup)mode

52Flash in operating mode

54Flash in power-down mode

(6)

(1)

Data guaranteed by design, not tested in production.

(2)

WU(WFI)

(3)

Measured from interrupt event to interrupt vector fetch.

(4)

Configured by the REGAH bit in the CLK_ICKR register.

(5)

Configured by the AHALT bit in the FLASH_CR1 register.

(6)

Plus 1 LSI clock depending on synchronization.

= 2 x 1/f

master

+ x 1/f

CPU.

Total current consumption and timing in forced reset state9.3.2.6

Table 28: Total current consumption and timing in forced reset state

DD(R)

state

(2)

(1)

TypConditionsParameterSymbol

UnitMax

500VDD= 5 VSupply current in reset

μA

400VDD= 3.3 V

DocID022186 Rev 362/103

Electrical characteristicsSTM8S005K6 STM8S005C6

(1)

TypConditionsParameterSymbol

UnitMax

RESETBL

Reset pin release to vector fetch

(1)

Data guaranteed by design, not tested in production.

(2)

Characterized with all I/Os tied to VSS.

Current consumption of on-chip peripherals9.3.2.7

Subject to general operating conditions for VDDand TA.

HSI internal RC/f

DD(TIM1)

DD(TIM2)

DD(TIM3)

CPU

= f

MASTER

= 16 MHz.

Table 29: Peripheral current consumption

(1)

μs150

UnitTyp.ParameterSymbol

230TIM1 supply current

115TIM2 supply current

90TIM3 timer supply current

DD(TIM4)

(1)

30TIM4 timer supply current

µA

DD(UART2)

DD(SPI)

DD(I2C)

DD(ADC1)

(1)

Data based on a differential IDDmeasurement between reset configuration and timer

(2)

(3)

110UART2 supply current

45SPI supply current

65I2C supply current

955ADC1 supply current when converting

counter running at 16 MHz. No IC/OC programmed (no I/O pads toggling). Not tested in production.

(2)

Data based on a differential IDDmeasurement between the on-chip peripheral when kept under reset and not clocked and the on-chip peripheral when clocked and not kept under reset. No I/O pads toggling. Not tested in production.

(3)

Data based on a differential IDDmeasurement between reset configuration and continuous A/D conversions. Not tested in production.

63/103DocID022186 Rev 3

2.5

2.55

2.6

2.65

2.7

2.75

2.8

2.85

2.9

2.95

2.5 3 3.5 4 4.5 5 5.5 6

DD(RUN)HSE

[mA]

VDD[V]

-40°C

25°C

85°C

0.5

1.5

2.5

3.5

4.5

0 5 10 15 20 25 30

DD(RUN)HSE

[mA]

fcpu[MHz]

-40°C

25°C

85°C

STM8S005K6 STM8S005C6Electrical characteristics

Current consumption curves9.3.2.8

The following figures show typical current consumption measured with code executing in RAM.

Figure 11: Typ. I

DD(RUN)

vs. V

HSE user external clock, f

DD ,

= 16 MHz

CPU

Figure 12: Typ. I

DD(RUN)

vs. f

HSE user external clock, VDD= 5 V

CPU ,

DocID022186 Rev 364/103

2.1

2.2

2.3

2.4

2.5

2.6

2.7

2.8

2.9

2.5 3 3.5 4 4.5 5 5.5 6

DD(RUN)HSI

[mA]

VDD[V]

-40°C

25°C

85°C

1.2

1.4

1.6

1.8

2.2

2.4

2.5 3 3.5 4 4.5 5 5.5 6

DD(WFI)HSE

[mA]

VDD[V]

-40°C

25°C

85°C

0.5

1.5

2.5

0 5 10 15 20 25 30

DD(WFI)HSE

[mA]

fcpu[MHz]

-40°C

25°C

85°C

Electrical characteristicsSTM8S005K6 STM8S005C6

Figure 13: Typ. I

Figure 14: Typ. I

DD(WFI)

DD(RUN)

vs. V

HSE user external clock, f

DD ,

HSI RC osc, f

DD ,

= 16 MHz

CPU

= 16 MHz

Figure 15: Typ. I

DD(WFI)

vs. f

, HSE user external clock VDD= 5 V

CPU

65/103DocID022186 Rev 3

1.1

1.2

1.3

1.4

1.5

1.6

1.7

1.8

1.9

2.5 3 3.5 4 4.5 5 5.5 6

DD(WFI)HSI

[mA]

VDD[V]

-40°C

25°C

85°C

STM8S005K6 STM8S005C6Electrical characteristics

Figure 16: Typ. I

DD(WFI)

vs. VDD, HSI RC osc, f

External clock sources and timing characteristics9.3.3

HSE user external clock

Subject to general operating conditions for VDDand TA.

Table 30: HSE user external clock characteristics

CPU

= 16 MHz

UnitMaxMinConditionsParameterSymbol

HSE_ext

User external clock source frequency

HSEH

(1)

OSCIN input pin high level voltage

HSEL

(1)

OSCIN input pin low level voltage

LEAK_HSE

(1)

Data based on characterization results, not tested in production.

OSCIN input leakage currentI

VSS< VIN< V

MHz160

VDD+ 0.3 V0.7 x V

0.3 x V

μA+1-1

DocID022186 Rev 366/103

HSEH

HSEL

External clock source

OSCIN

HSE

STM8

Electrical characteristicsSTM8S005K6 STM8S005C6

Figure 17: HSE external clocksource

HSE crystal/ceramic resonator oscillator

The HSE clock can be supplied with a 1 to 16 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph is based on characterization results with specified typical external components. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and start-up stabilization time. Refer to the crystal resonator manufacturer for more details (frequency, package, accuracy...).

HSE

(1)

DD(HSE)

SU(HSE)

External high speed

oscillator frequency

Feedback resistorR

Recommended load

capacitance

HSE oscillator power

consumption

Oscillator

transconductance

(4)

Table 31: HSE oscillator characteristics

(2)

C = 20 pF,

= 16 MHz

OSC

C = 10 pF,

=16 MHz

OSC

VDDis stabilizedStartup timet

6 (startup)

1.6 (stabilized)

6 (startup)

1.2 (stabilized)

UnitMaxTypMinConditionsParameterSymbol

MHz161

kΩ220

pF20

(3)

mA/V5

ms1

(1)

C is approximately equivalent to 2 x crystal Cload.

67/103DocID022186 Rev 3

OSCOUT

OSCIN

HSE

to core

STM8

Resonator

Consumption

control

Resonator

STM8S005K6 STM8S005C6Electrical characteristics

(2)

The oscillator selection can be optimized in terms of supply current using a high quality resonator with

small Rmvalue. Refer to crystal manufacturer for more details

(3)

Data based on characterization results, not tested in production.

(4)

SU(HSE)

is the start-up time measured from the moment it is enabled (by software) to a stabilized 16 MHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer.

Figure 18: HSE oscillator circuit diagram

HSE oscillator critical gmequation

mcrit

= (2 × Π × f

)2× Rm(2Co + C)

HSE

Rm: Notional resistance (see crystal specification)

Lm: Notional inductance (see crystal specification)

Cm: Notional capacitance (see crystal specification)

Co: Shunt capacitance (see crystal specification)

CL1= CL2= C: Grounded external capacitance

gm>> g

mcrit

Internal clock sources and timing characteristics9.3.4

Subject to general operating conditions for VDDand TA.

High speed internal RC oscillator (HSI)

Table 32: HSI oscillator characteristics

UnitMaxTypMinConditionsParameterSymbol

HSI

DocID022186 Rev 368/103

MHz16Frequencyf

ACC

15.5

15.6

15.7

15.8

15.9

16.1

16.2

16.3

16.4

16.5

2.5 3 3.5 4 4.5 5 5.5 6

HSIfrequency[MHz]

VDD[V]

-40°C

25°C

85°C

Accuracy of HSI

HSI

oscillator

User-trimmed with CLK_HSITRIMR register for given VDDand T conditions

(1)

Electrical characteristicsSTM8S005K6 STM8S005C6

UnitMaxTypMinConditionsParameterSymbol

(2)

%1.0

Accuracy of HSI

(3)

oscillator (factory calibrated) 5.0-5.0

VDD= 5 V,

-40 °C ≤ TA≤ 85 °C

su(HSI)

HSI oscillator wakeup time including calibration

DD(HSI)

consumption

(1)

Refer to application note.

(2)

Guaranteed by design, not tested in production.

(3)

Data based on characterization results, not tested in production.

Figure 19: Typical HSI frequency variation vs VDD@ 3 temperatures

5.0VDD= 5 V, TA= 25°C

(2)

µs1.0

(3)

170HSI oscillator power

µA250

Low speed internal RC oscillator (LSI)

Subject to general operating conditions for VDDand TA.

69/103DocID022186 Rev 3

100

105

110

115

120

125

130

135

140

145

150

2.5 3 3.5 4 4.5 5 5.5 6

LSIfrequency[MHz]

VDD[V]

-40°C 25°C 85°C

STM8S005K6 STM8S005C6Electrical characteristics

Table 33: LSI oscillator characteristics

UnitMaxTypMinParameterSymbol

LSI

su(LSI)

DD(LSI)

(1)

Guaranteeed by design, not tested in production.

LSI oscillator wakeup timet

Figure 20: Typical LSI frequency variation vs VDD@ 3 temperatures

(1)

kHz128Frequencyf

µs7

µA5LSI oscillator power consumptionI

Memory characteristics9.3.5

RAM and hardware registers

(1)

Minimum supply voltage without losing data stored in RAM (in halt mode or under reset) or in hardware registers (only in halt mode). Guaranteed by design, not tested in production. refer to Operating conditions for the value of V

(2)

Refer to the Operating conditions section for the value of V

Flash program memory/data EEPROM memory

General conditions: TA= -40 to 85°C.

Table 34: RAM and hardware registers

(1)

DocID022186 Rev 370/103

Halt mode (or reset)Data retention mode

IT-max

(2)

UnitMinConditionsParameterSymbol

Electrical characteristicsSTM8S005K6 STM8S005C6

Table 35: Flash program memory/data EEPROM memory

prog

erase

RET

execution/write/erase)

(including erase) for byte/word/block (1 byte/4 bytes/128 bytes)

(128 bytes)

(2)

(program

memory)

after 100 erase/write cycles at T = 85 °C

(2)

ConditionsParameterSymbol

CPU

(1)

≤ 16 MHzOperating voltage (all modes,

UnitMaxTypMin

V5.52.95f

ms6.66.0Standard programming time

ms3.33.0Fast programming time for 1 block

ms3.33.0Erase time for 1 block (128 bytes)t

cycles100TA= 85 °CErase/write cycles

100 kTA= 85 ° CErase/write cycles(data memory)

= 55° CData retention (program memory)

RET

years20T

20Data retention (data memory) after 10 k erase/write cycles at TA= 85 °C

RET

= 85° CData retention (data memory) after

1T 100 k erase/write cyclesat TA= 85 °C

programming or erasing for 1 to 128 bytes)

(1)

Data based on characterization results, not tested in production.

(2)

The physical granularity of the memory is 4 bytes, so cycling is performed on 4 bytes

even when a write/erase operation addresses a single byte.

mA2.0Supply current (Flash

71/103DocID022186 Rev 3

STM8S005K6 STM8S005C6Electrical characteristics

I/O port pin characteristics9.3.6

General characteristics

Subject to general operating conditions for VDDand TAunless otherwise specified. All unused pins must be kept at a fixed voltage: using the output mode of the I/O for example or an external pull-up or pull-down resistor.

Table 36: I/O static characteristics

UnitMaxTypMinConditionsParameterSymbol

hys

tR, t

lkg

lkg ana

voltage

Input high level voltage

Pull-up resistorR

time(10 % - 90 %)

Input leakage current, analog and digital

Analog input leakage current

(1)

Fast I/Os load = 50 pFRise and fall

Standard and high sink I/OsLoad = 50 pF

VSS≤ VIN≤ V

-0.3VDD= 5 VInput low level

0.7 x V

V0.3 x V

VVDD+ 0.3

mV700Hysteresis

kΩ805530VDD= 5 V, VIN= V

(3)

(2)

ns35

ns125

µA±1.0

nA±250

lkg(inj)

adjacent I/O

(1)

Hysteresis voltage between Schmitt trigger switching levels. Based on characterization

(2)

Injection current ±4 mALeakage current in

(2)

results, not tested in production.

(2)

Data based on characterization results, not tested in production.

(3)

Data guaranteed by design, not tested in production.

DocID022186 Rev 372/103

µA±1.0

2.5 3 3.5 4 4.5 5 5.5 6

/ V

[V]

VDD[V]

-40°C

25°C

85°C

2.5 3 3.5 4 4.5 5 5.5 6

Pull-Upresistance[kW]

VDD[V]

-40°C

25°C

85°C

100

120

140

0 1 2 3 4 5 6

Pull-Upcurrent[µA]

VDD[V]

-40°C

25°C

85°C

Electrical characteristicsSTM8S005K6 STM8S005C6

Figure 21: Typical VILand VIHvs VDD@ 3 temperatures

Figure 22: Typical pull-up resistance vs VDD@ 3 temperatures

1. The pull-up is a pure resistor (slope goes through 0).

Figure 23: Typical pull-up current vs VDD@ 3 temperatures

73/103DocID022186 Rev 3

STM8S005K6 STM8S005C6Electrical characteristics

Table 37: Output driving current (standard ports)

UnitMaxMinConditionsParameterSymbol

(1)

Output low level with four pins

sunk

IIO= 4 mA,

VDD= 3.3 V

V1.0

Output low level with eight pins sunk

Output high level with four

pins sourced

VDD= 5 V

IIO= 4 mA,

VDD= 3.3 V

Output high level with eight pins sourced

(1)

Data based on characterization results, not tested in production

VDD= 5 V

Table 38: Output driving current (true open drain ports)

IIO= 10 mA, VDD= 3.3 VOutput low level with two pins

sunk

IIO= 20 mA, VDD= 5 V

2.0IIO= 10 mA,

(1)

V2.0

2.4IIO= 10 mA,

UnitMaxConditionsParameterSymbol

(1)

V1.5

1.0IIO= 10 mA, VDD= 5 V

(1)

2.0

(1)

Data based on characterization results, not tested in production

Table 39: Output driving current (high sink ports)

Output low level with four pins

sunk

IIO= 10 mA,

VDD= 3.3 V

Output low level with eight pins sunk

DocID022186 Rev 374/103

VDD= 5 V

UnitMaxMinConditionsParameterSymbol

(1)

V1.1

0.9IIO= 10 mA,

0.25

0.5

0.75

1.25

1.5

0 2 4 6 8 10 12

[V]

IOL[mA]

-40°C

25°C

85°C

Electrical characteristicsSTM8S005K6 STM8S005C6

UnitMaxMinConditionsParameterSymbol

(1)

Output low level with four pins sunk

Output high level with four pins

sourced

IIO= 20 mA,

VDD= 5 V

IIO= 10 mA,

VDD= 3.3 V

1.9

1.6

(1)

Output high level with eight pins sourced

Output high level with four pins sourced

(1)

Data based on characterization results, not tested in production

VDD= 5 V

IIO= 20 mA,

VDD= 5 V

3.8IIO= 10 mA,

2.9

(1)

Typical output level curves9.3.7

The following figures show typical output level curves measured with output on a single pin.

Figure 24: Typ. VOL@ VDD= 5 V (standard ports)

75/103DocID022186 Rev 3

0.25

0.5

0.75

1.25

1.5

0 1 2 3 4 5 6 7

[V]

IOL[mA]

-40°C

25°C

85°C

0.25

0.5

0.75

1.25

1.5

1.75

0 5 10 15 20 25

[V]

IOL[mA]

-40°C

25°C

85°C

0.25

0.5

0.75

1.25

1.5

1.75

0 2 4 6 8 10 12 14

[V]

IOL[mA]

-40°C

25°C

85°C

STM8S005K6 STM8S005C6Electrical characteristics

Figure 25: Typ. VOL@ VDD= 3.3 V (standard ports)

Figure 26: Typ. VOL@ VDD= 5 V (true open drain ports)

Figure 27: Typ. VOL@ VDD= 3.3 V (true open drain ports)

DocID022186 Rev 376/103

0.25

0.5

0.75

1.25

1.5

0 5 10 15 20 25

[V]

IOL[mA]

-40°C

25°C

85°C

0.25

0.5

0.75

1.25

1.5

0 2 4 6 8 10 12 14

[V]

IOL[mA]

-40°C

25°C

85°C

0.25

0.5

0.75

1.25

1.5

1.75

0 2 4 6 8 10 12

- V

[V]

IOH[mA]

-40°C

25°C

85°C

Electrical characteristicsSTM8S005K6 STM8S005C6

Figure 28: Typ. VOL@ VDD= 5 V (high sink ports)

Figure 29: Typ. VOL@ VDD= 3.3 V (high sink ports)

Figure 30: Typ. VDD- VOH@ VDD= 5 V (standard ports)

77/103DocID022186 Rev 3

0.25

0.5

0.75

1.25

1.5

1.75

0 1 2 3 4 5 6 7

- V

[V]

IOH[mA]

-40°C

25°C

85°C

0.25

0.5

0.75

1.25

1.5

1.75

0 5 10 15 20 25

- V

[V]

IOH[mA]

-40°C

25°C

85°C

0.25

0.5

0.75

1.25

1.5

1.75

0 2 4 6 8 10 12 14

- V

[V]

IOH[mA]

-40°C

25°C

85°C

STM8S005K6 STM8S005C6Electrical characteristics

Figure 31: Typ. VDD- VOH@ VDD= 3.3 V (standard ports)

Figure 32: Typ. VDD- VOH@ VDD= 5 V (high sink ports)

Figure 33: Typ. VDD- VOH@ VDD= 3.3 V (high sink ports)

DocID022186 Rev 378/103

IL(NRST)

IH(NRST)

OL(NRST)

PU(NRST)

Electrical characteristicsSTM8S005K6 STM8S005C6

Reset pin characteristics9.3.8

Subject to general operating conditions for VDDand TAunless otherwise specified.

Table 40: NRST pin characteristics

NRST input low

level voltage

(1)

NRST input high

level voltage

(1)

NRST output low

level voltage

(1)

NRST pull-up

resistor

(2)

IOL=2 mA

-0.3

0.3 x V

VDD+ 0.30.7 x V

0.5

UnitMaxTypMinConditionsParameterSymbol

kΩ805530

I FP(NRST)

IN FP(NRST)

OP(NRST)

(1)

Data based on characterization results, not tested in production.

(2)

The RPUpull-up equivalent resistor is based on a resistive transistor

(3)

Data guaranteed by design, not tested in production.

NRST input filtered

(3)

pulse

NRST input not

filtered pulse

(3)

NRST output

(3)

pulse

500

μs

79/103DocID022186 Rev 3

0.5

1.5

2.5

3.5

4.5

5.5

2.5 3 3.5 4 4.5 5 5.5 6

/ V

[V]

VDD[V]

-40°C

25°C

85°C

2.5 3 3.5 4 4.5 5 5.5 6

NRESETPull-Up resistance [kW]

VDD[V]

-40°C

25°C

85°C

IID10246

100

120

140

2 2.5 3 3.5 4 4.5 5 5.5 6

NRESETPull-Up current [µA]

VDD[V]

-40°C

25°C

85°C

STM8S005K6 STM8S005C6Electrical characteristics

Figure 34: Typical NRST VILand VIHvs VDD@ 3 temperatures

Figure 35: Typical NRST pull-up resistance vs VDD@ 3 temperatures

Figure 36: Typical NRST pull-up current vs VDD@ 3 temperatures

DocID022186 Rev 380/103

External

reset

circuit

(optional)

0.1 μF

NRST

VDD

RPU

Filter

Internal reset

STM8

Electrical characteristicsSTM8S005K6 STM8S005C6

The reset network shown in the following figure protects the device against parasitic resets. The user must ensure that the level on the NRST pin can go below V

IL(NRST)

max. (see Table

40: NRST pin characteristics ), otherwise the reset is not taken into account internally.

For power consumption sensitive applications, the external reset capacitor value can be reduced to limit the charge/discharge current. If NRST signal is used to reset external circuitry, attention must be taken to the charge/discharge time of the external capacitor to fulfill the external devices reset timing conditions. Minimum recommended capacity is 100 nF.

Figure 37: Recommended reset pin protection

SPI serial peripheral interface9.3.9

Unless otherwise specified, the parameters given in the following table are derived from tests performed under ambient temperature, f t

MASTER

= 1/f

MASTER

Refer to I/O port characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO).

Table 41: SPI characteristics

SCK

c(SCK)

r(SCK)

f(SCK)

su(NSS)

(1)

frequency

and fall time

Slave modeNSS setup timet

frequency and VDDsupply voltage conditions.

UnitMaxMinConditionsParameterSymbol

MHz80Master modeSPI clock

60Slave mode

25Capacitive load: C = 30 pFSPI clock rise

4 x t

MASTER

h(NSS)

(1)

ns70Slave modeNSS hold timet

81/103DocID022186 Rev 3

STM8S005K6 STM8S005C6Electrical characteristics

UnitMaxMinConditionsParameterSymbol

w(SCKH)

w(SCKL)

su(MI)

su(SI)

h(MI)

h(SI)

a(SO)

dis(SO)

(1)

(1) (2)

(1) (3)

(1)

low time

setup time

time

access time

disable time

Master modeSCK high and

SCK

/2 -

5Master modeData input

5Slave modeData input

7Master modeData input hold

10Slave modeData input hold

Slave modeData output

25Slave modeData output

/2 +

SCK

3 x t

MASTER

v(SO)

v(MO)

h(SO)

h(MO)

(1)

Data output valid time

Data output hold time

(after enable edge)

28Slave mode

(after enable edge)

12Master mode

73Slave mode

36Master mode

(after enable edge)

(1)

Values based on design simulation and/or characterization results, and not tested in

production.

(2)

Min time is for the minimum time to drive the output and the max time is for the maximum

time to validate the data.

(3)

Min time is for the minimum time to invalidate the output and the max time is for the

maximum time to put the data in Hi-Z.

DocID022186 Rev 382/103

ai14134

SCK Input

CPHA=0

MOSI

INPUT

MISO

OUT PUT

CPHA=0

MSB OUT

MSB IN

BIT6 OUT

LSB IN

LSB OUT

CPOL=0

CPOL=1

BIT1 IN

NSSinput

SU(NSS)

c(SCK)

h(NSS)

a(SO)

w(SCKH)

w(SCKL)

v(SO)

h(SO)

r(SCK)

f(SCK)

dis(SO)

su(SI)

h(SI)

ai14135

SCK Input

CPHA=1

MOSI

INPUT

MISO

OUT PUT

CPHA=1

MSB OUT

MSB IN

BIT6 OUT

LSB IN

LSB OUT

CPOL=0

CPOL=1

BIT1 IN

SU(NSS)

c(SCK)

h(NSS)

a(SO)

w(SCKH)

w(SCKL)

v(SO)

h(SO)

r(SCK)

f(SCK)

dis(SO)

su(SI)

h(SI)

NSS input

Electrical characteristicsSTM8S005K6 STM8S005C6

Figure 38: SPI timing diagram - slave mode and CPHA = 0

Figure 39: SPI timing diagram - slave mode and CPHA = 1

1. Measurement points are made at CMOS levels: 0.3 VDDand 0.7 VDD.

(1)

83/103DocID022186 Rev 3

ai14136b

SCK intput

CPHA=0

MOSI

OUTUT

MISO

INPUT

CPHA=0

MSBIN

MSB OUT

BIT6 IN

LSB OUT

LSB IN

CPOL=0

CPOL=1

BIT1 OUT

NSSinput

c(SCK)

w(SCKH)

w(SCKL)

r(SCK)

f(SCK)

h(MI)

High

SCK output

CPHA=1

CPOL=0

CPOL=1

su(MI)

v(MO)

h(MO)

STM8S005K6 STM8S005C6Electrical characteristics

Figure 40: SPI timing diagram - master mode

(1)

1. Measurement points are made at CMOS levels: 0.3 VDDand 0.7 VDD.

w(SCLL)

w(SCLH)

su(SDA)

h(SDA)

r(SDA)

r(SCL)

f(SDA)

f(SCL)

I2C interface characteristics9.3.10

SDA data hold timet

Table 42: I2C characteristics

Standard mode I2CParameterSymbol

Min

(3)

(2)

Max

(2)

Min

(4)

(2)

Max

(1)

(2)

(3)

UnitFast mode I2C

μs1.34.7SCL clock low timet

μs0.64.0SCL clock high timet

ns100250SDA setup timet

ns900

ns3001000SDA and SCL rise time

ns300300SDA and SCL fall time

DocID022186 Rev 384/103

ai15385b

START

SDA

I²C bus

STM8Sx05xx

SDA

SCL

f(SDA)

r(SDA)

SCL

h(STA)

w(SCLH)

w(SCLL)

su(SDA)

r(SCL)

f(SCL)

h(SDA)

START REPEATED

START

su(STA)

su(STO)

STOP

su(STA:STO)

Electrical characteristicsSTM8S005K6 STM8S005C6

(1)

Standard mode I2CParameterSymbol

UnitFast mode I2C

Max

(2)

μs0.64.0START condition hold timet

μs0.64.7

h(STA)

su(STA)

Repeated START condition

Min

(2)

Max

(2)

Min

(2)

setup time

su(STO)

w(STO:STA)

STOP to START condition time

μs0.64.0STOP condition setup timet

μs1.34.7

(bus free)

(1)

MASTER

(2)

Data based on standard I2C protocol requirement, not tested in production.

(3)

The maximum hold time of the start condition has only to be met if the interface does not stretch the

, must be at least 8 MHz to achieve max fast I2C speed (400kHz).

pF400400Capacitive load for each bus lineC

low time.

(4)

The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge

the undefined region of the falling edge of SCL.

Figure 41: Typical application with I2C bus and timing diagram

1. Measurement points are made at CMOS levels: 0.3 x VDDand 0.7 x V

(1)

85/103DocID022186 Rev 3

STM8S005K6 STM8S005C6Electrical characteristics

10-bit ADC characteristics9.3.11

Subject to general operating conditions for V

Table 43: ADC characteristics

ADC

DDA

Positive reference voltageV

Negative reference voltageV

Conversion voltage range

(2)

REF+

REF-

AIN

Devices with external V

, f

DDA

MASTER

=2.95 to 5.5 VADC clock frequencyf

DDA

=4.5 to 5.5 V

DDA

REF+/VREF-

, and TAunless otherwise specified.

UnitMaxTypMinConditionsParameterSymbol

6.01.0V

(1)

2.75

V SSA

REF-

DDA

(1)

V DDAV SSA

REF+

pins

MHz4.01.0V

V5.53.0Analog supplyV

V0.5

ADC

pF3.0Internal sample and hold

capacitor

(2)

STAB

CONV

ADC

= 4 MHzSampling timet

= 6 MHz

= 4 MHzTotal conversion time

0.5f

µs0.75f

µs7.0Wakeup time from standbyt

µs3.5f (including sampling time, 10-bit resolution)

(1)

Data guaranteed by design, not tested in production..

(2)

During the sample time the input capacitance C

ADC

= 6 MHz

AIN

(3 pF max) can be charged/discharged

µs2.33f

1/f

by the external source. The internal resistance of the analog source must allow the capacitance to reach its final voltage level within tS.After the end of the sample time tS,

ADC

DocID022186 Rev 386/103

Electrical characteristicsSTM8S005K6 STM8S005C6

changes of the analog input voltage have no effect on the conversion result. Values for the sample clock tSdepend on programming.

|ET|

|EO|

|EG|

Table 44: ADC accuracy with R

(2)

ADC

= 2 MHzTotal unadjusted error

= 4 MHz

= 6 MHz

= 2 MHzOffset error

= 4 MHz

= 6 MHz

= 2 MHzGain error

= 4 MHz

< 10 kΩ , V

AIN

DDA

TypConditionsParameterSymbol

= 5 V

(1)

UnitMax

LSB2.51.0f

3.01.4f

3.51.6f

2.00.6f

2.51.1f

2.51.2f

2.00.2f

2.50.6f

= 6 MHz

ADC

|ED|

|EL|

(1)

Data based on characterisation results, not tested in production.

(2)

ADC accuracy vs. negative injection current: Injecting negative current on any of the

(2)

ADC

= 2 MHzDifferential linearity error

= 4 MHz

= 6 MHz

= 2 MHzIntegral linearity error

= 4 MHz

= 6 MHz

2.50.8f

1.50.7f

1.50.8f

1.50.6f

analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to standard analog pins which may potentially inject negative current.

87/103DocID022186 Rev 3

STM8S005K6 STM8S005C6Electrical characteristics

Any positive injection current within the limits specified for I

INJ(PIN)

port pin characteristics section does not affect the ADC accuracy.

|ET|

|EO|

|EG|

|ED|

Table 45: ADC accuracy with R

(2)

ADC

< 10 kΩ R

AIN

= 2 MHzTotal unadjusted error

= 4 MHz

= 2 MHzOffset error

= 4 MHz

= 2 MHzGain error

= 4 MHz

= 2 MHzDifferential linearity error

AIN

, V

and ΣI

DDA

TypConditionsParameterSymbol

INJ(PIN)

= 3.3 V

2.51.6f

1.50.7f

2.01.3f

1.50.2f

2.00.5f

1.00.7f

in the I/O

(1)

UnitMax

LSB2.01.1f

= 4 MHz

ADC

|EL|

(1)

Data based on characterisation results, not tested in production.

(2)

ADC accuracy vs. negative injection current: Injecting negative current on any of the

(2)

ADC

= 2 MHzIntegral linearity error

= 4 MHz

1.00.7f

1.50.6f

INJ(PIN)

and ΣI

INJ(PIN)

in I/O port

pin characteristics does not affect the ADC accuracy.

DocID022186 Rev 388/103

Figure 42: ADC accuracy characteristics

STM8

10-bit A/D

conversion

AIN

AINx

0.6 V

± 1 µA

ADC

1. Example of an actual transfer curve.

2. The ideal transfer curve

3. End point correlation line

Electrical characteristicsSTM8S005K6 STM8S005C6

ET= Total unadjusted error: maximum deviation between the actual and the ideal transfer curves.

EO= Offset error: deviation between the first actual transition and the first ideal one.

EG= Gain error: deviation between the last ideal transition and the last actual one.

ED= Differential linearity error: maximum deviation between actual steps and the ideal one.

EL= Integral linearity error: maximum deviation between any actual transition and the end point correlation line.

Figure 43: Typical application with ADC

EMC characteristics9.3.12

Susceptibility tests are performed on a sample basis during product characterization.

89/103DocID022186 Rev 3

STM8S005K6 STM8S005C6Electrical characteristics

Functional EMS (electromagnetic susceptibility)9.3.12.1

While executing a simple application (toggling 2 LEDs through I/O ports), the product is stressed by two electromagnetic events until a failure occurs (indicated by the LEDs).

FESD: Functional electrostatic discharge (positive and negative) is applied on all pins of

•

the device until a functional disturbance occurs. This test conforms with the IEC 61000-4-2 standard.

FTB: A burst of fast transient voltage (positive and negative) is applied to VDDand V

•

through a 100 pF capacitor, until a functional disturbance occurs. This test conforms with the IEC 61000-4-4 standard.

A device reset allows normal operations to be resumed. The test results are given in the table below based on the EMS levels and classes defined in application note AN1709 (EMC design guide for STMicrocontrollers).

Designing hardened software to avoid noise problems9.3.12.2

EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular.

Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application.

FESD

EFTB

Software recommendations

The software flowchart must include the management of runaway conditions such as:

Corrupted program counter

•

Unexpected reset

•

Critical data corruption (control registers...)

•

Prequalification trials

Most of the common failures (unexpected reset and program counter corruption) can be recovered by applying a low state on the NRST pin or the oscillator pins for 1 second.

To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring. See application note AN1015 (Software techniques for improving microcontroller EMC performance).

Table 46: EMS data

Level/ classConditionsParameterSymbol

Voltage limits to be applied on any I/O pin to induce a functional disturbance

Fast transient voltage burst limits to be applied through 100 pF on VDDand VSSpins to induce a functional disturbance

VDD= 5 V, TA= 25 °C, f conforming to IEC 1000-4-2

VDD= 5 V, TA= 25 °C ,f to IEC 1000-4-4

MASTER

= 16 MHz,

= 16 MHz,conforming

2/B

4/A

(1)

DocID022186 Rev 390/103

Electrical characteristicsSTM8S005K6 STM8S005C6

(1)

Data obtained with HSI clock configuration, after applying HW recommendations described in AN2860 (EMC

guidelines for STM8S microcontrollers).

Electromagnetic interference (EMI)9.3.12.3

Emission tests conform to the IEC61967-2 standard for test software, board layout and pin loading.

Table 47: EMI data

UnitConditionsParameterSymbol

General conditions

Monitored frequency band

Max f

8 MHz/ 8 MHz

EMI

Peak levelS

VDD= 5 V,

TA= +25 °C,

30 MHz

LQFP48 package conforming to

130 MHz

IEC61967-2

GHz

level

(1)

Data based on characterization results, not tested in production.

Absolute maximum ratings (electrical sensitivity)9.3.12.4

HSE/fCPU

(1)

8 MHz/ 16 MHz

dBµV14130.1 MHz to

192330 MHz to

-4.0-4.0130 MHz to 1

—1.52.0SAE EMI

Based on two different tests (ESD and LU) using specific measurement methods, the product is stressed in order to determine its performance in terms of electrical sensitivity. For more details, refer to the application note AN1181.

Electrostatic discharge (ESD)9.3.12.5

Electrostatic discharges (3 positive then 3 negative pulses separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts*(n+1) supply pin). This test conforms to the JESD22-A114A/A115A standard. For more details, refer to the application note AN1181.

91/103DocID022186 Rev 3

STM8S005K6 STM8S005C6Electrical characteristics

Table 48: ESD absolute maximum ratings

(1)

UnitMaximum

V2000ATA= +25°C,

V1000IVTA=+25°C, conforming

ESD(HBM)

ESD(CDM)

(1)

Data based on characterization results, not tested in production

Electrostatic discharge voltage (Human body model)

Electrostatic discharge voltage (Charge device model)

conforming to JESD22-A114

to JESD22-C101

ClassConditionsRatingsSymbol

value

Static latch-up9.3.12.6

Two complementary static tests are required on 10 parts to assess the latch-up performance:

A supply overvoltage (applied to each power supply pin)

•

A current injection (applied to each input, output and configurable I/O pin) are performed

•

on each sample.

This test conforms to the EIA/JESD 78 IC latch-up standard. For more details, refer to the application note AN1181.

Table 49: Electrical sensitivities

(1)

ConditionsParameterSymbol

(1)

Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the JEDEC specifications, that means when a device belongs to class A it exceeds the JEDEC standard. B class strictly covers all the JEDEC criteria (international standard).

Class

ATA= +25 °CStatic latch-up classLU

ATA= +85 °C

DocID022186 Rev 392/103

5B_ME

A1 K

ccc

D D1 D3

E1 E

Pin 1 identification

Package informationSTM8S005K6 STM8S005C6

Package information10

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK®packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark.

48-pin LQFP package mechanical data10.1

Figure 44: 48-pin low profile quad flat package (7 x 7)

Table 50: 48-pin low profile quad flat package mechanical data

mmDim.

inches

(1)

MaxTypMinMaxTypMin

0.06301.600A

0.00590.00200.1500.050A1

0.05710.05510.05311.4501.4001.350A2

0.01060.00870.00670.2700.2200.170b

0.00790.00350.2000.090c

0.36220.35430.34659.2009.0008.800D

93/103DocID022186 Rev 3

STM8S005K6 STM8S005C6Package information

mmDim.

inches

(1)

MaxTypMinMaxTypMin

0.28350.27560.26777.2007.0006.800D1

0.21655.500D3

0.36220.35430.34659.2009.0008.800E

0.28350.27560.26777.2007.0006.800E1

0.21655.500E3

0.01970.500e

0.02950.02360.01770.7500.6000.450L

0.03941.000L1

(1)

Values in inches are converted from mm and rounded to 4 decimal digits

7.0°3.5°0°7.0°3.5°0°k

0.00310.080ccc

DocID022186 Rev 394/103

5V_ME

A1 K

ccc

D D1 D3

E1 E

Pin 1 identification

Package informationSTM8S005K6 STM8S005C6

32-pin LQFP package mechanical data10.2

Figure 45: 32-pin low profile quad flat package (7 x 7)

Table 51: 32-pin low profile quad flat package mechanical data

mmDim.

inches

(1)

MaxTypMinMaxTypMin

0.06301.600A

0.00590.00200.1500.050A1

0.05710.05510.05311.4501.4001.350A2

0.01770.01460.01180.4500.3700.300b

0.00790.00350.2000.090c

0.36220.35430.34659.2009.0008.800D

0.22055.600D3

0.28350.27560.26777.2007.0006.800D1

0.36220.35430.34659.2009.0008.800E

0.28350.27560.26777.2007.0006.800E1

95/103DocID022186 Rev 3

STM8S005K6 STM8S005C6Package information

mmDim.

inches

(1)

0.22055.600E3

0.03150.800e

0.03941.000L1

(1)

Values in inches are converted from mm and rounded to 4 decimal digits

MaxTypMinMaxTypMin

0.02950.02360.01770.7500.6000.450L

7.0°3.5°0°7.0°3.5°0°k

0.00390.100ccc

DocID022186 Rev 396/103

Thermal characteristicsSTM8S005K6 STM8S005C6

Thermal characteristics11

The maximum chip junction temperature (T

Operating conditions

The maximum chip-junction temperature, T the following equation:

= T

Jmax

Where:

Amax

•

ΘJAis the package junction-to-ambient thermal resistance in ° C/W

•

Dmax

•

INTmax

•

power.

I/Omax

•

+ Σ((VDD-V and high level in the application.

+ (P

Amax

is the maximum ambient temperature in °C

is the sum of P

is the product of IDDandVDD, expressed in Watts. This is the maximum chip internal

represents the maximum power dissipation on output pinsWhere:P

OH)*IOH

LQFP 48 - 7 x 7 mm

x ΘJA)

Dmax

and P

INTmax

), taking into account the actual VOL/I

Table 52: Thermal characteristics

I/Omax(PDmax

) must never exceed the values given in

J max

, in degrees Celsius, may be calculated using

Jmax

= P

+ P

INTmax

OL andVOH/IOH

I/Omax

(1)

)

=Σ (VOL*IOL)

I/Omax

of the I/Os at low

UnitValueParameterSymbol

°C/W57Thermal resistance junction-ambient

LQFP 32 - 7 x 7 mm

1. Thermal resistances are based on JEDEC JESD51-2 with 4-layer PCB in a natural convection environment.

°C/W60Thermal resistance junction-ambient

Reference document11.1

JESD51-2 integrated circuits thermal test method environment conditions - natural convection (still air). Available from www.jedec.org.

Selecting the product temperature range11.2

When ordering the microcontroller, the temperature range is specified in the order code.

The following example shows how to calculate the temperature range needed for a given application.

Assuming the following application conditions:

Maximum ambient temperature T

•

= 15 mA, VDD= 5.5 V

DDmax

= 82 °C (measured according to JESD51-2)

Amaz

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STM8S005K6 STM8S005C6Thermal characteristics

Maximum 8 standard I/Os used at the same time in output at low level with IOL= 10 mA,

•

VOL= 2 V

Maximum 4 high sink I/Os used at the same time in output at low level with IOL= 20 mA,

•

VOL= 1.5 V

Maximum 2 true open drain I/Os used at the same time in output at low level with IOL=

•

20 mA, VOL= 2 V

This gives: P

Thus: P

Jmax

This is within the range of the suffix 6 version parts (-40 < TJ< 106° C). In this case, parts must be ordered at least with the temperature range suffix 6.

= 15 mA x 5.5 V = 82.5 mW

INTmax

= (10 mA x 2 V x 8 )+(20 mA x 2 V x 2)+(20 mA x 1.5 V x 4) = 360 mW

IOmax

= 82.5 mW and P

INTmax

= 82.5 mW + 360 mW

Dmax

= 443 mW

Dmax

for LQFP32 can be calculated as follows, using the thermal resistance ΘJA:

= 75° C + (59° C/W x 464 mW) = 75°C + 27°C = 102° C

IOmax

360 mW:

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Product class

Pin count K = 32 pins

C = 48 pins

Package type T = LQFP

Example:

Sub-family type 005 = Value line STM8S005x

Family type S = Standard

Temperature range 6 = -40 °C to 85 °C

Program memory size 6 = 32 Kbytes

Package pitch No character = 0.5 mm C = 0.8 mm

Packing No character = Tray or tube TR = Tapeand reel

STM8

005

K 6 T

Ordering informationSTM8S005K6 STM8S005C6

Ordering information12

Figure 46: STM8S005xx value line ordering information scheme

1. For a list of available options (e.g. memory size, package) and orderable part numbers or

for further information on any aspect of this device, please go to www.st.com or contact the ST sales office nearest to you.

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STM8S005K6 STM8S005C6STM8 development tools

STM8 development tools13

Development tools for the STM8 microcontrollers include the full-featured STice emulation system supported by a complete software tool package including C compiler, assembler and integrated development environment with high-level language debugger. In addition, the STM8 is to be supported by a complete range of tools including starter kits, evaluation boards and a low-cost in-circuit debugger/programmer.

Emulation and in-circuit debugging tools13.1

The STice emulation system offers a complete range of emulation and in-circuit debugging features on a platform that is designed for versatility and cost-effectiveness. In addition, STM8 application development is supported by a low-cost in-circuit debugger/programmer.

The STice is the fourth generation of full featured emulators from STMicroelectronics. It offers new advanced debugging capabilities including profiling and coverage to help detect and eliminate bottlenecks in application execution and dead code when fine tuning an application.

In addition, STice offers in-circuit debugging and programming of STM8 microcontrollers via the STM8 single wire interface module (SWIM), which allows non-intrusive debugging of an application while it runs on the target microcontroller.

For improved cost effectiveness, STice is based on a modular design that allows you to order exactly what you need to meet your development requirements and to adapt your emulation system to support existing and future ST microcontrollers.

STice key features

Occurrence and time profiling and code coverage (new features)

•

Advanced breakpoints with up to 4 levels of conditions

•

Data breakpoints

•

Program and data trace recording up to 128 KB records

•

Read/write on the fly of memory during emulation

•

In-circuit debugging/programming via SWIM protocol

•

8-bit probe analyzer

•

1 input and 2 output triggers

•

Power supply follower managing application voltages between 1.62 to 5.5 V

•

Modularity that allows you to specify the components you need to meet your development

•

requirements and adapt to future requirements

Supported by free software tools that include integrated development environment (IDE),

•

programming software interface and assembler for STM8.

Software tools13.2

STM8 development tools are supported by a complete, free software package from STMicroelectronics that includes ST Visual Develop (STVD) IDE and the ST Visual Programmer (STVP) software interface. STVD provides seamless integration of the Cosmic and Raisonance C compilers for STM8, which are available in a free version that outputs up to 16 Kbytes of code.

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ST STM8S005K6, STM8S005C6 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Contents

IntroductionSTM8S005K6 STM8S005C6

STM8S005K6 STM8S005C6Description

Block diagramSTM8S005K6 STM8S005C6

STM8S005K6 STM8S005C6Product overview

Central processing unit STM84.1

Single wire interface module (SWIM) and debug module (DM)4.2

Interrupt controller4.3

Flash program and data EEPROM memory4.4

Clock controller4.5

Power management4.6

Watchdog timers4.7

Auto wakeup counter4.8

Beeper4.9

TIM1 - 16-bit advanced control timer4.10

TIM2, TIM3 - 16-bit general purpose timers4.11

TIM4 - 8-bit basic timer4.12

Analog-to-digital converter (ADC1)4.13

Communication interfaces4.14

UART24.14.1

Pinout and pin descriptionSTM8S005K6 STM8S005C6

STM8S005 pinouts and pin description5.1

Alternate function remapping5.1.1

Memory and register mapSTM8S005K6 STM8S005C6

Memory map6.1

Register map6.2

I/O port hardware register map6.2.1

General hardware register map6.2.2

CPU/SWIM/debug module/interrupt controller registers6.2.3

STM8S005K6 STM8S005C6Interrupt vector mapping

STM8S005K6 STM8S005C6Option bytes

Electrical characteristicsSTM8S005K6 STM8S005C6

Parameter conditions9.1

Minimum and maximum values9.1.1

Typical values9.1.2

Typical curves9.1.3

Typical current consumption9.1.4

Loading capacitor9.1.5

Pin input voltage9.1.6

Absolute maximum ratings9.2

Operating conditions9.3

VCAP external capacitor9.3.1

Supply current characteristics9.3.2

Total current consumption in run mode9.3.2.1

Total current consumption in wait mode9.3.2.2

Total current consumption in active halt mode9.3.2.3

Total current consumption in halt mode9.3.2.4

Low power mode wakeup times9.3.2.5

Total current consumption and timing in forced reset state9.3.2.6

Current consumption of on-chip peripherals9.3.2.7

Current consumption curves9.3.2.8

External clock sources and timing characteristics9.3.3

Internal clock sources and timing characteristics9.3.4

Memory characteristics9.3.5

I/O port pin characteristics9.3.6

Typical output level curves9.3.7

Reset pin characteristics9.3.8

SPI serial peripheral interface9.3.9

I2C interface characteristics9.3.10

10-bit ADC characteristics9.3.11

EMC characteristics9.3.12

Functional EMS (electromagnetic susceptibility)9.3.12.1

Designing hardened software to avoid noise problems9.3.12.2

Electromagnetic interference (EMI)9.3.12.3

Absolute maximum ratings (electrical sensitivity)9.3.12.4

Electrostatic discharge (ESD)9.3.12.5

Static latch-up9.3.12.6

Package informationSTM8S005K6 STM8S005C6

48-pin LQFP package mechanical data10.1

32-pin LQFP package mechanical data10.2

Thermal characteristicsSTM8S005K6 STM8S005C6

Reference document11.1

Selecting the product temperature range11.2

Ordering informationSTM8S005K6 STM8S005C6

STM8S005K6 STM8S005C6STM8 development tools

Emulation and in-circuit debugging tools13.1