ST STM8S, STM8A Reference Manual

RM0016

Reference manual

STM8S and STM8A microcontroller families

Introduction

This reference manual provides complete information for application developers on how to
use STM8S and STM8A microcontroller memory and peripherals.

The STM8A is a family of microcontrollers designed for automotive applications, with
different memory densities, packages and peripherals:

■ The medium density STM8A devices are the STM8AF622x/4x, STM8AF6266/68,

STM8AF612x/4x, and STM8AF6166/68 microcontrollers with 8 to 32 Kbytes of Flash
memory.

■ The high density STM8A devices are the STM8AF52xx STM8AF6269/8x/Ax,

STM8AF51xx, and STM8AF6169/7x/8x/9x/Ax microcontrollers with 32 to 128 Kbytes of
Flash memory.

The STM8S is a family of microcontrollers designed for general purpose applications, with
different memory densities, packages and peripherals.

■ The value line low density STM8S devices are the STM8S003xx microcontrollers with

8 Kbytes of Flash memory.

■ The value line medium density STM8S devices are the STM8S005xx microcontrollers

with 32 Kbytes of Flash memory.

■ The value line high density STM8S devices are the STM8S007xx microcontrollers with

64 Kbytes of Flash memory.

■ The access line low density STM8S devices are the STM8S103xx and STM8S903xx

microcontrollers with 8 Kbytes of Flash memory.

■ The access line medium density STM8S devices are the STM8S105xx microcontrollers

with 16 to 32-Kbytes of Flash memory.

■ The performance line high density STM8S devices are the STM8S207xx and

STM8S208xx microcontrollers with 32 to 128 Kbytes of Flash memory.

Refer to the product datasheet for ordering information, pin description, mechanical and
electrical device characteristics, and for the complete list of available peripherals.

Reference documents

■ For information on programming, erasing and protection of the internal Flash memory

please refer to the STM8S and STM8A Flash programming manual (PM0051), and to the
STM8 SWIM communication protocol and debug module user manual (UM0470).

■ For information on the STM8 core, please refer to the STM8 CPU programming manual

December 2011 Doc ID 14587 Rev 8 1/449

(PM0044).

■ The bootloader user manual (UM0560) describes the usage of the integrated ROM

bootloader.

www.st.com

Contents RM0016

Contents

1 Central processing unit (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

1.2 CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

1.2.1 Description of CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

1.2.2 STM8 CPU register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

1.3 Global configuration register (CFG_GCR) . . . . . . . . . . . . . . . . . . . . . . . . 27

1.3.1 Activation level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

1.3.2 SWIM disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

1.3.3 Description of global configuration register (CFG_GCR) . . . . . . . . . . . . 28

1.3.4 Global configuration register map and reset values . . . . . . . . . . . . . . . . 28

2 Boot ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

3 Memory and register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

3.1 Memory layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

3.1.1 Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

3.1.2 Stack handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

3.2 Register description abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

4 Flash program memory and data EEPROM . . . . . . . . . . . . . . . . . . . . . 34

4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

4.2 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

4.3 Main Flash memory features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

4.4 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

4.4.1 STM8S and STM8A memory organization . . . . . . . . . . . . . . . . . . . . . . 36

4.4.2 Memory access/ wait state configuration . . . . . . . . . . . . . . . . . . . . . . . . 40

4.4.3 User boot area (UBC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

4.4.4 Data EEPROM (DATA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

4.4.5 Main program area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

4.4.6 Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

4.5 Memory protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

4.5.1 Readout protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

4.5.2 Memory access security system (MASS) . . . . . . . . . . . . . . . . . . . . . . . 44

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4.5.3 Enabling write access to option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . 46

4.6 Memory programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

4.6.1 Read-while-write (RWW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

4.6.2 Byte programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

4.6.3 Word programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

4.6.4 Block programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

4.6.5 Option byte programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

4.7 ICP and IAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

4.8 Flash registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

4.8.1 Flash control register 1 (FLASH_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . 51

4.8.2 Flash control register 2 (FLASH_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . 52

4.8.3 Flash complementary control register 2 (FLASH_NCR2) . . . . . . . . . . . 53

4.8.4 Flash protection register (FLASH_FPR) . . . . . . . . . . . . . . . . . . . . . . . . 54

4.8.5 Flash protection register (FLASH_NFPR) . . . . . . . . . . . . . . . . . . . . . . . 54

4.8.6 Flash program memory unprotecting key register (FLASH_PUKR) . . . 54

4.8.7 Data EEPROM unprotection key register (FLASH_DUKR) . . . . . . . . . . 55

4.8.8 Flash status register (FLASH_IAPSR) . . . . . . . . . . . . . . . . . . . . . . . . . . 55

4.8.9 Flash register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

5 Single wire interface module (SWIM) and debug module (DM) . . . . . 57

5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

5.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

5.3 SWIM modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

6 Interrupt controller (ITC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

6.1 ITC introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

6.2 Interrupt masking and processing flow . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

6.2.1 Servicing pending interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

6.2.2 Interrupt sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

6.3 Interrupts and low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

6.4 Activation level/low power mode control . . . . . . . . . . . . . . . . . . . . . . . . . . 62

6.5 Concurrent and nested interrupt management . . . . . . . . . . . . . . . . . . . . 63

6.5.1 Concurrent interrupt management mode . . . . . . . . . . . . . . . . . . . . . . . . 63

6.5.2 Nested interrupt management mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

6.6 External interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

6.7 Interrupt instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

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6.8 Interrupt mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

6.9 ITC and EXTI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

6.9.1 CPU condition code register interrupt bits (CCR) . . . . . . . . . . . . . . . . . 67

6.9.2 Software priority register x (ITC_SPRx) . . . . . . . . . . . . . . . . . . . . . . . . . 68

6.9.3 External interrupt control register 1 (EXTI_CR1) . . . . . . . . . . . . . . . . . . 69

6.9.4 External interrupt control register 1 (EXTI_CR2) . . . . . . . . . . . . . . . . . . 70

6.9.5 ITC and EXTI register map and reset values . . . . . . . . . . . . . . . . . . . . . 71

7 Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

8 Reset (RST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

8.1 “Reset state” and “under reset” definitions . . . . . . . . . . . . . . . . . . . . . . . . 73

8.2 Reset circuit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

8.3 Internal reset sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

8.3.1 Power-on reset (POR) and brown-out reset (BOR) . . . . . . . . . . . . . . . . 74

8.3.2 Watchdog reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

8.3.3 Software reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

8.3.4 SWIM reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

8.3.5 Illegal opcode reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

8.3.6 EMC reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

8.4 RST register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

8.4.1 Reset status register (RST_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

8.5 RST register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

9 Clock control (CLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

9.1 Master clock sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

9.1.1 HSE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

9.1.2 HSI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

9.1.3 LSI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

9.2 Master clock switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

9.2.1 System startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

9.2.2 Master clock switching procedures . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

9.3 Low speed clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

9.4 CPU clock divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

9.5 Peripheral clock gating (PCG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

9.6 Clock security system (CSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

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9.7 Clock-out capability (CCO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

9.8 CLK interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

9.9 CLK register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

9.9.1 Internal clock register (CLK_ICKR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

9.9.2 External clock register (CLK_ECKR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

9.9.3 Clock master status register (CLK_CMSR) . . . . . . . . . . . . . . . . . . . . . . 91

9.9.4 Clock master switch register (CLK_SWR) . . . . . . . . . . . . . . . . . . . . . . . 91

9.9.5 Switch control register (CLK_SWCR) . . . . . . . . . . . . . . . . . . . . . . . . . . 92

9.9.6 Clock divider register (CLK_CKDIVR) . . . . . . . . . . . . . . . . . . . . . . . . . . 93

9.9.7 Peripheral clock gating register 1 (CLK_PCKENR1) . . . . . . . . . . . . . . . 94

9.9.8 Peripheral clock gating register 2 (CLK_PCKENR2) . . . . . . . . . . . . . . . 95

9.9.9 Clock security system register (CLK_CSSR) . . . . . . . . . . . . . . . . . . . . . 96

9.9.10 Configurable clock output register (CLK_CCOR) . . . . . . . . . . . . . . . . . 97

9.9.11 HSI clock calibration trimming register (CLK_HSITRIMR) . . . . . . . . . . . 98

9.9.12 SWIM clock control register (CLK_SWIMCCR) . . . . . . . . . . . . . . . . . . . 99

9.10 CLK register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

10 Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

10.1 General considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

10.1.1 Clock management for low consumption . . . . . . . . . . . . . . . . . . . . . . . 102

10.2 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

10.2.1 Wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

10.2.2 Halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

10.2.3 Active-halt modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

10.3 Additional analog power controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

10.3.1 Fast Flash wakeup from Halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

10.3.2 Very low Flash consumption in Active-halt mode . . . . . . . . . . . . . . . . . 104

11 General purpose I/O ports (GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

11.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

11.2 GPIO main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

11.3 Port configuration and usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

11.3.1 Input modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

11.3.2 Output modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

11.4 Reset configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

11.5 Unused I/O pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

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11.6 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

11.7 Input mode details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

11.7.1 Alternate function input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

11.7.2 Interrupt capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

11.7.3 Analog channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

11.7.4 Schmitt trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

11.8 Output mode details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

11.8.1 Alternate function output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

11.8.2 Slope control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

11.9 GPIO registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

11.9.1 Port x output data register (Px_ODR) . . . . . . . . . . . . . . . . . . . . . . . . . 111

11.9.2 Port x pin input register (Px_IDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

11.9.3 Port x data direction register (Px_DDR) . . . . . . . . . . . . . . . . . . . . . . . 112

11.9.4 Port x control register 1 (Px_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

11.9.5 Port x control register 2 (Px_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

11.9.6 GPIO register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . 113

12 Auto-wakeup (AWU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

12.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

12.2 LSI clock measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

12.3 AWU functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

12.3.1 AWU operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

12.3.2 Time base selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

12.3.3 LSI clock frequency measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

12.4 AWU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

12.4.1 Control/status register (AWU_CSR) . . . . . . . . . . . . . . . . . . . . . . . . . . 118

12.4.2 Asynchronous prescaler register (AWU_APR) . . . . . . . . . . . . . . . . . . 118

12.4.3 Timebase selection register (AWU_TBR) . . . . . . . . . . . . . . . . . . . . . . 119

12.4.4 AWU register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . 119

13 Beeper (BEEP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

13.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

13.2 Beeper functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

13.2.1 Beeper operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

13.2.2 Beeper calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

13.3 Beeper registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

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13.3.1 Beeper control/status register (BEEP_CSR) . . . . . . . . . . . . . . . . . . . . 121

13.3.2 Beeper register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . 121

14 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

14.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

14.2 IWDG functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

14.3 IWDG registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

14.3.1 Key register (IWDG_KR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

14.3.2 Prescaler register (IWDG_PR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

14.3.3 Reload register (IWDG_RLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

14.3.4 IWDG register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . 125

15 Window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

15.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

15.2 WWDG main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

15.3 WWDG functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

15.4 How to program the watchdog timeout . . . . . . . . . . . . . . . . . . . . . . . . . . 128

15.5 WWDG low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

15.6 Hardware watchdog option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

15.7 Using Halt mode with the WWDG (WWDGHALT option) . . . . . . . . . . . . 130

15.8 WWDG interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

15.9 WWDG registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

15.9.1 Control register (WWDG_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

15.9.2 Window register (WWDG_WR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

15.10 Window watchdog register map and reset values . . . . . . . . . . . . . . . . . 131

16 Timer overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

16.1 Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

16.2 Glossary of timer signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

17 16-bit advanced control timer (TIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . 136

17.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

17.2 TIM1 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

17.3 TIM1 time base unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

17.3.1 Reading and writing to the 16-bit counter . . . . . . . . . . . . . . . . . . . . . . 140

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17.3.2 Write sequence for 16-bit TIM1_ARR register . . . . . . . . . . . . . . . . . . . 140

17.3.3 Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

17.3.4 Up-counting mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

17.3.5 Down-counting mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

17.3.6 Center-aligned mode (up/down counting) . . . . . . . . . . . . . . . . . . . . . . 145

17.3.7 Repetition down-counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

17.4 TIM1 clock/trigger controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

17.4.1 Prescaler clock (CK_PSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

17.4.2 Internal clock source (fMASTER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

17.4.3 External clock source mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

17.4.4 External clock source mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

17.4.5 Trigger synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

17.4.6 Synchronization between TIM1, TIM5 and TIM6 timers . . . . . . . . . . . 157

17.5 TIM1 capture/compare channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

17.5.1 Write sequence for 16-bit TIM1_CCRi registers . . . . . . . . . . . . . . . . . 164

17.5.2 Input stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

17.5.3 Input capture mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

17.5.4 Output stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

17.5.5 Forced output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

17.5.6 Output compare mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

17.5.7 PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

17.5.8 Using the break function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178

17.5.9 Clearing the OCiREF signal on an external event . . . . . . . . . . . . . . . . 181

17.5.10 Encoder interface mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182

17.6 TIM1 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184

17.7 TIM1 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

17.7.1 Control register 1 (TIM1_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

17.7.2 Control register 2 (TIM1_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

17.7.3 Slave mode control register (TIM1_SMCR) . . . . . . . . . . . . . . . . . . . . . 188

17.7.4 External trigger register (TIM1_ETR) . . . . . . . . . . . . . . . . . . . . . . . . . . 189

17.7.5 Interrupt enable register (TIM1_IER) . . . . . . . . . . . . . . . . . . . . . . . . . . 191

17.7.6 Status register 1 (TIM1_SR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192

17.7.7 Status register 2 (TIM1_SR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193

17.7.8 Event generation register (TIM1_EGR) . . . . . . . . . . . . . . . . . . . . . . . . 194

17.7.9 Capture/compare mode register 1 (TIM1_CCMR1) . . . . . . . . . . . . . . . 195

17.7.10 Capture/compare mode register 2 (TIM1_CCMR2) . . . . . . . . . . . . . . . 198

17.7.11 Capture/compare mode register 3 (TIM1_CCMR3) . . . . . . . . . . . . . . . 199

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17.7.12 Capture/compare mode register 4 (TIM1_CCMR4) . . . . . . . . . . . . . . . 200

17.7.13 Capture/compare enable register 1 (TIM1_CCER1) . . . . . . . . . . . . . . 201

17.7.14 Capture/compare enable register 2 (TIM1_CCER2) . . . . . . . . . . . . . . 204

17.7.15 Counter high (TIM1_CNTRH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204

17.7.16 Counter low (TIM1_CNTRL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205

17.7.17 Prescaler high (TIM1_PSCRH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205

17.7.18 Prescaler low (TIM1_PSCRL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205

17.7.19 Auto-reload register high (TIM1_ARRH) . . . . . . . . . . . . . . . . . . . . . . . 206

17.7.20 Auto-reload register low (TIM1_ARRL) . . . . . . . . . . . . . . . . . . . . . . . . 206

17.7.21 Repetition counter register (TIM1_RCR) . . . . . . . . . . . . . . . . . . . . . . . 206

17.7.22 Capture/compare register 1 high (TIM1_CCR1H) . . . . . . . . . . . . . . . . 207

17.7.23 Capture/compare register 1 low (TIM1_CCR1L) . . . . . . . . . . . . . . . . . 207

17.7.24 Capture/compare register 2 high (TIM1_CCR2H) . . . . . . . . . . . . . . . . 208

17.7.25 Capture/compare register 2 low (TIM1_CCR2L) . . . . . . . . . . . . . . . . . 208

17.7.26 Capture/compare register 3 high (TIM1_CCR3H) . . . . . . . . . . . . . . . . 209

17.7.27 Capture/compare register 3 low (TIM1_CCR3L) . . . . . . . . . . . . . . . . . 209

17.7.28 Capture/compare register 4 high (TIM1_CCR4H) . . . . . . . . . . . . . . . . 210

17.7.29 Capture/compare register 4 low (TIM1_CCR4L) . . . . . . . . . . . . . . . . . 210

17.7.30 Break register (TIM1_BKR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211

17.7.31 Deadtime register (TIM1_DTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212

17.7.32 Output idle state register (TIM1_OISR) . . . . . . . . . . . . . . . . . . . . . . . . 213

17.7.33 TIM1 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . 214

18 16-bit general purpose timers (TIM2, TIM3, TIM5) . . . . . . . . . . . . . . . 216

18.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216

18.2 TIM2/TIM3 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216

18.3 TIM5 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217

18.4 TIM2/TIM3/TIM5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . 217

18.4.1 Time base unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218

18.4.2 Clock/trigger controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219

18.4.3 Capture/compare channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220

18.5 TIM2/TIM3/TIM5 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221

18.6 TIM2/TIM3/TIM5 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223

18.6.1 Control register 1 (TIMx_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223

18.6.2 Control register 2 (TIM5_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224

18.6.3 Slave mode control register (TIM5_SMCR) . . . . . . . . . . . . . . . . . . . . . 225

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18.6.4 Interrupt enable register (TIMx_IER) . . . . . . . . . . . . . . . . . . . . . . . . . . 226

18.6.5 Status register 1 (TIMx_SR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227

18.6.6 Status register 2 (TIMx_SR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228

18.6.7 Event generation register (TIMx_EGR) . . . . . . . . . . . . . . . . . . . . . . . . 229

18.6.8 Capture/compare mode register 1 (TIMx_CCMR1) . . . . . . . . . . . . . . . 230

18.6.9 Capture/compare mode register 2 (TIMx_CCMR2) . . . . . . . . . . . . . . . 232

18.6.10 Capture/compare mode register 3 (TIMx_CCMR3) . . . . . . . . . . . . . . . 233

18.6.11 Capture/compare enable register 1 (TIMx_CCER1) . . . . . . . . . . . . . . 234

18.6.12 Capture/compare enable register 2 (TIMx_CCER2) . . . . . . . . . . . . . . 235

18.6.13 Counter high (TIMx_CNTRH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235

18.6.14 Counter low (TIMx_CNTRL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236

18.6.15 Prescaler register (TIMx_PSCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236

18.6.16 Auto-reload register high (TIMx_ARRH) . . . . . . . . . . . . . . . . . . . . . . . 236

18.6.17 Auto-reload register low (TIMx_ARRL) . . . . . . . . . . . . . . . . . . . . . . . . 237

18.6.18 Capture/compare register 1 high (TIMx_CCR1H) . . . . . . . . . . . . . . . . 237

18.6.19 Capture/compare register 1 low (TIMx_CCR1L) . . . . . . . . . . . . . . . . . 238

18.6.20 Capture/compare register 2 high (TIMx_CCR2H) . . . . . . . . . . . . . . . . 238

18.6.21 Capture/compare register 2 low (TIMx_CCR2L) . . . . . . . . . . . . . . . . . 238

18.6.22 Capture/compare register 3 high (TIMx_CCR3H) . . . . . . . . . . . . . . . . 239

18.6.23 Capture/compare register 3 low (TIMx_CCR3L) . . . . . . . . . . . . . . . . . 239

19 8-bit basic timer (TIM4, TIM6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243

19.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243

19.2 TIM4 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244

19.3 TIM6 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244

19.4 TIM4/TIM6 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244

19.5 TIM4/TIM6 clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244

19.6 TIM4/TIM6 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245

19.6.1 Control register 1 (TIMx_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245

19.6.2 Control register 2 (TIM6_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246

19.6.3 Slave mode control register (TIM6_SMCR) . . . . . . . . . . . . . . . . . . . . . 246

19.6.4 Interrupt enable register (TIMx_IER) . . . . . . . . . . . . . . . . . . . . . . . . . . 247

19.6.5 Status register 1 (TIMx_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248

19.6.6 Event generation register (TIMx_EGR) . . . . . . . . . . . . . . . . . . . . . . . . 248

19.6.7 Counter (TIMx_CNTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249

19.6.8 Prescaler register (TIMx_PSCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250

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19.6.9 Auto-reload register (TIMx_ARR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250

19.6.10 TIM4/TIM6 register map and reset values . . . . . . . . . . . . . . . . . . . . . . 251

20 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253

20.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253

20.2 SPI main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253

20.3 SPI functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254

20.3.1 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254

20.3.2 Configuring the SPI in slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258

20.3.3 Configuring the SPI master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258

20.3.4 Configuring the SPI for simplex communications . . . . . . . . . . . . . . . . 259

20.3.5 Data transmission and reception procedures . . . . . . . . . . . . . . . . . . . 259

20.3.6 CRC calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266

20.3.7 Status flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267

20.3.8 Disabling the SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268

20.3.9 Error flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269

20.3.10 SPI low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270

20.3.11 SPI interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271

20.4 SPI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271

20.4.1 SPI control register 1 (SPI_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271

20.4.2 SPI control register 2 (SPI_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272

20.4.3 SPI interrupt control register (SPI_ICR) . . . . . . . . . . . . . . . . . . . . . . . . 274

20.4.4 SPI status register (SPI_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275

20.4.5 SPI data register (SPI_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276

20.4.6 SPI CRC polynomial register (SPI_CRCPR) . . . . . . . . . . . . . . . . . . . . 276

20.4.7 SPI Rx CRC register (SPI_RXCRCR) . . . . . . . . . . . . . . . . . . . . . . . . . 276

20.4.8 SPI Tx CRC register (SPI_TXCRCR) . . . . . . . . . . . . . . . . . . . . . . . . . 277

20.5 SPI register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277

21 Inter-integrated circuit (I2C) interface . . . . . . . . . . . . . . . . . . . . . . . . . 278

21.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278

21.2 I

21.3 I

21.4 I

2

C main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278

2

C general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279

2

C functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281

21.4.1 I2C slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281

21.4.2 I

2

C master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283

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21.4.3 Error conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289

21.4.4 SDA/SCL line control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291

21.5 I2C low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291

21.6 I

21.7 I

2

C interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292

2

C registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293

21.7.1 Control register 1 (I2C_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293

21.7.2 Control register 2 (I2C_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294

21.7.3 Frequency register (I2C_FREQR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296

21.7.4 Own address register LSB (I2C_OARL) . . . . . . . . . . . . . . . . . . . . . . . 297

21.7.5 Own address register MSB (I2C_OARH) . . . . . . . . . . . . . . . . . . . . . . . 297

21.7.6 Data register (I2C_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298

21.7.7 Status register 1 (I2C_SR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298

21.7.8 Status register 2 (I2C_SR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300

21.7.9 Status register 3 (I2C_SR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301

21.7.10 Interrupt register (I2C_ITR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302

21.7.11 Clock control register low (I2C_CCRL) . . . . . . . . . . . . . . . . . . . . . . . . 303

21.7.12 Clock control register high (I2C_CCRH) . . . . . . . . . . . . . . . . . . . . . . . 304

21.7.13 TRISE register (I2C_TRISER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305

21.7.14 I

2

C register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306

22 Universal asynchronous receiver transmitter (UART) . . . . . . . . . . . . 307

22.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307

22.2 UART main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308

22.3 UART functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309

22.3.1 UART character description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313

22.3.2 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314

22.3.3 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317

22.3.4 High precision baud rate generator . . . . . . . . . . . . . . . . . . . . . . . . . . . 321

22.3.5 Clock deviation tolerance of the UART receiver . . . . . . . . . . . . . . . . . . 322

22.3.6 Parity control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323

22.3.7 Multi-processor communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324

22.3.8 LIN (local interconnection network) mode . . . . . . . . . . . . . . . . . . . . . . 325

22.3.9 UART synchronous communication . . . . . . . . . . . . . . . . . . . . . . . . . . . 326

22.3.10 Single wire half duplex communication . . . . . . . . . . . . . . . . . . . . . . . . 328

22.3.11 Smartcard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328

22.3.12 IrDA SIR ENDEC block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330

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22.4 LIN mode functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333

22.4.1 Master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333

22.4.2 Slave mode with automatic resynchronization disabled . . . . . . . . . . . 337

22.4.3 Slave mode with automatic resynchronization enabled . . . . . . . . . . . . 340

22.4.4 LIN mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345

22.5 UART low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346

22.6 UART interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346

22.7 UART registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348

22.7.1 Status register (UART_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348

22.7.2 Data register (UART_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350

22.7.3 Baud rate register 1 (UART_BRR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 350

22.7.4 Baud rate register 2 (UART_BRR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . 351

22.7.5 Control register 1 (UART_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351

22.7.6 Control register 2 (UART_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352

22.7.7 Control register 3 (UART_CR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354

22.7.8 Control register 4 (UART_CR4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355

22.7.9 Control register 5 (UART_CR5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356

22.7.10 Control register 6 (UART_CR6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357

22.7.11 Guard time register (UART_GTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358

22.7.12 Prescaler register (UART_PSCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359

22.7.13 UART register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . 360

23 Controller area network (beCAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362

23.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362

23.2 beCAN main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362

23.3 beCAN general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363

23.3.1 CAN 2.0B active core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363

23.3.2 Control, status and configuration registers . . . . . . . . . . . . . . . . . . . . . 363

23.3.3 Tx mailboxes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364

23.3.4 Acceptance filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364

23.4 Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365

23.4.1 Initialization mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365

23.4.3 Sleep mode (low power) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366

23.4.4 Time triggered communication mode . . . . . . . . . . . . . . . . . . . . . . . . . 366

23.5 Test modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367

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23.4.2 Normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366

Contents RM0016

23.5.1 Silent mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367

23.5.2 Loop back mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367

23.5.3 Loop back combined with silent mode . . . . . . . . . . . . . . . . . . . . . . . . . 368

23.6 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368

23.6.1 Transmission handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368

23.6.2 Reception handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371

23.6.3 Identifier filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372

23.6.4 Message storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378

23.6.5 Error management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380

23.6.6 Bit timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381

23.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383

23.8 Register access protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384

23.9 Clock system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384

23.10 beCAN low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384

23.11 beCAN registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385

23.11.1 CAN master control register (CAN_MCR) . . . . . . . . . . . . . . . . . . . . . . 385

23.11.2 CAN master status register (CAN_MSR) . . . . . . . . . . . . . . . . . . . . . . . 386

23.11.3 CAN transmit status register (CAN_TSR) . . . . . . . . . . . . . . . . . . . . . . 387

23.11.4 CAN transmit priority register (CAN_TPR) . . . . . . . . . . . . . . . . . . . . . 388

23.11.5 CAN receive FIFO register (CAN_RFR) . . . . . . . . . . . . . . . . . . . . . . . 389

23.11.6 CAN interrupt enable register (CAN_IER) . . . . . . . . . . . . . . . . . . . . . . 390

23.11.7 CAN diagnostic register (CAN_DGR) . . . . . . . . . . . . . . . . . . . . . . . . . 391

23.11.8 CAN page select register (CAN_PSR) . . . . . . . . . . . . . . . . . . . . . . . . 391

23.11.9 CAN error status register (CAN_ESR) . . . . . . . . . . . . . . . . . . . . . . . . . 392

23.11.10 CAN error interrupt enable register (CAN_EIER) . . . . . . . . . . . . . . . . 393

23.11.11 CAN transmit error counter register (CAN_TECR) . . . . . . . . . . . . . . . 393

23.11.12 CAN receive error counter register (CAN_RECR) . . . . . . . . . . . . . . . . 394

23.11.13 CAN bit timing register 1 (CAN_BTR1) . . . . . . . . . . . . . . . . . . . . . . . . 394

23.11.14 CAN bit timing register 2 (CAN_BTR2) . . . . . . . . . . . . . . . . . . . . . . . . 395

23.11.15 Mailbox registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 396

23.11.16 CAN filter registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401

23.12 CAN register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407

23.12.1 Page mapping for CAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 408

24 Analog/digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411

24.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411

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24.2 ADC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411

24.3 ADC extended features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411

24.4 ADC pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414

24.5 ADC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414

24.5.1 ADC on-off control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414

24.5.2 ADC clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414

24.5.3 Channel selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415

24.5.4 Conversion modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415

24.5.5 Overrun flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416

24.5.6 Analog watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417

24.5.7 Conversion on external trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418

24.5.8 Analog zooming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418

24.5.9 Timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418

24.6 ADC low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 420

24.7 ADC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 420

24.8 Data alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423

24.9 Reading the conversion result . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423

24.10 Schmitt trigger disable registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 424

24.11 ADC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425

24.11.1 ADC data buffer register x high (ADC_DBxRH) (x=0..7 or 0..9 ) . . . . . 425

24.11.2 ADC data buffer register x low (ADC_DBxRL) (x=or 0..7 or 0..9) . . . . 426

24.11.3 ADC control/status register (ADC_CSR) . . . . . . . . . . . . . . . . . . . . . . . 427

24.11.4 ADC configuration register 1 (ADC_CR1) . . . . . . . . . . . . . . . . . . . . . . 428

24.11.5 ADC configuration register 2 (ADC_CR2) . . . . . . . . . . . . . . . . . . . . . . 429

24.11.6 ADC configuration register 3 (ADC_CR3) . . . . . . . . . . . . . . . . . . . . . . 430

24.11.7 ADC data register high (ADC_DRH) . . . . . . . . . . . . . . . . . . . . . . . . . . 431

24.11.8 ADC data register low (ADC_DRL) . . . . . . . . . . . . . . . . . . . . . . . . . . . 431

24.11.9 ADC Schmitt trigger disable register high (ADC_TDRH) . . . . . . . . . . . 432

24.11.10 ADC Schmitt trigger disable register low (ADC_TDRL) . . . . . . . . . . . . 432

24.11.11 ADC high threshold register high (ADC_HTRH) . . . . . . . . . . . . . . . . . 433

24.11.12 ADC high threshold register low (ADC_HTRL) . . . . . . . . . . . . . . . . . . 433

24.11.13 ADC low threshold register high (ADC_LTRH) . . . . . . . . . . . . . . . . . . 434

24.11.14 ADC low threshold register low (ADC_LTRL) . . . . . . . . . . . . . . . . . . . 434

24.11.15 ADC watchdog status register high (ADC_AWSRH) . . . . . . . . . . . . . . 435

24.11.16 ADC watchdog status register low (ADC_AWSRL) . . . . . . . . . . . . . . . 435

24.11.17 ADC watchdog control register high (ADC_AWCRH) . . . . . . . . . . . . . 436

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Contents RM0016

24.11.18 ADC watchdog control register low (ADC_AWCRL) . . . . . . . . . . . . . . 436

24.12 ADC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437

25 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439

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RM0016 List of tables

List of tables

Table 1. Interrupt levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 2. CPU register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 3. CFG_GCR register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 4. List of abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 5. Block size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Table 6. Memory access versus programming method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Table 7. Flash register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Table 8. Software priority levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Table 9. Interrupt enabling/disabling inside an ISR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Table 10. Vector address map versus software priority bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Table 11. Dedicated interrupt instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Table 12. Interrupt register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Table 13. RST register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Table 14. Devices with 4 trimming bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Table 15. Devices with 3 trimming bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Table 16. CLK interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Table 17. Peripheral clock gating bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Table 18. Peripheral clock gating bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Table 19. CLK register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

Table 20. Low power mode management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Table 21. I/O port configuration summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Table 22. Effect of low power modes on GPIO ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

Table 23. Recommended and non-recommended configurations for analog input . . . . . . . . . . . . . 109

Table 24. GPIO register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

Table 25. Time base calculation table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

Table 26. AWU register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

Table 27. Beeper register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

Table 28. Watchdog timeout period (LSI clock frequency = 128 kHz) . . . . . . . . . . . . . . . . . . . . . . . 123

Table 29. IWDG register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

Table 30. Window watchdog timing example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

Table 31. Effect of low power modes on WWDG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

Table 32. WWDG register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

Table 33. Timer characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

Table 34. Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

Table 35. Glossary of internal timer signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

Table 36. Explanation of indices‘i’, ‘n’, and ‘x’ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

Table 37. Counting direction versus encoder signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182

Table 38. Output control for complementary OCi and OCiN channels with break feature . . . . . . . . 202

Table 39. TIM1 register map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214

Table 40. TIM2 register map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239

Table 41. TIM3 register map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241

Table 42. TIM5 register map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241

Table 43. TIM4 register map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251

Table 44. TIM6 register map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251

Table 45. SPI behavior in low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270

Table 46. SPI interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271

Table 47. SPI register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277

Table 48. I

2

C interface behavior in low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291

Doc ID 14587 Rev 8 17/449

List of tables RM0016

Table 49. I2C Interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292

Table 50. I2C_CCR values for SCL frequency table (fMASTER = 10 MHz or 16 MHz). . . . . . . . . . 305

Table 51. I

2

C register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306

Table 52. UART configurations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307

Table 53. Noise detection from sampled data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320

Table 54. Baud rate programming and error calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322

Table 55. UART receiver tolerance when UART_DIV[3:0] is zero . . . . . . . . . . . . . . . . . . . . . . . . . . 322

Table 56. UART receiver’s tolerance when UART_DIV[3:0] is different from zero. . . . . . . . . . . . . . 323

Table 57. Frame format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323

Table 58. LIN mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345

Table 59. UART interface behavior in low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346

Table 60. UART interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346

Table 61. UART1 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360

Table 62. UART2 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360

Table 63. UART3 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361

Table 64. Example of filter numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376

Table 65. Transmit mailbox mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378

Table 66. Receive mailbox mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379

Table 67. beCAN behavior in low power modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384

Table 68. beCAN control and status page - register map and reset values . . . . . . . . . . . . . . . . . . . 409

Table 69. beCAN mailbox pages - register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . 409

Table 70. beCAN filter configuration page - register map and reset values . . . . . . . . . . . . . . . . . . . 410

Table 72. Low power modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 420

Table 73. ADC Interrupts in single and non-buffered continuous mode (ADC1 and ADC2). . . . . . . 420

Table 74. ADC interrupts in buffered continuous mode (ADC1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421

Table 75. ADC interrupts in scan mode (ADC1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 422

Table 76. ADC1 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437

Table 77. ADC2 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 438

Table 78. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439

18/449 Doc ID 14587 Rev 8

RM0016 List of figures

List of figures

Figure 1. Programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 2. Stacking order. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 3. Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 4. Default stack model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Figure 5. Customized stack model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Figure 6. Flash memory and data EEPROM organization on low density STM8S . . . . . . . . . . . . . . 38

Figure 7. Flash memory and data EEPROM organization on medium density STM8S and STM8A. 39

Figure 8. Flash memory and data EEPROM organization high density STM8S and STM8A . . . . . . 40

Figure 9. UBC area size definition on low density STM8S devices . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Figure 10. UBC area size definition on medium density STM8S

and STM8A with up to 32 Kbytes of Flash program memory . . . . . . . . . . . . . . . . . . . . . . . 42

Figure 11. UBC area size definition on high density STM8S and

STM8A with up to 128 Kbytes of Flash program memory . . . . . . . . . . . . . . . . . . . . . . . . . 43

Figure 12. SWIM pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Figure 13. Interrupt processing flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Figure 14. Priority decision process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Figure 15. Concurrent interrupt management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Figure 16. Nested interrupt management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Figure 17. Power supply overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Figure 18. Reset circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Figure 19. VDD/VDDIO voltage detection: POR/BOR threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Figure 20. Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Figure 21. HSE clock sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Figure 22. Clock switching flowchart (automatic mode example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Figure 23. Clock switching flowchart (manual mode example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Figure 24. GPIO block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

Figure 25. AWU block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

Figure 26. Beep block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

Figure 27. Independent watchdog (IWDG) block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

Figure 28. Watchdog block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

Figure 29. Approximate timeout duration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

Figure 30. Window watchdog timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

Figure 31. TIM1 general block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

Figure 32. Time base unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

Figure 33. 16-bit read sequence for the counter (TIM1_CNTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

Figure 34. Counter in up-counting mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

Figure 35. Counter update when ARPE = 0 (ARR not preloaded) with prescaler = 2 . . . . . . . . . . . . 142

Figure 36. Counter update event when ARPE = 1 (TIM1_ARR preloaded). . . . . . . . . . . . . . . . . . . . 142

Figure 37. Counter in down-counting mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

Figure 38. Counter update when ARPE = 0 (ARR not preloaded) with prescaler = 2 . . . . . . . . . . . . 144

Figure 39. Counter update when ARPE = 1 (ARR preloaded), with prescaler = 1 . . . . . . . . . . . . . . 144

Figure 40. Counter in center-aligned mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

Figure 41. Counter timing diagram, f

Figure 42. Update rate examples depending on mode and TIM1_RCR register settings . . . . . . . . . 148

Figure 43. Clock/trigger controller block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

CK_CNT

Figure 44. Control circuit in normal mode, f

Figure 45. TI2 external clock connection example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

Figure 46. Control circuit in external clock mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

= f

CK_PSC

CK_PSC

, TIM1_ARR = 06h, ARPE = 1 . . . . . . . . . . . 146

= f

MASTER

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

Doc ID 14587 Rev 8 19/449

List of figures RM0016

Figure 47. External trigger input block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

Figure 48. Control circuit in external clock mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

Figure 49. Control circuit in trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

Figure 50. Control circuit in trigger reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

Figure 51. Control circuit in trigger gated mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

Figure 52. Control circuit in external clock mode 2 + trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . 156

Figure 53. Timer chaining system implementation example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

Figure 54. Trigger/master mode selection blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

Figure 55. Master/slave timer example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

Figure 56. Gating timer B with OC1REF of timer A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

Figure 57. Gating timer B with the counter enable signal of timer A (CNT_EN) . . . . . . . . . . . . . . . . 160

Figure 58. Triggering timer B with the UEV of timer A (TIMERA-UEV) . . . . . . . . . . . . . . . . . . . . . . . 161

Figure 59. Triggering timer B with counter enable CNT_EN of timer A . . . . . . . . . . . . . . . . . . . . . . 162

Figure 60. Triggering Timer A and B with Timer A TI1 input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

Figure 61. Capture/compare channel 1 main circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

Figure 62. 16-bit read sequence for the TIM1_CCRi register in capture mode . . . . . . . . . . . . . . . . . 164

Figure 63. Channel input stage block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

Figure 64. Input stage of TIM 1 channel 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

Figure 65. PWM input signal measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

Figure 66. PWM input signal measurement example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

Figure 67. Channel output stage block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

Figure 68. Detailed output stage of channel with complementary output (channel 1) . . . . . . . . . . . . 169

Figure 69. Output compare mode, toggle on OC1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

Figure 70. Edge-aligned counting mode PWM mode 1 waveforms (ARR = 8) . . . . . . . . . . . . . . . . . 172

Figure 71. Center-aligned PWM waveforms (ARR = 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

Figure 72. Example of one-pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174

Figure 73. Complementary output with deadtime insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

Figure 74. Deadtime waveforms with a delay greater than the negative pulse . . . . . . . . . . . . . . . . . 176

Figure 75. Deadtime waveforms with a delay greater than the positive pulse . . . . . . . . . . . . . . . . . . 176

Figure 76. Six-step generation, COM example (OSSR = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178

Figure 77. Behavior of outputs in response to a break (channel without complementary output) . . . 179

Figure 78. Behavior of outputs in response to a break (TIM1 complementary outputs) . . . . . . . . . . 180

Figure 79. ETR activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181

Figure 80. Example of counter operation in encoder interface mode . . . . . . . . . . . . . . . . . . . . . . . . 183

Figure 81. Example of encoder interface mode with IC1 polarity inverted. . . . . . . . . . . . . . . . . . . . . 183

Figure 82. TIM2/TIM3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217

Figure 83. TIM5 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218

Figure 84. Time base unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218

Figure 85. Input stage block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220

Figure 86. Input stage of TIM 2 channel 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220

Figure 87. Output stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221

Figure 88. Output stage of channel 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221

Figure 89. TIM4 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243

Figure 90. TIM6 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243

Figure 91. SPI block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254

Figure 92. Single master/ single slave application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255

Figure 93. Data clock timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257

Figure 94. TXE/RXNE/BSY behavior in full duplex mode (RXONLY = 0).

Case of continuous transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262

Figure 95. TXE/RXNE/BSY behavior in slave / full duplex mode

(BDM = 0, RXONLY = 0). Case of continuous transfers. . . . . . . . . . . . . . . . . . . . . . . . . . 262

Figure 96. TXE/BSY in master transmit-only mode

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RM0016 List of figures

(BDM = 0 and RXONLY = 0). Case of continuous transfers. . . . . . . . . . . . . . . . . . . . . . . 263

Figure 97. TXE/BSY in slave transmit-only mode (BDM = 0 and RXONLY = 0).

Case of continuous transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264

Figure 98. RXNE behavior in receive-only mode (BDM = 0 and RXONLY = 1).

Case of continuous transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265

Figure 99. TXE/BSY behavior when transmitting (BDM = 0 and RXLONY = 0).

Case of discontinuous transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266

Figure 100. I
Figure 101. I

2

C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279

2

C block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280

Figure 102. Transfer sequence diagram for slave transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282

Figure 103. Transfer sequence diagram for slave receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283

Figure 104. Transfer sequence diagram for master transmitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285

Figure 105. Method 1: transfer sequence diagram for master receiver . . . . . . . . . . . . . . . . . . . . . . . . 286

Figure 106. Method 2: transfer sequence diagram for master receiver when N >2 . . . . . . . . . . . . . . . 287

Figure 107. Method 2: transfer sequence diagram for master receiver when N=2 . . . . . . . . . . . . . . . 288

Figure 108. Method 2: transfer sequence diagram for master receiver when N=1 . . . . . . . . . . . . . . . 289

Figure 109. I2C interrupt mapping diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292

Figure 110. UART1 block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310

Figure 111. UART2 block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311

Figure 112. UART3 block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312

Figure 113. Word length programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313

Figure 114. Configurable stop bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315

Figure 115. TC/TXE behavior when transmitting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316

Figure 116. Start bit detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317

Figure 117. Data sampling for noise detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319

Figure 118. How to code UART_DIV in the BRR registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321

Figure 119. Mute mode using idle line detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324

Figure 120. Mute mode using Address mark detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325

Figure 121. UART example of synchronous transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327

Figure 122. UART data clock timing diagram (M=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327

Figure 123. UART data clock timing diagram (M=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327

Figure 124. RX data setup/hold time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328

Figure 125. ISO 7816-3 asynchronous protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329

Figure 126. Parity error detection using 1.5 stop bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330

Figure 127. IrDA SIR ENDEC- block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332

Figure 128. IrDA data modulation (3/16) - normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332

Figure 129. Break detection in LIN mode (11-bit break length - LBDL bit is set) . . . . . . . . . . . . . . . . . 335

Figure 130. Break detection in LIN mode vs framing error detection. . . . . . . . . . . . . . . . . . . . . . . . . . 336

Figure 131. LIN identifier field parity bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338

Figure 132. LIN identifier field parity check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338

Figure 133. LIN header reception time-out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339

Figure 134. LIN synch field measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341

Figure 135. UARTDIV read / write operations when LDUM = 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341

Figure 136. UARTDIV read / write operations when LDUM = 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342

Figure 137. Bit sampling in reception mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345

Figure 138. UART interrupt mapping diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347

Figure 139. CAN network topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363

Figure 140. beCAN block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364

Figure 141. beCAN operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365

Figure 142. beCAN in silent mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367

Figure 143. beCAN in loop back mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367

Figure 144. beCAN in combined mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368

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List of figures RM0016

Figure 145. Transmit mailbox states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370

Figure 146. Receive FIFO states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371

Figure 147. 32-bit filter bank configuration (FSCx bits = 0b11 in CAN_FCRx register) . . . . . . . . . . . . 374

Figure 148. 16-bit filter bank configuration (FSCx bits = 0b10 in CAN_FCRx register) . . . . . . . . . . . . 374

Figure 149. 16/8-bit filter bank configuration (FSCx bits = 0b01 in CAN_FCRx register) . . . . . . . . . . 375

Figure 150. 8-bit filter bank configuration (FSCx bits = 0b00 in CAN_FCRx register) . . . . . . . . . . . . . 375

Figure 151. Filter banks configured as in the example in Table 64. . . . . . . . . . . . . . . . . . . . . . . . . . . 377

Figure 152. CAN error state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380

Figure 153. Bit timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381

Figure 154. CAN frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382

Figure 155. Event flags and interrupt generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383

Figure 156. CAN register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407

Figure 157. CAN page mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 408

Figure 158. ADC1 block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412

Figure 159. ADC2 block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 413

Figure 160. Analog watchdog guarded area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417

Figure 161. Timing diagram in single mode (CONT = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 419

Figure 162. Timing diagram in continuous mode (CONT = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 419

Figure 163. Right alignment of data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423

Figure 164. Left alignment of data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423

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RM0016 Central processing unit (CPU)

1 Central processing unit (CPU)

1.1 Introduction

The CPU has an 8-bit architecture. Six internal registers allow efficient data manipulations.
The CPU is able to execute 80 basic instructions. It features 20 addressing modes and can
address six internal registers. For the complete description of the instruction set, refer to the
STM8 microcontroller family programming manual (PM0044).

1.2 CPU registers

The six CPU registers are shown in the programming model in Figure 1. Following an
interrupt, the registers are pushed onto the stack in the order shown in Figure 2. They are
popped from stack in the reverse order. The interrupt routine must therefore handle it, if
needed, through the POP and PUSH instructions.

1.2.1 Description of CPU registers

Accumulator (A)

The accumulator is an 8-bit general purpose register used to hold operands and the results
of the arithmetic and logic calculations as well as data manipulations.

Index registers (X and Y)

These are 16-bit registers used to create effective addresses. They may also be used as a
temporary storage area for data manipulations and have an inherent use for some
instructions (multiplication/division). In most cases, the cross assembler generates a
PRECODE instruction (PRE) to indicate that the following instruction refers to the Y register.

Program counter (PC)

The program counter is a 24-bit register used to store the address of the next instruction to
be executed by the CPU. It is automatically refreshed after each processed instruction. As a
result, the STM8 core can access up to 16 Mbytes of memory.

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Central processing unit (CPU) RM0016

07

A ACCUMULATOR

07815

SP STACK POINTER

SH S

X INDEX

Y INDEX

07815

PC PROGRAM COUNTER

PCH PCL

07

CC CODE CONDITION

VI1HI0NZC

1623

PCE

07815

XH XL

07815

XH XL

0

Figure 1. Programming model

Stack pointer (SP)

The stack pointer is a 16-bit register. It contains the address of the next free location of the
stack. Depending on the product, the most significant bits can be forced to a preset value.

The stack is used to save the CPU context on subroutine calls or interrupts. The user can
also directly use it through the POP and PUSH instructions.

The stack pointer can be initialized by the startup function provided with the C compiler. For
applications written in C language, the initialization is then performed according to the
address specified in the linker file for C users. If you use your own linker file or startup file,
make sure the stack pointer is initialized properly (with the address given in the datasheets).
For applications written in assembler, you can use either the startup function provided by ST
or write your own by initializing the stack pointer with the correct address.

The stack pointer is decremented after data has been pushed onto the stack and
incremented after data is popped from the stack. It is up to the application to ensure that the
lower limit is not exceeded.

A subroutine call occupies two or three locations. An interrupt occupies nine locations to
store all the internal registers (except SP). For more details refer to Figure 2.

Note: The WFI/HALT instructions save the context in advance. If an interrupt occurs while the CPU

is in one of these modes, the latency is reduced.

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RM0016 Central processing unit (CPU)

JUMP TO INTERRUPT ROUTINE GIVEN BY THE INTERRUPT VECTOR

INTERRUPT GENERATION (execute pipeline)

YH

YL

PCE

PCL

CC

STACK
(PUSH)

UNSTACK

INTERRUPT

RETURN

PCH

JUMP TO THE ADDRESS GIVEN BY PROGRAM COUNTER (Reload Pipeline)

IRET INSTRUCTION

(POP)

9 CPU CYCLES

9 CPU CYCLES

POP PCL

POP PCH

POP PCE

POP Y

POP X

POP A

POP CC

A

XH

XL

PUSH PCL
PUSH PCH
PUSH PCE

PUSH Y
PUSH X
PUSH A

PUSH CC

Complete instruction in execute stage (1-6 cycles latency)

Figure 2. Stacking order

Condition code register (CC)

The condition code register is an 8-bit register which indicates the result of the instruction
just executed as well as the state of the processor. The 6th bit (MSB) of this register is
reserved. These bits can be individually tested by a program and specified action taken as a
result of their state. The following paragraphs describe each bit:

● V: Overflow

When set, V indicates that an overflow occurred during the last signed arithmetic operation,
on the MSB result bit. See the INC, INCW, DEC, DECW, NEG, NEGW, ADD, ADDW, ADC,
SUB, SUBW, SBC, CP, and CPW instructions.

● I1: Interrupt mask level 1

The I1 flag works in conjunction with the I0 flag to define the current interruptability level as
shown in Ta bl e 1 . These flags can be set and cleared by software through the RIM, SIM,
HALT, WFI, IRET, TRAP, and POP instructions and are automatically set by hardware when
entering an interrupt service routine.

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Central processing unit (CPU) RM0016

Table 1. Interrupt levels

Interruptability Priority I1 I0

Interruptable main

Lowest

10

Interruptable level 1 0 1

Interruptable level 2 0 0

Non interruptable 1 1

● H: Half carry bit

Highest

The H bit is set to 1 when a carry occurs between the bits 3 and 4 of the ALU during an ADD
or ADC instruction. The H bit is useful in BCD arithmetic subroutines.

● I0: Interrupt mask level 0

See Flag I1.

● N: Negative

When set to 1, this bit indicates that the result of the last arithmetic, logical or data
manipulation is negative (i.e. the most significant bit is a logic 1).

● Z: Zero

When set to 1, this bit indicates that the result of the last arithmetic, logical or data
manipulation is zero.

● C: Carry

When set, C indicates that a carry or borrow out of the ALU occurred during the last
arithmetic operation on the MSB operation result bit. This bit is also affected during bit test,
branch, shift, rotate and load instructions. See the ADD, ADC, SUB, and SBC instructions.

In a division operation, C indicates if trouble occurred during execution (quotient overflow or
zero division). See the DIV instruction.

In bit test operations, C is the copy of the tested bit. See the BTJF and BTJT instructions.
In shift and rotate operations, the carry is updated. See the RRC, RLC, SRL, SLL, and SRA
instructions.

This bit can be set, reset or complemented by software using the SCF, RCF, and CCF
instructions.

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RM0016 Central processing unit (CPU)

Example: Addition

$B5 + $94 = "C" + $49 = $149

C7 0

0 10110101

C7 0

+0 10010100

C7 0

=1 01001001

1.2.2 STM8 CPU register map

The CPU registers are mapped in the STM8 address space as shown inTa bl e 2 . These
registers can only be accessed by the debug module but not by memory access instructions
executed in the core.

Table 2. CPU register map

Address

offset

Register name765432 1 0

0x00 A MSB----- -LSB

0x01 PCE MSB -

-

--- -LSB

0x02 PCH MSB----- -LSB

0x03 PCL MSB----- -LSB

0x04 XH MSB----- -LSB

0x05 XL MSB----- -LSB

0x06 YH MSB----- -LSB

0x07 YL MSB----- -LSB

0x08 SPH MSB----- -LSB

0x09 SPL MSB----- -LSB

0x0A CC V 0 I1 H I0 N Z C

1.3 Global configuration register (CFG_GCR)

1.3.1 Activation level

The MCU activation level is configured by programming the AL bit in the CFG_GCR register.

For information on the use of this bit refer to Section 6.4: Activation level/low power mode

control on page 62.

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Central processing unit (CPU) RM0016

1.3.2 SWIM disable

By default, after an MCU reset, the SWIM pin is configured to allow communication with an
external tool for debugging or Flash/EEPROM programming. This pin can be configured by
the application for use as a general purpose I/O. This is done by setting the SWD bit in the
CFG_GCR register.

1.3.3 Description of global configuration register (CFG_GCR)

Address offset: 0x00
Reset value: 0x00

76543210

Reserved

Bits 7:2 Reserved

Bit 1 AL: Activation level

This bit is set and cleared by software. It configures main or interrupt-only activation.
0: Main activation level. An IRET instruction causes the context to be retrieved from the stack and

the main program continues after the WFI instruction.
1: Interrupt-only activation level. An IRET instruction causes the CPU to go back to WFI/Halt mode
without restoring the context.

Bit 0 SWD: SWIM disable

0: SWIM mode enabled
1: SWIM mode disabled

When SWIM mode is enabled, the SWIM pin cannot be used as general purpose I/O.

AL SWD

rw rw

1.3.4 Global configuration register map and reset values

The CFG_GCR is mapped in the STM8 address space. Refer to the corresponding
datasheets for the base address.

Table 3. CFG_GCR register map

Address

offset

0x00

Register name765432 1 0

CFG_GCR

Reset value

-

0

-

0

-

0

-

0

-

0

-

0

AL

SWD

0

0

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RM0016 Boot ROM

2 Boot ROM

The internal 2 Kbyte boot ROM (available in some devices) contains the bootloader code. Its
main tasks are to download the application program to the internal Flash/EEPROM through
the SPI, CAN, or UART interface, and to program the code, data, option bytes and interrupt
vectors in internal Flash/EEPROM.

To perform bootlloading in LIN mode, a different bootloader communication protocol is
implemented on UART2/UART3 and UART1.

The boot loader starts executing after reset. Refer to the STM8 bootloader user manual
(UM0560) for more details.

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Memory and register map RM0016

00 000h

RAM upper limit

Data EEPROM lower limit

Data EEPROM upper limit

00 4800h

00 5000h

00 6000h

00 6800h

00 7F00h

00 8000h

00 8080h

RAM

Stack

Reserved

Data EEPROM

Reserved

Option bytes

Reserved

HW registers

Reserved

Boot ROM (optional)

Reserved

Registers for CPU, SWIM, ITC, DM

Interrupt vectors

Program EEPROM

Program memory upper limit

ai 18468

Option bytes upper limit

HW registers upper limit

3 Memory and register map

For details on the memory map, I/O port hardware register map and CPU/SWIM/debug
module/interrupt controller registers, refer to the product datasheets.

3.1 Memory layout

3.1.1 Memory map

Figure 3. Memory map

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The RAM upper limit, data EEPROM upper and lower limit, Option Byte upper limit,
hardware (HW) registers upper limit, and the program memory upper limit are specific to the
device configuration. Please refer to the datasheets for quantitative information.

RM0016 Memory and register map

ai15055

Default stack model

End address

Stack roll-over limit

(1)

Stack pointer initialization value

Start address

RAM

3.1.2 Stack handling

Default stack model

The stack of the STM8S and STM8A microcontrollers is implemented in the user RAM area.
The default stack model is shown in Figure 4.

Figure 4. Default stack model

1. The stack roll-over limit is not implemented on all devices. Refer to the datasheets for detailed information.

Stack pointer initialization value

This is the default value of the stack pointer. The user must take care to initialize this pointer.
Correct loading of this pointer is usually performed by the initialization code generated by
the development tools (linker file). In the default stack model this pointer is initialized to the
RAM end address.

Stack roll-over limit

In some devices, a stack roll-over limit is implemented at a fixed address. If the stack pointer
is decreased below the stack roll-over limit, using a push operation or during context saving
for subroutines or interrupt routines, it is reset to the RAM end address. The stack pointer
does not roll over if stack pointer arithmetic is used.

Such behavior of the stack pointer is of particular importance when developing software on
a device with a different memory configuration than the target device.

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Memory and register map RM0016

ai15056

Customized stack model

End address

Stack roll-over limit

(1)

Stack pointer initialization value

Start address

RAM

Optional guard cells

(2)

Flexible stack size

Customized stack model

STM8S and STM8A stack pointer handling allows a customized stack model to be
implemented. This permits a flexible stack size without restrictions due to the stack roll-over
limit. Implementing the customized stack also benefits portability of the software on products
with different memory configurations. Figure 5 shows the customized stack model.

Figure 5. Customized stack model

1. The stack roll-over limit is not implemented on all devices.

2. The guard cells are RAM locations that have to be continuously polled by the application program to detect
whether a stack overflow has taken place.

In this stack model, the initial stack pointer must be placed beyond the stack roll-over limit.
Consequently, the growing stack never reaches the stack roll-over limit. It is clear that in this
implementation the stack size is not limited by the roll-over mechanism. Nevertheless, the
user has to define the stack position and stack size in the link file, and he has to ensure that
the stack pointer does not exceed the defined stack area (stack overflow or under-run).

The RAM locations above and below the customized stack can be regularly used as RAM to
store variables or other information.

Guard cells can be implemented at the lower end of the stack to detect if the stack pointer
exceeds the defined limit. These cells are standard RAM locations, initialized with fixed
values that the stack overwrites if an overflow occurs. The user software can regularly poll
these cells, detect the overflow condition, and put the application in a fail safe state.

During the software validation phase hardware breakpoints can be set at both limits of the
stack to validate that neither a stack overflow nor an under-run happens.

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RM0016 Memory and register map

3.2 Register description abbreviations

In the register descriptions of each chapter in this reference manual, the following
abbreviations are used:

Table 4. List of abbreviations

Abbreviation Description

read/write (rw) Software can read and write to these bits.

read-only (r) Software can only read these bits.

write only (w)

read/write once (rwo)

read/clear (rc_w1)

read/clear (rc_w0)

Software can only write to this bit. Reading the bit returns a meaningless
value.

Software can only write once to this bit but can read it at any time. Only a
reset can return this bit to its reset value.

Software can read and clear this bit by writing 1. Writing ‘0’ has no effect on
the bit value.

Software can read and clear this bit by writing 0. Writing ‘1’ has no effect on
the bit value.

read/set (rs) Software can read and set this bit. Writing ‘0’ has no effect on the bit value.

read/clear by read
(rc_r)

Software can read this bit. Reading this bit automatically clears it to ‘0’.
Writing ‘0’ has no effect on the bit value.

Reserved (Res.) Reserved bit, must be kept at reset value.

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4 Flash program memory and data EEPROM

4.1 Introduction

The embedded Flash program memory and data EEPROM memories are controlled by a
common set of registers. Using these registers, the application can program or erase
memory contents and set write protection, or configure specific low power modes. The
application can also program the device option bytes.

4.2 Glossary

● Block

A block is a set of bytes that can be programmed or erased in one single programming
operation. Operations that are performed at block level are faster than standard
programming and erasing. Refer to Tab le 5 for the details on block size.

● Page

A page is a set of blocks.
A dedicated option byte can be used to configure, by increments of one page, the size

of the user boot code.

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4.3 Main Flash memory features

● STM8S and STM8A EEPROM is divided into two memory areas

– Up to 128 Kbytes of Flash program memory. The density differs according to the

device. Refer to Section 4.4: Memory organization for details

– Up to 2 Kbytes of data EEPROM including option bytes. Data EEPROM density

differs according to the device. Refer to Section 4.4: Memory organization for
details.

● Programming modes

– Byte programming and automatic fast byte programming (without erase operation)
– Word programming
– Block programming and fast block programming mode (without erase operation)
– Interrupt generation on end of program/erase operation and on illegal program

operation.

● Read-while-write capability (RWW). This feature is not available on all devices. Refer to

the datasheets for details

● In-application programming (IAP) and in-circuit programming (ICP) capabilities

● Protection features

– Memory readout protection (ROP)
– Program memory write protection with memory access security system (MASS

keys)
– Data memory write protection with memory access security system (MASS keys)
– Programmable write protected user boot code area (UBC).

● Memory state configurable to operating or power-down (I

modes

) in Halt and Active-halt

DDQ

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4.4 Memory organization

4.4.1 STM8S and STM8A memory organization

STM8S and STM8A EEPROM is organized in 32-bit words (4 bytes per word).

The memory organization differs according to the devices:

● Low density STM8S devices

– 8 Kbytes of Flash program memory organized in 128 pages or blocks of 64 bytes

each. The Flash program memory is divided into 2 areas, the user boot code area

(UBC), which size can be configured by option byte, and the main program

memory area. The Flash program memory is mapped in the upper part of the

STM8S addressing space and includes the reset and interrupt vectors.
– Up to 640 bytes of data EEPROM (DATA) organized in pages or blocks of 64 bytes

each. One block (64 bytes) contains the option bytes of which 11 are used to

configure the device hardware features. The options bytes can be programmed in

user, IAP and ICP/SWIM modes.

● Medium density STM8S devices

– From 16 to 32 Kbytes of Flash program memory organized in up to 64 pages of 4

blocks of 128 bytes each. The Flash program memory is divided into 2 areas, the

user boot code area (UBC), which size can be configured by option byte, and the

main program memory area. The Flash program memory is mapped in the upper

part of the STM8S addressing space and includes the reset and interrupt vectors.
– Up to 1 Kbyte of data EEPROM (DATA) organized in up to 2 pages of 4 blocks of

128 bytes each. One block (128 bytes) contains the option bytes of which 13 are

used to configure the device hardware features. The options bytes can be

programmed in user, IAP and ICP/SWIM modes.

● Medium density STM8A devices

– From 8 to 32 Kbytes of Flash program memory organized in up to 64 pages of 4

blocks of 128 bytes each. The Flash program memory is divided into 2 areas, the

user boot code area (UBC), which size can be configured by option byte, and the

main program memory area. The Flash program memory is mapped in the upper

part of the STM8A addressing space and includes the reset and interrupt vectors.
– Up to 1 Kbyte of data EEPROM (DATA) organized in up to 2 pages of 4 blocks of

128 bytes each. One block (128 bytes) contains the option bytes of which 13 are

used to configure the device hardware features. The options bytes can be

programmed in user, IAP and ICP/SWIM modes.

● High density STM8S devices

– From 32 to 128 Kbytes of Flash program memory organized in up to 256 pages of

4 blocks of 128 bytes each. The Flash program memory is divided into 2 areas, the

user boot code area (UBC), which size can be configured by option byte, and the

main program memory area. The Flash program memory is mapped in the upper

part of the STM8S addressing space and includes the reset and interrupt vectors.
– Up to 2 Kbytes of data EEPROM (DATA) organized in up to 4 pages of 4 blocks of

128 bytes each. The size of the DATA area is fixed for a given microcontroller. One

block (128 bytes) contains the option bytes of which 15 are used to configure the

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device hardware features. The options bytes can be programmed in user, IAP and

ICP/SWIM modes.

● High density STM8A devices

– From 32 to 128 Kbytes of Flash program memory organized in up to 256 pages of

4 blocks of 128 bytes each. The Flash program memory is divided into 2 areas, the

user boot code area (UBC), which size can be configured by option byte, and the

main program memory area. The Flash program memory is mapped in the upper

part of the STM8A addressing space and includes the reset and interrupt vectors.
– Up to 2 Kbytes of data EEPROM (DATA) organized in up to 4 pages of 4 blocks of

128 bytes each. The size of the DATA area is fixed for a given microcontroller. One

block (128 bytes) contains the option bytes of which 15 are used to configure the

device hardware features. The options bytes can be programmed in user, IAP and

ICP/SWIM modes.

The page defines the granularity of the user boot code area as described in Section 4.4.3:

User boot area (UBC).

Figure 6, Figure 7, and Figure 8 show the Flash memory and data EEPROM organization

for STM8S and STM8A devices. Refer to the STM8S and STM8A programming manual
(PM0051) for more information.

Note: The EEPROM access time allows the device to run up to 16 MHz. For clock frequencies

above 16 MHz, Flash/data EEPROM access must be configured for 1 wait state. This is
enabled by the device option byte (refer to the option bytes section of the STM8S and
STM8A datasheets).

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ai15503

USER BOOT CODE (UBC)

(permanently write protected)

0x00 8000

MAIN PROGRAM

(write access possible for IAP

and using MASS mechanism)

0x00 9FFF

Programmable size

from 2 pages (1 Kbytes)

up to 8 Kbytes
(1 page steps)

DATA MEMORY
(up to 640 bytes)

8 Kbytes of

FLASH PROGRAM

MEMORY

Flash program

memory

Interrupt vectors (128 bytes)

OPTION BYTES (1 block)

0x00 483F

0x00 4000

DATA EEPROM

1 page = 1 block = 64 bytes

0x00 4800

0x00 427F

Figure 6. Flash memory and data EEPROM organization on low density STM8S

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Figure 7. Flash memory and data EEPROM organization on medium density STM8S and STM8A

1 page = 512 bytes

1 block = 128 bytes

00 4000h

DATA MEMORY

DATA EEPROM

00 43FFh

00 4800h

00 487Fh

(up to 1 Kbyte)

OPTION BYTES (1 block)

00 8000h

Programmable size

from 2 pages (1 Kbyte)

up to 32 Kbytes

Interrupt vectors (128 bytes)

USER BOOT CODE (UBC)

(permanently write protected)

(1 page steps)

Flash program

memory

MAIN PROGRAM

(write access possible for IAP

and using MASS mechanism)

00 FFFFh

ai15502

1. The memory mapping is given for the STM8A devices featuring 32 Kbytes of Flash program memory and 1 Kbytes of
SRAM.

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ai15501b

USER BOOT CODE (UBC)

(permanently write protected)

0x00 8000

MAIN PROGRAM

(write access possible for IAP

and using MASS mechanism)

0x02 7FFF

Programmable size

from 2 pages (1 Kbytes)

up to 64 or 128 Kbytes

(1 page steps)

DATA MEMORY

(up to 2 Kbytes)

32 to 128 Kbytes of

Flash Program

Memory

Flash program

memory

Interrupt vectors (128 bytes)

OPTION BYTES (1 block)

0x00 487F

0x00 4000

DATA EEPROM

1 page = 512 bytes

1 block = 128 bytes

0x00 47FF

Figure 8. Flash memory and data EEPROM organization high density STM8S and STM8A

4.4.2 Memory access/ wait state configuration

4.4.3 User boot area (UBC)

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The Flash/ data EEPROM access time allows the device to run at up to 16 MHz without wait
states.

When using the high-speed external clock (HSE) at higher frequencies up to 24 MHz, one
wait state is necessary. In this case the device option byte should be programmed to insert
this wait state. Refer to the datasheet option byte section.

The user boot area (UBC) contains the reset and the interrupt vectors. It can be used to
store the IAP and communication routines. The UBC area has a second level of protection
to prevent unintentional erasing or modification during IAP programming. This means that it
is always write protected and the write protection cannot be unlocked using the MASS keys.

The size of the UBC area can be obtained by reading the UBC option byte.

The size of the UBC area can be configured in ICP mode (using the SWIM interface)
through the UBC option byte. The UBC option byte specifies the number of pages allocated
for the UBC area starting from address 0x00 8000.

RM0016 Flash program memory and data EEPROM

0x00 9FFF

0x00 9FC0

0x00 9F80

0x00 9F40

0x00 9F00

0x00 8100

0x00 8080

0x00 8040

Page 127

Page 126

Page 125

Page 124

Page 3

Page 2

Page 1

Page 0

0x00 8000

UBC[7:0] =0x01

64 bytes

64 bytes

64 bytes

64 bytes

64 bytes

64 bytes to 8 Kbytes

64 bytes

user boot code area

UBC[7:0] =0x02

128 bytes

64 bytes

0x00 80C0

64 bytes

64 bytes

Interrupt vectors

UBC[7:0] =0x7F

8 Kbytes

Refer to Figure 9, Figure 10, and Figure 11 for a description of the UBC area memory
mapping and to the option byte section in the datasheets for more details on the UBC option
byte.

Figure 9. UBC area size definition on low density STM8S devices

1. N (number of protected pages) = UBC[7:0].

2. UBC[7:0] = 0x00 means no user boot code area is defined. Refer to the datasheets for the description of
the UBC option byte.

3. The first 2 pages (128 bytes) contain the interrupt vectors.

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0x00 FFFF

0x00 FE00

0x00 FC00

0x00 FA00

0x00 F800

0x00 8800

0x00 8600

0x00 8400

0x00 8200

Page 63

Page 62

Page 61

Page 60

Page 3

Page 2

Page 1

Page 0

0x00 8000

UBC[7:0] =0x01

512 bytes

512 bytes

512 bytes

512 bytes

512 bytes

512 bytes

512 bytes

1K to 32 Kbytes

1 Kbytes

UBC[7:0] =0x3E

32 Kbytes

User boot code area

UBC[7:0] =0x02

2 Kbytes

0x00 807F

Interrupt vector table

Figure 10. UBC area size definition on medium density STM8S

and STM8A with up to 32 Kbytes of Flash program memory

1. N (number of protected pages) = UBC[7:0] + 2 for UBC[7:0] > 1.

2. UBC[7:0] =0x00 means no user boot code area is defined. Refer to the datasheets for the description of the
UBC option byte.

3. The first 2 pages (1 Kbytes) contain the 128 bytes of interrupt vectors (32 IT vectors).

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0x02 7FFF

0x02 7E00

0x02 7C00

0x02 7A00

0x02 7800

0x00 8800

0x00 8600

0x00 8400

0x00 8200

Page 255

Page 254

Page 253

Page 252

Page 3

Page 2

Page 1

Page 0

0x00 8000

UBC[7:0] =0x01

512 bytes

512 bytes

512 bytes

512 bytes

512 bytes

512 bytes

512 bytes

1K to 128 Kbytes

1 Kbytes

UBC[7:0] =0xFE

128 Kbytes

User boot code area

UBC[7:0] =0x02

2 Kbytes

0x00 807F

Interrupt vector table

Figure 11. UBC area size definition on high density STM8S and

STM8A with up to 128 Kbytes of Flash program memory

1. UBC[7:0] = 0x00 means no user boot code area is defined. Refer to the datasheets for the description of
the UBC option byte.

2. The first 2 pages (1 Kbytes) contain the interrupt vectors, of which only 128 bytes (32 IT vectors) are used.

4.4.4 Data EEPROM (DATA)

The data EEPROM area can be used to store application data. By default, the DATA area is
write protected to prevent unintentional modification when the main program is updated in
IAP mode. The write protection can be unlocked only by using a specific MASS key
sequence (refer to Enabling write access to the DATA area).

Refer to Section 4.4: Memory organization for the size of the DATA area.

4.4.5 Main program area

4.4.6 Option bytes

The main program is the part of the Flash program memory which is used to store the
application code (see Figure 6, Figure 7 and Figure 8).

The option bytes are used to configure device hardware features and memory protection.
They are located in a dedicated memory array of one block.

The option bytes can be modified both in ICP/SWIM and in IAP mode, with OPT bit of the
FLASH_CR2 register set to 1 and the NOPT bit of the FLASH_NCR2 register set to 0 (see

Section 4.8.2: Flash control register 2 (FLASH_CR2) and Section 4.8.3: Flash
complementary control register 2 (FLASH_NCR2)).

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Refer to the option byte section in the datasheet for more information on option bytes, and to
the STM8 SWIM protocol and debug module user manual (UM0470) for details on how to
program them.

4.5 Memory protection

4.5.1 Readout protection

Readout protection is selected by programming the ROP option byte to 0xAA. When readout
protection is enabled, reading or modifying the Flash program memory and DATA area in
ICP mode (using the SWIM interface) is forbidden, whatever the write protection settings.
Furthermore, on medium and high density STM8S and STM8A, the debug module (DM)
cannot start code execution by the CPU when the readout protection is active, and the CPU
is stalled.

Even if no protection can be considered as totally unbreakable, the readout feature provides
a very high level of protection for a general purpose microcontroller.

Removing the readout protection

The readout protection can be disabled on the program memory, UBC, and DATA areas, by
reprogramming the ROP option byte in ICP mode. In this case, the Flash program memory,
the DATA area and the option bytes are automatically erased and the device can be
reprogrammed.

Refer to Table 6: Memory access versus programming method for details on memory
access when readout protection is enabled or disabled.

4.5.2 Memory access security system (MASS)

After reset, the main program and DATA areas are protected against unintentional write
operations. They must be unlocked before attempting to modify their content. This unlock
mechanism is managed by the memory access security system (MASS).

The UBC area specified in the UBC option byte is always write protected (see Section 4.4.3:

User boot area (UBC)).

Once the memory has been modified, it is recommended to enable the write protection
again to protect the memory content against corruption.

Enabling write access to the main program memory

After a device reset, it is possible to disable the main program memory write protection by
writing consecutively two values called MASS keys to the FLASH_PUKR register (see

Section 4.8.6: Flash program memory unprotecting key register (FLASH_PUKR)). These

programmed keys are then compared to two hardware key values:

● First hardware key: 0b0101 0110 (0x56)

● Second hardware key: 0b1010 1110 (0xAE)

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The following steps are required to disable write protection of the main program area:

1. Write a first 8-bit key into the FLASH_PUKR register. When this register is written for

the first time after a reset, the data bus content is not latched into the register, but
compared to the first hardware key value (0x56).

2. If the key available on the data bus is incorrect, the FLASH_PUKR register remains

locked until the next reset. Any new write commands sent to this address are
discarded.

3. If the first hardware key is correct when the FLASH_PUKR register is written for the

second time, the data bus content is still not latched into the register, but compared to
the second hardware key value (0xAE).

4. If the key available on the data bus is incorrect, the write protection on program

memory remains locked until the next reset. Any new write commands sent to this
address is discarded.

5. If the second hardware key is correct, the main program memory is write unprotected

and the PUL bit of the FLASH_IAPSR is set (see Section 4.8.8: Flash status register

(FLASH_IAPSR) register.

Before starting programming, the application must verify that PUL bit is effectively set. The
application can choose, at any time, to disable again write access to the Flash program
memory by clearing the PUL bit.

Enabling write access to the DATA area

After a device reset, it is possible to disable the DATA area write protection by writing
consecutively two values called MASS keys to the FLASH_DUKR register (see

Section 4.8.9: Flash register map and reset values). These programmed keys are then

compared to two hardware key values:

● First hardware key: 0b1010 1110 (0xAE)

● Second hardware key: 0b0101 0110 (0x56)

The following steps are required to disable write protection of the DATA area:

1. Write a first 8-bit key into the FLASH_DUKR register. When this register is written for

the first time after a reset, the data bus content is not latched into the register, but
compared to the first hardware key value (0xAE).

2. If the key available on the data bus is incorrect, the application can re-enter two MASS

keys to try unprotecting the DATA area.

3. If the first hardware key is correct, the FLASH_DUKR register is programmed with the

second key. The data bus content is still not latched into the register, but compared to
the second hardware key value (0x56).

4. If the key available on the data bus is incorrect, the data EEPROM area remains write

protected until the next reset. Any new write command sent to this address is ignored.

5. If the second hardware key is correct, the DATA area is write unprotected and the DUL

bit of the FLASH_IAPSR register is set (see Section 4.8.8: Flash status register

(FLASH_IAPSR)).

Before starting programming, the application must verify that the DATA area is not write
protected by checking that the DUL bit is effectively set. The application can choose, at any
time, to disable again write access to the DATA area by clearing the DUL bit.

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4.5.3 Enabling write access to option bytes

The procedure for enabling write access to the option byte area is the same as the one used
for data EEPROM. However, the OPT bit in the Flash control register 2 (FLASH_CR2) must
be set, and the corresponding NOPT bit in the Flash complementary control register 2

(FLASH_NCR2) must be cleared to enable write access to the option bytes.

4.6 Memory programming

The main program memory, and the DATA area must be unlocked before attempting to
perform any program operation. The unlock mechanism depends on the memory area to be
programmed as described in Section 4.5.2: Memory access security system (MASS).

4.6.1 Read-while-write (RWW)

The RWW feature allows write operations to be performed on data EEPROM while reading
and executing the program memory. Execution time is therefore optimized. The opposite
operation is not allowed: Data memory cannot be read while writing to the program memory.

This RWW feature is always enabled and can be used at any time. Any access to Flash
control registers FLASH_CR1 and FLASH_CR2 while writing to the memory stalls the CPU,
making RWW unavailable.

Note: The RWW feature is not available on all devices. Refer to the datasheets for addition

information.

4.6.2 Byte programming

The main program memory and the DATA area can be programmed at byte level. To
program one byte, the application writes directly to the target address.

● In the main program memory:

The application stops for the duration of the byte program operation.

● In DATA area:

– Devices with RWW capability: Program execution does not stop, and the byte

program operation is performed using the read-while-write (RWW) capability in
IAP mode.

– Devices without RWW capability: The application stops for the duration of the byte

program operation.

To erase a byte, simply write 0x00 at the corresponding address.

The application can read the FLASH_IAPSR register to verify that the programming or
erasing operation has been correctly executed:

● EOP flag is set after a successful programming operation

● WR_PG_DIS is set when the software has tried to write to a protected page. In this

case, the write procedure is not performed.

As soon as one of these flags are set, a Flash interrupt is generated if it has been previously
enabled by setting the IE bit of the FLASH_CR1 register.

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Automatic fast byte programming

The programming duration can vary according to the initial content of the target address. If
the word (4 bytes) containing the byte to be programmed is not empty, the whole word is
automatically erased before the program operation. On the contrary if the word is empty, no
erase operation is performed and the programming time is shorter (see t

PROG

in Ta bl e

“Flash program memory” in the datasheet).

However, the programming time can be fixed by setting the FIX bit of the FLASH_CR1
register to force the program operation to systematically erase the byte whatever its content
(see Section 4.8.1: Flash control register 1 (FLASH_CR1)). The programming time is
consequently fixed and equal to the sum of the erase and write time (see t

PROG

in Ta bl e

“Flash program memory” in the datasheet).

Note: To write a byte fast (no erase), the whole word (4 bytes) into which it is written must be

erased beforehand. Consequently, It is not possible to do two fast writes to the same word
(without an erase before the second write): The first write will be fast but the second write to
the other byte will require an erase.

4.6.3 Word programming

A word write operation allows an entire 4-byte word to be programmed in one shot, thus
minimizing the programming time.

As for byte programming, word operation is available both for the main program memory and
data EEPROM. On some devices, the read-while-write (RWW) capability is also available
when a word programming operation is performed on the data EEPROM. Refer to the
datasheets for additional information.

● In the main program memory:

The application stops for the duration of the byte program operation.

● In DATA area

– Devices with RWW capability: Program execution does not stop, and the byte

program operation is performed using the read-while-write (RWW) capability in
IAP mode.

– Devices without RWW capability: The application stops for the duration of the byte

program operation.

To program a word, the WPRG/NWPRG bits in the FLASH_CR2 and FLASH_NCR2
registers must be previously set/cleared to enable word programming mode (see

Section 4.8.2: Flash control register 2 (FLASH_CR2) and Section 4.8.2: Flash control
register 2 (FLASH_CR2)). Then, the 4 bytes of the word to be programmed must be loaded

starting with the first address. The programming cycle starts automatically when the 4 bytes
have been written.

As for byte operation, the EOP and the WR_PG_DIS control flags of FLASH_IAPSR,
together with the Flash interrupt, can be used to determine if the operation has been
correctly completed.

4.6.4 Block programming

Block program operations are much faster than byte or word program operations. In a block
program operation, a whole block is programmed or erased in a single programming cycle.
Refer to Ta bl e 5 for details on the block size according to the devices.

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Block operations can be performed both to the main program memory and DATA area:

● In the main program memory:

Block program operations to the main program memory have to be executed totally
from RAM.

● In the DATA area

– Devices with RWW capability: DATA block operations can be executed from the

main program memory. However, the data loading phase (see below) has to be
executed from RAM.

– Devices without RWW capability: Block program operations must be executed

totally from RAM.

There are three possible block operations:

● Block programming, also called standard block programming: The block is

automatically erased before being programmed.

● Fast block programming: No previous erase operation is performed.

● Block erase

During block programming, interrupts are masked by hardware.

Standard block programming

A standard block program operation allows a whole block to be written in one shot. The
block is automatically erase before being programmed.

To program a whole block in standard mode, the PRG/NPRG bits in the FLASH_CR2 and
FLASH_NCR2 registers must be previously set/cleared to enable standard block
programming (see Section 4.8.2: Flash control register 2 (FLASH_CR2) and Section 4.8.2:

Flash control register 2 (FLASH_CR2)). Then, the block of data to be programmed must be

loaded sequentially to the destination addresses in the main program memory or DATA
area. This causes all the bytes of data to be latched. To start programming the whole block,
all bytes of data must be written. All bytes written in a programming sequence must be in the
same block. This means that they must have the same high address: Only the six least
significant bits of the address can change. When the last byte of the target block is loaded,
the programming starts automatically. It is preceded by an automatic erase operation of the
whole block.

When programming a block in DATA area, the application can check the HVOFF bit in the

Flash status register (FLASH_IAPSR). As soon the HVOFF flag is reset the actual

programming phase starts and the application can return to main program memory.

The EOP and the WR_PG_DIS control flags of the FLASH_IAPSR together with the Flash
interrupt can be used to determine if the operation has been correctly completed.

Fast block programming

Fast block programming allows programming without first erasing the memory contents.
Fast block programming is therefore twice as fast as standard programming.

This mode is intended only for programming parts that have already been erased. It is very
useful for programming blank parts with the complete application code, as the time saving is
significant.

Fast block programming is performed by using the same sequence as standard block
programming. To enable fast block programming mode, the FPRG/NFPRG bits of the
FLASH_CR2 and FLASH_NCR2 registers must be previously set/cleared.

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The HVOFF flag can also be polled by the application which can execute other instructions
(RWW) during the actual programming phase of the DATA.

The EOP and WR_PG_DIS bits of the FLASH_IAPSR register can be checked to determine
if the fast block programming operation has been correctly completed.

Caution: The data programmed in the block are not guaranteed when the block is not blank before

the fast block program operation.

Block erasing

A block erase allows a whole block to be erased.

To erase a whole block, the ERASE/NERASE bits in the FLASH_CR2 and FLASH_NCR2
registers must be previously set/cleared to enable block erasing (see Section 4.8.2: Flash

control register 2 (FLASH_CR2) and Section 4.8.3: Flash complementary control register 2
(FLASH_NCR2)). The block is then erased by writing ‘0x00 00 00 00’ to any word inside the

block. The word start address must end with ‘0’, ‘4’, ‘8’, or ‘C’.

The EOP and the WR_PG_DIS control flags of the FLASH_IAPSR together with the Flash
interrupt can be used to determine if the operation has been correctly completed.

Table 5. Block size

STM8 microcontroller family Block size

Low density STM8S 64 bytes

Medium density STM8S and STM8A (up to 32 Kbytes) 128 bytes

High density STM8S and STM8A (up to 128 Kbytes) 128 bytes

4.6.5 Option byte programming

Option byte programming is very similar to data EEPROM byte programming.

The application writes directly to the target address. The program does not stop and the
write operation is performed using the RWW capability.

Refer to the datasheet for details of the option byte contents.

4.7 ICP and IAP

The in-circuit programming (ICP) method is used to update the entire content of the memory,
using the SWIM interface to load the user application into the microcontroller. ICP offers
quick and efficient design iterations and eliminates unnecessary package handling or
socketing of devices. The SWIM interface (single wire interface module) uses the SWIM pin
to connect to the programming tool.

In contrast to the ICP method, in-application programming (IAP) can use any communication
interface supported by the microcontroller (I/Os, I
be programmed in the memory. IAP allows the Flash program memory content to be
reprogrammed during application execution. Nevertheless, part of the application must have
been previously programmed in the Flash program memory using ICP.

2

C, SPI, USART...) to download the data to

Refer to the STM8S and STM8A Flash programming manual (PM0051) and STM8 SWIM
protocol and debug manual (UM0470) for more information on programming procedures.

Doc ID 14587 Rev 8 49/449

Flash program memory and data EEPROM RM0016

Table 6. Memory access versus programming method

Mode ROP Memory Area

User boot code area (UBC) R/E

Readout

Main program R/W/E

protection

enabled

User, IAP, and bootloader (if
available)

Readout

Data EEPROM area (DATA) R/W

Option bytes R

User boot code area (UBC) R/E

Main program R/W/E

protection

disabled

Data EEPROM area (DATA) R/W

Option bytes R/W

User boot code area (UBC) P

Readout

Main program P

protection

enabled

SWIM active

(ICP mode)

Readout

Data EEPROM area (DATA) P

Option bytes P/W

User boot code area (UBC) R/E

Main program R/W/E

protection

disabled

Data EEPROM area (DATA) R/W

Option bytes R/W

(1)

Access from

core

(2)

(3)

(4)

(2)

(3)

(5)

(6)

ROP

(4)

(2)

(3)

(5)

1. R/W/E = Read, write, and execute
R/E = Read and execute (write operation forbidden)
R = Read (write and execute operations forbidden)
P = The area cannot be accessed (read, execute and write operations forbidden)
P/W

= Protected, write forbidden except for ROP option byte.

ROP

2. The Flash program memory is write protected (locked) until the correct MASS key is written in the FLASH_PUKR. It is
possible to lock the memory again by resetting the PUL bit in the FLASH_IAPSR register. If incorrect keys are provided, the
device must be reset and new keys programmed.

3. The data memory is write protected (locked) until the correct MASS key is written in the FLASH_DUKR. It is possible to lock
the memory again by resetting the DUL bit in the IAPSR register. If incorrect keys are provided, another key program
sequence can be performed without resetting the device.

4. To program the UBC area, the application must first clear the UBC option byte.

5. The option bytes are write protected (locked) until the correct MASS key is written in the FLASH_DUKR (with OPT set to 1).
It is possible to lock the memory again by resetting the DUL bit in the FLASH_IAPSR register. If incorrect keys are
provided, another key program sequence can be performed without resetting the device.

6. When ROP is removed, the whole memory is erased, including the option bytes.

50/449 Doc ID 14587 Rev 8

RM0016 Flash program memory and data EEPROM

4.8 Flash registers

4.8.1 Flash control register 1 (FLASH_CR1)

Address offset: 0x00
Reset value: 0x00

76543210

Reserved

Bits 7:4 Reserved

Bit 3 HALT: Power-down in Halt mode

This bit is set and cleared by software.
0: Flash in power-down mode when MCU is in Halt mode
1: Flash in operating mode when MCU is in Halt mode

Bit 2 AHALT: Power-down in Active-halt mode

This bit is set and cleared by software.
0: Flash in operating mode when MCU is in Active-halt mode
1: Flash in power-down when MCU is in Active-halt mode

Bit 1 IE: Flash Interrupt enable

This bit is set and cleared by software.
0: Interrupt disabled
1: Interrupt enabled. An interrupt is generated if the EOP or WR_PG_DIS flag in the

FLASH_IAPSR register is set.

HALT AHALT IE FIX

rw rw rw rw

Bit 0 FIX: Fixed Byte programming time

This bit is set and cleared by software.
0: Standard programming time of (1/2 t

) if the memory is already erased and t

prog

prog

otherwise.
1: Programming time fixed at t

prog

.

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Flash program memory and data EEPROM RM0016

4.8.2 Flash control register 2 (FLASH_CR2)

Address offset: 0x01
Reset value: 0x00

76543210

OPT WPRG ERASE FPRG

rw rw rw rw rw

Reserved

Bit 7 OPT: Write option bytes

This bit is set and cleared by software.
0: Write access to option bytes disabled
1: Write access to option bytes enabled

Bit 6 WPRG: Word programming

This bit is set by software and cleared by hardware when the operation is completed.
0: Word program operation disabled
1: Word program operation enabled

Bit 5 ERASE

(1)

: Block erasing

This bit is set by software and cleared by hardware when the operation is completed.
0: Block erase operation disabled
1: Block erase operation enabled

Bit 4 FPRG

(1)

: Fast block programming

This bit is set by software and cleared by hardware when the operation is completed.
0: Fast block program operation disabled
1: Fast block program operation enabled

Bits 3:1 Reserved

Bit 0 PRG: Standard block programming

This bit is set by software and cleared by hardware when the operation is completed.
0: Standard block programming operation disabled
1: Standard block programming operation enabled (automatically first erasing)

1. The ERASE and FPRG bits are locked when the memory is busy.

PRG

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RM0016 Flash program memory and data EEPROM

4.8.3 Flash complementary control register 2 (FLASH_NCR2)

Address offset: 0x02

Reset value: 0xFF

76543210

NOPT NWPRG NERASE NFPRG

rw rw rw rw rw

Reserved

Bit 7 NOPT: Write option bytes

This bit is set and cleared by software.
0: Write access to option bytes enabled
1: Write access to option bytes disabled

Bit 6 NWPRG: Word programming

This bit is cleared by software and set by hardware when the operation is completed.
0: Word programming enabled
1: Word programming disabled

Bit 5 NERASE: Block erase

This bit is cleared by software and set by hardware when the operation is completed.
0: Block erase enabled
1: Block erase disabled

Bit 4 NFPRG: Fast block programming

This bit is cleared by software and set by software reading the register.
0: Fast block programming enabled (no erase before programming, the programmed data

values are not guaranteed when the block is not blank (fully erased) before the operation)
1: Fast block programming disabled

Bits 3:1 Reserved.

NPRG

Bit 0 NPRG: Block programming

This bit is cleared by software and set by hardware when the operation is completed.
0: Block programming enabled
1: Block programming disabled

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Flash program memory and data EEPROM RM0016

4.8.4 Flash protection register (FLASH_FPR)

Address offset: 0x03

Reset value: 0x00

76543210

Reserved

WPB5 WPB4 WPB3 WPB2 WPB1 WPB0

ro ro ro ro ro ro

Bits 7:6 Reserved.

Bits 5:0 WPB[5:0]: User boot code area protection bits

These bits show the size of the boot code area. They are loaded at startup with the content of
the UBC option byte. Refer to the datasheets for the protected pages according to the bit
values.

4.8.5 Flash protection register (FLASH_NFPR)

Address offset: 0x04

Reset value: 0xFF

76543210

Reserved

Bits 7:6 Reserved.

NWPB5 NWPB4 NWPB3 NWPB2 NWPB1 NWPB0

ro ro ro ro ro ro

Bits 5:0 WPB[5:0]: User boot code area protection bits

These bits show the size of the boot code area. They reflect the content of the NUBC option
byte. Refer o the datasheet for the protected pages according to the bit values.

4.8.6 Flash program memory unprotecting key register (FLASH_PUKR)

Address offset: 0x08
Reset value: 0x00

76543210

MASS_PRG KEYS

rw

Bits 7:0 PUK [7:0]: Main program memory unlock keys

This byte is written by software (all modes). It returns 0x00 when read.
Refer to Enabling write access to the main program memory on page 44 for the description

of main program area write unprotection mechanism.

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RM0016 Flash program memory and data EEPROM

4.8.7 Data EEPROM unprotection key register (FLASH_DUKR)

Address offset: 0x0A
Reset value: 0x00

76543210

MASS_DATA KEYS

rw

Bits 7:0 DUK[7:0]: Data EEPROM write unlock keys

This byte is written by software (all modes). It returns 0x00 when read.
Refer to Enabling write access to the DATA area on page 45 for the description of main
program area write unprotection mechanism.

4.8.8 Flash status register (FLASH_IAPSR)

Address offset: 0x05
Reset value: 0x40

76543210

Reserved HVOFF

res. r rc_w0 rc_r rc_w0 rc_r

Reserved

DUL EOP PUL WR_PG_DIS

Bit 7 Reserved.

Bit 6 HVOFF: End of high voltage flag

This bit is set and cleared by hardware.
0: HV ON, start of actual programming
1: HV OFF, end of high voltage

Bits 5:4 Reserved, forced by hardware to 0.

Bit 3 DUL: Data EEPROM area unlocked flag

This bit is set by hardware and cleared by software by programming it to 0.
0: Data EEPROM area write protection enabled
1: Data EEPROM area write protection has been disabled by writing the correct MASS

keys

Bit 2 EOP: End of programming (write or erase operation) flag

This bit is set by hardware. It is cleared by software by reading the register, or when a new
write/erase operation starts.
0: No EOP event occurred
1: An EOP operation occurred. An interrupt is generated if the IE bit is set in the
FLASH_CR1 register.

Bit 1 PUL: Flash Program memory unlocked flag

This bit is set by hardware and cleared by software by programming it to 0.
0: Write protection of main Program area enabled
1: Write protection of main Program area has been disabled by writing the correct MASS

keys.

Bit 0 WR_PG_DIS: Write attempted to protected page flag

This bit is set by hardware and cleared by software by reading the register.
0: No WR_PG_DIS event occurred
1: A write attempt to a write protected page occurred. An interrupt is generated if the IE bit
is set in the FLASH_CR1 register.

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Flash program memory and data EEPROM RM0016

4.8.9 Flash register map and reset values

For details on the Flash register boundary addresses, refer to the general hardware register
map in the datasheets.

Table 7. Flash register map and reset values

AddressRegister name7654 3 2 1 0

0x00

0x01

0x02

0x03

0x04

0x05

0x06-0x07 Reserved

0x08

0x09 Reserved

0x0A

FLASH_CR1

Reset value

FLASH_CR2

Reset value

FLASH_NCR2

Reset value

FLASH_FPR

Reset value

FLASH_NFPR

Reset value

FLASH_IAPSR

Reset value

FLASH_PUKR

Reset value

FLASH_DUKR

Reset value

-

0

OPT

0

NOPT1NWPRG

-

0

-

1

-

0

PUK7

0

DUK7

0

­0

WPRG

0

1

­0

­1

HVOFF

1

PUK6

0

DUNP60DUK5

-

0

ERASE0FPRG

NERASE1NFPRG

WPB5

0

NWPB51NWPB41NWPB31NWPB21NWPB1

- - DUL

PUK5

0

0

-

0

0

1

WPB4

0

PUK4

0

DUK4

0

HALT

0

-

0

-

1

WPB3

0

0

PUK3

0

DUK3

0

AHALT

0

­0

­1

WPB2

0

EOP

0

PUK2

0

DUK2

0

IE

0

-

0

-

1

WPB1

0

1

PUL

0

PUK1

0

DUK1

0

FIX

0

PRG

0

NPRG

1

WPB0

0

NWPB0

1

WR_PG_DIS

0

PUK0

0

DUK0

0

56/449 Doc ID 14587 Rev 8

RM0016 Single wire interface module (SWIM) and debug module (DM)

MCU

SWIM/PA0

Jumper selection for
debug purposes

I/O for application

SWIM interface for tools

5 Single wire interface module (SWIM) and debug

module (DM)

5.1 Introduction

In-circuit debugging mode or in-circuit programming mode are managed through a single
wire hardware interface featuring ultrafast memory programming. Coupled with an in-circuit
debugging module, it also offers a non-intrusive emulation mode, making the in-circuit
debugger extremely powerful, close in performance to a full-featured emulator.

5.2 Main features

● Based on an asynchronous, high sink (8 mA), open-drain, bidirectional communication.

● Allows reading or writing any part of memory space.

● Access to CPU registers (A, X, Y, CC, SP). They are memory mapped for read or write

access.

● Non intrusive read/write on the fly to the RAM and peripheral registers.

● Device reset capability with status flag in the Reset status register (RST_SR).

● Clock speed selectable in the SWIM clock control register (CLK_SWIMCCR).

SWIM pin can be used as a standard I/O with some restrictions if you also want to use it for
debug. The most secure way is to provide on the PCB a strap option.

Figure 12. SWIM pin connection

5.3 SWIM modes

After a power-on reset, the SWIM is reset and enters OFF mode.

1. OFF: Default state after power-on reset. The SWIM pin cannot be used by the
application as an I/O.

2. I/O: This state is entered by software writing to the SWD bit in the Global configuration

register (CFG_GCR). In this state, the SWIM pin can be used by the application as a

standard I/O pin. In case of a reset, the SWIM goes back to OFF mode.

3. SWIM: This state is entered when a specific sequence is performed on the SWIM pin.
In this state, the SWIM pin is used by the host tool to control the STM8 with 3

Note: Refer to the STM8 SWIM communication Protocol and Debug Module User Manual for a

commands (SRST system reset, ROTF read on the fly, WOTF write on the fly).

description of the SWIM and Debug module (DM) registers.

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Interrupt controller (ITC) RM0016

6 Interrupt controller (ITC)

6.1 ITC introduction

● Management of hardware interrupts

– External interrupt capability on most I/O pins with dedicated interrupt vector and

edge sensitivity setting per port

– Peripheral interrupt capability

● Management of software interrupt (TRAP)

● Nested or concurrent interrupt management with flexible interrupt priority and level

management:
– Up to 4 software programmable nesting levels
– Up to 32 interrupt vectors fixed by hardware
– 2 non maskable events: RESET, TRAP
– 1 non-maskable top level hardware interrupt (TLI)

This interrupt management is based on:

● Bit I1 and I0 of the CPU Condition Code register (CCR)

● Software priority registers (ITC_SPRx)

● Reset vector address 0x00 8000 at the beginning of program memory. In devices with

boot ROM, the reset initialization routine is programmed in ROM by
STMicroelectronics.

● Fixed interrupt vector addresses located at the high addresses of the memory map

(0x00 8004 to 0x00 807C) sorted by hardware priority order.

6.2 Interrupt masking and processing flow

The interrupt masking is managed by bits I1 and I0 of the CCR register and by the
ITC_SPRx registers which set the software priority level of each interrupt vector (see

Ta bl e 8 ). The processing flow is shown in Figure 13.

When an interrupt request has to be serviced:

1. Normal processing is suspended at the end of the current instruction execution.

2. The PC, X,Y, A and CCR registers are saved onto the stack.

3. Bits I1 and I0 of CCR register are set according to the values in the ITC_SPRx registers
corresponding to the serviced interrupt vector.

4. The PC is then loaded with the interrupt vector of the interrupt to service and the first
instruction of the interrupt service routine is fetched .

The interrupt service routine should end with the IRET instruction which causes the content
of the saved registers to be recovered from the stack. As a consequence of the IRET
instruction, bits I1 and I0 are restored from the stack and the program execution resumes.

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RM0016 Interrupt controller (ITC)

“IRET”

RESTORE PC, X, Y, A, CCR

STACK PC, X, Y, A, CCR

LOAD I1:0 FROM INTERRUPT SW REG.

FETCH NEXT

RESET

TRAP

PENDING

INSTRUCTION

I1:0

FROM STACK

LOAD PC FROM INTERRUPT VECTOR

Y

N

Y

N

Y

N

Interrupt has the same or a

lower software priority

THE INTERRUPT
STAYS PENDING

than current one

Interrupt has a higher

software priority

than current one

EXECUTE

INSTRUCTION

INTERRUPT

Table 8. Software priority levels

Software priority Level I1 I0

Level 0 (main)

Level 1 0 1

Level 2 0 0

Low

High

10

Level 3 (= software priority disabled) 1 1

Figure 13. Interrupt processing flowchart

Caution: If the interrupt mask bits I0 and I1 are set within an interrupt service routine (ISR) with the

instruction SIM, removal of the interrupt mask with RIM causes the software priority to be
set to level 0.

To restore the correct priority when disabling and enabling interrupts inside an ISR, follow
the procedures presented in Ta bl e 8 for disabling and enabling the interrupts.

Table 9. Interrupt enabling/disabling inside an ISR

Disabling the interrupts Enabling the interrupts

#asm
PUSH CC
POP ISR_CC

(1)

SIM
#endasm

1. IRS_CC is a variable which stores the current value of the CC register.

Doc ID 14587 Rev 8 59/449

#asm
PUSH ISR_CC
POP CC
#endasm

(1)

Interrupt controller (ITC) RM0016

PENDING

SOFTWARE

Different

INTERRUPTS

Same

HIGHEST HARDWARE

PRIORITY SERVICED

PRIORITY

HIGHEST SOFTWARE

PRIORITY SERVICED

6.2.1 Servicing pending interrupts

Several interrupts can be pending at the same time. The interrupt to be taken into account is
determined by the following two-step process:

1. The highest software priority interrupt is serviced.

2. If several interrupts have the same software priority then the interrupt with the highest
hardware priority is serviced first.

When an interrupt request is not serviced immediately, it is latched and then processed
when its software priority combined with the hardware priority becomes the highest one.

Note: 1 The hardware priority is exclusive while the software one is not. This allows the previous

process to succeed with only one interrupt.

2 RESET, TLI and TRAP are considered as having the highest software priority in the decision

process.

See Figure 14 for a description of pending interrupt servicing process.

Figure 14. Priority decision process

6.2.2 Interrupt sources

60/449 Doc ID 14587 Rev 8

Two interrupt source types are managed by the STM8 interrupt controller:

● Non-maskable interrupts: RESET, TLI and TRAP

● Maskable interrupts: external interrupts or interrupts issued by internal peripherals

Non-maskable interrupt sources

Non-maskable interrupt sources are processed regardless of the state of bits I1 and I0 of
the CCR register (see Figure 13). PC, X, Y, A and CCR registers are stacked only when a

RM0016 Interrupt controller (ITC)

TRAP interrupt occurs. The corresponding vector is then loaded in the PC register and bits
I1 and I0 of the CCR register are set to disable interrupts (level 3).

● TRAP (non-maskable software interrupt)

This software interrupt source is serviced when the TRAP instruction is executed. It is
serviced as a TLI according to the flowchart shown in Figure 13.

A TRAP interrupt does not allow the processor to exit from Halt mode.

● RESET

The RESET interrupt source has the highest STM8 software and hardware priorities.
This means that all the interrupts are disabled at the beginning of the reset routine.
They must be re-enabled by the RIM instruction (see Table 11: Dedicated interrupt

instruction set).

A RESET interrupt allows the processor to exit from Halt mode.

See RESET chapter for more details on RESET interrupt management.

● TLI (top level hardware interrupt)

This hardware interrupt occurs when a specific edge is detected on the corresponding
TLI input.

Caution: A TRAP instruction must not be used in a TLI service routine.

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Interrupt controller (ITC) RM0016

Maskable interrupt sources

Maskable interrupt vector sources are serviced if the corresponding interrupt is enabled and
if its own interrupt software priority in ITC_SPRx registers is higher than the one currently
being serviced (I1 and I0 in CCR register). If one of these two conditions is not met, the
interrupt is latched and remains pending.

● External interrupts

External interrupts can be used to wake up the MCU from Halt mode. The device
sensitivity to external interrupts can be selected by software through the External
Interrupt Control registers (EXTI_CRx).

When several input pins connected to the same interrupt line are selected
simultaneously, they are logically ORed.

When external level-triggered interrupts are latched, if the given level is still present at
the end of the interrupt routine, the interrupt remains activated except if it has been
inactivated in the routine.

● Peripheral interrupts

Most peripheral interrupts cause the MCU to wake up from Halt mode. See the interrupt
vector table in the datasheet.

A peripheral interrupt occurs when a specific flag is set in the peripheral status register
and the corresponding enable bit is set in the peripheral control register.

The standard sequence for clearing a peripheral interrupt performs an access to the
status register followed by a read or write to an associated register. The clearing
sequence resets the internal latch. A pending interrupt (that is an interrupt waiting to be
serviced) is therefore lost when the clear sequence is executed.

6.3 Interrupts and low power modes

All interrupts allow the processor to exit from Wait mode.

Only external and other specific interrupts allow the processor to exit from Halt and Active­halt mode (see wakeup from halt and wakeup from Active-halt in the interrupt vector table in
the datasheet).

When several pending interrupts are present while waking up from Halt mode, the first
interrupt serviced can only be an interrupt with exit-from-Halt mode capability. It is selected
through the decision process shown in Figure 14. If the highest priority pending interrupt
cannot wake up the device from Halt mode, it will be serviced next.

If any internal or external interrupt (from a timer for example) occurs while the HALT
instruction is executing, the HALT instruction is completed but the interrupt invokes the
wakeup process immediately after the HALT instruction has finished executing. In this case
the MCU is actually waking up from Halt mode to Run mode, with the corresponding delay of
t

as specified in the datasheet.

WUH

6.4 Activation level/low power mode control

The MCU activation level is configured by programming the AL bit in the CFG_GCR register
(see global configuration register (CFG_GCR)).

This bit is used to control the low power modes of the MCU. In very low power applications,
the MCU spends most of the time in WFI and is woken up (through interrupts) at specific

62/449 Doc ID 14587 Rev 8

RM0016 Interrupt controller (ITC)

MAIN

IT4

IT2

IT1

TRAP

IT1

MAIN

IT0

I1

HARDWARE PRIORITY

SOFTWARE

3

3

3

3

3

3/0

3

11

11

11

11

11

11 / 10

11

RIM

IT2

IT1

IT4

TRAP

IT3

IT0

IT3

I0

10

PRIORITY
LEVEL

USED STACK = 10 BYTES

moments in order to execute a specific task. Some of these recurring tasks are short
enough to be treated directly in an ISR (interrupt service routine), rather than going back to
the main program. To cover this case, you can set the AL bit before entering Low power
mode (by executing WFI instruction), then the interrupt routine returns directly to Low power
mode. The run time/ISR execution is reduced due to the fact that the register context is
saved only on the first interrupt.

As a consequence, all the operations can be executed in ISR in very simple applications. In
more complex ones, an interrupt routine may relaunch the main program by simply resetting
the AL bit.

For example, an application may need to be woken up by the auto-wakeup unit (AWU) every
50 ms in order to check the status of some pins/sensors/push-buttons. Most of the time, as
these pins are not active, the MCU can return to Low power mode without running the main
program. If one of these pins is active, the ISR decides to launch the main program by
resetting the AL bit.

6.5 Concurrent and nested interrupt management

STM8 devices feature two interrupt management modes:

● Concurrent mode

● Nested mode

6.5.1 Concurrent interrupt management mode

In this mode, all interrupts are interrupt priority level 3 so that none of them can be
interrupted, except by a TLI, RESET, or TRAP.

The hardware priority is given in the following order from the lowest to the highest priority,
that is: MAIN, IT4, IT3, IT2, IT1, IT0, TRAP/TLI (same priority), and RESET.

Figure 15 shows an example of concurrent interrupt management mode.

Figure 15. Concurrent interrupt management

Doc ID 14587 Rev 8 63/449

Interrupt controller (ITC) RM0016

6.5.2 Nested interrupt management mode

In this mode, interrupts are allowed during interrupt routines. This mode is activated as soon
as an interrupt priority level lower than level 3 is set.

The hardware priority is given in the following order from the lowest to the highest priority,
that is: MAIN, IT4, IT3, IT2, IT1, IT0, and TRAP.

The software priority is configured for each interrupt vector by setting the corresponding
I1_x and I0_x bits of the ITC_SPRx register. I1_x and I0_x bits have the same meaning as
I1 and I0 bits of the CCR register (see Tab le 1 0 ).

Level 0 can not be programmed (I1_x=1, I0_x=0). In this case, the previously stored value is
kept. For example: if previous value is 0xCF, and programmed value equals 64h, the result is
44h.

The RESET and TRAP vectors have no software priorities. When one is serviced, bits I1
and I0 of the CCR register are both set.

Caution: If bits I1_x and I0_x are modified while the interrupt x is executed, the device operates as

follows: if the interrupt x is still pending (new interrupt or flag not cleared) and the new
software priority is higher than the previous one, then the interrupt x is re-entered.
Otherwise, the software priority remains unchanged till the next interrupt request (after the
IRET of the interrupt x).

During the execution of an interrupt routine, the HALT, POPCC, RIM, SIM and WFI
instructions change the current software priority till the next IRET instruction or one of the
previously mentioned instructions is issued. See Section 6.7 for the list of dedicated
interrupt instructions.

Figure 16 shows an example of nested interrupt management mode.

Warning: A stack overflow may occur without notifying the software of

the failure.

Table 10. Vector address map versus software priority bits

Vector address ITC_SPRx bits

0x00 8008h I1_0 and I0_0 bits

0x00 800Ch I1_1 and I0_1 bits

... ...

0x00 807Ch I1_29 and I0_29 bits

1. ITC_SPRx register bits corresponding to the TLI can be read and written. However they are not significant

in the interrupt process management.

(1)

64/449 Doc ID 14587 Rev 8

RM0016 Interrupt controller (ITC)

MAIN

IT2

TRAP

MAIN

IT0

IT2

IT1

IT4

TRAP

IT3

IT0

HARDWARE PRIORITY

3

2

1

3

3

3/0

3

11

00

01

11

11

11

RIM

IT1

IT4

IT4

IT1

IT2

IT3

I1 I0

11 / 10

10

SOFTWARE
PRIORITY
LEVEL

USED STACK = 20 BYTES

Figure 16. Nested interrupt management

6.6 External interrupts

Five interrupt vectors are dedicated to external Interrupt events:

● 5 lines on Port A: PA[6:2]

● 8 lines on Port B: PB[7:0]

● 8 lines on Port C: PC[7:0]

● 7 lines on Port D: PD[6:0]

● 8 lines on Port E: PE[7:0]

PD7 is the Top Level Interrupt source (TLI), except for 20-pin packages on which the Top
Level Interrupt source (TLI) can be available on the PC3 pin using an alternate function
remapping option bit. Refer to option bytes section in the product datasheet for more details.

To generate an interrupt, the corresponding GPIO port must be configured in input mode
with interrupts enabled. Refer to the register description in the GPIO chapter for details.

The interrupt sensitivity must be configured in the external interrupt control register 1
(EXTI_CR1) and external interrupt control register 2 (EXTI_CR2) (see Section 6.9.3 and

Section 6.9.4.).

6.7 Interrupt instructions

Ta bl e 1 1 shows the interrupt instructions.

Table 11. Dedicated interrupt instruction set

Instruction New description Function/example I1 H I0 N Z C

HALT Entering Halt mode 1 0

IRET Interrupt routine return Pop CCR, A, X, Y, PC I1 H I0 N Z C

JRM Jump if I1:0=11 (level 3) I1:0=11 ?

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Interrupt controller (ITC) RM0016

Table 11. Dedicated interrupt instruction set (continued)

Instruction New description Function/example I1 H I0 N Z C

JRNM Jump if I1:0<>11 I1:0<>11 ?

POP CC Pop CCR from the stack Memory => CCR I1 H I0 N Z C

PUSH CC Push CC on the stack CC =>Memory

RIM Enable interrupt (level 0 set) Load 10 in I1:0 of CCR 1 0

SIM Disable interrupt (level 3 set) Load 11 in I1:0 of CCR 1 1

TRAP Software trap Software NMI 1 1

WFI Wait for interrupt 1 0

6.8 Interrupt mapping

Refer to the corresponding device datasheet for the table of interrupt vector addresses.

66/449 Doc ID 14587 Rev 8

RM0016 Interrupt controller (ITC)

6.9 ITC and EXTI registers

6.9.1 CPU condition code register interrupt bits (CCR)

Address: refer to the general hardware register map table in the datasheet.
Reset value: 0x28

76543210

V–I1HI0NZC

rrrwrrwrrr

Bits 5, 3

(1)

I[1:0]: Software interrupt priority bits

(2)

These two bits indicate the software priority of the current interrupt request. When an
interrupt request occurs, the software priority of the corresponding vector is loaded
automatically from the software priority registers (ITC_SPRx).

The I[1:0] bits can be also set/cleared by software using the RIM, SIM, HALT, WFI, IRET or
PUSH/POP instructions (see Figure 16: Nested interrupt management).

I1 I0 Priority Level

1 0 Level 0 (main)

01Level 1

00Level 2

1 1 Level 3 (= software priority disabled*)

1. Refer to the central processing section for details on the other CCR bits.

2. TLI, TRAP and RESET events can interrupt a level-3 program.

Low

High

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Interrupt controller (ITC) RM0016

6.9.2 Software priority register x (ITC_SPRx)

Address offset: 0x00 to 0x07
Reset value: 0xFF

76543210

ITC_SPR1 VECT3SPR[1:0] VECT2SPR[1:0] VECT1SPR[1:0] VECT0SPR[1:0]

ITC_SPR2 VECT7SPR[1:0] VECT6SPR[1:0] VECT5SPR[1:0] VECT4SPR[1:0]

ITC_SPR3 VECT11SPR[1:0] VECT10SPR[1:0] VECT9SPR[1:0] VECT8SPR[1:0]

ITC_SPR4 VECT15SPR[1:0] VECT14SPR[1:0] VECT13SPR[1:0] VECT12SPR[1:0]

ITC_SPR5 VECT19SPR[1:0] VECT18SPR[1:0] VECT17SPR[1:0] VECT16SPR[1:0]

ITC_SPR6 VECT23SPR[1:0] VECT22SPR[1:0] VECT21SPR[1:0] VECT20SPR[1:0]

ITC_SPR7 VECT27SPR[1:0] VECT26SPR[1:0] VECT25SPR[1:0] VECT24SPR[1:0]

ITC_SPR8 Reserved VECT29SPR[1:0] VECT28SPR[1:0]

rw rw rw rw rw

Bits 7:0 VECTxSPR[1:0]: Vector x software priority bits

These eight read/write registers (ITC_SPR1 to ITC_SPR8) are written by software to define
the software priority of each interrupt vector.
The list of vectors is given in Table 10: Vector address map versus software priority bits.
Refer to Section 6.9.1: CPU condition code register interrupt bits (CCR) for the values to be
programmed for each priority.
ITC_SPR1 bits 1:0 are forced to 1 by hardware (TLI)
ITC_SPR8 bits 7:4 are forced to 1 by hardware.

Note: It is forbidden to write 10 (priority level 0). If 10 is written, the previous value is kept

and the interrupt priority remains unchanged.

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RM0016 Interrupt controller (ITC)

6.9.3 External interrupt control register 1 (EXTI_CR1)

Address offset: 0x00

Reset value: 0x00

76543210

PDIS[1:0] PCIS[1:0] PBIS[1:0] PAIS[1:0]

rw rw rw rw

Bits 7:6 PDIS[1:0]: Port D external interrupt sensitivity bits

These bits can only be written when I1 and I0 in the CCR register are both set to 1 (level 3).
They define the sensitivity of Port D external interrupts.

00: Falling edge and low level
01: Rising edge only
10: Falling edge only
11: Rising and falling edge

Bits 5:4 PCIS[1:0]: Port C external interrupt sensitivity bits

These bits can only be written when I1 and I0 in the CCR register are both set to 1 (level 3).
They define the sensitivity of Port C external interrupts.

00: Falling edge and low level
01: Rising edge only
10: Falling edge only
11: Rising and falling edge

Bits 3:2 PBIS[1:0]: Port B external interrupt sensitivity bits

These bits can only be written when I1 and I0 in the CCR register are both set to 1 (level 3).
They define the sensitivity of Port B external interrupts.

00: Falling edge and low level
01: Rising edge only
10: Falling edge only
11: Rising and falling edge

Bits 1:0 PAIS[1:0]: Port A external interrupt sensitivity bits

These bits can only be written when I1 and I0 in the CCR register are both set to 1 (level 3).
They define the sensitivity of Port A external interrupts.
00: Falling edge and low level
01: Rising edge only
10: Falling edge only
11: Rising and falling edge

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Interrupt controller (ITC) RM0016

6.9.4 External interrupt control register 1 (EXTI_CR2)

Address offset: 0x01

Reset value: 0x00

76543210

Reserved

Bits 7:3 Reserved.

Bit 2 TLIS: Top level interrupt sensitivity

This bit is set and cleared by software. This bit can be written only when external interrupt
is disabled on the corresponding GPIO port (PD7 or PC3, refer to Section 6.6: External

interrupts on page 65).

0: Falling edge
1: Rising edge

Bits 1:0 PEIS[1:0]: Port E external interrupt sensitivity bits

These bits can only be written when I1 and I0 in the CCR register are both set to 1 (level 3).
They define the sensitivity of the Port E external interrupts.
00: Falling edge and low level
01: Rising edge only
10: Falling edge only
11: Rising and falling edge

TLIS PEIS[1:0]

rw rw

70/449 Doc ID 14587 Rev 8

RM0016 Interrupt controller (ITC)

6.9.5 ITC and EXTI register map and reset values

Table 12. Interrupt register map

Add.

offset

ITC-SPR block

0x00

0x01

0x02

0x03

0x04

0x05

0x06

0x07

ITC-EXTI block

0x00 EXTI_CR1

0x01 EXTI_CR2

1. The address offsets are expressed for the ITC-SPR block base address (see CPU/SWIM/debug module/interrupt controller registers table in the
datasheet).

Register

name

(1)

ITC_SPR1

Reset value

ITC_SPR2

Reset value

ITC_SPR3

Reset value

ITC_SPR4

Reset value

ITC_SPR5

Reset value

ITC_SPR6

Reset value

ITC_SPR7

Reset value

ITC_SPR8

Reset value

(2)

76543210

VECT3SPR11VECT3SPR01VECT2SPR11VECT2SPR01VECT1SPR11VECT1SPR01Reserved

1

VECT7SPR11VECT7SPR01VECT6SPR11VECT6SPR01VECT5SPR11VECT5SPR01VECT4SPR11VECT4SPR0

VECT11SPR11VECT11SPR01VECT10SPR11VECT10SPR01VECT9SPR11VECT9SPR01VECT8SPR11VECT8SPR0

VECT15SPR11VECT15SPR01VECT14SPR11VECT14SPR01VECT13SPR11VECT13SPR01VECT12SPR11VECT12SPR0

VECT19SPR11VECT19SPR01VECT18SPR11VECT18SPR01VECT17SPR11VECT17SPR01VECT16SPR11VECT16SPR0

VECT23SPR11VECT23SPR0

VECT22SPR11VECT22SPR01VECT21SPR11VECT21SPR01VECT20SPR11VECT20SPR0

1

VECT27SPR11VECT27SPR01VECT26SPR11VECT26SPR01VECT25SPR11VECT25SPR01VECT24SPR11VECT24SPR0

------

PDIS1

0

-

0

PDIS0

0

­000-0

PCIS1

0

PCIS0

0

PBIS1

0

PBIS0

TLIS

VECT28SPR11VECT28SPR0

0

0

PA IS 1

0

PEIS1

0

2. The address offsets are expressed for the ITC-EXTI block base address (see General hardware register map table in the datasheet).

Reserved

1

1

1

1

1

1

1

1

PA IS 0

0

PEIS0

0

Doc ID 14587 Rev 8 71/449

Power supply RM0016

Low Power Voltage Regulator

V

DD

V

CAP

V

DDIO

Main Voltage Regulator

I/O buffers

MCU core

1.8V

3V-5.5V

RAM

Flash

3V-5.5V

A/D converter

V

DDA

V

SSA

3V-5.5V

V

REF+

V

REF-

CPU

V

18

7 Power supply

The MCU has four distinct power supplies:

● V

DD/VSS

● V

DDIO/VSSIO

● V

DDA/VSSA

● V

REF+/VREF-

The V

DD/VSS

internal Low Power Voltage Regulator (LPVR). The 2 regulator outputs are connected and
provide the 1.8 V supply (V

In low power modes the system automatically switches from the MVR to the LPVR in order
to reduce current consumption.

To stabilize the MVR, a capacitor must be connected to the VCAP pin (for more details refer
to the datasheet electrical characteristics section).

Depending on the package size, there are one or two pairs of dedicated pins for
V

DDIO/VSSIO

V

DDA/VSSA

: Main power supply (3 V to 5.5 V)

: I/O power supply (3 V to 5.5 V)

: Power supply for the analog functions

: Reference supply for Analog Digital Converter

pins are used to supply the internal Main Voltage Regulator (MVR) and the

) to the MCU core (CPU, Flash and RAM)

18

to supply power to the I/Os.

and V

REF+/VREF-

are connected to the Analog to Digital Converter (ADC).

Figure 17. Power supply overview

72/449 Doc ID 14587 Rev 8

RM0016 Reset (RST)

NRST

R

PU

V

DD_IO

PULSE

GENERATOR

SWIM RESET

EXTERNAL

RESET

(min 20 µs)

SYSTEM NRESET

ILLEGAL OPCODE RESET
EMC RESET

IWDG/WWDG/SOFTWARE RESET

POR/BOR RESET

Filter

(typ 45 kΩ)

8 Reset (RST)

There are 9 reset sources:

● External reset through the NRST pin

● Power-on reset (POR)

● Brown-out Reset (BOR)

● Independent watchdog reset (IWDG)

● Window watchdog reset (WWDG)

● Software reset

● SWIM reset

● Illegal opcode reset

● EMC reset: generated if critical registers are corrupted or badly loaded

These sources act on the RESET

pin and it is always kept low during the delay phase. The

RESET service routine vector is fixed at address 6000h in the memory map.

Figure 18. Reset circuit

8.1 “Reset state” and “under reset” definitions

When a reset occurs, there is a reset phase from the external pin pull-down to the internal
reset signal release. During this phase, the microcontroller sets some hardware
configurations before going to the reset vector.

At the end of this phase, most of the registers are configured with their “reset state” values.
During the reset phase, i.e. “under reset”, some pin configurations may be different from
their “reset state” configuration.

8.2 Reset circuit description

The NRST pin is both an input and an open-drain output with integrated RPU weak pull-up
resistor.

The low pulse of duration t
reset detection is asynchronous and therefore the MCU can enter reset even in Halt mode.

The NRST pin also acts as an open-drain output for resetting external devices.

INFP(NRST)

Doc ID 14587 Rev 8 73/449

on the NRST pin generates an external reset. The

Reset (RST) RM0016

V

DD/VDDIO

NRST

V

IT+

V

IT-

An internal temporization maintains a pulse of duration t

OP(NRST)

source. An additional internal weak pull-up ensures a high level on the reset pin when the
reset is not forced.

8.3 Internal reset sources

Each internal reset source is linked to a specific flag bit in the Reset status register

(RST_SR) except POR/BOR which have no flag. These flags are set respectively at reset

depending on the given reset source. So they are used to identify the last reset source. They
are cleared by software writing the logic value “1”.

8.3.1 Power-on reset (POR) and brown-out reset (BOR)

During power-on, the POR keeps the device under reset until the supply voltages (V
V

) reach the voltage level at which the BOR starts to function. At this point, the BOR

DDIO

reset replaces the POR and the POR is automatically switched off. The BOR reset is
maintained till the supply voltage reaches the operating voltage range.

See Electrical parameters section of the datasheet for more details.

The BOR also generates a reset when the supply voltage drops below the V
When this occurs, the POR is re-armed for the next power-on phase.

An hysteresis is implemented to ensure clean detection of voltage rise and fall.

The BOR always remains active even when the MCU is put into Low Power mode.

whatever the internal reset

DD and

threshold.

IT-

Figure 19. V

DD/VDDIO

voltage detection: POR/BOR threshold

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RM0016 Reset (RST)

8.3.2 Watchdog reset

Refer to Section 15: Window watchdog (WWDG) and Section 14: Independent watchdog

(IWDG) for details.

8.3.3 Software reset

The application software can trigger reset by clearing bit T6 in the WWDG_CR register.
Refer to Section 15: Window watchdog (WWDG).

8.3.4 SWIM reset

An external device connected to the SWIM interface can request the SWIM block to
generate an MCU reset.

8.3.5 Illegal opcode reset

In order to provide enhanced robustness to the device against unexpected behavior, a
system of illegal opcode detection is implemented. If a code to be executed does not
correspond to any opcode or prebyte value, a reset is generated. This, combined with the
Watchdog, allows recovery from an unexpected fault or interference.

Note: A valid prebyte associated with a valid opcode forming an unauthorized combination does

not generate a reset.

8.3.6 EMC reset

To protect the application against spurious write access or system hang-up, possibly caused
by electromagnetic disturbance, the most critical registers are implemented as two bitfields
that must contain complementary values. Mismatches are automatically detected by this
mechanism, triggering an EMC reset and allowing the application to cleanly recover normal
operations.

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Reset (RST) RM0016

8.4 RST register description

8.4.1 Reset status register (RST_SR)

Address offset: 0x00

Reset value: 0xXX

76543210

Reserved

EMCF SWIMF ILLOPF IWDGF WWDGF

rc_w1 rc_w1 rc_w1 rc_w1 rc_w1

Bits 7:5 Reserved.

Bit 4 EMCF: EMC reset flag

This bit is set by hardware and cleared by software writing “1”.
0: No EMC reset occurred
1: An EMC reset occurred (possible cause: complementary register or option byte mismatch).

Bit 3 SWIMF: SWIM reset flag

This bit is set by hardware and cleared by software writing “1”.
0: No SWIM reset occurred
1: A SWIM reset occurred

Bit 2 ILLOPF: Illegal opcode reset flag

This bit is set by hardware and cleared by software writing “1”.
0: No ILLOP reset occurred
1: An ILLOP reset occurred

Bit 1 IWDGF: Independent Watchdog reset flag

This bit is set by hardware and cleared by software writing “1”.
0: No IWDG reset occurred
1: An IWDG reset occurred

Bit 0 WWDGF: Window Watchdog reset flag

This bit is set by hardware and cleared by software writing “1”.
0: No WWDG reset occurred
1: An WWDG reset occurred

8.5 RST register map

Refer to the corresponding datasheet for the base address.

Table 13. RST register map

Address

offset

0x00

76/449 Doc ID 14587 Rev 8

Register Name765432 1 0

RST_SR

Reset value

-

x

-

x

-

x

EMCFxSWIMFxILLOPFxIWDGF

x

WWDGF

x

RM0016 Clock control (CLK)

9 Clock control (CLK)

The clock controller is designed to be powerful, very robust, and at the same time easy to
use. Its purpose is to allow you to obtain the best performance in your application while at
the same time get the full benefit of all the microcontroller’s power saving capabilities.

You can manage all the different clock sources independently and distribute them to the
CPU and to the various peripherals. Prescalers are available for the master and CPU clocks.

A safe and glitch-free switch mechanism allows you to switch the master clock on the fly
from one clock source to another one.

EMC-hardened clock configuration registers

To protect the application against spurious write access or system hang-up, possibly caused
by electromagnetic disturbance, the most critical CLK registers are implemented as two
bitfields that must contain complementary values. Mismatches are automatically detected
by the CLK, triggering an EMC reset and allowing the application to cleanly recover normal
operations. See CLK register description for more details.

Doc ID 14587 Rev 8 77/449

Clock control (CLK) RM0016

HSE OSC

1-24MHz

OSCIN

OSCOUT

HSI RC
16 MHz

LSI RC

128 kHz

/1

/2

/4

/8

fMASTER

fHSE

fHSIDIV

fLSI

HSIDIV[1:0]

/1

/2

/4

/8

/16

/32

/64

/128

CPUDIV[2:0]

fCPU

CKM[7:0]

to Timers

Peripheral clock

To CPU and

To independent watchdog

window watchdog

I2C
SPI
ADC
AWU
CAN

CCO

fHSI
fHSIDIV
fHSE
fLSI
fMASTER
fCPU
fCPU/2
fCPU/4
fCPU/8
fCPU/16
fCPU/32
fCPU/64

Configurable clock output

CCOSEL[3:0]

Master
Clock
Switch

enable (8 bits)

To auto wakeup unit (AWU)

HSE Ext.

EXTCLK OPT BIT

CKAWUSEL OPT BIT

128 kHz

PRSC(1:0) OPT BITS

fHSI

CSS

LSI_EN OPT BIT

UART

Figure 20. Clock tree

1. Legend: HSE = High speed external clock signal; HSI = High speed internal clock signal; LSI = Low Speed internal clock

signal.

78/449 Doc ID 14587 Rev 8

RM0016 Clock control (CLK)

OSCOUT

EXTERNAL

SOURCE

(I/O available)

OSCIN OSCOUT

LOAD

CAPACITORS

C

L2

C

L1

9.1 Master clock sources

4 different clock sources can be used to drive the master clock:

● 1-24 MHz high speed external crystal oscillator (HSE)

● Up to 24 MHz high speed user-external clock (HSE user-ext)

● 16 MHz high speed internal RC oscillator (HSI)

● 128 kHz low speed internal RC (LSI)

Each clock source can be switched on or off independently when it is not used, to optimize
power consumption.

9.1.1 HSE

The high speed external clock signal (HSE) can be generated from two possible clock
sources:

● HSE external crystal/ceramic resonator

● HSE user external clock

Figure 21. HSE clock sources

Hardware configuration

External clockCrystal/ceramic resonators

The resonator and the load capacitors have to be placed as close as possible to the
oscillator pins in order to minimize output distortion and start-up stabilization time. The
loading capacitance values must be adjusted according to the selected oscillator.

Doc ID 14587 Rev 8 79/449

Clock control (CLK) RM0016

External crystal/ceramic resonator (HSE crystal)

The 1 to 24 MHz external oscillator has the advantage of producing a very accurate rate on
the main clock with 50% duty cycle.

The associated hardware configuration is shown in Figure 21. Refer to the electrical
characteristics section for more details.

At start up the clock signal produced by the oscillator is not stable, and by default a delay of
2048 osc cycles is inserted before the clock signal is released. You can program a shorter
stabilization time in the HSECNT option byte, please refer to option bytes section in the
datasheet.

The HSERDY flag in the External clock register (CLK_ECKR) indicates if the high-speed
external oscillator is stable or not. At startup, the clock is not released until this bit is set by
hardware.

The HSE Crystal can be switched on and off using the HSEEN bit in the External clock

register (CLK_ECKR).

External source (HSE user-ext)

In this mode, an external clock source must be provided. It can have a frequency of up to
24 MHz. You select this mode by programming the EXTCLK option bit. Refer to the option
bytes section of the datasheet. The external clock signal (square, sinus or triangle) with
~50% duty cycle has to drive the OSCIN pin while the OSCOUT pin is available as standard
I/O (see Figure 20).

Note: For clock frequencies above 16 MHz, Flash /data EEPROM access must be configured for 1

wait state. This is enabled by the device option byte. Refer to the datasheet option byte
section.

9.1.2 HSI

The HSI clock signal is generated from an internal 16 MHz RC oscillator together with a
programmable divider (factor 1 to 8). This is programmed in the Clock divider register

(CLK_CKDIVR).

Note: At startup the master clock source is automatically selected as HSI RC clock output divided

by 8 (f

The HSI RC oscillator has the advantage of providing a 16 MHz master clock source with
50% duty cycle at low cost (no external components). It also has a faster startup time than
the HSE crystal oscillator however, even with calibration the frequency is less accurate than
an external crystal oscillator or ceramic resonator.

The HSIRDY flag in the Internal clock register (CLK_ICKR) indicates if the HSI RC is stable
or not. At startup, the HSI RC output clock is not released until this bit is set by hardware.

The HSI RC can be switched on and off using the HSIEN bit in the Internal clock register

(CLK_ICKR).

Backup source

The HSI/8 signal can also be used as a backup source (Auxiliary clock) if the HSE crystal
oscillator fails. Refer to Section 9.6: Clock security system (CSS).

HSI

/8).

80/449 Doc ID 14587 Rev 8

RM0016 Clock control (CLK)

Fast wakeup feature

If the FHWU bit in the Internal clock register (CLK_ICKR) is set, this automatically selects
the HSI clock as master clock after MCU wakeup from Halt or Active-halt (see Low power
chapter).

Calibration

Each device is factory calibrated by ST.

After reset, the factory calibration value is automatically loaded in an internal calibration
register.

If the application is subject to voltage or temperature variations this may affect the RC
oscillator speed. You can trim the HSI frequency in the application using the HSI clock

calibration trimming register (CLK_HSITRIMR). In this register there are 3 or 4 bits providing

an additional trimming value that is added to the internal HSI calibration register value.

The width of the trimming steps with 4 bits is half the trimming step width with 3 bits.

Table 14. Devices with 4 trimming bits

Trimming bits value Trimming steps Trimming bits value Trimming steps

0111b +6 1111b -1

0101b +5 1110b -2

9.1.3 LSI

0100b +4 1101b -3

0011b +3 1100b -4

0010b +2 1011b -5

0001b +1 1010b -6

0000b 0 1001b -7

Table 15. Devices with 3 trimming bits

Trimming bits value Trimming steps Trimming bits value Trimming steps

011b +3 111b -1

010b +2 110b -2

001b +1 101b -3

000b 0 100b -4

As the trimming step width depends on the absolute frequency of the RC oscillator, a
successive approximation method needs to be applied for the trimming. This method is
described in a separate technical document.

The 128 kHz LSI RC acts as a low power, low cost alternative master clock source as well
as a low power clock source that can be kept running in Halt mode for the independent
watchdog (IWDG) and auto-wakeup unit (AWU).

The LSI RC can be switched on and off using the LSIEN bit in the Internal clock register

(CLK_ICKR).

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Clock control (CLK) RM0016

The LSIRDY flag in the Internal clock register (CLK_ICKR) indicates if the low-speed
internal oscillator is stable or not. At startup, the clock is not released until this bit is set by
hardware.

Calibration

Like the HSI RC, the LSI RC device is factory calibrated by ST. However, it is not possible to
perform further trimming.

Note: When using the independent watchdog with the LSI as clock source, in order to guarantee

that the CPU will never run on the same clock in case of corruption, the LSI clock cannot be
the master clock if LSI_EN option bit is reset. Refer to the option bytes section in the
datasheet.

9.2 Master clock switching

The clock switching feature provides an easy to use, fast and secure way for the application
to switch from one master clock source to another.

9.2.1 System startup

For fast system startup, after a reset the clock controller configures the master clock source
as HSI RC clock output divided by 8 (HSI/8). This is to take advantage of the short
stabilization time of the HSI oscillator. The /8 divider is to ensure safe start-up in case of
poor V

Once the master clock is released, the user program can switch the master clock to another
clock source.

conditions.

DD

9.2.2 Master clock switching procedures

To switch clock sources, you can proceed in one of two ways:

● Automatic switching

● Manual switching

Automatic switching

The automatic switching enables, the user to launch a clock switch with a minimum number
of instructions. The software can continue doing other operations without taking care of the
switch event exact time.

To enable automatic switching, follow the sequence below (refer to the flowchart in

Figure 22):

1. Enable the switching mechanism by setting the SWEN bit in the Switch control register

(CLK_SWCR).

2. Write the 8-bit value used to select the target clock source in the Clock master switch

register (CLK_SWR). The SWBSY bit in the CLK_SWCR register is set by hardware,

and the target source oscillator starts. The old clock source continues to drive the CPU
and peripherals.

As soon as the target clock source is ready (stabilized), the content of the CLK_SWR
register is copied to the Clock master status register (CLK_CMSR).

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RM0016 Clock control (CLK)

The SWBSY bit is cleared and the new clock source replaces the old one. The SWIF flag in
the CLK_SWCR is set and an interrupt is generated if the SWIEN bit is set.

Manual switching

The manual switching is not as immediate as the automatic switching but it offers to the user
a precise control of the switch event time.

To enable manual switching, follow the sequence below (refer to the flowchart in Figure 23):

1. Write the 8-bit value used to select the target clock source in the Clock master switch

register (CLK_SWR). Then the SWBSY bit is set by hardware, and the target source

oscillator starts. The old clock source continues to drive the CPU and peripherals.

2. The software has to wait until the target clock source is ready (stabilized). This is
indicated by the SWIF flag in the CLK_SWCR register and by an interrupt if the SWIEN
bit is set.

3. The final software action is to set, at the chosen time, the SWEN bit in the CLK_SWCR
register to execute the switch.

In both manual and automatic switching modes, the old master clock source will not be
powered off automatically in case it is required by other blocks (the LSI RC may be used to
drive the independent watchdog for example). The clock source can be powered off using
the bits in the Internal clock register (CLK_ICKR) and External clock register (CLK_ECKR).

If the clock switch does not work for any reason, software can reset the current switch
operation by clearing the SWBSY flag. This will restore the CLK_SWR register to its
previous content (old master clock).

Doc ID 14587 Rev 8 83/449

Clock control (CLK) RM0016

Reset

MCU in Run mode with HSI/8

Write target clock source in CLK_SWR

Target clock source ready after

CLK_SWR

CLK_CMSR

SWBSY

0

Set SWEN bit in CLK_SWCR

Target clock source powered on

SWBSY

1

stabilization time

Switch busy

MCU in Run mode

with new master clock source

SOFTWARE ACTIONHARDWARE ACTION

Reset switch busy flag

Update clock master status

Clear SWIF flag

Set SWIEN bit in CLK_SWCR to enable interrupt if suitable

Interrupt if activated

SWIF

1

Switch done

Figure 22. Clock switching flowchart (automatic mode example)

84/449 Doc ID 14587 Rev 8

RM0016 Clock control (CLK)

Reset

MCU in Run mode with HSI/8

Write target clock source in CLK_SWR

Target clock source ready after

CLK_SWR

CLK_CMSR

SWBSY

0

Target clock source powered on

SWIF

SWBSY 1

stabilization time

Switch busy

1

MCU in Run mode

with new master clock source

SOFTWARE ACTIONHARDWARE ACTION

Reset switch busy flag

Update clock master status

Clear SWIF flag

Set SWIEN bit in CLK_SWCR to enable interrupt if suitable

Set SWEN bit in CLK_SWCR to execute switch

Interrupt if activated

Ready for the switch

Figure 23. Clock switching flowchart (manual mode example)

9.3 Low speed clock selection

divided according to the CKAWUSEL option bit. Refer to option bytes section in the
datasheet.

The Low speed clock source for the AWU or the independent watchdog can be LSI or HSE

The division factor for HSE has to be programmed in the HSEPRSC[1:0] option bits Refer to
in the option bytes section of the datasheet. The goal is to get 128 kHz at the output of the
HSE prescaler.

9.4 CPU clock divider

The CPU clock (f
programmed in the CPUDIV[2:0] bits in the Clock divider register (CLK_CKDIVR). Seven
division factors (1 to 128 in steps of power of 2) can be selected (refer to Figure 20).

The f

signal is the clock for both the CPU and the window watchdog.

CPU

) is derived from the master clock (f

CPU

MASTER

), divided by a factor

Doc ID 14587 Rev 8 85/449

Clock control (CLK) RM0016

9.5 Peripheral clock gating (PCG)

Gating the clock to unused peripherals helps reduce power consumption. Peripheral clock
Gating (PCG) mode allows you to selectively enable or disable the f

MASTER

connection to the following peripherals at any time in Run mode:

● ADC

● I2C

● AWU (register clock, not counter clock)

● SPI

● TIM[4:1]

● UART

● CAN (register clock, not CAN clock)

After a device reset, all peripheral clocks are enabled. You can disable the clock to any
peripheral by clearing the corresponding PCKEN bit in the Peripheral clock gating register 1

(CLK_PCKENR1) and in the Peripheral clock gating register 2 (CLK_PCKENR2). But you

have to disable properly the peripheral using the appropriate bit, before stopping the
corresponding clock.

To enable a peripheral, you must first enable the corresponding PCKEN bit in the
CLK_PCKENR registers and then set the peripheral enable bit in the peripheral’s control
registers.

clock

The AWU counter is driven by an internal or external clock (LSI or HSE) independent from
f

MASTER

, so that it continues to run even if the register clock to this peripheral is switched off.

86/449 Doc ID 14587 Rev 8

RM0016 Clock control (CLK)

9.6 Clock security system (CSS)

The Clock Security System (CSS) monitors HSE crystal clock source failures. When
f

MASTER

broken or disconnected resonator or any other reason, the clock controller activates a stall­safe recovery mechanism by automatically switching f
(HSI/8). Once selected the auxiliary clock source remains enabled until the MCU is reset.

You enable the clock security system by setting the CSSEN bit in the Clock security system

register (CLK_CSSR). For safety reason, once CSS is enabled it cannot be disabled until

the next reset.

The following conditions must be met so that the CSS can detect HSE quartz crystal
failures:

● HSE crystal on: (HSEEN = 1 in the External clock register (CLK_ECKR))

● HSE oscillator in quartz crystal configuration (EXTCLK option bit is reset)

● CSS function enabled: (CSSEN = 1 in the CLK_CSSR register)

If HSE is the current clock master when a failure is detected, the CSS performs the following
actions:

● The CSSD bit is set in the CLK_CSSR register and an interrupt is generated if the

● The Clock master status register (CLK_CMSR), Clock master switch register

● The HSIEN bit in the Internal clock register (CLK_ICKR) register is set (HSI on).

● The HSEEN bit in the External clock register (CLK_ECKR) is cleared (HSE off)

● The AUX bit is set to indicate that the HSI/8 auxiliary clock source is forced.

depends on HSE crystal, i.e. when HSE is selected, if the HSE clock fails due to a

MASTER

to the auxiliary clock source

CSSIEN bit is set.

(CLK_SWR) register and the HSIDIV[1:0] bits in the Clock divider register
(CLK_CKDIVR) are set to their reset values (CKM[7:0]= SWI[7:0]=E1h). HSI/8

becomes the master clock.

You can clear the CSSD bit by software but the AUX bit is cleared only by reset.

To select a faster clock speed, you can modify the HSIDIV[1:0] bits in the CLK_CKDIVR
register after the CSSD bit in the CLK_CSSR register is cleared.

If HSE is not the current clock master when a failure is detected, the master clock is not
switched to the auxiliary clock and none of the above actions are performed except:

● The HSEEN bit is cleared in the CLK_ECKR register, HSE is then switched OFF

● The CSSD bit is set in the CLK_CSSR register and interrupt is generated if CSSDIE is

also set, it can be cleared by software.

If HSE is not the current clock master and the master clock switch to HSE is ongoing, the
SWBSY bit in the CLK_SWCR register must be cleared by software before clearing the
CSSD bit.

If HSE is selected by CCOSEL to be in output mode (see Clock-out capability (CCO)) when
a failure is detected, the selection is automatically changed to force HSI (HSIDIV) instead of
HSE.

Doc ID 14587 Rev 8 87/449

Clock control (CLK) RM0016

9.7 Clock-out capability (CCO)

The configurable Clock Output (CCO) capability allows you to output a clock on the external
CCO pin. You can select one of 6 clock signals as CCO clock:

● f

HSE

●

f

HSI

●

f

HSIDIV

●

f

LSI

●

f

MASTER

●

f

(with current prescaling selection)

CPU

Note: 50% duty cycle is not guaranteed on all possible prescaled values

The selection is controlled by the CCOSEL[3:0] bits in the Configurable clock output register

(CLK_CCOR).

The user has to select first the desired clock for the dedicated I/O pin (see Pin Description
chapter). This I/O must be set at 1 in the corresponding Px_CR1 register to be set as input
with pull-up or push-pull output.

The sequence to really output the chosen clock starts with CCOEN=1 in Configurable clock

output register (CLK_CCOR).

The CCOBSY is set to indicate that the configurable clock output system is operating. As
long as the CCOBSY bit is set, the CCOSEL bits are write protected.

The CCO automatically activates the target oscillator if needed. The CCORDY bit is set
when the chosen clock is ready.

To disable the clock output the user has to clear the CCOEN bit. Both CCOBSY and
CCORDY remain at 1 till the shut down is completed. The time between the clear of CCOEN
and the reset of the two flags can be relatively long, for instance in case the selected clock
output is very slow compared to f

9.8 CLK interrupts

The following interrupts can be generated by the clock controller:

● Master clock source switch event

● Clock Security System event

Both interrupts are individually maskable.

Table 16. CLK interrupt requests

Interrupt event

CSS event CSSD CSSDIE Yes No

Master clock switch event SWIF SWIEN Yes No

CPU

.

Event

flag

Enable
control

bit

Exit

from

wait

Exit

from

Halt

88/449 Doc ID 14587 Rev 8

RM0016 Clock control (CLK)

9.9 CLK register description

9.9.1 Internal clock register (CLK_ICKR)

Address offset: 0x00

Reset value: 0x01

76543210

Reserved

REGAH LSIRDY LSIEN FHW HSIRDY HSIEN

rw r rw rw r rw

Bits 7:6 Reserved, must be kept cleared.

Bit 5 REGAH: Regulator power off in Active-halt mode

This bit is set and cleared by software. When it is set, the main voltage regulator is powered off as
soon as the MCU enters Active-halt mode, so the wakeup time is longer.

0: MVR regulator ON in Active-halt mode
1: MVR regulator OFF in Active-halt mode

Bit 4 LSIRDY: Low speed internal oscillator ready

This bit is set and cleared by hardware.
0: LSI clock not ready
1: LSI clock ready

Bit 3 LSIEN: Low speed internal RC oscillator enable

This bit is set and cleared by software. It is set by hardware whenever the LSI oscillator is required,
for example:

– When switching to the LSI clock (see CLK_SWR register)
– When LSI is selected as the active CCO source (see CLK_CCOR register)
– When BEEP is enabled (BEEPEN bit set in the BEEP_CSR register)
– When LSI measurement is enabled (MSR bit set in the AWU_CSR register)

It cannot be cleared when LSI is selected as master clock source (CLK_CMSR register), as active
CCO source or as clock source for the AWU peripheral or independent Watchdog.
0: Low-speed internal RC off
1: Low-speed internal RC on

Bit 2 FHWU: Fast wakeup from Halt/Active-halt modes

This bit is set and cleared by software.
0: Fast wakeup from Halt/Active-halt modes disabled
1: Fast wakeup from Halt/Active-halt modes enabled

Bit 1 HSIRDY: High speed internal oscillator ready

This bit is set and cleared by hardware.
0: HSI clock not ready
1: HSI clock ready

Doc ID 14587 Rev 8 89/449

Clock control (CLK) RM0016

Bit 0 HSIEN: High speed internal RC oscillator enable

This bit is set and cleared by software. It is set by hardware whenever the HSI oscillator is required,
for example:

– When activated as safe oscillator by the CSS
– When switching to HSI clock (see CLK_SWR register)
– When HSI is selected as the active CCO source (see CLK_CCOR register)

It cannot be cleared when HSI is selected as clock master (CLK_CMSR register), as active CCO
source or if the safe oscillator (AUX) is enabled.

0: High-speed internal RC off
1: High-speed internal RC on

9.9.2 External clock register (CLK_ECKR)

Address offset: 0x01

Reset value: 0x00

76543210

Reserved

Bits 7:2 Reserved, must be kept cleared.

Bit 1 HSERDY: High speed external crystal oscillator ready

This bit is set and cleared by hardware.
0: HSE clock not ready
1: HSE clock ready (HSE clock is stabilized and available)

Bit 0 HSEEN: High speed external crystal oscillator enable

This bit is set and cleared by software. It can be used to switch the external crystal oscillator on or
off. It is set by hardware in the following cases:

– When switching to HSE clock (see CLK_SWR register)
– When HSE is selected as the active CCO source (see CLK_CCOR register)

It cannot be cleared when HSE is selected as clock master (indicated in CLK_CMSR register) or as
the active CCO source.

0: HSE clock off
1: HSE clock on

HSERDY HSEEN

rrw

90/449 Doc ID 14587 Rev 8

RM0016 Clock control (CLK)

9.9.3 Clock master status register (CLK_CMSR)

Address offset:0x03

Reset value: 0xE1

76543210

CKM[7:0]

rrrrrrrr

Bits 7:0 CKM[7:0]: Clock master status bits

These bits are set and cleared by hardware. They indicate the currently selected master clock
source. An invalid value occurring in this register will automatically generate an MCU reset.

0xE1: HSI selected as master clock source (reset value)
0xD2: LSI selected as master clock source (only if LSI_EN option bit is set)
0xB4: HSE selected as master clock source

9.9.4 Clock master switch register (CLK_SWR)

Address offset: 0x04

Reset value: 0xE1

76543210

SWI[7:0]

rw rw rw rw rw rw rw rw

Bits 7:0 SWI[7:0]: Clock master selection bits

These bits are written by software to select the master clock source. Its contents are write protected
while a clock switch is ongoing (while the SWBSY bit is set). They are set to the reset value (HSI) if
the AUX bit is set in the CLK_CSSR register. If Fast Halt wakeup mode is selected (FHW bit =1 in
CLK_ICKR register) then these bits are set by hardware to E1h (HSI selected) when resuming from
Halt/Active-halt mode.
0xE1: HSI selected as master clock source (reset value)
0xD2: LSI selected as master clock source (only if LSI_EN option bit is set)
0xB4: HSE selected as master clock source

Doc ID 14587 Rev 8 91/449

Clock control (CLK) RM0016

9.9.5 Switch control register (CLK_SWCR)

Address offset: 0x05

Reset value: 0xXX

76543210

Reserved

Bits 7:4 Reserved.

Bit 3 SWIF: Clock switch interrupt flag

This bit is set by hardware and cleared by software writing 0. Its meaning depends on the status of
the SWEN bit. Refer to Figure 22 and Figure 23.

● In manual switching mode (SWEN = 0):

0: Target clock source not ready
1: Target clock source ready

● In automatic switching mode (SWEN = 1):

0: No clock switch event occurred
1: Clock switch event occurred

Bit 2 SWIEN: Clock switch interrupt enable

This bit is set and cleared by software.
0: Clock switch interrupt disabled
1: Clock switch interrupt enabled

Bit 1 SWEN: Switch start/stop

This bit is set and cleared by software. Writing a 1 to this bit enables switching the master clock to
the source defined in the CLK_SWR register.

0: Disable clock switch execution
1: Enable clock switch execution

SWIF SWIEN SWEN SWBSY

rc_w0 rw rw rw

Bit 0 SWBSY: Switch busy

This bit is set and cleared by hardware. It can be cleared by software to reset the clock switch
process.
0: No clock switch ongoing
1: Clock switch ongoing

92/449 Doc ID 14587 Rev 8

RM0016 Clock control (CLK)

9.9.6 Clock divider register (CLK_CKDIVR)

Address offset: 0x06

Reset value: 0x18

76543210

Reserved

HSIDIV[1:0] CPUDIV[2:0]

rw rw rw rw rw

Bits 7:5 Reserved, must be kept cleared.

Bits 4:3 HSIDIV[1:0]: High speed internal clock prescaler

These bits are written by software to define the HSI prescaling factor.
00: f
01: f
10: f
11: f

HSI

HSI

HSI

HSI

= f
= f
= f
= f

HSI RC output

HSI RC output

HSI RC output

HSI RC output

/2
/4
/8

Bits 2:0 CPUDIV[2:0]: CPU clock prescaler

These bits are written by software to define the CPU clock prescaling factor.
000: f

CPU=fMASTER

001: f
010: f
011: f
100: f
101: f
110: f
111: f

CPU=fMASTER

CPU=fMASTER

CPU=fMASTER

CPU=fMASTER

CPU=fMASTER

CPU=fMASTER

CPU=fMASTER

/2
/4
/8
/16
/32
/64
/128

Doc ID 14587 Rev 8 93/449

Clock control (CLK) RM0016

9.9.7 Peripheral clock gating register 1 (CLK_PCKENR1)

Address offset: 0x07

Reset value: 0xFF

76543210

PCKEN1[7:0]

rw rw rw rw rw rw rw rw

Bits 7:0 PCKEN1[7:0]: Peripheral clock enable

These bits are written by software to enable or disable the f
peripheral (see Ta b le 1 7 ).

0: f

MASTER

1: f

MASTER

Table 17. Peripheral clock gating bits

to peripheral disabled

to peripheral enabled

Control bit Peripheral

PCKEN17 TIM1

MASTER

clock to the corresponding

PCKEN16 TIM3

PCKEN15 TIM2/TIM5 (product dependent)

PCKEN14 TIM4/ TIM6 (product dependent)

PCKEN13

PCKEN12

UART1/2/3 (product dependent, see datasheet

for bit assignment table)

PCKEN11 SPI

PCKEN10 I

2

C

94/449 Doc ID 14587 Rev 8

RM0016 Clock control (CLK)

9.9.8 Peripheral clock gating register 2 (CLK_PCKENR2)

Address offset: 0x0A

Reset value: 0xFF

76543210

PCKEN2[7:0]

rw rw rw rw rw rw rw rw

Bits 7:0 PCKEN2[7:0]: Peripheral clock enable

These bits are written by software to enable or disable the f
peripheral. See Ta b le 1 7

0: f

MASTER

1: f

MASTER

Table 18. Peripheral clock gating bits

to peripheral disabled

to peripheral enabled

Control bit Peripheral

PCKEN27 CAN (product dependent, see datasheet)

MASTER

clock to the corresponding

PCKEN26 Reserved

PCKEN25 Reserved

PCKEN24 Reserved

PCKEN23 ADC

PCKEN22 AWU

PCKEN21 Reserved

PCKEN20 Reserved

Doc ID 14587 Rev 8 95/449

Clock control (CLK) RM0016

9.9.9 Clock security system register (CLK_CSSR)

Address offset: 0x08

Reset value: 0x00

76543210

Reserved

CSSD CSSDIE AUX CSSEN

rc_w0 rw r rwo

Bits 7:4 Reserved, must be kept cleared.

Bit 3 CSSD: Clock security system detection

This bit is set by hardware and cleared by software writing 0.
0: CSS is off or no HSE crystal clock disturbance detected.
1: HSE crystal clock disturbance detected.

Bit 2 CSSDIE: Clock security system detection interrupt enable

This bit is set and cleared by software.
0: Clock security system interrupt disabled
1: Clock security system interrupt enabled

Bit 1 AUX: Auxiliary oscillator connected to master clock

This bit is set and cleared by hardware.
0: Auxiliary oscillator is off.
1: Auxiliary oscillator (HSI/8) is on and selected as current clock master source.

Bit 0 CSSEN: Clock security system enable

This bit can be read many times and be written once-only by software.
0: Clock security system off
1: Clock security system on

96/449 Doc ID 14587 Rev 8

RM0016 Clock control (CLK)

9.9.10 Configurable clock output register (CLK_CCOR)

Address offset: 0x09

Reset value: 0x00

76543210

Reserved

CCOBSY CCORDY CCOSEL[3:0] CCOEN

r r rw rw rw rw rw

Bit 7 Reserved, must be kept cleared.

Bit 6 CCOBSY: Configurable clock output busy

This bit is set and cleared by hardware. It indicates that the selected CCO clock source is being
switched-on and stabilized. While CCOBSY is set, the CCOSEL bits are write-protected. CCOBSY
remains set until the CCO clock is enabled.
0: CCO clock not busy
1: CCO clock busy

Bit 5 CCORDY: Configurable clock output ready

This bit is set and cleared by hardware. It indicates that the CCO clock is being output.
0: CCO clock not available
1: CCO clock available

Bits 4:1 CCOSEL[3:0]: Configurable clock output selection.

These bits are written by software to select the source of the output clock available on the CLK_CCO
pin. They are write-protected when CCOBSY is set.

0000: f

HSIDIV

0001: f

LSI

0010: f

HSE

0011: Reserved
0100: f

CPU

0101: f
0110: f
0111: f
1000: f
1001: f
1010: f
1011: f
1100: f
1101: f
1110: f
1111: f

/2

CPU

/4

CPU

/8

CPU

/16

CPU

/32

CPU

/64

CPU

HSI

MASTER

CPU

CPU

CPU

Bit 0 CCOEN: Configurable clock output enable

This bit is set and cleared by software.
0: CCO clock output disabled
1: CCO clock output enabled

Doc ID 14587 Rev 8 97/449

Clock control (CLK) RM0016

9.9.11 HSI clock calibration trimming register (CLK_HSITRIMR)

Address offset: 0x0C

Reset value: 0x00

76543210

Reserved

Bits 7:4 Reserved, must be kept cleared.

Bits 3:0 HSITRIM[3:0] HSI trimming value

These bits are written by software to fine tune the HSI calibration.

Note: In high density STM8S and STM8A devices, only bits 2:0 are available.

In other devices, bits 3:0 are available to achieve a better HSI resolution. Compatibility with bits
2:0 can be selected through options bytes (refer to datasheet).

HSITRIM[3:0]

rw rw rw rw

98/449 Doc ID 14587 Rev 8

RM0016 Clock control (CLK)

9.9.12 SWIM clock control register (CLK_SWIMCCR)

Address offset: 0x0D

Reset value: 0bXXXX XXX0

76543210

Bits 7:1 Reserved.

Bit 0 SWIMCLK SWIM clock divider

This bit is set and cleared by software.
0: SWIM clock divided by 2
1: SWIM clock not divided by 2

Reserved

SWIMCLK

rw

Doc ID 14587 Rev 8 99/449

Clock control (CLK) RM0016

9.10 CLK register map and reset values

Table 19. CLK register map and reset values

Address

offset

0x00

0x01

0x02 Reserved area (1 byte)

0x03

0x04

0x05

0x06

0x07

0x08

0x09

0x0A

0x0B Reserved area (1 byte)

0x0C

0x0D

Register name76543210

CLK_ICKR

Reset value

CLK_ECKR

Reset value

CLK_CMSR

Reset value

CLK_SWR

Reset value

CLK_SWCR

Reset value

CLK_CKDIVR

Reset value

CLK_PCKENR1

-

0

-

0

CKM7

1

SWI7

1

-

x

-

0

PCKEN171PCKEN161PCKEN151PCKEN141PCKEN131PCKEN121PCKEN111PCKEN10

-

0

-

0

CKM6

1

SWI6

1

-

x

-

0

REGAH

0

-

0

CKM5

1

SWI5

1

-

x

-

0

Reset value

CLK_CSSR

Reset value

CLK_CCOR

Reset value

CLK_PCKENR2

-

0

-

0

PCKEN271PCKEN261PCKEN251PCKEN241PCKEN231PCKEN221PCKEN211PCKEN20

-

0

CCOBSY

0

-

0

CCORDY0CCOSEL30CCOSEL20CCOSEL10CCOSEL00CCOEN

Reset value

CLK_HSITRIMR

Reset value

CLK_SWIMCCR

Reset value

-

0

-

x

-

0

-

x

-

0

-

x

LSIRDY

0

-

0

CKM4

0

SWI4

0

­x

HSIDIV1

1

-

0

-

0

­x

LSIEN

0

-

0

CKM3

0

SWI3

0

SWIF

x

HSIDIV01CPUDIV20CPUDIV120CPUDIV0

FHWU0HSIRDY0HSIEN

1

-

HSERDY0HSEEN

0

CKM2

0

SWI2

0

SWIEN

x

CKM1

0

SWI1

0

SWENxSWBSY

0

CKM0

1

SWI0

1

x

0

1

CSSD

0

CSSDIE

0

AUX

0

CSSEN

0

0

1

HSITRIM20HSITRIM10HSITRIM0

-

0

­x

-

x

-

x

0

SWIMCLK

0

100/449 Doc ID 14587 Rev 8