ST STM8L101F1, STM8L101F2, STM8L101F3, STM8L101G2, STM8L101G3 User Manual

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8-bit ultralow power microcontroller with up to 8 Kbytes Flash,

UFQFPN28

UFQFPN32

LQFP32

TSSOP20

UFQFPN20

Features

■ Main microcontroller features

– Supply voltage range 1.65 V to 3.6 V – Low power consumption (Halt: 0.3 µA,

Active-halt: 0.8 µA, Dynamic Run: 150 µA/MHz)

– STM8 Core with up to 16 CISC MIPS

throughput

– Temp. range: -40 to 85 °C and 125 °C

■ Memories

– Up to 8 Kbytes of Flash program including

up to 2 Kbytes of data EEPROM – Error correction code (ECC) – Flexible write and read protection modes – In-application and in-circuit programming – Data EEPROM capability – 1.5 Kbytes of static RAM

■ Clock management

– Internal 16 MHz RC with fast wakeup time

(typ. 4 µs) – Internal low consumption 38 kHz RC

driving both the IWDG and the AWU

■ Reset and supply management

– Ultralow power, ultrasafe power-on-reset

/power down reset – Three low power modes: Wait, Active-halt,

Halt

■ Interrupt management

– Nested interrupt controller with software

priority control – Up to 29 external interrupt sources

■ I/Os

– Up to 30 I/Os, all mappable on external

interrupt vectors – I/Os with prog. input pull-ups, high

sink/source capability and one LED driver

infrared output

STM8L101xx

multifunction timers, comparators, USART, SPI, I2C

■ Peripherals

– Two 16-bit general purpose timers (TIM2

and TIM3) with up and down counter and 2

channels (used as IC, OC, PWM) – One 8-bit timer (TIM4) with 7-bit prescaler – Infrared remote control (IR) – Independent watchdog – Auto-wakeup unit – Beeper timer with 1, 2 or 4 kHz frequencies – SPI synchronous serial interface – Fast I2C Multimaster/slave 400 kHz – USART with fractional baud rate generator – 2 comparators with 4 inputs each

■ Development support

– Hardware single wire interface module

(SWIM) for fast on-chip programming and

non intrusive debugging – In-circuit emulation (ICE)

■ 96-bit unique ID

Table 1. Device summary

Reference Part number

STM8L101F1, STM8L101F2,

STM8L101xx

STM8L101F3, STM8L101G2, STM8L101G3 STM8L101K3

October 2010 Doc ID 15275 Rev 11 1/81

www.st.com

Contents STM8L101xx

Contents

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3 Product overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3.1 Central processing unit STM8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3.2 Development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3.3 Single wire data interface (SWIM) and debug module . . . . . . . . . . . . . . . 10

3.4 Interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3.5 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

3.6 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

3.7 Voltage regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

3.8 Clock control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

3.9 Independent watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

3.10 Auto-wakeup counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

3.11 General purpose and basic timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

3.12 Beeper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

3.13 Infrared (IR) interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

3.14 Comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

3.15 USART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3.16 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3.17 I²C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

5 Memory and register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

6 Interrupt vector mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

7 Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

8 Unique ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

2/81 Doc ID 15275 Rev 11

STM8L101xx Contents

9 Electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

9.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

9.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

9.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

9.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

9.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

9.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

9.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

9.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

9.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

9.3.2 Power-up / power-down operating conditions . . . . . . . . . . . . . . . . . . . . 41

9.3.3 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

9.3.4 Clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

9.3.5 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

9.3.6 I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

9.3.7 Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

9.3.8 Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

9.3.9 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

9.4 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

10 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

10.1 ECOPACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

10.2 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

11 Device ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

12 STM8 development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

12.1 Emulation and in-circuit debugging tools . . . . . . . . . . . . . . . . . . . . . . . . . 74

12.2 Software tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

12.2.1 STM8 toolset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

12.2.2 C and assembly toolchains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

12.3 Programming tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

13 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Doc ID 15275 Rev 11 3/81

List of tables STM8L101xx

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table 2. Device features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Table 3. Legend/abbreviation for table 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Table 4. STM8L101xx pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Table 5. Flash and RAM boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 6. I/O Port hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 7. General hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 8. CPU/SWIM/debug module/interrupt controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 9. Interrupt mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 10. Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 11. Option byte description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 12. Unique ID registers (96 bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 13. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 14. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 15. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 16. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Table 17. Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Table 18. Total current consumption in Run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Table 19. Total current consumption in Wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 20. Total current consumption and timing in Halt and Active-halt mode at

VDD = 1.65 V to 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Table 21. Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Table 22. HSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table 23. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Table 24. RAM and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Table 25. Flash program memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Table 26. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Table 27. Output driving current (standard ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Table 28. Output driving current (true open drain ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Table 29. Output driving current (PA0 with high sink LED driver capability). . . . . . . . . . . . . . . . . . . . 53

Table 30. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Table 31. SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Table 32. I2C characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Table 33. Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Table 34. EMS data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Table 35. EMI data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Table 36. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Table 37. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Table 38. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Table 39. UFQFPN32 - 32-lead ultra thin fine pitch quad flat no-lead package (5 x 5),

package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Table 40. LQFP32- 32-pin low profile quad flat package (7x7), package mechanical data . . . . . . . . 69

Table 41. UFQFPN28 - 28-lead ultra thin fine pitch quad flat no-lead package (4 x 4),

Table 42. UFQFPN20 3 x 3 mm 0.6 mm mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Table 43. 20-lead thin shrink small package, mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Table 44. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

4/81 Doc ID 15275 Rev 11

STM8L101xx List of figures

List of figures

Figure 1. STM8L101xx device block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 2. Standard 20-pin UFQFPN package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 3. 20-pin UFQFPN package pinout for STM8L101F1U6ATR,

STM8L101F2U6ATR and STM8L101F3U6ATR part numbers. . . . . . . . . . . . . . . . . . . . . . 15

Figure 4. 20-pin TSSOP package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 5. Standard 28-pin UFQFPN package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 6. 28-pin UFQFPN package pinout for STM8L101G3U6ATR and

STM8L101G2U6ATR part numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 7. 32-pin package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 8. Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 9. Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 10. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Figure 11. IDD(RUN) vs. VDD, fCPU = 2 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Figure 12. IDD(RUN) vs. VDD, fCPU = 16 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Figure 13. IDD(WAIT) vs. VDD, fCPU = 2 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Figure 14. IDD(WAIT) vs. VDD, fCPU = 16 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Figure 15. Typ. IDD(Halt) vs. VDD, fCPU = 2 MHz and 16 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Figure 16. Typical HSI frequency vs. V Figure 17. Typical HSI accuracy vs. temperature, V

Figure 18. Typical HSI accuracy vs. temperature, VDD = 1.65 V to 3.6 V. . . . . . . . . . . . . . . . . . . . . . 47

Figure 19. Typical LSI RC frequency vs. VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Figure 20. Typical VIL and VIH vs. VDD (standard I/Os) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Figure 21. Typical VIL and VIH vs. VDD (true open drain I/Os). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Figure 22. Typical pull-up resistance R Figure 23. Typical pull-up current IPU vs. V

Figure 24. Typ. VOL at VDD = 3.0 V (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Figure 25. Typ. VOL at VDD = 1.8 V (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Figure 26. Typ. VOL at VDD = 3.0 V (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Figure 27. Typ. VOL at VDD = 1.8 V (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Figure 28. Typ. VDD - VOH at VDD = 3.0 V (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Figure 29. Typ. VDD - VOH at VDD = 1.8 V (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Figure 30. Typical NRST pull-up resistance R Figure 31. Typical NRST pull-up current I

Figure 32. Recommended NRST pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Figure 33. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Figure 34. SPI timing diagram - slave mode and CPHA = 1 Figure 35. SPI timing diagram - master mode

Figure 36. Typical application with I2C bus and timing diagram 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Figure 37. UFQFPN32 - 32-lead ultra thin fine pitch quad flat no-lead package outline (5 x 5). . . . . . 67

Figure 38. UFQFPN32 recommended footprint

Figure 39. LQFP32 - 32-pin low profile quad flat package outline (7 x 7) . . . . . . . . . . . . . . . . . . . . . . 69

Figure 40. LQFP32 recommended footprint Figure 41. UFQFPN28 - 28-lead ultra thin fine pitch quad flat no-lead package outline (4 x 4)

Figure 42. UFQFPN28 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Figure 43. UFQFPN20 3 x 3 mm 0.6 mm package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Figure 44. UFQFPN20 recommended footprint

Figure 45. TSSOP20 - 20-lead thin shrink small package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Figure 46. TSSOP20 recommended footprint

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

vs. VDD with VIN=VSS. . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

with VIN=VSS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

vs. VDD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

(1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

(1)

= 3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

vs. VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

(1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

(1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

(1)

. . . . 70

Doc ID 15275 Rev 11 5/81

List of figures STM8L101xx

Figure 47. STM8L101xx ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

6/81 Doc ID 15275 Rev 11

STM8L101xx Introduction

1 Introduction

This datasheet provides the STM8L101xx pinout, ordering information, mechanical and

electrical device characteristics.

For complete information on the STM8L101xx microcontroller memory, registers and

peripherals, please refer to the STM8L reference manual.

The STM8L101xx devices are members of the STM8L low power 8-bit family. They are

referred to as low-density devices in the STM8L101xx microcontroller family reference

manual (RM0013) and in the STM8L Flash programming manual (PM0054).

All devices of the SM8L product line provide the following benefits:

● Reduced system cost

– Up to 8 Kbytes of low-density embedded Flash program memory including up to

2 Kbytes of data EEPROM

– High system integration level with internal clock oscillators and watchdogs.

– Smaller battery and cheaper power supplies.

● Low power consumption and advanced features

– Up to 16 MIPS at 16 MHz CPU clock frequency

– Less than 150 µA/MH, 0.8 µA in Active-halt mode, and 0.3 µA in Halt mode

– Clock gated system and optimized power management

● Short development cycles

– Application scalability across a common family product architecture with

compatible pinout, memory map and modular peripherals.

– Full documentation and a wide choice of development tools

● Product longevity

– Advanced core and peripherals made in a state-of-the art technology

– Product family operating from 1.65 V to 3.6 V supply

2 Description

The STM8L101xx low power family features the enhanced STM8 CPU core providing

increased processing power (up to 16 MIPS at 16 MHz) while maintaining the advantages of

a CISC architecture with improved code density, a 24-bit linear addressing space and an

optimized architecture for low power operations.

The family includes an integrated debug module with a hardware interface (SWIM) which

allows non-intrusive in-application debugging and ultrafast Flash programming.

All STM8L101xx microcontrollers feature low power low-voltage single-supply program

Flash memory. The 8-Kbyte devices embed data EEPROM.

The STM8L101xx low power family is based on a generic set of state-of-the-art peripherals.

The modular design of the peripheral set allows the same peripherals to be found in different

ST microcontroller families including 32-bit families. This makes any transition to a different

Doc ID 15275 Rev 11 7/81

Description STM8L101xx

family very easy, and simplified even more by the use of a common set of development

tools.

All STM8L low power products are based on the same architecture with the same memory

mapping and a coherent pinout.

Table 2. Device features

Features STM8L101xx

Flash

2 Kbytes of Flash program

memory

4 Kbytes of Flash program

memory

RAM 1.5 Kbytes

Independent watchdog (IWDG), Auto-wakeup unit (AWU), Beep,

Peripheral functions

Serial peripheral interface (SPI), Inter-integrated circuit (I²C),

Universal synchronous / asynchronous receiver / transmitter (USART),

2 comparators, Infrared (IR) interface

Timers Two 16-bit timers, one 8-bit timer

Operating voltage 1.65 to 3.6 V

Operating temperature -40 to +85 °C

UFQFPN28 4x 4

Packages UFQFPN20 3x3

UFQFPN20 3x3

TSSOP20 4.4 x 6.4

8 Kbytes of Flash program

memory including up to

2 Kbytes of Data EEPROM

-40 to +85 °C or

-40 to +125 °C

UFQFPN28 4x4 UFQFPN20 3x3

UFQFPN32

LQFP32

8/81 Doc ID 15275 Rev 11

STM8L101xx Product overview

STM8

16 MHz int RC

Clock

controller

Clocks

AWU

Beeper

Address and data bus

38 kHz int RC

Debug module

I²C1

SPI

USART

Up to 8 Kbytes

Flash memory

controller

1.5 Kbytes

to core and peripherals

IWDG

Core

16-bit Timer 2

(SWIM)

up to 16 MHz

Nested interrupt

up to 29 external

multimaster

8-bit Timer 4

SRAM

interrupts

(including up to 2 Kbytes data EEPROM)

Power

Volt. reg.

DD18

=1.65 V

3.6 V

NRST

POR/PDR

Reset

COMP1

COMP2

Port A

Port B

Port C

Port D

RX, TX, CK

SDA, SCL

PA[6:0]

PB[7:0]

PC[6:0]

PD[7:0]

MOSI, MISO, SCK, NSS

BEEP

SWIM

COMP1_CH[4:1]

COMP_REF

Infrared interface

IR_TIM

16-bit Timer 3

TIM2_CH[2:1]

TIM3_CH[2:1]

TIM2_TRIG

TIM3_TRIG

COMP2_CH[4:1]

3 Product overview

Figure 1. STM8L101xx device block diagram

Legend:

AWU: Auto-wakeup unit Int. RC: internal RC oscillator I²C: Inter-integrated circuit multimaster interface POR/PDR: Power on reset / power down reset SPI: Serial peripheral interface SWIM: Single wire interface module USART: Universal synchronous / asynchronous receiver / transmitter IWDG: Independent watchdog

Doc ID 15275 Rev 11 9/81

Product overview STM8L101xx

3.1 Central processing unit STM8

The 8-bit STM8 core is designed for code efficiency and performance.

It features 21 internal registers, 20 addressing modes including indexed, indirect and relative addressing, and 80 instructions.

3.2 Development tools

Development tools for the STM8 microcontrollers include:

● The STice emulation system offering tracing and code profiling

● The STVD high-level language debugger including C compiler, assembler and

integrated development environment

● The STVP Flash programming software

The STM8 also comes with starter kits, evaluation boards and low-cost in-circuit debugging/programming tools.

3.3 Single wire data interface (SWIM) and debug module

The debug module with its single wire data interface (SWIM) permits non-intrusive real-time in-circuit debugging and fast memory programming.

The Single wire interface is used for direct access to the debugging module and memory programming. The interface can be activated in all device operation modes.

The non-intrusive debugging module features a performance close to a full-featured emulator. Beside memory and peripherals, also CPU operation can be monitored in realtime by means of shadow registers.

3.4 Interrupt controller

The STM8L101xx features a nested vectored interrupt controller:

● Nested interrupts with 3 software priority levels

● 26 interrupt vectors with hardware priority

● Up to 29 external interrupt sources on 10 vectors

● Trap and reset interrupts

10/81 Doc ID 15275 Rev 11

STM8L101xx Product overview

3.5 Memory

The STM8L101xx devices have the following main features:

● 1.5 Kbytes of RAM

● The EEPROM is divided into two memory arrays (see the STM8L reference manual for

details on the memory mapping):

– Up to 8 Kbytes of low-density embedded Flash program including up to 2 Kbytes

of data EEPROM. Data EEPROM and Flash program areas can be write protected independently by using the memory access security mechanism (MASS).

– 64 option bytes (one block) of which 5 bytes are already used for the device.

Error correction code is implemented on the EEPROM.

3.6 Low power modes

To minimize power consumption, the product features three low power modes:

● Wait mode: CPU clock stopped, selected peripherals at full clock speed.

● Active-halt mode: CPU and peripheral clocks are stopped. The programmable wakeup

time is controlled by the AWU unit.

● Halt mode: CPU and peripheral clocks are stopped, the device remains powered on.

Wakeup is triggered by an external interrupt.

3.7 Voltage regulators

The STM8L101xx embeds an internal voltage regulator for generating the 1.8 V power supply for the core and peripherals.

This regulator has two different modes: main voltage regulator mode (MVR) and low power voltage regulator mode (LPVR). When entering Halt or Active-halt modes, the system automatically switches from the MVR to the LPVR in order to reduce current consumption.

3.8 Clock control

The STM8L101xx embeds a robust clock controller. It is used to distribute the system clock to the core and the peripherals and to manage clock gating for low power modes. This system clock is a 16-MHz High Speed Internal RC oscillator (HSI RC), followed by a programmable prescaler.

In addition, a 38 kHz low speed internal RC oscillator is used by the independent watchdog (IWDG) and Auto-wakeup unit (AWU).

3.9 Independent watchdog

The independent watchdog (IWDG) peripheral can be used to resolve processor malfunctions due to hardware or software failures.

It is clocked by the 38 kHZ LSI internal RC clock source, and thus stays active even in case of a CPU clock failure.

Doc ID 15275 Rev 11 11/81

Product overview STM8L101xx

3.10 Auto-wakeup counter

The auto-wakeup (AWU) counter is used to wakeup the device from Active-halt mode.

3.11 General purpose and basic timers

STM8L101xx devices contain two 16-bit general purpose timers (TIM2 and TIM3) and one 8-bit basic timer (TIM4).

16-bit general purpose timers

The 16-bit timers consist of 16-bit up/down auto-reload counters driven by a programmable prescaler. They perform a wide range of functions, including:

● Time base generation

● Measuring the pulse lengths of input signals (input capture)

● Generating output waveforms (output compare, PWM and One pulse mode)

● Interrupt capability on various events (capture, compare, overflow, break, trigger)

● Synchronization with other timers or external signals (external clock, reset, trigger and

enable)

8-bit basic timer

The 8-bit timer consists of an 8-bit up auto-reload counter driven by a programmable prescaler. It can be used for timebase generation with interrupt generation on timer overflow.

3.12 Beeper

The STM8L101xx devices include a beeper function used to generate a beep signal in the range of 1, 2 or 4 kHz when the LSI clock is operating at a frequency of 38 kHz.

3.13 Infrared (IR) interface

The STM8L101xx devices contain an infrared interface which can be used with an IR LED for remote control functions. Two timer output compare channels are used to generate the infrared remote control signals.

3.14 Comparators

The STM8L101xx features two zero-crossing comparators (COMP1 and COMP2) sharing the same current bias and voltage reference. The voltage reference can be internal (comparison with ground) or external (comparison to a reference pin voltage).

Each comparator is connected to 4 channels, which can be used to generate interrupt, timer input capture or timer break. Their polarity can be inverted.

12/81 Doc ID 15275 Rev 11

STM8L101xx Product overview

3.15 USART

The USART interface (USART) allows full duplex, asynchronous communications with external devices requiring an industry standard NRZ asynchronous serial data format. It offers a very wide range of baud rates.

3.16 SPI

The serial peripheral interface (SPI) provides half/ full duplex synchronous serial communication with external devices. It can be configured as the master and in this case it provides the communication clock (SCK) to the external slave device. The interface can also operate in multi-master configuration.

3.17 I²C

The inter-integrated circuit (I2C) bus interface is designed to serve as an interface between the microcontroller and the serial I

C bus. It provides multi-master capability, and controls all I²C bus-specific sequencing, protocol, arbitration and timing. It manages standard and fast speed modes.

Doc ID 15275 Rev 11 13/81

Pin description STM8L101xx

67 8

16171819

PD0 (HS) / TIM3_CH2 / COMP1_CH3

PA3 (HS)

PA2 (HS)

PB0 (HS) / TIM2_CH1 / COMP1_CH1

NRST / PA1 (HS)

PC3 (HS) / USART_TX

PC4 (HS) / USART_CK / CCO

PC2 (HS) / USART_RX

PC1 / I²C_SCL

PB4 (HS) / SPI_NSS

PB5 (HS) / SPI_SCK

PB6 (HS) / SPI_MOSI

PB7 (HS) / SPI_MISO

PC0 / I²C_SDA

PB1 (HS) / TIM3_CH1 /COMP1_CH2

PB2 (HS) / TIM2_CH2 / COMP2_CH1

PB3 (HS) / TIM2_TRIG / COMP2_CH2

PA0 (HS) / SWIM / BEEP / IR_TIM

4 Pin description

Figure 2. Standard 20-pin UFQFPN package pinout

1. HS corresponds to 20 mA high sink/source capability.

2. High sink LED driver capability available on PA0. Refer to the description of the IR_CR register in the

STM8L reference manual (RM0013).

Note: The COMP_REF pin is not available in this standard 20-pin UFQFPN package. It is available

on Port A6 in the 20-pin UFQFPN package pinout for STM8L101F1U6ATR,

STM8L101F2U6ATR and STM8L101F3U6ATR part numbers (Figure 3 on page 15).

14/81 Doc ID 15275 Rev 11

STM8L101xx Pin description

67 8

16171819

PD0 (HS) / TIM3_CH2 / COMP1_CH3

PA6 (HS) / COMP_REF

PA2 (HS)

PB0 (HS) / TIM2_CH1 / COMP1_CH1

NRST / PA1 (HS)

PC3 (HS) / USART_TX

PC4 (HS) / USART_CK / CCO

PC2 (HS) / USART_RX

PC1 / I²C_SCL

PB4 (HS) / SPI_NSS

PB5 (HS) / SPI_SCK

PB6 (HS) / SPI_MOSI

PB7 (HS) / SPI_MISO

PC0 / I²C_SDA

PB1 (HS) / TIM3_CH1 /COMP1_CH2

PB2 (HS) / TIM2_CH2 / COMP2_CH1

PB3 (HS) / TIM2_TRIG / COMP2_CH2

PA0 (HS) / SWIM / BEEP / IR_TIM

Figure 3. 20-pin UFQFPN package pinout for STM8L101F1U6ATR,

STM8L101F2U6ATR and STM8L101F3U6ATR part numbers

1. Please refer to the warning below.

2. HS corresponds to 20 mA high sink/source capability.

3. High sink LED driver capability available on PA0. Refer to the description of the IR_CR register in the

STM8L reference manual (RM0013).

Warning: For the STM8L101F1U6ATR, STM8L101F2U6ATR and

STM8L101F3U6ATR part numbers (devices with COMP_REF pin), all ports available on 32-pin packages must be considered as active ports. To avoid spurious effects, you have to configure them as input pull-up. A small increase in consumption (typ. < 300 µA) may occur during the power up and reset phase until these ports are properly configured.

Doc ID 15275 Rev 11 15/81

Pin description STM8L101xx

PA 3 ( H S )

PA 2 ( HS )

NRST / PA1 (HS)

PA0 (HS) / SWIM / BEEP / IR_TIM

PC4 (HS) / USART_CK/ CCO

PC3 (HS) / USART_TX

PC0 / I²C_SDA

PC1 / I²C_SCL

PB7 (HS) / SPI_MISO

PB6 (HS) / SPI_MOSI

PB1 (HS) / TIM3_CH1 / COMP1_CH2

PB2 (HS) / TIM2_CH2 / COMP2_CH1

PB3 (HS) /TIM2_TRIG /COMP2_CH2

PB4 (HS) / SPI_NSS

PB5 (HS) / SPI_SCK

PD0 (HS) / TIM3_CH2 / COMP1_CH3

PB0 (HS) / TIM2_CH1 / COMP1_CH1

PC2 (HS) / USART_RX

Figure 4. 20-pin TSSOP package pinout

1. HS corresponds to 20 mA high sink/source capability.

2. High sink LED driver capability available on PA0. Refer to the description of the IR_CR register in the

STM8L reference manual (RM0013).

16/81 Doc ID 15275 Rev 11

STM8L101xx Pin description

PD3

(HS) / COMP2_CH4

PB0 (HS) / TIM2_CH1 / COMP1_CH1

PB1 (HS) / TIM3_CH1 / COMP1_CH2

PB2 (HS) / TIM2_CH2 / COMP2_CH1

PD0 (HS) / TIM3_CH2 / COMP1_CH3

PD1 (HS) / TIM3_TRIG / COMP1_CH4

PD2(HS) / COMP2_CH3

PA5 (HS) / TIM3_BKIN

NRST / PA1 (HS)

PA2 ( H S )

PA3 (HS)

PA4 (HS) / TIM2_BKIN

PB6 (HS) / SPI_MOSI

PB5 (HS) / SPI_SCK

PB4 (HS) / SPI_NSS

PB3 (HS) / TIM2_TRIG / COMP2_CH2

PC0 / I²C_SDA

PD4 (HS)

PB7 (HS) / SPI_MISO

PC4 (HS) / USART_CK / CCO

PC3 (HS) / USART_TX

PC2 (HS) / USART_RX

PC1 / I²C_SCL

PA0 (HS) / SWIM / BEEP / IR_TIM

PC6 (HS)

PC5 (HS)

98 10 11 12 13 14

2728 26 25 24 23 22

Figure 5. Standard 28-pin UFQFPN package pinout

1. HS corresponds to 20 mA high sink/source capability.

2. High sink LED driver capability available on PA0. Refer to the description of the IR_CR register in the

STM8L reference manual (RM0013).

Note: The COMP_REF pin is not available in this standard 28-pin UFQFPN package. It is available

on Port A6 in the 28-pin UFQFPN package pinout for STM8L101G3U6ATR and

STM8L101G2U6ATR part numbers (Figure 6 on page 18).

Doc ID 15275 Rev 11 17/81

Pin description STM8L101xx

PD3(HS) / COMP2_CH4

PB0 (HS) / TIM2_CH1 / COMP1_CH1

PB1 (HS) / TIM3_CH1 / COMP1_CH2

PB2 (HS) / TIM2_CH2 / COMP2_CH1

PD0 (HS) / TIM3_CH2 / COMP1_CH3

PD1 (HS) / TIM3_TRIG / COMP1_CH4

PD2(HS) / COMP2_CH3

PA6 (HS) / COMP_REF

NRST / PA1 (HS)

PA2 ( H S )

PA3 (HS)

PA4 (HS) / TIM2_BKIN

PB6 (HS) / SPI_MOSI

PB5 (HS) / SPI_SCK

PB4 (HS) / SPI_NSS

PB3 (HS) / TIM2_TRIG / COMP2_CH2

PC0 / I²C_SDA

PD4 (HS)

PB7 (HS) / SPI_MISO

PC4 (HS) / USART_CK / CCO

PC3 (HS) / USART_TX

PC2 (HS) / USART_RX

PC1 / I²C_SCL

PA0 (HS) / SWIM / BEEP / IR_TIM

PC6 (HS)

PC5 (HS)

98 10 11 12 13 14

2728 26 25 24 23 22

Figure 6. 28-pin UFQFPN package pinout for STM8L101G3U6ATR and

STM8L101G2U6ATR part numbers

1. HS corresponds to 20 mA high sink/source capability.

2. High sink LED driver capability available on PA0. Refer to the description of the IR_CR register in the

STM8L reference manual (RM0013).

Warning: For the STM8L101G3U6ATR and STM8L101G2U6ATR part

numbers (devices with COMP_REF pin), all ports available on 32-pin packages must be considered as active ports. To avoid spurious effects, you have to configure them as input pull-up. A small increase in consumption (typ. < 300 µA) may occur during the power up and reset phase until these ports are properly configured.

18/81 Doc ID 15275 Rev 11

STM8L101xx Pin description

PA5 (HS) / TIM3_BKIN

PA6 (HS) / COMP_REF

NRST / PA1 (HS)

PA2 (HS)

PA3 (HS)

PA4 (HS) / TIM2_BKIN

PD1 (HS) / TIM3_TRIG / COMP1_CH4

PD2 (HS) / / COMP2_CH3

PD3 (HS) / COMP2_CH4

PB0 (HS) / TIM2_CH1 / COMP1_CH1

PB1 (HS) / TIM3_CH1 / COMP1_CH2

PB2 (HS) / TIM2_CH2 / COMP2_CH1

PB3 (HS) / TIM2_TRIG / COMP2_CH2

PD0 (HS) / TIM3_CH2 / COMP1_CH3

PD7 (HS)

PD6 (HS)

PB4 (HS) / SPI_NSS

PB5 (HS) / SPI_SCK

PB7 (HS) / SPI_MISO

PD5 (HS)

PD4 (HS)

PB6 (HS) / SPI_MOSI

PC3 (HS) / USART_TX

PC2 (HS) / USART_RX

PC1 / I²C_SCL

PC0 / I²C_SDA

PA0 (HS) / SWIM / BEEP / IR_TIM

PC6 (HS)

PC5 (HS)

PC4 (HS) / USART_CK / CCO

910111213 14 15 16

32 31 30 29

28 27 26 25

Figure 7. 32-pin package pinout

1. Example given for the UFQFPN32 package. The pinout is the same for the LQFP32 package.

2. HS corresponds to 20 mA high sink/source capability.

3. High sink LED driver capability available on PA0. Refer to the description of the IR_CR register in the

STM8L reference manual (RM0013).

Doc ID 15275 Rev 11 19/81

Pin description STM8L101xx

Table 3. Legend/abbreviation for table 4

Typ e I= input, O = output, S = power supply

Level

Input CM = CMOS

Output HS = high sink/source (20 mA)

Port and control configuration

Input float = floating, wpu = weak pull-up

Output T = true open drain, OD = open drain, PP = push pull

Bold X (pin state after reset release).

Reset state

Unless otherwise specified, the pin state is the same during the reset phase (i.e. “under reset”) and after internal reset release (i.e. at reset state).

(1)

TSSOP20

UFQFPN20 with COMP_REF

standard UFQFPN28

(1)

UFQFPN32 or LQFP32

UFQFPN28 with COMP_REF

Pin name

(2)

Input Output

Typ e

wpu

floating

Main function

Alternate function

(after reset)

Ext. interrupt

High sink/source

I/O X HS X X Reset PA 1

Table 4. STM8L101xx pin description

Pin number

standard UFQFPN20

1 14111NRST/PA1

2 25222PA2 I/OX XXHSXXPort A2

3 - 6333PA3 I/OX XXHSXXPort A3

- - - 4 4 4 PA4/TIM2_BKIN I/O X XXHSXXPort A4 Timer 2 - break input

- - - 5 - 5 PA5/TIM3_BKIN I/O X XXHSXXPort A5 Timer 3 - break input

- 3 - - 5 6 PA6/COMP_REF I/O X XXHSXXPort A6

4 47667V

5 58778V

6 69889

---9910

---101011

---111112

PD0/TIM3_CH2/ COMP1_CH3

PD1/TIM3_TRIG/ COMP1_CH4

PD2/ COMP2_CH3

PD3/ COMP2_CH4

S Ground

S Power supply

I/O X XXHSXXPort D0

I/O X XXHSXXPort D1

I/O X XXHSXXPort D2

I/O X XXHSXXPort D3

Comparator external reference

Timer 3 - channel 2 / Comparator 1 channel 3

Timer 3 - trigger / Comparator 1 channel 4

Comparator 2 channel 3

Comparator 2 channel 4

20/81 Doc ID 15275 Rev 11

STM8L101xx Pin description

Table 4. STM8L101xx pin description (continued)

Pin number

(1)

TSSOP20

standard UFQFPN20

UFQFPN20 with COMP_REF

standard UFQFPN28

UFQFPN28 with COMP_REF

7 7 10 12 12 13

8 8 11 13 13 14

9 9 12 14 14 15

10 10 13 15 15 16

Pin name

UFQFPN32 or LQFP32

PB0/TIM2_CH1/ COMP1_CH1

PB1/TIM3_CH1/ COMP1_CH2

PB2/ TIM2_CH2/ COMP2_CH1/

PB3/TIM2_TRIG/ COMP2_CH2

Input Output

Typ e

wpu

floating

Ext. interrupt

High sink/source

(3)

I/O X

XHSX XPort B0

(3)X(3)

I/O X XXHSXXPort B1

I/O X XXHSXXPort B2

I/O X XXHSXXPort B3

Main function

Alternate function

(after reset)

Timer 2 - channel 1 / Comparator 1 channel 1

Timer 3 - channel 1 / Comparator 1 channel 2

Timer 2 - channel 2 / Comparator 2 channel 1

Timer 2 - trigger / Comparator 2 channel 2

11 11 14 16 16 17 PB4/SPI_NSS

(3)

I/O X

(3)X(3)

XHSX XPort B4

SPI master/slave select

12 12 15 17 17 18 PB5/SPI_SCK I/O X XXHSXXPort B5 SPI clock

13 13 16 18 18 19 PB6/SPI_MOSI I/O X XXHSXXPort B6

14 14 17 19 19 20 PB7/SPI_MISO I/O X XXHSXXPort B7

SPI master out/ slave in

SPI master in/ slave out

- - - 202021PD4 I/O X XXHSXXPor t D4

- ----22PD5 I/OX XXHSXXPort D5

- ----23PD6 I/OX XXHSXXPort D6

- ----24PD7 I/OX XXHSXXPort D7

15 15 18 21 21 25 PC0/I2C_SDA I/O X XT

16 16 19 22 22 26 PC1/I2C_SCL I/O X XT

(4)

Port C0 I2C data

Port C1 I2C clock

17 17 20 23 23 27 PC2/USART_RX I/O X XXHSXXPort C2 USART receive

18 18 1 24 24 28 PC3/USART_TX I/O X XXHSXXPort C3 USART transmit

19 19 2 25 25 29

PC4/USART_CK/ CCO

I/O X XXHSXXPort C4

USART synchronous clock / Configurable clock output

- - - 262630PC5 I/O X XXHSXXPor t C5

Doc ID 15275 Rev 11 21/81

Pin description STM8L101xx

Table 4. STM8L101xx pin description (continued)

Pin number

(1)

TSSOP20

standard UFQFPN20

UFQFPN20 with COMP_REF

(1)

standard UFQFPN28

UFQFPN32 or LQFP32

UFQFPN28 with COMP_REF

Pin name

Input Output

Typ e

wpu

floating

Ext. interrupt

High sink/source

Main function

Alternate function

(after reset)

- - - 272731PC6 I/O X XXHSXXPor t C6

SWIM input and output /Beep output/Timer Infrared

20 20 3 28 28 32

(5)

/SWIM/

PA 0 BEEP/IR_TIM

(6)

I/O X X

(5)

XHS

(6)

XXPort A0

output

1. Please refer to the warning below.

2. At power-up, the PA1/NRST pin is a reset input pin with pull-up. To be used as a general purpose pin (PA1), it can be configured only as output open-drain or push-pull, not as a general purpose input. Refer to Section Configuring NRST/PA1 pin as general purpose output in the STM8L101xx reference manual (RM0013).

3. A pull-up is applied to PB0 and PB4 during the reset phase. These two pins are input floating after reset release.

4. In the open-drain output column, ‘T’ defines a true open-drain I/O (P-buffer and protection diode to V implemented).

5. The PA0 pin is in input pull-up during the reset phase and after reset release.

6. High sink LED driver capability available on PA0.

are not

Warning: For the STM8L101F1U6ATR, STM8L101F2U6ATR,

STM8L101F3U6ATR, STM8L101G2U6ATR and STM8L101G3U6ATR part numbers (devices with COMP_REF pin), all ports available on 32-pin packages must be considered as active ports. To avoid spurious effects, you have to configure them as input pull-up. A small increase in consumption (typ. < 300 µA) may occur during the power up and reset phase until these ports are properly configured.

22/81 Doc ID 15275 Rev 11

STM8L101xx Memory and register map

GPIO and peripheral registers

(2)

0x00 0000

Reserved

Flash program memory

(up to 8 Kbytes)

(1)

Interrupt vectors

0x00 4800

0x00 48FF

RAM

0x00 05FF

(1.5 Kbytes)

(1)

(up to 513 bytes)

(1)

0x 004900

Option bytes

0x00 5000

0x00 57FF

0x00 5800

0x00 7FFF

0x00 8000

0x00 9FFF

0x00 0600

0x00 47FF

0x00 49FF

0x00 7EFF

0x00 8080

0x00 807F

CPU/SWIM/Debug/ITC

Registers

0x00 7F00

Reserved

including

Stack

including

Data EEPROM

(up to 2 Kbytes)

0x 004925

0x 004931

0x 004924

0x 004930

Unique ID

Reserved

Low-density

5 Memory and register map

Figure 8. Memory map

1. Table 5 lists the boundary addresses for each memory size. The top of the stack is at the RAM end address.

2. Refer to Table 7 for an overview of hardware register mapping, to Table 6 for details on I/O port hardware registers, and to Ta b le 8 for information on CPU/SWIM/debug module controller registers.

Doc ID 15275 Rev 11 23/81

Memory and register map STM8L101xx

Table 5. Flash and RAM boundary addresses

Memory area Size Start address End address

RAM 1.5 Kbytes 0x00 0000 0x00 05FF

2 Kbytes 0x00 8000 0x00 87FF

Flash program memory

Table 6. I/O Port hardware register map

4 Kbytes 0x00 8000 0x00 8FFF

8 Kbytes 0x00 8000 0x00 9FFF

Address Block Register label Register name

0x00 5000

PA_ODR Port A data output latch register 0x00

Reset

status

0x00 5001 PA_IDR Port A input pin value register 0xxx

0x00 5002 PA_DDR Port A data direction register 0x00

Por t A

0x00 5003 PA_CR1 Port A control register 1 0x00

0x00 5004 PA_CR2 Port A control register 2 0x00

0x00 5005

PB_ODR Port B data output latch register 0x00

0x00 5006 PB_IDR Port B input pin value register 0xxx

0x00 5007 PB_DDR Port B data direction register 0x00

Por t B

0x00 5008 PB_CR1 Port B control register 1 0x00

0x00 5009 PB_CR2 Port B control register 2 0x00

0x00 500A

PC_ODR Port C data output latch register 0x00

0x00 500B PC_IDR Port C input pin value register 0xxx

0x00 500C PC_DDR Port C data direction register 0x00

Por t C

0x00 500D PC_CR1 Port C control register 1 0x00

0x00 500E PC_CR2 Port C control register 2 0x00

0x00 500F

PD_ODR Port D data output latch register 0x00

0x00 5010 PD_IDR Port D input pin value register 0xxx

0x00 5011 PD_DDR Port D data direction register 0x00

Por t D

0x00 5012 PD_CR1 Port D control register 1 0x00

0x00 5013 PD_CR2 Port D control register 2 0x00

24/81 Doc ID 15275 Rev 11

STM8L101xx Memory and register map

Table 7. General hardware register map

Address Block Register label Register name

0x00 5050

FLASH_CR1 Flash control register 1 0x00

Reset status

0x00 5051 FLASH_CR2 Flash control register 2 0x00

0x00 5052 FLASH _PUKR

Flash

Flash Program memory unprotection

0x00

0x00 5053 FLASH _DUKR Data EEPROM unprotection register 0x00

0x00 5054 FLASH _IAPSR

Flash in-application programming status

0xX0

0x00 5055

Reserved area (75 bytes)

0x00 509F

0x00 50A0

EXTI_CR1 External interrupt control register 1 0x00

0x00 50A1 EXTI_CR2 External interrupt control register 2 0x00

0x00 50A2 EXTI_CR3 External interrupt control register 3 0x00

ITC-EXTI

0x00 50A3 EXTI_SR1 External interrupt status register 1 0x00

0x00 50A4 EXTI_SR2 External interrupt status register 2 0x00

0x00 50A5 EXTI_CONF External interrupt port select register 0x00

0x00 50A6

WFE_CR1 WFE control register 1 0x00

WFE

0x00 50A7 WFE_CR2 WFE control register 2 0x00

0x00 50A8

Reserved area (8 bytes)

0x00 50AF

0x00 50B0

RST_CR Reset control register 0x00

RST

0x00 50B1 RST_SR Reset status register 0x01

0x00 50B2

Reserved area (14 bytes)

0x00 50BF

0x00 50C0

CLK_CKDIVR Clock divider register 0x03

0x00 50C1

0x00 50C2

CLK

Reserved area (2 bytes)

0x00 50C3 CLK_PCKENR Peripheral clock gating register 0x00

0x00 50C4 Reserved (1 byte)

0x00 50C5 CLK_CCOR Configurable clock control register 0x00

0x00 50C6

0x00 50DF

Reserved area (25 bytes)

Doc ID 15275 Rev 11 25/81

Memory and register map STM8L101xx

Table 7. General hardware register map (continued)

Address Block Register label Register name

0x00 50E0

0x00 50E1 IWDG_PR IWDG prescaler register 0x00

IWDG

IWDG_KR IWDG key register 0xXX

Reset status

0x00 50E2 IWDG_RLR IWDG reload register 0xFF

0x00 50E3

Reserved area (13 bytes)

0x00 50EF

0x00 50F0

0x00 50F1 AWU_APR

AWU

AWU_CSR AWU control/status register 0x00

AWU asynchronous prescaler buffer

0x3F

0x00 50F2 AWU_TBR AWU timebase selection register 0x00

0x00 50F3 BEEP BEEP_CSR BEEP control/status register 0x1F

0x00 50F4

Reserved area (268 bytes)

0x00 51FF

0x00 5200

SPI_CR1 SPI control register 1 0x00

0x00 5201 SPI_CR2 SPI control register 2 0x00

0x00 5202 SPI_ICR SPI interrupt control register 0x00

SPI

0x00 5203 SPI_SR SPI status register 0x02

0x00 5204 SPI_DR SPI data register 0x00

0x00 5205

Reserved area (11 bytes)

0x00 520F

0x00 5210

I2C_CR1 I2C control register 1 0x00

0x00 5211 I2C_CR2 I2C control register 2 0x00

0x00 5212 I2C_FREQR I2C frequency register 0x00

0x00 5213 I2C_OARL I2C own address register low 0x00

0x00 5214 I2C_OARH I2C own address register high 0x00

0x00 5215 Reserved area (1 byte)

0x00 5216 I2C_DR I2C data register 0x00

I2C

0x00 5217 I2C_SR1 I2C status register 1 0x00

0x00 5218 I2C_SR2 I2C status register 2 0x00

0x00 5219 I2C_SR3 I2C status register 3 0x00

0x00 521A I2C_ITR I2C interrupt control register 0x00

0x00 521B I2C_CCRL I2C Clock control register low 0x00

0x00 521C I2C_CCRH I2C Clock control register high 0x00

0x00 521D I2C_TRISER I2C TRISE register 0x02

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STM8L101xx Memory and register map

Table 7. General hardware register map (continued)

Address Block Register label Register name

Reset status

0x00 521E

Reserved area (18 bytes)

0x00 522F

0x00 5230

USART_SR USART status register 0xC0

0x00 5231 USART_DR USART data register 0xXX

0x00 5232 USART_BRR1 USART baud rate register 1 0x00

0x00 5233 USART_BRR2 USART baud rate register 2 0x00

USART

0x00 5234 USART_CR1 USART control register 1 0x00

0x00 5235 USART_CR2 USART control register 2 0x00

0x00 5236 USART_CR3 USART control register 3 0x00

0x00 5237 USART_CR4 USART control register 4 0x00

0x00 5238

Reserved area (18 bytes)

0x00 524F

Doc ID 15275 Rev 11 27/81

Memory and register map STM8L101xx

Table 7. General hardware register map (continued)

Address Block Register label Register name

0x00 5250

TIM2_CR1 TIM2 control register 1 0x00

Reset status

0x00 5251 TIM2_CR2 TIM2 control register 2 0x00

0x00 5252 TIM2_SMCR TIM2 slave mode control register 0x00

0x00 5253 TIM2_ETR TIM2 external trigger register 0x00

0x00 5254 TIM2_IER TIM2 interrupt enable register 0x00

0x00 5255 TIM2_SR1 TIM2 status register 1 0x00

0x00 5256 TIM2_SR2 TIM2 status register 2 0x00

0x00 5257 TIM2_EGR TIM2 event generation register 0x00

0x00 5258 TIM2_CCMR1 TIM2 capture/compare mode register 1 0x00

0x00 5259 TIM2_CCMR2 TIM2 capture/compare mode register 2 0x00

0x00 525A TIM2_CCER1 TIM2 capture/compare enable register 1 0x00

TIM2

0x00 525B TIM2_CNTRH TIM2 counter high 0x00

0x00 525C TIM2_CNTRL TIM2 counter low 0x00

0x00 525D TIM2_PSCR TIM2 prescaler register 0x00

0x00 525E TIM2_ARRH TIM2 auto-reload register high 0xFF

0x00 525F TIM2_ARRL TIM2 auto-reload register low 0xFF

0x00 5260 TIM2_CCR1H TIM2 capture/compare register 1 high 0x00

0x00 5261 TIM2_CCR1L TIM2 capture/compare register 1 low 0x00

0x00 5262 TIM2_CCR2H TIM2 capture/compare register 2 high 0x00

0x00 5263 TIM2_CCR2L TIM2 capture/compare register 2 low 0x00

0x00 5264 TIM2_BKR TIM2 break register 0x00

0x00 5265 TIM2_OISR TIM2 output idle state register 0x00

0x00 5266

Reserved area (26 bytes)

0x00 527F

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STM8L101xx Memory and register map

Table 7. General hardware register map (continued)

Address Block Register label Register name

0x00 5280

TIM3_CR1 TIM3 control register 1 0x00

Reset status

0x00 5281 TIM3_CR2 TIM3 control register 2 0x00

0x00 5282 TIM3_SMCR TIM3 slave mode control register 0x00

0x00 5283 TIM3_ETR TIM3 external trigger register 0x00

0x00 5284 TIM3_IER TIM3 interrupt enable register 0x00

0x00 5285 TIM3_SR1 TIM3 status register 1 0x00

0x00 5286 TIM3_SR2 TIM3 status register 2 0x00

0x00 5287 TIM3_EGR TIM3 event generation register 0x00

0x00 5288 TIM3_CCMR1 TIM3 capture/compare mode register 1 0x00

0x00 5289 TIM3_CCMR2 TIM3 capture/compare mode register 2 0x00

0x00 528A TIM3_CCER1 TIM3 capture/compare enable register 1 0x00

TIM3

0x00 528B TIM3_CNTRH TIM3 counter high 0x00

0x00 528C TIM3_CNTRL TIM3 counter low 0x00

0x00 528D TIM3_PSCR TIM3 prescaler register 0x00

0x00 528E TIM3_ARRH TIM3 auto-reload register high 0xFF

0x00 528F TIM3_ARRL TIM3 auto-reload register low 0xFF

0x00 5290 TIM3_CCR1H TIM3 capture/compare register 1 high 0x00

0x00 5291 TIM3_CCR1L TIM3 capture/compare register 1 low 0x00

0x00 5292 TIM3_CCR2H TIM3 capture/compare register 2 high 0x00

0x00 5293 TIM3_CCR2L TIM3 capture/compare register 2 low 0x00

0x00 5294 TIM3_BKR TIM3 break register 0x00

0x00 5295 TIM3_OISR TIM3 output idle state register 0x00

0x00 5296

Reserved area (74 bytes)

0x00 52DF

0x00 52E0

TIM4_CR1 TIM4 control register 1 0x00

0x00 52E1 TIM4_CR2 TIM4 control register 2 0x00

0x00 52E2 TIM4_SMCR TIM4 Slave mode control register 0x00

0x00 52E3 TIM4_IER TIM4 interrupt enable register 0x00

0x00 52E4 TIM4_SR1 TIM4 Status register 1 0x00

TIM4

0x00 52E5 TIM4_EGR TIM4 event generation register 0x00

0x00 52E6 TIM4_CNTR TIM4 counter 0x00

0x00 52E7 TIM4_PSCR TIM4 prescaler register 0x00

0x00 52E8 TIM4_ARR TIM4 auto-reload register low 0xFF

Doc ID 15275 Rev 11 29/81

Memory and register map STM8L101xx

Table 7. General hardware register map (continued)

Address Block Register label Register name

Reset status

0x00 52E9

Reserved area (23 bytes)

0x00 52FE

0x00 52FF IRTIM IR_CR Infra-red control register 0x00

0x00 5300

0x00 5301 COMP_CSR Comparator status register 0x00

COMP

COMP_CR Comparator control register 0x00

0x00 5302 COMP_CCS Comparator channel selection register 0x00

Table 8. CPU/SWIM/debug module/interrupt controller registers

Address Block Register label Register name

0x00 7F00

A Accumulator 0x00

0x00 7F01 PCE Program counter extended 0x00

0x00 7F02 PCH Program counter high 0x80

0x00 7F03 PCL Program counter low 0x00

0x00 7F04 XH X index register high 0x00

0x00 7F05 XL X index register low 0x00

CPU

0x00 7F06 YH Y index register high 0x00

Reset

status

0x00 7F07 YL Y index register low 0x00

0x00 7F08 SPH Stack pointer high 0x05

0x00 7F09 SPL Stack pointer low 0xFF

0x00 7F0A CC Condition code register 0x28

0x00 7F0B

Reserved area (85 bytes)

0x00 7F5F

0x00 7F60 CFG CFG_GCR Global configuration register 0x00

0x00 7F61

0x00 7F6F

0x00 7F70

ITC_SPR1 Interrupt Software priority register 1 0xFF

Reserved area (15 bytes)

0x00 7F71 ITC_SPR2 Interrupt Software priority register 2 0xFF

0x00 7F72 ITC_SPR3 Interrupt Software priority register 3 0xFF

0x00 7F73 ITC_SPR4 Interrupt Software priority register 4 0xFF

0x00 7F74 ITC_SPR5 Interrupt Software priority register 5 0xFF

0x00 7F75 ITC_SPR6 Interrupt Software priority register 6 0xFF

ITC-SPR

(1)

0x00 7F76 ITC_SPR7 Interrupt Software priority register 7 0xFF

0x00 7F77 ITC_SPR8 Interrupt Software priority register 8 0xFF

30/81 Doc ID 15275 Rev 11

STM8L101xx Memory and register map

Table 8. CPU/SWIM/debug module/interrupt controller registers (continued)

Address Block Register label Register name

Reset

status

0x00 7F78

Reserved area (2 bytes)

0x00 7F79

0x00 7F80 SWIM SWIM_CSR SWIM control status register 0x00

0x00 7F81

Reserved area (15 bytes)

0x00 7F8F

0x00 7F90

DM_BK1RE Breakpoint 1 register extended byte 0xFF

0x00 7F91 DM_BK1RH Breakpoint 1 register high byte 0xFF

0x00 7F92 DM_BK1RL Breakpoint 1 register low byte 0xFF

0x00 7F93 DM_BK2RE Breakpoint 2 register extended byte 0xFF

0x00 7F94 DM_BK2RH Breakpoint 2 register high byte 0xFF

0x00 7F95 DM_BK2RL Breakpoint 2 register low byte 0xFF

0x00 7F96 DM_CR1 Debug module control register 1 0x00

0x00 7F97 DM_CR2 Debug module control register 2 0x00

0x00 7F98 DM_CSR1 Debug module control/status register 1 0x10

0x00 7F99 DM_CSR2 Debug module control/status register 2 0x00

0x00 7F9A DM_ENFCTR Enable function register 0xFF

1. Refer to Table 7: General hardware register map on page 25 (addresses 0x00 50A0 to 0x00 50A5) for a list of external interrupt registers.

Doc ID 15275 Rev 11 31/81

Interrupt vector mapping STM8L101xx

6 Interrupt vector mapping

Source

block

Description

Wakeup

from Halt

mode

Wakeup

from

Active-halt

mode

Wakeup

from Wait

(WFI

mode)

Wakeup

from Wait

(WFE

mode)

Vector

address

Table 9. Interrupt mapping

IRQ

No.

RESET Reset Yes Yes Yes Yes 0x00 8000

TRAP Software interrupt - - - - 0x00 8004

0Reserved 0x00 8008

1 FLASH EOP/WR_PG_DIS - - Yes Yes

2-3 Reserved - - - -

4 AWU Auto wakeup from Halt - Yes Yes Yes

(1)

0x00 800C

0x00 8010

-0x00 8017

0x00 8018

5 Reserved - - - - 0x00 801C

6 EXTIB External interrupt port B Yes Yes Yes Yes 0x00 8020

7 EXTID External interrupt port D Yes Yes Yes Yes 0x00 8024

8 EXTI0 External interrupt 0 Yes Yes Yes Yes 0x00 8028

9 EXTI1 External interrupt 1 Yes Yes Yes Yes 0x00 802C

10 EXTI2 External interrupt 2 Yes Yes Yes Yes 0x00 8030

11 EXTI3 External interrupt 3 Yes Yes Yes Yes 0x00 8034

12 EXTI4 External interrupt 4 Yes Yes Yes Yes 0x00 8038

13 EXTI5 External interrupt 5 Yes Yes Yes Yes 0x00 803C

14 EXTI6 External interrupt 6 Yes Yes Yes Yes 0x00 8040

15 EXTI7 External interrupt 7 Yes Yes Yes Yes 0x00 8044

16 Reserved 0x00 8048

17 Reserved - - - -

18 COMP Comparators - - Yes Yes

19 TIM2

Update /Overflow/Trigger/Break

- - Yes Yes 0x00 8054

(1)

0x00 804C

-0x00 804F

0x00 8050

20 TIM2 Capture/Compare - - Yes Yes 0x00 8058

21 TIM3 Update /Overflow/Break - - Yes Yes

22 TIM3 Capture/Compare - - Yes Yes

23-

Reserved ----

25 TIM4 Update /Trigger - - Yes Yes

26 SPI End of Transfer Yes Yes Yes Yes

(1)

0x00 805C

0x00 8060

0x00 8064-

0x00 806B

0x00 806C

0x00 8070

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STM8L101xx Interrupt vector mapping

Table 9. Interrupt mapping (continued)

IRQ

Source

No.

block

27 USART

Description

Transmission complete/transmit data

Wakeup

from Halt

mode

Wakeup

from

Active-halt

mode

--YesYes

Wakeup

from Wait

(WFI

mode)

Wakeup

from Wait

(WFE

mode)

(1)

Vector

address

0x00 8074

28 USART

Receive Register DATA FULL/overrun/idle line

--YesYes

(1)

0x00 8078

detected/parity error

29 I2C I2C interrupt

1. In WFE mode, this interrupt is served if it has been previously enabled. After processing the interrupt, the processor goes back to WFE mode. Refer to SectionWait for event (WFE) mode in the RM0013 reference manual.

(2)

Ye s Ye s Ye s Ye s

2. The device is woken up from Halt or Active-halt mode only when the address received matches the interface address.

(1)

0x00 807C

Doc ID 15275 Rev 11 33/81

Option bytes STM8L101xx

7 Option bytes

Option bytes contain configurations for device hardware features as well as the memory protection of the device. They are stored in a dedicated row of the memory.

All option bytes can be modified only in ICP mode (with SWIM) by accessing the EEPROM address. See Tab le 1 0 for details on option byte addresses.

Refer to the STM8L Flash programming manual (PM0054) and STM8 SWIM and Debug Manual (UM0320) for information on SWIM programming procedures.

Table 10. Option bytes

Addr. Option name

Option

byte

No.

7654 3 2 1 0

Option bits Factory

default setting

Read-out

0x4800

protection

OPT1 ROP[7:0] 0x00

(ROP)

0x4807 - - Must be programmed to 0x00 0x00

0x4802

UBC (User

Boot code size)

OPT2 UBC[7:0] 0x00

0x4803 DATASIZE OPT3 DATASIZE[7:0] 0x00

0x4808

Independent

watchdog

option

Table 11. Option byte description

OPT4

[1:0]

Reserved

IWDG

_HALT

IWDG

_HW

0x00

ROP[7:0] Memory readout protection (ROP)

OPT1

0xAA: Enable readout protection (write access via SWIM protocol) Refer to Read-out protection section in the STM8L reference manual

(RM0013) for details.

UBC[7:0] Size of the user boot code area

0x00: no UBC 0x01-0x02: UBC contains only the interrupt vectors. 0x03: Page 0 and 1 reserved for the interrupt vectors. Page 2 is available to

OPT2

store user boot code. Memory is write protected ... 0x7F - Page 0 to 126 reserved for UBC, memory is write protected

Refer to User boot area (UBC) section in the STM8L reference manual (RM0013) for more details.

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STM8L101xx Option bytes

Table 11. Option byte description (continued)

DATASIZE[7:0] Size of the data EEPROM area

0x00: no data EEPROM area 0x01: 1 page reserved for data storage from 0x9FC0 to 0x9FFF

OPT3

0x02: 2 pages reserved for data storage from 0x9F80 to 0x9FFF

(1)

... 0x20: 32 pages reserved for data storage from 0x9800 to 0x9FFF

Refer to Data EEPROM (DATA) section in the STM8L reference manual (RM0013) for more details.

IWDG_HW: Independent watchdog

0: Independent watchdog activated by software 1: Independent watchdog activated by hardware

OPT4

IWDG_HALT: Independent window watchdog reset on Halt/Active-halt

0: Independent watchdog continues running in Halt/Active-halt mode 1: Independent watchdog stopped in Halt/Active-halt mode

1. 0x00 is the only allowed value for 4 Kbyte STM8L101xx devices.

(1)

Caution: After a device reset, read access to the program memory is not guaranteed if address

0x4807 is not programmed to 0x00.

Doc ID 15275 Rev 11 35/81

Unique ID STM8L101xx

8 Unique ID

STM8L101xx devices feature a 96-bit unique device identifier which provides a reference number that is unique for any device and in any context. The 96 bits of the identifier can never be altered by the user.

The unique device identifier can be read in single bytes and may then be concatenated using a custom algorithm.

The unique device identifier is ideally suited:

● For use as serial numbers

● For use as security keys to increase the code security in the program memory while

using and combining this unique ID with software cryptograhic primitives and protocols before programming the internal memory

● To activate secure boot processes.

Table 12. Unique ID registers (96 bits)

Address

0x4925

0x4926 U_ID[15:8]

0x4927

0x4928 U_ID[31:24]

Content

description

X co-ordinate on

the wafer

Y co-ordinate on

the wafer

76543 2 1 0

Unique ID bits

U_ID[7:0]

U_ID[23:16]

0x4929 Wafer number U_ID[39:32]

0x492A

U_ID[47:40]

0x492B U_ID[55:48]

0x492C U_ID[63:56]

0x492D U_ID[71:64]

Lot number

0x492E U_ID[79:72]

0x492F U_ID[87:80]

0x4930 U_ID[95:88]

36/81 Doc ID 15275 Rev 11

STM8L101xx Electrical parameters

50 pF

STM8L PIN

9 Electrical parameters

9.1 Parameter conditions

Unless otherwise specified, all voltages are referred to VSS.

9.1.1 Minimum and maximum values

Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at T the selected temperature range).

= 25 °C and TA = TA max (given by

Note: The values given at 85

Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean±3Σ).

9.1.2 Typical values

Unless otherwise specified, typical data are based on TA = 25 °C, V only as design guidelines and are not tested.

9.1.3 Typical curves

Unless otherwise specified, all typical curves are given only as design guidelines and are not tested.

9.1.4 Loading capacitor

The loading conditions used for pin parameter measurement are shown in Figure 9.

Figure 9. Pin loading conditions

°C <TA ≤ 125 °C are only valid for suffix 3 versions.

= 3 V. They are given

Doc ID 15275 Rev 11 37/81

Electrical parameters STM8L101xx

STM8L PIN

9.1.5 Pin input voltage

The input voltage measurement on a pin of the device is described in Figure 10.

Figure 10. Pin input voltage

9.2 Absolute maximum ratings

Stresses above those listed as “absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

Table 13. Voltage characteristics

Symbol Ratings Min Max Unit

- V

External supply voltage -0.3 4.0

Input voltage on true open drain pins (PC0 and PC1)

Input voltage on any other pin

(1)

(2)

VSS-0.3 VDD + 4.0

VSS-0.3 4.0

see Absolute maximum

ESD

Electrostatic discharge voltage

ratings (electrical sensitivity)

on page 63

1. Positive injection is not possible on these I/Os. VIN maximum must always be respected. I never be exceeded. A negative injection is induced by V

2. I

must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum

INJ(PIN)

cannot be respected, the injection current must be limited externally to the I injection is induced by V

while a negative injection is induced by VIN<VSS.

IN>VDD

IN<VSS

INJ(PIN)

value. A positive

must

38/81 Doc ID 15275 Rev 11

STM8L101xx Electrical parameters

Table 14. Current characteristics

Symbol Ratings Max. Unit

VDD

VSS

Total current into V

Total current out of V

Output current sunk by IR_TIM pin (with high sink LED driver capability)

power line (source) 80

ground line (sink) 80

Output current sunk by any other I/O and control pin 25

Output current sourced by any I/Os and control pin -25

INJ(PIN)

ΣI

INJ(PIN)

1. Positive injection is not possible on these I/Os. VIN maximum must always be respected. I never be exceeded. A negative injection is induced by VIN<VSS.

2. I

must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum

INJ(PIN)

cannot be respected, the injection current must be limited externally to the I injection is induced by V

3. When several inputs are submitted to a current injection, the maximum ΣI positive and negative injected currents (instantaneous values). These results are based on characterization with ΣI

Table 15. Thermal characteristics

Injected current on any other pin

Total injected current (sum of all I/O and control pins)

while a negative injection is induced by VIN<VSS.

IN>VDD

maximum current injection on four I/O port pins of the device.

INJ(PIN)

(2)

Injected current on true open-drain pins (PC0 and PC1)

(1)

(3)

value. A positive

INJ(PIN)

is the absolute sum of the

INJ(PIN)

-5

±5

±25

INJ(PIN)

must

Symbol Ratings Value Unit

STG

Storage temperature range -65 to +150

Maximum junction temperature 150

° C

Doc ID 15275 Rev 11 39/81

Electrical parameters STM8L101xx

9.3 Operating conditions

Subject to general operating conditions for VDD and TA.

9.3.1 General operating conditions

Table 16. General operating conditions

Symbol Parameter Conditions Min Max Unit

MASTER

Master clock frequency 1.65 V ≤ V

Standard operating voltage 1.65 3.6 V

< 3.6 V 2 16 MHz

(1)

LQFP32 - 288

UFQFPN32 - 288 Power dissipation at TA= 85 °C for suffix 6 devices

UFQFPN28 - 250

TSSOP20 - 181

(2)

UFQFPN20 - 196

LQFP32 - 83

UFQFPN32 - 185 Power dissipation at T for suffix 3 devices

= 125 °C

UFQFPN28 - 62

TSSOP20 - 45

UFQFPN20 - 49

1. f

MASTER

2. To calculate P

in table “Thermal characteristics”

Temperature range

Junction temperature range

= f

CPU

Dmax(TA

1.65 V ≤ V (6 suffix version)

1.65 V ≤ V (3 suffix version)

-40 °C ≤ T (6 suffix version)

-40 °C ≤ T (3 suffix version)

) use the formula given in thermal characteristics P

Dmax

< 3.6 V

≤ 85 °C

≤ 125 °C

=(T

-TA)/ΘJA with T

Jmax

− 40 85

− 40 125

- 40 105 °C

− 40 130 °C

in this table and

Jmax

°C

40/81 Doc ID 15275 Rev 11

STM8L101xx Electrical parameters

9.3.2 Power-up / power-down operating conditions

Table 17. Operating conditions at power-up / power-down

Symbol Parameter Conditions Min Typ

Max Unit

VDD

TEMP

POR

PDR

VDD rise time rate 20 - 1300 µs/V

Reset release delay VDD rising - 1 - ms

Power on reset

(1)

threshold

Power down reset

(1)

threshold

1. Data based on characterization results, not tested in production.

2. Data guaranteed, each individual device tested in production.

1.35 - 1.65

(2)

1.40 - 1.60 V

Doc ID 15275 Rev 11 41/81

Electrical parameters STM8L101xx

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.6 1.7 1.8 1.9 2 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 3.6

[V]

DD(RUN)HSI

[mA]

-40°C

25°C

85°C

125°C

ai17018

2.1

2.2

2.3

2.4

2.5

2.6

2.7

2.8

2.9

1.6 1.7 1.8 1.9 2 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 3.6

[V]

DD(RUN)HSI

[mA]

-40°C

25°C

85°C

125°C

9.3.3 Supply current characteristics

Total current consumption

The MCU is placed under the following conditions:

● All I/O pins in input mode with a static value at V

● All peripherals are disabled except if explicitly mentioned.

or VSS (no load)

Subject to general operating conditions for V

and TA.

Table 18. Total current consumption in Run mode

RAM

(2)

MASTER

= 2 MHz 0.39 0.6

= 4 MHz 0.55 0.7

= 8 MHz 0.9 1.2

= 16 MHz 1.6 2.1

= 2 MHz 0.55 0.7

= 4 MHz 0.88 1.8

= 8 MHz 1.5 2.5

= 16 MHz 2.7 3.5

Symbol Parameter Conditions

Code executed from

Supply

DD (Run)

current in Run

(4) (5)

mode

Code executed from

Flash

1. Based on characterization results, unless otherwise specified.

2. All peripherals off, VDD from 1.65 V to 3.6 V, HSI internal RC osc. , f

3. Maximum values are given for TA = − 40 to 125 °C.

4. CPU executing typical data processing.

5. An approximate value of I I

DD(Run)

= f

x 150 µA/MHz +215 µA.

MASTER

6. Data guaranteed, each individual device tested in production.

can be given by the following formula:

DD(Run)

(1)

CPU=fMASTER

Typ Ma x

(6)

(3)

Unit

Figure 11. I

DD(RUN)

vs. V

1. Typical current consumption measured with code executed from Flash.

42/81 Doc ID 15275 Rev 11

DD, fCPU

= 2 MHz Figure 12. I

DD(RUN)

vs. VDD, f

CPU

= 16 MHz

STM8L101xx Electrical parameters

ai17015

100

150

200

250

300

1.6 1.7 1.8 1.9 2 2.1 2 .2 2.3 2.4 2.5 2 .6 2.7 2.8 2 .9 3 3.1 3.2 3.3 3.4 3.5 3 .6

[V]

DD(RUN)HSI

[µA]

-40°C

25°C

85°C

125°C

ai17016

200

250

300

350

400

450

500

550

600

1.6 2.1 2.6 3.1 3.6

[V]

DD(WFI)HSI

[µA]

-40°C

25°C

85°C

125°C

Figure 13. I

Table 19. Total current consumption in Wait mode

(1)

Symbol Parameter Conditions Typ Max

DD (Wait)

Supply current in Wait mode

1. Based on characterization results, unless otherwise specified.

2. Maximum values are given for TA = -40 to 125 °C.

DD(WAIT)

vs. VDD, f

CPU not clocked, all peripherals off, HSI internal RC osc.

= 2 MHz Figure 14. I

CPU

MASTER

= 2 MHz 245 400

MASTER

= 4 MHz 300 450

MASTER

= 8 MHz 380 600

MASTER

= 16 MHz 510 800

DD(WAIT)

vs. VDD,f

CPU

(2)

= 16 MHz

Unit

µA

1. Typical current consumption measured with code executed from Flash.

Doc ID 15275 Rev 11 43/81

Electrical parameters STM8L101xx

ai17014b

1.6 2.1 2.6 3.1 3.6

[V]

DD(HALT)

[µA]

-40°C

25°C

85°C

125°C

Table 20. Total current consumption and timing in Halt and Active-halt mode at

= 1.65 V to 3.6 V

Symbol Parameter Conditions Typ Max Unit

DD(AH)

DD(WUFAH)

WU(AH)

DD(Halt)

DD(WUFH)

Supply current in Active-halt mode

Supply current during wakeup time from Active-halt mode

Wakeup time from Active-

(3)

halt mode to Run mode

Supply current in Halt mode

Supply current during wakeup time from Halt mode

(1)(2)

= -40 °C to 25 °C 0.8 2 μA

= 55 °C 1 2.5 μA

T LSI RC osc. (at 37 kHz)

= 16 MHz 4 6.5 μs

CPU

= 85 °C 1.4 3.2 μA

= 105 °C 2.9 7.5 μA

= 125 °C 5.8 13 μA

TA = -40 °C to 25 °C 0.35 1.2

= 55 °C 0.6 1.8 μA

= 85 °C 1 2.5

= 105 °C 2.5 6.5 μA

= 125 °C 5.4 12

2-mA

(4)

μA

(4)

μA

(4)

μA

2-mA

Wakeup time from Halt mode

1. T

(3)

WU(Halt)

= -40 to 125 °C, no floating I/O, unless otherwise specified.

to Run mode

= 16 MHz 4 6.5 μs

CPU

2. Data based on characterization results, not tested in production.

3. Measured from interrupt event to interrupt vector fetch. To get tWU for another CPU frequency use tWU(FREQ) = tWU(16 MHz) + 1.5 (T The first word of interrupt routine is fetched 5 CPU cycles after t

FREQ-T16 MHz

4. Data guaranteed, each individual device tested in production.

Figure 15. Typ. I

DD(Halt)

vs. V

DD, fCPU

= 2 MHz and 16 MHz

1. Typical current consumption measured with code executed from Flash.

44/81 Doc ID 15275 Rev 11

STM8L101xx Electrical parameters

Current consumption of on-chip peripherals

Measurement made for f

Table 21. Peripheral current consumption

MASTER

Symbol Parameter Typ. V

DD(TIM2)

DD(TIM3)

DD(TIM4)

DD(USART)

DD(SPI)

DD(I²C1)

DD(COMP)

TIM2 supply current

TIM3 supply current

TIM4 timer supply current

USART supply current

SPI supply current

I2C supply current

Comparator supply current

= from 2 MHz to 16 MHz

(1)

(2)

= 3.0 V Unit

µA/MHz

20 µA

1. Data based on a differential IDD measurement between all peripherals off and a timer counter running at 16 MHz. The CPU is in Wait mode in both cases. No IC/OC programmed, no I/O pin toggling. Not tested in production.

2. Data based on a differential IDD measurement between the on-chip peripheral when kept under reset and not clocked and the on-chip peripheral when clocked and not kept under reset. The CPU is in Wait mode in both cases. No I/O pin toggling. Not tested in production.

Doc ID 15275 Rev 11 45/81

Electrical parameters STM8L101xx

ai17013

15.2

15.4

15.6

15.8

16.2

16.4

16.6

16.8

1.65 1.8 1.95 2.1 2.25 2.4 2.55 2.7 2.85 3 3.15 3.3 3.45 3.6

[V]

HSI frequency [MHz]

-40°C

25°C

85°C

125°C

9.3.4 Clock and timing characteristics

Internal clock sources

Subject to general operating conditions for VDD and TA.

High speed internal RC oscillator (HSI)

Table 22. HSI oscillator characteristics

Symbol Parameter Conditions Min Typ Max Unit

Frequency VDD = 3.0 V - 16 - MHz

HSI

= 3.0 V, TA = 25 °C -1 1 %

= 3.0 V, -10 °C ≤ TA ≤ 85 °C -2.5 2 %

= 3.0 V, -10 °C ≤ TA ≤ 125 °C -4.5 2 %

ACC

Accuracy of HSI

HSI

oscillator (factory calibrated)

= 3.0 V, 0 °C ≤ TA ≤ 55 °C -1.5

= 3.0 V, -10 °C ≤ TA ≤ 70 °C -2

1.65 V ≤ V

-40 °C ≤ T

DD(HSI)

HSI oscillator power consumption

≤ 3.6 V,

≤ 125 °C

(1)

(2)

-4.5

- 70 100

1.5

(2)

µA

= 3.0 V, TA = -40 to 125 °C unless otherwise specified.

1. V

2. Data based on characterization results, not tested in production.

Figure 16. Typical HSI frequency vs. V

46/81 Doc ID 15275 Rev 11

STM8L101xx Electrical parameters

ai17021

-5.0%

-4.5%

-4.0%

-3.5%

-3.0%

-2.5%

-2.0%

-1.5%

-1.0%

-0.5%

0.0%

0.5%

1.0%

1.5%

2.0%

2.5%

3.0%

3.5%

-50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140

Temperature (°C)

RC accuracy

3V min

3V typical

3V max

ai17019

-5.0%

-4.5%

-4.0%

-3.5%

-3.0%

-2.5%

-2.0%

-1.5%

-1.0%

-0.5%

0.0%

0.5%

1.0%

1.5%

2.0%

2.5%

3.0%

3.5%

-50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140

Temperature (°C)

RC accuracy

Min 1.65V-3.6V

Max 1.65V-3.6V

3V typical

Figure 17. Typical HSI accuracy vs. temperature, VDD = 3 V

Figure 18. Typical HSI accuracy vs. temperature, V

= 1.65 V to 3.6 V

Low speed internal RC oscillator (LSI)

Table 23. LSI oscillator characteristics

Symbol Parameter Conditions Min Typ Max Unit

(1)

drift(LSI)

1. V

2. For each individual part, this value is the frequency drift from the initial measured frequency.

Frequency 26 38 56 kHz

LSI

LSI oscillator frequency

(2)

drift

= 1.65 V to 3.6 V, TA = -40 to 125 °C unless otherwise specified.

0 °C ≤ TA ≤ 85 °C -12 - 11 %

Doc ID 15275 Rev 11 47/81

Electrical parameters STM8L101xx

ai17012b

1.62.12.63.13.6

[V]

LSI frequency [MHz]

-40°C

25°C

85°C

125°C

Figure 19. Typical LSI RC frequency vs. V

48/81 Doc ID 15275 Rev 11

STM8L101xx Electrical parameters

9.3.5 Memory characteristics

TA = -40 to 125 °C unless otherwise specified.

Table 24. RAM and hardware registers

Symbol Parameter Conditions Min Typ Max Unit

Data retention mode

1. Minimum supply voltage without losing data stored in RAM (in Halt mode or under Reset) or in hardware registers (only in Halt mode). Guaranteed by characterization, not tested in production.

Flash memory

(1)

Halt mode (or Reset) 1.4 - - V

Table 25. Flash program memory

Symbol Parameter Conditions Min Typ

Operating voltage

(all modes, read/write/erase)

Programming time for 1- or 64-byte (block) erase/write cycles (on programmed byte)

prog

Programming time for 1- to 64-byte (block) write cycles (on erased byte)

Programming/ erasing consumption

prog

Data retention (program memory) after 10k erase/write cycles

= +85 °C

at T

Data retention (data memory) after 10k erase/write cycles

RET

= 16 MHz 1.65 - 3.6 V

MASTER

-6-ms

-3-ms

=+25 °C, VDD = 3.0 V -

=+25 °C, VDD = 1.8 V - -

= 55 °C 20

RET

= 55 °C 20

RET

(1)

at TA = +85 °C

Data retention (data memory) after 300k erase/write cycles

= +125 °C

at T

Erase/write cycles (program memory) See notes

Erase/write cycles

(data memory) See notes

= 85 °C 1

RET

(1)(2)

(1)(3)

300

(1)

(1)(4)

Max

(1)

0.7

Unit

years

kcycles

1. Data based on characterization results, not tested in production.

2. Retention guaranteed after cycling is 10 years at 55 °C.

3. Retention guaranteed after cycling is 1 year at 55 °C.

4. Data based on characterization performed on the whole data memory (2 Kbytes).

Doc ID 15275 Rev 11 49/81

Electrical parameters STM8L101xx

9.3.6 I/O port pin characteristics

General characteristics

Subject to general operating conditions for VDD and TA unless otherwise specified. All unused pins must be kept at a fixed voltage: using the output mode of the I/O for example or an external pull-up or pull-down resistor.

Table 26. I/O static characteristics

Symbol Parameter Conditions Min Typ

(1)

Max Unit

Input low level voltage

Input high level voltage

Schmitt trigger voltage hysteresis

hys

Input leakage current

lkg

(2)

(4)

Standard I/Os VSS-0.3 - 0.3 x V

True open drain I/Os V

Standard I/Os 0.70 x V

-0.3 - 0.3 x V

-VDD+0.3

True open drain I/Os V

< 2 V

True open drain I/Os

≥ 2 V

Standard I/Os - 200 -

(3)

0.70 x V

True open drain I/Os - 250 -

≤ VIN≤ V

Standard I/Os

True open drain I/Os

PA0 with high sink LED

≤ VIN≤ V

- - 50

- - 200

driver capability

Weak pull-up equivalent resistor

(7)

I/O pin capacitance - 5 - pF

1. VDD = 3.0 V, TA = -40 to 85 °C unless otherwise specified.

2. Data based on characterization results, not tested in production.

3. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested.

4. The max. value may be exceeded if negative current is injected on adjacent pins.

5. Not tested in production.

pull-up equivalent resistor based on a resistive transistor (corresponding I

6. R

Figure 22).

7. Data guaranteed by Design, not tested in production.

(6)

IN=VSS

30 45 60 kΩ

current characteristics described in

5.2

5.5

(5)

50/81 Doc ID 15275 Rev 11

STM8L101xx Electrical parameters

ai17011

0.5

1.5

2.5

1.6 2.1 2.6 3.1 3.6

[V]

and V

[V]

-40°C

25°C

85°C

125°C

0.5

1.5

2.5

1.6 2.1 2.6 3.1 3.6

[V]

and V

[V]

-40°C

25°C

85°C

125°C

ai17010

0.5

1.5

2.5

1.62.12.63.13.6

[V]

and V

[V]

-40°C

25°C

85°C

125°C

ai17009

1.65 1.8 1.95 2.1 2.25 2.4 2.55 2.7 2.85 3 3.15 3.3 3.45 3.6

[V]

Pull-U p r es ist anc e [k ]

-40°C

25°C

85°C

125°C

Figure 20. Typical VIL and V

Figure 21. Typical V

and V

vs. VDD (standard I/Os)

vs. VDD (true open drain I/Os)

Figure 22. Typical pull-up resistance R

vs. VDD with VIN=V

Doc ID 15275 Rev 11 51/81

Electrical parameters STM8L101xx

ai17008

100

120

1.65 1.8 1.95 2.1 2.25 2.4 2.55 2.7 2.85 3 3.15 3.3 3.45 3.6

[V]

Pull-Up cur rent [µA]

-40°C

25°C

85°C

125°C

Figure 23. Typical pull-up current IPU vs. VDD with VIN=V

52/81 Doc ID 15275 Rev 11

STM8L101xx Electrical parameters

Output driving current

Subject to general operating conditions for V

Table 27. Output driving current (standard ports)

I/O

Symbol Parameter Conditions Min Max Unit

Typ e

Output low level voltage for an I/O pin

(1)

Standard

(2)

Output high level voltage for an I/O pin

and TA unless otherwise specified.

= +2 mA,

= 3.0 V

= +2 mA,

= 1.8 V

= +10 mA,

= 3.0 V

= -2 mA,

= 3.0 V

= -1 mA,

= 1.8 V

= -10 mA,

= 3.0 V

-0.45V

-1.2V

-0.45 - V

-1.2 - V

1. The IIO current sunk must always respect the absolute maximum rating specified in Table 14 and the sum of I

(I/O ports and control pins) must not exceed I

VSS

2. The IIO current sourced must always respect the absolute maximum rating specified in Table 14 and the sum of I

(I/O ports and control pins) must not exceed I

VDD

Table 28. Output driving current (true open drain ports)

I/O

Symbol Parameter Conditions Min Max Unit

Type

= +3 mA,

= 3.0 V

(1)

Output low level voltage for an I/O pin

Open drain

1. The IIO current sunk must always respect the absolute maximum rating specified in Table 14 and the sum of IIO (I/O ports and control pins) must not exceed I

VSS

= +1 mA,

= 1.8 V

-0.45V

Table 29. Output driving current (PA0 with high sink LED driver capability)

I/O

Symbol Parameter Conditions Min Max Unit

Type

= +20 mA,

(1)

1. The IIO current sunk must always respect the absolute maximum rating specified in Table 14 and the sum of IIO (I/O ports and control pins) must not exceed I

Output low level voltage for an I/O pin

VSS

I V

= 2.0 V

-0.9V

Doc ID 15275 Rev 11 53/81

Electrical parameters STM8L101xx

ai17005

0.25

0.5

0.75

1.25

1.5

0 5 10 15 20 25

[mA]

[V]

-40°C

25°C

85°C

125°C

0.1

0.2

0.3

0.4

0.5

01234567

IOL [mA]

[V]

-40°C

25°C

85°C

125°C

ai17004

ai17003

0.1

0.2

0.3

0.4

0.5

01234 56

[mA]

[V]

-40°C

25°C

85°C

125°C

ai17002

0.1

0.2

0.3

0.4

0.5

00.511.522.53

[mA]

[V]

-40°C

25°C

85°C

125°C

ai17001

0.25

0.5

0.75

1.25

1.5

1.75

0246 81012141618202224

[mA]

- V

[V]

-40°C

25°C

85°C

125°C

0.1

0.2

0.3

0.4

0123456

[mA]

- V

[V]

-40°C

25°C

85°C

125°C

Figure 24. Typ. VOL at VDD = 3.0 V (standard

ports)

Figure 26. Typ. VOL at VDD = 3.0 V (true open

drain ports)

Figure 25. Typ. VOL at VDD = 1.8 V (standard

ports)

Figure 27. Typ. VOL at VDD = 1.8 V (true open

drain ports)

Figure 28. Typ. V

- V

(standard ports)

54/81 Doc ID 15275 Rev 11

at VDD = 3.0 V

Figure 29. Typ. V

(standard ports)

- V

at VDD = 1.8 V

STM8L101xx Electrical parameters

ai17007

1.65 1.8 1.95 2.1 2.25 2.4 2.55 2.7 2.85 3 3.15 3.3 3.45 3.6

[V]

Pull-Up resistance [k ]

-40°C

25°C

85°C

125°C

NRST pin

The NRST pin input driver is CMOS. A permanent pull-up is present. R

PU(NRST)

Subject to general operating conditions for V

Table 30. NRST pin characteristics

Symbol Parameter Conditions Min Typ

IH(NRST)

OL(NRST)

PU(NRST)

OP(NRST)

NF(NRST)

1. Data based on characterization results, not tested in production.

2. The RPU pull-up equivalent resistor is based on a resistive transistor (Figure 30). Corresponding I characteristics are described in Figure 31.

3. Data guaranteed by design, not tested in production.

has the same value as RPU (see Table 26 on page 50).

and TA unless otherwise specified.

IL(NRST)

F(NRST)

NRST input low level voltage

NRST input high level voltage

NRST output low level voltage IOL = 2 mA - - VDD-0.8

NRST pull-up equivalent resistor

NRST input filtered pulse

NRST output pulse width 20 - - ns

NRST input not filtered pulse

(1)

(2)

(3)

(1)

Max Unit

1.4 - V

-0.8

30 45 60 kΩ

- - 50 ns

300 - - ns

current

Figure 30. Typical NRST pull-up resistance RPU vs. V

Doc ID 15275 Rev 11 55/81

Electrical parameters STM8L101xx

ai17006

100

120

1.65 1.8 1.95 2.1 2.25 2.4 2.55 2.7 2.85 3 3.15 3.3 3.45 3.6

[V]

Pull-Up cur rent [µA]

-40°C

25°C

85°C

125°C

0.1μF

EXTERNAL

RESET

CIRCUIT

STM8L

Filter

INTERNAL RESET

RSTIN

Figure 31. Typical NRST pull-up current Ipu vs. V

The reset network shown in Figure 32 protects the device against parasitic resets. The user must ensure that the level on the NRST pin can go below the V

max. level specified in

Ta bl e 3 0 . Otherwise the reset is not taken into account internally. For power consumption-

sensitive applications, the capacity of the external reset capacitor can be reduced to limit the charge/discharge current. If the NRST signal is used to reset the external circuitry, the user must pay attention to the charge/discharge time of the external capacitor to meet the reset timing conditions of the external devices. The minimum recommended capacity is 10 nF

Figure 32. Recommended NRST pin configuration

56/81 Doc ID 15275 Rev 11

STM8L101xx Electrical parameters

9.3.7 Communication interfaces

Serial peripheral interface (SPI)

Unless otherwise specified, the parameters given in Ta bl e 3 1 are derived from tests performed under ambient temperature, f conditions summarized in Section 9.3.1. Refer to I/O port characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO).

Table 31. SPI characteristics

Symbol Parameter Conditions

MASTER

frequency and VDD supply voltage

(1)

Min Max Unit

SCK

1/t

c(SCK)

r(SCK)

f(SCK)

su(NSS)

h(NSS)

w(SCKH)

w(SCKL)

su(MI)

su(SI)

h(MI)

h(SI)

a(SO)

dis(SO)

v(SO)

v(MO)

h(SO)

h(MO)

(2)

(2)(3)

(2)(4)

(2)

SPI clock frequency

Master mode 0 8

Slave mode 0 8

SPI clock rise and fall time Capacitive load: C = 30 pF - 30

NSS setup time Slave mode 4 x T

MASTER

NSS hold time Slave mode 80 -

SCK high and low time

Master mode,

MASTER

= 8 MHz, f

SCK

= 4 MHz

105 145

Master mode 30 -

Data input setup time

Slave mode 3 -

Master mode 15 -

Data input hold time

Slave mode 0 -

Data output access time Slave mode - 3x T

MASTER

Data output disable time Slave mode 30 -

Data output valid time Slave mode (after enable edge) - 60

Data output valid time

Master mode (after enable edge)

-20

Slave mode (after enable edge) 15 -

Data output hold time

Master mode (after enable edge)

MHz

1. Parameters are given by selecting 10-MHz I/O output frequency.

2. Values based on design simulation and/or characterization results, and not tested in production.

3. Min time is for the minimum time to drive the output and max time is for the maximum time to validate the data.

4. Min time is for the minimum time to invalidate the output and max time is for the maximum time to put the data in Hi-Z.

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Electrical parameters STM8L101xx

ai14134

SCK Input

CPHA=0

MOSI

INPUT

MISO

OUT PUT

CPHA=0

MS B O U T

MSB IN

BI T6 O UT

LSB IN

LSB OUT

CPOL=0

CPOL=1

BIT1 IN

NSS input

SU(NSS)

c(SCK)

h(NSS)

a(SO)

w(SCKH)

w(SCKL)

v(SO)

h(SO)

r(SCK)

f(SCK)

dis(SO)

su(SI)

h(SI)

Figure 33. SPI timing diagram - slave mode and CPHA = 0

Figure 34. SPI timing diagram - slave mode and CPHA = 1

NSS input

SU(NSS)

CPHA=1 CPOL=0

CPHA=1 CPOL=1

SCK Input

MISO

OUT PUT

MOSI

INPUT

a(SO)

w(SCKH)

w(SCKL)

su(SI)

MS B O U T

MSB IN

1. Measurement points are done at CMOS levels: 0.3V

v(SO)

h(SI)

c(SCK)

and 0.7V

BI T6 O UT

BIT1 IN

DD.

(1)

h(SO)

h(NSS)

r(SCK)

f(SCK)

LSB IN

dis(SO)

LSB OUT

ai14135

58/81 Doc ID 15275 Rev 11

STM8L101xx Electrical parameters

ai14136

SCK Input

CPHA=0

MOSI

OUTUT

MISO

INP UT

CPHA=0

MSBIN

M SB OUT

BIT6 IN

LSB OUT

LSB IN

CPOL=0

CPOL=1

B I T1 OUT

NSS input

c(SCK)

w(SCKH)

w(SCKL)

r(SCK)

f(SCK)

h(MI)

High

SCK Input

CPHA=1

CPOL=0

CPOL=1

su(MI)

v(MO)

h(MO)

Figure 35. SPI timing diagram - master mode

(1)

1. Measurement points are done at CMOS levels: 0.3V

and 0.7V

DD.

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Electrical parameters STM8L101xx

Inter IC control interface (I2C)

Subject to general operating conditions for VDD,

The STM8L I

C interface meets the requirements of the Standard I2C communication

MASTER

, and TA unless otherwise specified.

protocol described in the following table with the restriction mentioned below:

Refer to I/O port characteristics for more details on the input/output alternate function characteristics (SDA and SCL).

Table 32. I2C characteristics

Standard mode

Symbol Parameter

w(SCLL)

w(SCLH)

su(SDA)

h(SDA)

r(SDA)

r(SCL)

f(SDA)

f(SCL)

h(STA)

su(STA)

su(STO)

w(STO:STA)

1. f

SCK

Data based on standard I

The maximum hold time of the START condition has only to be met if the interface does not stretch the low

3. period of SCL signal.

The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the

4. undefined region of the falling edge of SCL

SCL clock low time 4.7 - 1.3 -

SCL clock high time 4.0 - 0.6 -

SDA setup time 250 - 100 -

SDA data hold time 0

SDA and SCL rise time - 1000 - 300

SDA and SCL fall time - 300 - 300

START condition hold time 4.0 - 0.6 -

Repeated START condition setup time

STOP condition setup time 4.0 - 0.6 - μs

STOP to START condition time (bus free)

Capacitive load for each bus line - 400 - 400 pF

must be at least 8 MHz to achieve max fast I2C speed (400 kHz).

C protocol requirement, not tested in production.

I2C

(2)

Min

Max

(3)

4.7 - 0.6 -

4.7 - 1.3 - μs

Fast mode I2C

(2)

-0

Min

(2)

(4)

Max

900

(1)

(2)

(3)

Unit

μs

Note: For speeds around 200 kHz, achieved speed can have ± 5% tolerance

For other speed ranges, achieved speed can have

2% tolerance

The above variations depend on the accuracy of the external components used.

60/81 Doc ID 15275 Rev 11

STM8L101xx Electrical parameters

REPEATED START

START

STOP

START

f(SDA)

r(SDA)

su(SDA)th(SDA)

f(SCL)

r(SCL)

w(SCLL)

w(SCLH)

h(STA)

su(STO)

su(STA)tw(STO:STA)

SDA

SCL

4.7kΩ SDA

STM8L

SCL

100Ω

4.7kΩ

I2CBUS

Figure 36.

Typical application with I2C bus and timing diagram

1. Measurement points are done at CMOS levels: 0.3 x VDD and 0.7 x V

9.3.8 Comparator characteristics

offset

START

Comparator external reference -0.1 - VDD-1.25 V

(2)

Comparator input voltage range -0.25 - VDD+0.25 V

Comparator offset error - - ± 20 mV

Startup time (after BIAS_EN) - - 3

Analog comparator consumption - - 25

Analog comparator consumption during power-down

Table 33. Comparator characteristics

Symbol Parameter Conditions Min

IN(COMP_REF)

DD(COMP)

(1)

Typ Max

--60

(1)

Unit

µs

µA

100-mV input step

with 5-mV overdrive,

--2

propag

(2)

Comparator propagation delay

input rise time = 1 ns

1. Data guaranteed by design, not tested in production.

2. The comparator accuracy depends on the environment. In particular, the following cases may reduce the accuracy of the comparator and must be avoided:

- Negative injection current on the I/Os close to the comparator inputs

- Switching on I/Os close to the comparator inputs

- Negative injection current on not used comparator input.

- Switching with a high dV/dt on not used comparator input. These phenomena are even more critical when a big external serial resistor is added on the inputs.

Doc ID 15275 Rev 11 61/81

(1)

µs

Electrical parameters STM8L101xx

9.3.9 EMC characteristics

Susceptibility tests are performed on a sample basis during product characterization.

Functional EMS (electromagnetic susceptibility)

Based on a simple running application on the product (toggling 2 LEDs through I/O ports), the product is stressed by two electromagnetic events until a failure occurs (indicated by the LEDs).

● ESD: Electrostatic discharge (positive and negative) is applied on all pins of the device

until a functional disturbance occurs. This test conforms with the IEC 61000-4-2 standard.

● FTB: A burst of fast transient voltage (positive and negative) is applied to V

through a 100 pF capacitor, until a functional disturbance occurs. This test conforms with the IEC 61000-4-4 standard.

A device reset allows normal operations to be resumed. The test results are given in the table below based on the EMS levels and classes defined in application note AN1709.

Designing hardened software to avoid noise problems

EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular.

and VSS

Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application.

Prequalification trials:

Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the oscillator pins for 1 second.

To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015).

Table 34. EMS data

Symbol Parameter Conditions

Voltage limits to be applied on any I/O pin to

FESD

induce a functional disturbance

Fast transient voltage burst limits to be

applied through 100 pF on VDD and V

EFTB

pins to induce a functional disturbance

LQFP32, V

= 3.3 V 3B

= 3.3 V, f

HSI

/2 4A

HSI

Level/

Class

62/81 Doc ID 15275 Rev 11

STM8L101xx Electrical parameters

Electromagnetic interference (EMI)

Based on a simple application running on the product (toggling 2 LEDs through the I/O ports), the product is monitored in terms of emission. This emission test is in line with the norm SAE J 1752/3 which specifies the board and the loading of each pin.

Table 35. EMI data

(1)

Max vs.

Unit

16 MHz

dBμV30 MHz to 130 MHz -6

Symbol Parameter Conditions

= 3.6 V,

TA = +25 °C,

EMI

Peak level

LQFP32 conforming to IEC61967-2

Monitored

frequency band

0.1 MHz to 30 MHz -3

130 MHz to 1 GHz -5

SAE EMI Level 1 -

1. Not tested in production.

Absolute maximum ratings (electrical sensitivity)

Based on two different tests (ESD and LU) using specific measurement methods, the product is stressed in order to determine its performance in terms of electrical sensitivity. For more details, refer to the application note AN1181.

Electrostatic discharge (ESD)

Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts*(n+1) supply pin).

This test conforms to the JESD22-A114A/A115A standard.

Table 36. ESD absolute maximum ratings

Symbol Ratings Conditions

ESD(HBM)

ESD(CDM)

Electrostatic discharge voltage (human body model)

Electrostatic discharge voltage (charge device model)

= +25 °C

Maximum

(1)

value

2000

500

Unit

1. Data based on characterization results, not tested in production.

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Electrical parameters STM8L101xx

Static latch-up

● LU: 2 complementary static tests are required on 10 parts to assess the latch-up

performance. A supply overvoltage (applied to each power supply pin) and a current injection (applied to each input, output and configurable I/O pin) are performed on each sample. This test conforms to the EIA/JESD 78 IC latch-up standard. For more details, refer to the application note AN1181.

Table 37. Electrical sensitivities

Symbol Parameter Class

LU Static latch-up class II

9.4 Thermal characteristics

The maximum chip junction temperature (T

) must never exceed the values given in

Jmax

Table 16: General operating conditions on page 40.

The maximum chip-junction temperature, T

, in degrees Celsius, may be calculated

Jmax

using the following equation:

Jmax

= T

Amax

+ (P

Dmax

x ΘJA)

Where:

● T

● Θ

● P

is the maximum ambient temperature in °C

Amax

is the package junction-to-ambient thermal resistance in °C/W

is the sum of P

Dmax

is the product of I

INTmax

and P

I/Omax (PDmax

and VDD, expressed in watts. This is the maximum chip

internal power.

● P

represents the maximum power dissipation on output pins

I/Omax

where: P

I/Omax =

taking into account the actual V

Σ (VOL*IOL) + Σ((VDD-V

OH)*IOH

OL/IOL and VOH/IOH

the application.

= P

INTmax

+ P

I/Omax

)

of the I/Os at low and high level in

64/81 Doc ID 15275 Rev 11

STM8L101xx Electrical parameters

Table 38. Thermal characteristics

(1)

Symbol Parameter Value Unit

Thermal resistance junction-ambient LQFP 32 - 7 x 7 mm

Thermal resistance junction-ambient UFQFPN 32 - 5 x 5 mm

Thermal resistance junction-ambient UFQFPN 28 - 4 x 4 mm

Thermal resistance junction-ambient UFQFPN 20 - 3 x 3 mm - 0.6 mm

Thermal resistance junction-ambient TSSOP 20

1. Thermal resistances are based on JEDEC JESD51-2 with 4-layer PCB in a natural convection environment.

60 °C/W

25 °C/W

80 °C/W

102 °C/W

110 °C/W

Doc ID 15275 Rev 11 65/81

Package characteristics STM8L101xx

10 Package characteristics

10.1 ECOPACK

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark.

66/81 Doc ID 15275 Rev 11

STM8L101xx Package characteristics

Seating plane

ddd C

Pin # 1 ID R = 0.30

A0B8_ME

Bottom view

10.2 Package mechanical data

Figure 37. UFQFPN32 - 32-lead ultra thin fine pitch

quad flat no-lead package outline

(1)(2)(3)

(5x5)

Figure 38. UFQFPN32 recommended

footprint

(1)(4)

1. Drawing is not to scale.

2. All leads/pads should be soldered to the PCB to improve the lead/pad solder joint life.

3. There is an exposed die pad on the underside of the UFQFPN package. It is recommended to connect and solder this backside pad to PCB ground.

4. Dimensions are in millimeters.

Table 39. UFQFPN32 - 32-lead ultra thin fine pitch quad flat no-lead package (5 x 5),

package mechanical data

mm inches

Dim.

Min Typ Max Min Typ Max

A 0.5 0.55 0.6 0.0197 0.0217 0.0236

A1 0.00 0.02 0.05 0 0.0008 0.0020

A3 0.152 0.006

b 0.18 0.23 0.28 0.0071 0.0091 0.0110

D 4.90 5.00 5.10 0.1929 0.1969 0.2008

D2 3.50 0.1378

E 4.90 5.00 5.10 0.1929 0.1969 0.2008

E2 3.40 3.50 3.60 0.1339 0.1378 0.1417

e 0.500 0.0197

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(1)

Package characteristics STM8L101xx

Table 39. UFQFPN32 - 32-lead ultra thin fine pitch quad flat no-lead package (5 x 5),

package mechanical data (continued)

mm inches

Dim.

Min Typ Max Min Typ Max

L 0.30 0.40 0.50 0.0118 0.0157 0.0197

ddd 0.08 0.0031

Number of pins

N32

1. Values in inches are converted from mm and rounded to 4 decimal digits.

(1)

68/81 Doc ID 15275 Rev 11

STM8L101xx Package characteristics

Figure 39. LQFP32 - 32-pin low profile quad flat

package outline (7 x 7)

Seating plane

AA2

ccc

24 17

E3 E1 E

932

Pin 1 identification

(1)

Gage plane

0.25 mm

5V_ME

footprint

(1)(2)

Figure 40. LQFP32 recommended

1. Drawing is not to scale.

2. Dimensions are in millimeters.

Table 40. LQFP32- 32-pin low profile quad flat package (7x7), package mechanical data

mm inches

Dim.

Min Typ Max Min Typ Max

(1)

5V_F

A1.60.063

A1 0.05 0.15 0.002 0.0059

A2 1.35 1.4 1.45 0.0531 0.0551 0.0571

b 0.3 0.37 0.45 0.0118 0.0146 0.0177

c 0.09 0.2 0.0035 0.0079

D 8.8 9 9.2 0.3465 0.3543 0.3622

D1 6.8 7 7.2 0.2677 0.2756 0.2835

D3 5.6 0.2205

E 8.8 9 9.2 0.3465 0.3543 0.3622

E1 6.8 7 7.2 0.2677 0.2756 0.2835

E3 5.6 0.2205

e 0.8 0.0315

L 0.45 0.6 0.75 0.0177 0.0236 0.0295

L1 1 0.0394

K 0.0° 3.5° 7.0° 0.0° 3.5° 7.0°

ccc 0.1 0.0039

N32

1. Values in inches are converted from mm and rounded to 4 decimal digits.

Number of pins

Doc ID 15275 Rev 11 69/81

Package characteristics STM8L101xx

A0B0_ME

dddddd

Figure 41. UFQFPN28 - 28-lead ultra thin fine pitch

quad flat no-lead package outline (4 x 4)

Figure 42. UFQFPN28 recommended

(1)

footprint

(1)(2)

1. Drawing is not to scale

2. Dimensions are in millimeters

Table 41. UFQFPN28 - 28-lead ultra thin fine pitch quad flat no-lead package (4 x 4),

package mechanical data

mm inches

Dim.

Min Typ Max Min Typ Max

(1)

A 0.5 0.55 0.6 0.0197 0.0217 0.0236

A1 0 0.02 0.05 0 0.0008 0.002

A3 0.152 0.0060

b 0.18 0.25 0.3 0.0071 0.0098 0.0118

D 4 0.1575

E 4 0.1575

e 0.5 0.0197

L1 0.25 0.35 0.45 0.0098 0.0138 0.0177

L2 0.3 0.4 0.5 0.0118 0.0157 0.0197

ddd 0.08 0.0031

N28

1. Values in inches are converted from mm and rounded to 4 decimal digits.

70/81 Doc ID 15275 Rev 11

Number of pins

STM8L101xx Package characteristics

1620

ddd

A0A5_ME

BJ

Figure 43. UFQFPN20 3 x 3 mm 0.6 mm package

outline

(1)

1. Drawing is not to scale

2. Dimensions are in millimeters

Figure 44. UFQFPN20 recommended

footprint

(1)(2)

Table 42. UFQFPN20 3 x 3 mm 0.6 mm mechanical data

Symbol

millimeters

inches

(1)

Min Typ Max Min Typ Max

D 2.900 3.000 3.100 0.1181

E 2.900 3.000 3.100 0.1181

A 0.500 0.550 0.600 0.0197 0.0217 0.0236

A1 0 0.020 0.050 0 0.0008 0.002

A3 0.152 0.006

e 0.500 0.0197

L1 0.500 0.550 0.600 0.0197 0.0217 0.0236

L2 0.300 0.350 0.400 0.0118 0.0138 0.0157

L3 0.150 0.0059

L4 0.200 0.0079

b 0.180 0.250 0.300 0.0071 0.0098 0.0118

ddd 0.050 0.002

1. Values in inches are rounded to 4 decimal digits

Doc ID 15275 Rev 11 71/81

Package characteristics STM8L101xx

TSSOP20-M

EE1

BJ

Figure 45. TSSOP20 - 20-lead thin shrink small

package outline

(1)

Figure 46. TSSOP20 recommended

1. Drawing is not to scale

2. Dimensions are in millimeters

Table 43. 20-lead thin shrink small package, mechanical data

mm inches

Dim.

Min Typ Max Min Typ Max

footprint

(1)(2)

(1)

A 1.2 0.0472

A1 0.05 0.15 0.002 0.0059

A2 0.8 1 1.05 0.0315 0.0394 0.0413

b 0.19 0.3 0.0075 0.0118

CP 0.1 0.0039

c 0.09 0.2 0.0035 0.0079

D 6.4 6.5 6.6 0.252 0.2559 0.2598

E 6.2 6.4 6.6 0.2441 0.252 0.2598

E1 4.3 4.4 4.5 0.1693 0.1732 0.1772

e - 0.65 - 0.1693 0.0256 -

L 0.45 0.6 0.75 0.1693 0.0236 0.0295

L1 1 0.0394

a0° 8°0° 8°

N20

1. Values in inches are converted from mm and rounded to 4 decimal digits.

Number of pins

72/81 Doc ID 15275 Rev 11

STM8L101xx Device ordering information

STM8 L 101 F 3 U 6 A TR

Product class

STM8 microcontroller

Pin count

K = 32 pins

G = 28 pins

F = 20 pins

Package

U = UFQFPN T = LQFP

P = TSSOP

Example:

Sub-family type

101 = sub-family

Family type

L = Low power

Temperature range

3 = -40 °C to 125 °C

6 = -40 °C to 85 °C

Program memory size

1 = 2 Kbytes

2 = 4 Kbytes

3 = 8 Kbytes

COMP_REF availability on UFQFPN20 and UFQFPN28

A = COMP_REF available

Blank = COMP_REF not available

Shipping

TR = Tape and reel Blank = Tray

11 Device ordering information

Figure 47. STM8L101xx ordering information scheme

1. For a list of available options (e.g. memory size, package) and orderable part numbers or for further information on any aspect of this device, please go to www.st.com or contact the ST Sales Office nearest to you.

Doc ID 15275 Rev 11 73/81

STM8 development tools STM8L101xx

12 STM8 development tools

Development tools for the STM8 microcontrollers include the full-featured STice emulation system supported by a complete software tool package including C compiler, assembler and integrated development environment with high-level language debugger. In addition, the STM8 is to be supported by a complete range of tools including starter kits, evaluation boards and a low-cost in-circuit debugger/programmer.

12.1 Emulation and in-circuit debugging tools

The STice emulation system offers a complete range of emulation and in-circuit debugging features on a platform that is designed for versatility and cost-effectiveness. In addition, STM8 application development is supported by a low-cost in-circuit debugger/programmer.

The STice is the fourth generation of full featured emulators from STMicroelectronics. It offers new advanced debugging capabilities including profiling and coverage to help detect and eliminate bottlenecks in application execution and dead code when fine tuning an application.

In addition, STice offers in-circuit debugging and programming of STM8 microcontrollers via the STM8 single wire interface module (SWIM), which allows non-intrusive debugging of an application while it runs on the target microcontroller.

For improved cost effectiveness, STice is based on a modular design that allows you to order exactly what you need to meet your development requirements and to adapt your emulation system to support existing and future ST microcontrollers.

STice key features

● Occurrence and time profiling and code coverage (new features)

● Program and data trace recording up to 128 KB records

● Read/write on the fly of memory during emulation

● In-circuit debugging/programming via SWIM protocol

● 8-bit probe analyzer

● Power supply follower managing application voltages between 1.62 to 5.5 V

● Modularity that allows you to specify the components you need to meet your

development requirements and adapt to future requirements

● Supported by free software tools that include integrated development environment

(IDE), programming software interface and assembler for STM8.

74/81 Doc ID 15275 Rev 11

STM8L101xx STM8 development tools

12.2 Software tools

STM8 development tools are supported by a complete, free software package from STMicroelectronics that includes ST Visual Develop (STVD) IDE and the ST Visual Programmer (STVP) software interface. STVD provides seamless integration of the Cosmic and Raisonance C compilers for STM8. A free version that outputs up to 32 Kbytes of code is available.

12.2.1 STM8 toolset

STM8 toolset with STVD integrated development environment and STVP programming software is available for free download at www.st.com/mcu. This package includes:

ST Visual Develop – Full-featured integrated development environment from ST, featuring

● Seamless integration of C and ASM toolsets

● Full-featured debugger

● Project management

● Syntax highlighting editor

● Integrated programming interface

● Support of advanced emulation features for STice such as code profiling and coverage

ST Visual Programmer (STVP) – Easy-to-use, unlimited graphical interface allowing read, write and verify of your STM8 microcontroller’s Flash program memory, data EEPROM and option bytes. STVP also offers project mode for saving programming configurations and automating programming sequences.

12.2.2 C and assembly toolchains

Control of C and assembly toolchains is seamlessly integrated into the STVD integrated development environment, making it possible to configure and control the building of your application directly from an easy-to-use graphical interface.

Available toolchains include:

● Cosmic C compiler for STM8 – One free version that outputs up to 32 Kbytes of code

is available. For more information, see www.cosmic-software.com.

● Raisonance C compiler for STM8 – One free version that outputs up to 32 Kbytes of

code. For more information, see www.raisonance.com.

● STM8 assembler linker – Free assembly toolchain included in the STVD toolset,

which allows you to assemble and link your application source code.

12.3 Programming tools

During the development cycle, STice provides in-circuit programming of the STM8 Flash microcontroller on your application board via the SWIM protocol. Additional tools are to include a low-cost in-circuit programmer as well as ST socket boards, which provide dedicated programming platforms with sockets for programming your STM8.

For production environments, programmers will include a complete range of gang and automated programming solutions from third-party tool developers already supplying programmers for the STM8 family.

Doc ID 15275 Rev 11 75/81

Revision history STM8L101xx

13 Revision history

Table 44. Document revision history

Date Revision Changes

19-Dec-2008 1 Initial release.

Added TSSOP28 package Modified packages on first page COMPx_OUT pins removed Added Figure 6: 28-pin TSSOP package pinout on page 17

Modified Section 9: Electrical parameters on page 37. Updated UBC[7:0] description in Section 7: Option bytes. Updated low power current consumption on cover page. Updated Table 13: Voltage characteristics, Table 20: Total current

22-Apr-2009 2

24-Apr-2009 3

14-May-2009 4

15-May-2009 5

consumption and timing in Halt and Active-halt mode at VDD = 1.65 V to 3.6 V, Table 26: I/O static characteristics, Table 30: NRST pin characteristics, and Section 9.3.9: EMC characteristics.

Updated PA1/NRST, PC0 and PC1 in Table 4: STM8L101xx pin

description.

Added ECC feature. Changed internal RC frequency to 38 kHz. Updated electrical characteristics in Ta b l e 1 6, Ta b l e 1 8, Ta b l e 1 9,

Ta bl e 2 0 , Tab l e 22 , Ta bl e 2 3 , and Tab l e 2 6.

Corrected title on cover page. Changed VFQFPN32 to WFQFPN32 and updated Ta b le 39 :

UFQFPN32 - 32-lead ultra thin fine pitch quad flat no-lead package (5 x 5), package mechanical data.

Updated Ta bl e 1 3 , Tab l e 2 6, and Ta b l e 3 3.

Replaced WFQFPN20 3 x 3 mm 0.8 mm package by UFQFPN20 3 x 3 mm 0.6 mm package (first page, Table 16: General operating

conditions on page 40, Table 38: Thermal characteristics on page 65, Section 10.2: Package mechanical data on page 67)

Added one UFQFPN20 version with COMP_REF Modified Figure 40: LQFP32 recommended footprint(1) on page 69 Added I

values in Table 25: Flash program memory on page 49

PROG

Updated Table 31: SPI characteristics on page 57

Added STM8L101F3U6ATR part number in Section 4: Pin

description on page 14 and in Figure 47: STM8L101xx ordering information scheme on page 73

76/81 Doc ID 15275 Rev 11

STM8L101xx Revision history

Table 44. Document revision history (continued)

Date Revision Changes

Removed TSSOP28 package Modified consumption value on first page Added BEEP_CSR (address 00 50F3h) in Table 7: General

hardware register map on page 25

TIM2_PSCRL replaced with TIM2_PSCR and CLK_PCKEN replaced with CLK_PCKENR in Table 7: General hardware register

map on page 25

Added graphs in Section 9: Electrical parameters on page 37

(AH) and tWU(Halt) max values in Tabl e 2 0 : To t a l c u r r e n t

12-Jun-2009 6

Added t

consumption and timing in Halt and Active-halt mode at VDD = 1.65 V to 3.6 V on page 44

Modified Table 20: Total current consumption and timing in Halt and

Active-halt mode at VDD = 1.65 V to 3.6 V on page 44

Updated Table 22: HSI oscillator characteristics on page 46,

Table 23: LSI oscillator characteristics on page 47 and Ta b l e 2 4: RAM and hardware registers on page 49

Modified Table 27: Output driving current (standard ports) on

page 53

Removed note 1 in Table 37: Electrical sensitivities on page 64 Added note to Table 39: UFQFPN32 - 32-lead ultra thin fine pitch

quad flat no-lead package (5 x 5), package mechanical data on page 67 and

Table 41: UFQFPN28 - 28-lead ultra thin fine pitch quad flat no-lead package (4 x 4), package mechanical data on page 70

Doc ID 15275 Rev 11 77/81

Revision history STM8L101xx

Table 44. Document revision history (continued)

Date Revision Changes

Added STM8L101F2U6ATR, STM8L101G2U6ATR and STM8L101G3U6ATR part numbers Modified Section 2: Description on page 7. Modified Table 2: Device features on page 8 (Flash) Modified Figure 1: STM8L101xx device block diagram on page 9 Modified Section 3.5: Memory on page 11 Added note below Figure 2: Standard 20-pin UFQFPN package

pinout on page 14 and Figure 5: Standard 28-pin UFQFPN package pinout on page 17

Added Figure 6: 28-pin UFQFPN package pinout for

STM8L101G3U6ATR and STM8L101G2U6ATR part numbers on page 18

Modified reset values for Px_IDR registers in Table 6: I/O Port

hardware register map on page 24

Added Section 6: Interrupt vector mapping on page 32 Modified OPT numbers in Section 7: Option bytes on page 34 Modified OPT2 in Table 10: Option bytes on page 34 Added Section 8: Unique ID on page 36 TIM_IR pin replaced with IR_TIM pin

07-Sep-2009 7

Modified Table 20: Total current consumption and timing in Halt and

Active-halt mode at VDD = 1.65 V to 3.6 V on page 44

Modified Figure 15: Typ. IDD(Halt) vs. VDD, fCPU = 2 MHz and

16 MHz on page 44 and Figure 19: Typical LSI RC frequency vs. VDD on page 48

Modified Table 27: Output driving current (standard ports) on

page 53

Updated Table 29: Output driving current (PA0 with high sink LED

driver capability) on page 53

Modified : Functional EMS (electromagnetic susceptibility) on

page 62

Modified conditions in Table 35: EMI data on page 63 Added note to Figure 37: UFQFPN32 - 32-lead ultra thin fine pitch

quad flat no-lead package outline (5 x 5) on page 67

Modified Figure 41: UFQFPN28 - 28-lead ultra thin fine pitch quad

flat no-lead package outline (4 x 4)(1) on page 70

Added Figure 44: UFQFPN20 recommended footprint (1) on

page 71

Added Figure 46: TSSOP20 recommended footprint (1) on page 72 CMP replaced with COMP

78/81 Doc ID 15275 Rev 11

STM8L101xx Revision history

Table 44. Document revision history (continued)

Date Revision Changes

Modified status of the document (datasheet instead of preliminary data) Replaced WFQFPN32 with UFQFPN32 and WFQFPN28 with UFQFPN28. Modified title of the reference manual mentioned in Section 2:

Description on page 7

Added references to “low-density” in Section 2: Description on

page 7, Section 3.5: Memory on page 11 and in Figure 8: Memory map on page 23

29-Nov-2009 8

18-Jun-2010 9

Modified Figure 8: Memory map on page 23 (unique ID are added)

Table 7: General hardware register map on page 25: Modified

reserved areas and IR block replaced with IRTIM block Modified t

in Table 17: Operating conditions at power-up /

TEMP

power-down on page 41

Modified Table 23: LSI oscillator characteristics on page 47 Modified Table 25: Flash program memory on page 49 (t

PROG

)

Modified Table 16: General operating conditions on page 40 and

Table 38: Thermal characteristics on page 65

Modified Section 10: Package characteristics on page 66

Modified Introduction and Description Modified one reserved area (0x00 5055 to 0x00 509F) in Ta b l e 7 :

General hardware register map on page 25

ModifiedTable 4: STM8L101xx pin description on page 20: modified note 2 and removed “wpu” for PC0 and PC1 Removed one note to Table 22: HSI oscillator characteristics on

page 46

Modified first paragraph in Section : NRST pin on page 55 Modified OPT3 description in Table 11: Option byte description on

page 34

Added note 5 to Table 18: Total current consumption in Run mode on

page 42

Modified V

ESD(CDM)

in Table 36: ESD absolute maximum ratings on

page 63

Modified Figure 36: Typical application with I2C bus and timing

diagram 1) on page 61

Modified COMP_REF availability information in Figure 47:

STM8L101xx ordering information scheme on page 73

Modified Section 12.2: Software tools on page 75

Doc ID 15275 Rev 11 79/81

Revision history STM8L101xx

Table 44. Document revision history (continued)

Date Revision Changes

Modified Table 3: Legend/abbreviation for table 4 on page 20 and

Table 4: STM8L101xx pin description on page 20 (for PA0, PA1, PB0

and PB4)

21-Jul-2010 10

14-Oct-2010 11

Modified Table 13: Voltage characteristics on page 38 and Ta b l e 1 4:

Current characteristics on page 39

Modified V

in Table 26: I/O static characteristics on page 50

Added notes below UFQFPN32 package

Added STM8L101F1 devices:

Modified Table 1: Device summary on page 1, Table 2: Device

features on page 8 and Table 5: Flash and RAM boundary addresses on page 24

Modified warning below Figure 3 on page 15 and belowTa b le 4:

STM8L101xx pin description on page 20

Modified Figure 47: STM8L101xx ordering information scheme on

page 73

Modifed text above Figure 32: Recommended NRST pin

configuration on page 56

Modified Figure 32 on page 56

80/81 Doc ID 15275 Rev 11

STM8L101xx

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Doc ID 15275 Rev 11 81/81

ST STM8L101F1, STM8L101F2, STM8L101F3, STM8L101G2, STM8L101G3 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Table 1. Device summary

1 Introduction

2 Description

Table 2. Device features

3 Product overview

Figure 1. STM8L101xx device block diagram

3.1 Central processing unit STM8

3.2 Development tools

3.3 Single wire data interface (SWIM) and debug module

3.4 Interrupt controller

3.5 Memory

3.6 Low power modes

3.7 Voltage regulators

3.8 Clock control

3.9 Independent watchdog

3.10 Auto-wakeup counter

3.11 General purpose and basic timers

3.12 Beeper

3.13 Infrared (IR) interface

3.14 Comparators

3.15 USART

3.16 SPI

3.17 I²C

4 Pin description

Figure 2. Standard 20-pin UFQFPN package pinout

Figure 4. 20-pin TSSOP package pinout

Figure 5. Standard 28-pin UFQFPN package pinout

Figure 7. 32-pin package pinout

Table 3. Legend/abbreviation for table 4

Table 4. STM8L101xx pin description

5 Memory and register map

Figure 8. Memory map

Table 5. Flash and RAM boundary addresses

Table 6. I/O Port hardware register map

Table 7. General hardware register map

Table 8. CPU/SWIM/debug module/interrupt controller registers

6 Interrupt vector mapping

Table 9. Interrupt mapping

7 Option bytes

Table 10. Option bytes

Table 11. Option byte description

8 Unique ID

Table 12. Unique ID registers (96 bits)

9 Electrical parameters

9.1 Parameter conditions

9.1.1 Minimum and maximum values

9.1.2 Typical values

9.1.3 Typical curves

9.1.4 Loading capacitor

Figure 9. Pin loading conditions

9.1.5 Pin input voltage

Figure 10. Pin input voltage

9.2 Absolute maximum ratings

Table 13. Voltage characteristics

Table 14. Current characteristics

Table 15. Thermal characteristics

9.3 Operating conditions

9.3.1 General operating conditions

Table 16. General operating conditions

9.3.2 Power-up / power-down operating conditions

Table 17. Operating conditions at power-up / power-down

9.3.3 Supply current characteristics

Table 18. Total current consumption in Run mode

Table 19. Total current consumption in Wait mode

Table 21. Peripheral current consumption

9.3.4 Clock and timing characteristics

Table 22. HSI oscillator characteristics

Figure 17. Typical HSI accuracy vs. temperature, VDD = 3 V

Table 23. LSI oscillator characteristics

9.3.5 Memory characteristics

Table 24. RAM and hardware registers

Table 25. Flash program memory

9.3.6 I/O port pin characteristics

Table 26. I/O static characteristics

Table 27. Output driving current (standard ports)

Table 28. Output driving current (true open drain ports)