Datasheet STM8L052R8 Datasheet (ST)

STM8L052R8

LQFP64

Value Line, 8-bit ultralow power MCU, 64-KB Flash,

256-byte data EEPROM, RTC, LCD, timers, USART, I2C, SPI, ADC

Datasheet − production data

Features

■ Operating conditions

– Operating power supply: 1.8 V to 3.6 V
– Temperature range: -40 °C to 85 °C

■ Low power features

– 5 low power modes: Wait, Low power run

(5.9 µA), Low power wait (3 µA), Active-halt
with full RTC (1.4 µA), Halt (400 nA)

– Dynamic power consumption:

200 µA/MHz + 330 µA
– Ultra-low leakage per I/0: 50 nA
– Fast wakeup from Halt: 4.7 µs

■ Advanced STM8 core

– Harvard architecture and 3-stage pipeline
– Max freq. 16 MHz, 16 CISC MIPS peak
– Up to 40 external interrupt sources

■ Reset and supply management

– Low power, ultra-safe BOR reset with 5

programmable thresholds
– Ultra low power POR/PDR
– Programmable voltage detector (PVD)

■ Clock management

– 32 kHz and 1 to 16 MHz crystal oscillators
– Internal 16 MHz factory-trimmed RC
– 38 kHz low consumption RC
– Clock security system

■ Low power RTC

– BCD calendar with alarm interrupt

– Digital calibration with +/- 0.5ppm accuracy
– Advanced anti-tamper detection

■ LCD: 8x24 or 4x28 w/ step-up converter

■ Memories

– 64 KB Flash program memory and

256 bytes data EEPROM with ECC, RWW
– Flexible write and read protection modes
– 4 KB of RAM

■ DMA

– 4 channels supporting ADC, SPIs, I2C,

USARTs, timers

– 1 channel for memory-to-memory

■ 12-bit ADC up to 1 Msps/28 channels

– Internal reference voltage

■ Timers

– Three 16-bit timers with 2 channels (used

as IC, OC, PWM), quadrature encoder

– One 16-bit advanced control timer with 3

channels, supporting motor control
– One 8-bit timer with 7-bit prescaler
– 2 watchdogs: 1 Window, 1 Independent
– Beeper timer with 1, 2 or 4 kHz frequencies

■ Communication interfaces

– Two synchronous serial interfaces (SPI)
–Fast I

2

C 400 kHz SMBus and PMBus

– Three USARTs (ISO 7816 interface + IrDA)

■ Up to 54 I/Os, all mappable on interrupt vectors

■ Development support

– Fast on-chip programming and non-

intrusive debugging with SWIM
– Bootloader using USART

June 2012 Doc ID 023337 Rev 1 1/109

This is information on a product in full production.

www.st.com

1

Contents STM8L052R8

Contents

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.1 Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.2 Ultra low power continuum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

3.1 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3.2 Central processing unit STM8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.2.1 Advanced STM8 Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.2.2 Interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.3 Reset and supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.3.1 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.3.2 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.3.3 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.4 Clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.5 Low power real-time clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.6 LCD (Liquid crystal display) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.7 Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.8 DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.9 Analog-to-digital converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.10 System configuration controller and routing interface . . . . . . . . . . . . . . . 19

3.11 Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.11.1 TIM1 - 16-bit advanced control timer . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.11.2 16-bit general purpose timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.11.3 8-bit basic timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.12 Watchdog timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.12.1 Window watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.12.2 Independent watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.13 Beeper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.14 Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.14.1 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.14.2 I²C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

2/109 Doc ID 023337 Rev 1

STM8L052R8 Contents

3.14.3 USART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.15 Infrared (IR) interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.16 Development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

4.1 System configuration options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

5 Memory and register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

5.1 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

5.2 Register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

6 Interrupt vector mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

7 Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

8 Electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

8.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

8.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

8.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

8.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

8.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

8.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

8.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

8.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

8.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

8.3.2 Embedded reset and power control block characteristics . . . . . . . . . . . 59

8.3.3 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

8.3.4 Clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

8.3.5 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

8.3.6 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

8.3.7 I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

8.3.8 Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

8.3.9 LCD controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

8.3.10 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

8.3.11 12-bit ADC1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

8.3.12 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

8.4 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

Doc ID 023337 Rev 1 3/109

Contents STM8L052R8

9 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

9.1 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

10 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

4/109 Doc ID 023337 Rev 1

STM8L052R8 List of tables

List of tables

Table 1. High density value line STM8L05xxx low power device features and

peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Table 2. Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 3. Legend/abbreviation for Table 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 4. High density value line STM8L05xxx pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 5. Flash and RAM boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 6. I/O port hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 7. General hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 8. CPU/SWIM/debug module/interrupt controller registers. . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Table 9. Interrupt mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Table 10. Option byte addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Table 11. Option byte description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Table 12. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Table 13. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Table 14. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Table 15. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Table 16. Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 59

Table 17. Total current consumption in Run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Table 18. Total current consumption in Wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Table 19. Total current consumption and timing in Low power run mode at VDD = 1.8 V to

3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Table 20. Total current consumption in Low power wait mode at VDD = 1.8 V to 3.6 V . . . . . . . . . . 69

Table 21. Total current consumption and timing in Active-halt mode

at VDD = 1.8 V to 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Table 22. Typical current consumption in Active-halt mode, RTC clocked by LSE external crystal. . 71

Table 23. Total current consumption and timing in Halt mode at VDD = 1.8 to 3.6 V . . . . . . . . . . . . 72

Table 24. Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Table 25. Current consumption under external reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Table 26. HSE external clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Table 27. LSE external clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Table 28. HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Table 29. LSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Table 30. HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Table 31. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Table 32. RAM and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Table 33. Flash program and data EEPROM memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Table 34. I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Table 35. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Table 36. Output driving current (high sink ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Table 37. Output driving current (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Table 38. Output driving current (PA0 with high sink LED driver capability). . . . . . . . . . . . . . . . . . . . 85

Table 39. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Table 40. SPI1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Table 41. I2C characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Table 42. LCD characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Table 43. Reference voltage characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Table 44. ADC1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Table 45. ADC1 accuracy with VDDA = 3.3 V to 2.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Doc ID 023337 Rev 1 5/109

List of tables STM8L052R8

Table 46. ADC1 accuracy with VDDA = 2.4 V to 3.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Table 47. ADC1 accuracy with VDDA = VREF

= 1.8 V to 2.4 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

+

Table 48. EMS data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

Table 49. EMI data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Table 50. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Table 51. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Table 52. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

Table 53. LQFP64 – 10 x 10 mm, 64-pin low-profile quad flat package mechanical data . . . . . . . . 105

Table 54. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

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STM8L052R8 List of figures

List of figures

Figure 1. High density value line STM8L05xxx device block diagram . . . . . . . . . . . . . . . . . . . . . . 12

Figure 2. High density value line STM8L05xxx clock tree diagram . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 3. STM8L052R8 64-pin LQFP64 package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 4. Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 5. Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Figure 6. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Figure 7. Power supply thresholds. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Figure 8. Typical I
Figure 9. Typical I
Figure 10. Typical I
Figure 11. Typical I
Figure 12. Typical I
Figure 13. Typical I

DD(RUN)

DD(RUN)

DD(Wait)

DD(Wait)

DD(LPR)

DD(LPW)

Figure 14. Typical IDD(AH) vs. V
Figure 15. Typical IDD(Halt) vs. V

from RAM vs. VDD (HSI clock source), f

from Flash vs. V
from RAM vs. V
from Flash (HSI clock source), f
vs. V

vs. V

(LSI clock source), all peripherals OFF . . . . . . . . . . . . . . . . . . . . 68

DD

(LSI clock source), all peripherals OFF

DD

(LSI clock source) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

DD

(internal reference voltage OFF) . . . . . . . . . . . . . . . . . . . . . . . . 72

DD

(HSI clock source), f

DD

(HSI clock source), f

DD

= 16 MHz 1). . . . . . . . . . . . . . . . . . . 66

CPU

=16 MHz

CPU

= 16 MHz

CPU

= 16 MHz 1). . . . . . . . . . . . . 66

CPU

Figure 16. HSE oscillator circuit diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Figure 17. LSE oscillator circuit diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Figure 18. Typical HSI frequency vs. V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

DD

Figure 19. Typical LSI clock source frequency vs. VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Figure 20. Typical VIL and VIH vs. VDD (standard I/Os). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Figure 21. Typical VIL and VIH vs. VDD (true open drain I/Os). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Figure 22. Typical pull-up resistance R
Figure 23. Typical pull-up current I

pu

vs. VDD with VIN=VSS. . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

PU

vs. VDD with VIN=VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Figure 24. Typical VOL @ VDD = 3.0 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Figure 25. Typical VOL @ VDD = 1.8 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Figure 26. Typical VOL @ VDD = 3.0 V (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Figure 27. Typical VOL @ VDD = 1.8 V (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Figure 28. Typical VDD - VOH @ VDD = 3.0 V (high sink ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Figure 29. Typical VDD - VOH @ VDD = 1.8 V (high sink ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Figure 30. Typical NRST pull-up resistance R
Figure 31. Typical NRST pull-up current I

vs. VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

PU

vs. VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

pu

Figure 32. Recommended NRST pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Figure 33. SPI1 timing diagram - slave mode and CPHA=0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Figure 34. SPI1 timing diagram - slave mode and CPHA=1
Figure 35. SPI1 timing diagram - master mode

(1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

(1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Figure 36. Typical application with I2C bus and timing diagram 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Figure 37. ADC1 accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Figure 38. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Figure 39. Power supply and reference decoupling (V

not connected to V

REF+

Figure 40. Power supply and reference decoupling (VREF+ connected to VDDA) . . . . . . . . . . . . . . 100

Figure 41. LQFP64 – 10 x 10 mm, 64 pin low-profile quad flat package outline . . . . . . . . . . . . . . . . 105

Figure 42. Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

Figure 43. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

1) . . . . . . . . . . . . . . . . . 64

1) . . . . . . . . . . . . . . . . 64

(1)

. . . . . . . . . . . . . . . . . 69

). . . . . . . . . . . . . 100

DDA

Doc ID 023337 Rev 1 7/109

Introduction STM8L052R8

1 Introduction

This document describes the features, pinout, mechanical data and ordering information of
the high density value line STM8L052R8 microcontroller with a Flash memory density of
64 Kbytes.

For further details on the whole STMicroelectronics high density family please refer to

Section 2.2: Ultra low power continuum.

For detailed information on device operation and registers, refer to the reference manual
(RM0031).

For information on to the Flash program memory and data EEPROM, refer to the
programming manual (PM0054).

For information on the debug module and SWIM (single wire interface module), refer to the
STM8 SWIM communication protocol and debug module user manual (UM0470).

For information on the STM8 core, refer to the STM8 CPU programming manual (PM0044).

High density value line devices provide the following benefits:

● Integrated system

– 64 Kbytes of high density embedded Flash program memory
– 256 bytes of data EEPROM
– 4 Kbytes of RAM
– Internal high speed and low-power low speed RC
– Embedded reset

● Ultra low power consumption

– 1 µA in Active-halt mode
– Clock gated system and optimized power management
– Capability to execute from RAM for Low power wait mode and low power run mode

● Advanced features

– Up to 16 MIPS at 16 MHz CPU clock frequency
– Direct memory access (DMA) for memory-to-memory or peripheral-to-memory

access

● Short development cycles

– Application scalability across a common family product architecture with

compatible pinout, memory map and modular peripherals

– Wide choice of development tools

These features make the value line STM8L05xxx ultra low power microcontroller family
suitable for a wide range of consumer and mass market applications.

Refer to Table 1: High density value line STM8L05xxx low power device features and

peripheral counts and Section 3: Functional overview for an overview of the complete range

of peripherals proposed in this family.

Figure 1 shows the block diagram of the high density value line STM8L05xxx family.

8/109 Doc ID 023337 Rev 1

STM8L052R8 Description

2 Description

The high density value line STM8L05xxx devices are members of the STM8L ultra low
power 8-bit family.

The value line STM8L05xxx ultra low power family features the enhanced STM8 CPU core
providing increased processing power (up to 16 MIPS at 16 MHz) while maintaining the
advantages of a CISC architecture with improved code density, a 24-bit linear addressing
space and an optimized architecture for low power operations.

The family includes an integrated debug module with a hardware interface (SWIM) which
allows non-intrusive In-application debugging and ultra-fast Flash programming.

High density value line STM8L05xxx microcontrollers feature embedded data EEPROM and
low-power, low-voltage, single-supply program Flash memory.

All devices offer 12-bit ADC, real-time clock, four 16-bit timers, one 8-bit timer as well as
standard communication interface such as two SPIs, I2C, three USARTs and 8x24 or 4x28­segment LCD. The 8x24 or
STM8L05xxx.

4x 28-segment LCD is available on the high density value line

The STM8L05xxx family operates from 1.8 V to 3.6 V and is available in the
temperature range.

The modular design of the peripheral set allows the same peripherals to be found in different
ST microcontroller families including 32-bit families. This makes any transition to a different
family very easy, and simplified even more by the use of a common set of development
tools.

All value line STM8L ultra low power products are based on the same architecture with the
same memory mapping and a coherent pinout.

-40 to +85 °C

Doc ID 023337 Rev 1 9/109

Description STM8L052R8

2.1 Device overview

Table 1. High density value line STM8L05xxx low power device features and

peripheral counts

Features STM8L052R8

Flash (Kbytes) 64

Data EEPROM (bytes) 256

RAM (Kbytes) 4

LCD 8x24 or 4x28

Basic

1

(8-bit)

Timers

General purpose

Advanced control

3

(16-bit)

1

(16-bit)

SPI 2
Communication
interfaces

I2C 1

USART 3

GPIOs 54

12-bit synchronized ADC
(number of channels)

(1)

1

(28)

RTC, window watchdog, independent watchdog,

Others

16-MHz and 38-kHz internal RC,

1- to 16-MHz and 32-kHz external oscillator

CPU frequency 16 MHz

Operating voltage 1.8 V to 3.6 V

Operating temperature -40 to +85 °C

Package LQFP64

1. The number of GPIOs given in this table includes the NRST/PA1 pin but the application can use the
NRST/PA1 pin as general purpose output only (PA1).

10/109 Doc ID 023337 Rev 1

STM8L052R8 Description

2.2 Ultra low power continuum

The ultra low power value line STM8L05xxx and STM8L15xxx are fully pin-to-pin, software
and feature compatible. Besides the full compatibility within the STM8L family, the devices
are part of STMicroelectronics microcontrollers ultra low power strategy which also includes
STM8L101xx and STM32L15xxx. The STM8L and STM32L families allow a continuum of
performance, peripherals, system architecture, and features.

They are all based on STMicroelectronics 0.13 µm ultra-low leakage process.

Note: 1 The STM8L05xxx is pin-to-pin compatible with STM8L101xx devices.

2 The STM32L family is pin-to-pin compatible with the general purpose STM32F family.

Please refer to STM32L15x documentation for more information on these devices.

Performance

All families incorporate highly energy-efficient cores with both Harvard architecture and
pipelined execution: advanced STM8 core for STM8L families and ARM Cortex™-M3 core
for STM32L family. In addition specific care for the design architecture has been taken to
optimize the mA/DMIPS and mA/MHz ratios.

This allows the ultra low power performance to range from 5 up to 33.3 DMIPs.

Shared peripherals

STM8L05x, STM8L15x and STM32L15xx share identical peripherals which ensure a very
easy migration from one family to another:

● Analog peripheral: ADC1

● Digital peripherals: RTC and some communication interfaces

Common system strategy

To offer flexibility and optimize performance, the STM8L and STM32L devices use a
common architecture:

● Same power supply range from 1.8 to 3.6 V

● Architecture optimized to reach ultra-low consumption both in low power modes and

Run mode

● Fast startup strategy from low power modes

● Flexible system clock

● Ultra-safe reset: same reset strategy for both STM8L and STM32L including power-on

reset, power-down reset, brownout reset and programmable voltage detector

Features

ST ultra low power continuum also lies in feature compatibility:

● More than 10 packages with pin count from 20 to 100 pins and size down to 3 x 3 mm

● Memory density ranging from 4 to 128 Kbytes

Doc ID 023337 Rev 1 11/109

Functional overview STM8L052R8

MS30323V1

Clock
controller
and CSS

Clocks

Address, control and data buses

64-Kbyte

4-Kbyte RAM

to core and
peripherals

IWDG

(38 kHz clock)

Port A

Port B

Port C

Power

VOLT. REG.

LCD driver

WWDG

256 bytes

Port D

Port E

Beeper

RTC

Program memory

Data EEPROM

@V

DD

V

DD18

V

DD

=1.8 V

V

SS

SWIM

SCL, SDA,

SPI1_MOSI, SPI1_MISO,

SPI1_SCK, SPI1_NSS

USART1_RX, USART1_TX,

USART1_CK

ADC1_INx

V

DDA, VSSA

SMB

@V

DDA/VSSA

12-bit ADC1

V

REF+

3.6 V

NRST

PA[7:0]

PB[7:0]

PC[7:0]

PD[7:0]

PE[7:0]

PF[7:0]

BEEP

ALARM, CALIB,
TAMP1/2/3

SEGx, COMx

POR/PDR

OSC_IN,

OSC_OUT

OSC32_IN,

OSC32_OUT

to

BOR

PVD

PVD_IN

RESET

DMA1 (4 channels)

3 channels

2 channels

2 channels

V

LCD

= 2.5 to 3.6 V

LCD booster

Internal reference

voltage

VREFINT out

IR_TIM

1-16 MHz oscillator

16 MHz internal RC

32 kHz oscillator

STM8 Core

16-bit Timer 1

16-bit Timer 2

38 kHz internal RC

Interrupt controller

16-bit Timer 3

Debug module

(SWIM)

8-bit Timer 4

Infrared interface

SPI1

I²C1

USART1

V

REF-

Port F

16-bit Timer 5

2 channels

SPI2

SPI2_MOSI, SPI2_MISO,

SPI2_SCK, SPI2_NSS

USART2_RX, USART2_TX,

USART2_CK

USART2

USART3_RX, USART3_TX,

USART3_CK

USART3

PG[7:0]

Port G

YPSY

up to

up to

3 Functional overview

Figure 1. High density value line STM8L05xxx device block diagram

1. Legend:
ADC: Analog-to-digital converter
BOR: Brownout reset
DMA: Direct memory access
I²C: Inter-integrated circuit multimaster interface
LCD: Liquid crystal display
POR/PDR: Power on reset / power down reset
RTC: Real-time clock
SPI: Serial peripheral interface
SWIM: Single wire interface module
USART: Universal synchronous asynchronous receiver transmitter
WWDG: Window watchdog
IWDG: independent watchdog

12/109 Doc ID 023337 Rev 1

STM8L052R8 Functional overview

3.1 Low power modes

The high density value line STM8L05xxx devices support five low power modes to achieve
the best compromise between low power consumption, short startup time and available
wakeup sources:

● Wait mode: The CPU clock is stopped, but selected peripherals keep running. An

internal or external interrupt, event or a Reset can be used to exit the microcontroller
from Wait mode (WFE or WFI mode).

● Low power run mode: The CPU and the selected peripherals are running. Execution

is done from RAM with a low speed oscillator (LSI or LSE). Flash memory and data
EEPROM are stopped and the voltage regulator is configured in ultra low power mode.
The microcontroller enters Low power run mode by software and can exit from this
mode by software or by a reset.
All interrupts must be masked. They cannot be used to exit the microcontroller from this
mode.

● Low power wait mode: This mode is entered when executing a Wait for event in Low

power run mode. It is similar to Low power run mode except that the CPU clock is
stopped. The wakeup from this mode is triggered by a Reset or by an internal or
external event (peripheral event generated by the timers, serial interfaces, DMA
controller (DMA1) and I/O ports). When the wakeup is triggered by an event, the
system goes back to Low power run mode.
All interrupts must be masked. They cannot be used to exit the microcontroller from this
mode.

● Active-halt mode: CPU and peripheral clocks are stopped, except RTC. The wakeup

can be triggered by RTC interrupts, external interrupts or reset.

● Halt mode: CPU and peripheral clocks are stopped, the device remains powered on.

The wakeup is triggered by an external interrupt or reset. A few peripherals have also a
wakeup from Halt capability. Switching off the internal reference voltage reduces power
consumption. Through software configuration it is also possible to wake up the device
without waiting for the internal reference voltage wakeup time to have a fast wakeup
time of 5 µs.

Doc ID 023337 Rev 1 13/109

Functional overview STM8L052R8

3.2 Central processing unit STM8

3.2.1 Advanced STM8 Core

The 8-bit STM8 core is designed for code efficiency and performance with an Harvard
architecture and a 3-stage pipeline.

It contains 6 internal registers which are directly addressable in each execution context, 20
addressing modes including indexed indirect and relative addressing, and 80 instructions.

Architecture and registers

● Harvard architecture

● 3-stage pipeline

● 32-bit wide program memory bus - single cycle fetching most instructions

● X and Y 16-bit index registers - enabling indexed addressing modes with or without

offset and read-modify-write type data manipulations

● 8-bit accumulator

● 24-bit program counter - 16-Mbyte linear memory space

● 16-bit stack pointer - access to a 64-Kbyte level stack

● 8-bit condition code register - 7 condition flags for the result of the last instruction

Addressing

● 20 addressing modes

● Indexed indirect addressing mode for lookup tables located anywhere in the address

space

● Stack pointer relative addressing mode for local variables and parameter passing

Instruction set

● 80 instructions with 2-byte average instruction size

● Standard data movement and logic/arithmetic functions

● 8-bit by 8-bit multiplication

● 16-bit by 8-bit and 16-bit by 16-bit division

● Bit manipulation

● Data transfer between stack and accumulator (push/pop) with direct stack access

● Data transfer using the X and Y registers or direct memory-to-memory transfers

3.2.2 Interrupt controller

The high density value line STM8L05xxx devices feature a nested vectored interrupt
controller:

● Nested interrupts with 3 software priority levels

● 32 interrupt vectors with hardware priority

● Up to 40 external interrupt sources on 11 vectors

● Trap and reset interrupts

14/109 Doc ID 023337 Rev 1

STM8L052R8 Functional overview

3.3 Reset and supply management

3.3.1 Power supply scheme

The device requires a 1.8 V to 3.6 V operating supply voltage (VDD). The external power
supply pins must be connected as follows:

● V

● V

● V

3.3.2 Power supply supervisor

The device has an integrated ZEROPOWER power-on reset (POR)/power-down reset
(PDR), coupled with a brownout reset (BOR) circuitry that ensures proper operation starting
from 1.8 V. After the 1.8 V BOR threshold is reached, the option byte loading process starts,
either to confirm or modify default thresholds, or to disable BOR permanently.

, V

, V

, V

, V

, V

SS1

DD1

SS2

DD2

SS3

= 1.8 to 3.6 V: external power supply for I/Os and

DD3

for the internal regulator. Provided externally through V
ground pin is VSS. V

SS1/VSS2/VSS3/VSS4

and V

DD1/VDD2/VDD3

unconnected.

SSA ; VDDA

V

must be connected to VDD and VSS, respectively.

SSA

REF+

externally through V

= 1.8 to 3.6 V: external power supplies for analog peripherals. V

; V

(for ADC1): external reference voltage for ADC1. Must be provided

REF-

REF+

and V

REF-

pin.

pins, the corresponding

DD

must not be left

DDA

and

Five BOR thresholds are available through option bytes, starting from 1.8 V to 3 V. To
reduce the power consumption in Halt mode, it is possible to automatically switch off the
internal reference voltage (and consequently the BOR) in Halt mode. The device remains
under reset when V

DD

for any external reset circuit.

The device features an embedded programmable voltage detector (PVD) that monitors the
V

DD/VDDA

power supply and compares it to the V
levels between 1.85 V and 3.05 V, chosen by software, with a step around 200 mV. An
interrupt can be generated when V
V

DD/VDDA

is higher than the V
a warning message and/or put the MCU into a safe state. The PVD is enabled by software.

3.3.3 Voltage regulator

The high density value line STM8L05xxx embeds an internal voltage regulator for
generating the 1.8 V power supply for the core and peripherals.

This regulator has two different modes:

● Main voltage regulator mode (MVR) for Run, Wait for interrupt (WFI) and Wait for event

(WFE) modes

● Low power voltage regulator mode (LPVR) for Halt, Active-halt, Low power run and Low

power wait modes

When entering Halt or Active-halt modes, the system automatically switches from the MVR
to the LPVR in order to reduce current consumption.

is below a specified threshold, V

threshold. This PVD offers 7 different

PVD

DD/VDDA

threshold. The interrupt service routine can then generate

PVD

drops below the V

POR/PDR

PVD

or V

, without the need

BOR

threshold and/or when

Doc ID 023337 Rev 1 15/109

Functional overview STM8L052R8

3.4 Clock management

The clock controller distributes the system clock (SYSCLK) coming from different oscillators
to the core and the peripherals. It also manages clock gating for low power modes and
ensures clock robustness.

Features

● Clock prescaler: To get the best compromise between speed and current

consumption the clock frequency to the CPU and peripherals can be adjusted by a
programmable prescaler.

● Safe clock switching: Clock sources can be changed safely on the fly in run mode

through a configuration register.

● Clock management: To reduce power consumption, the clock controller can stop the

clock to the core, individual peripherals or memory.

● System clock sources: 4 different clock sources can be used to drive the system

clock:

– 1-16 MHz High speed external crystal (HSE)

– 16 MHz High speed internal RC oscillator (HSI)

– 32.768 kHz Low speed external crystal (LSE)

– 38 kHz Low speed internal RC (LSI)

● RTC and LCD clock sources: The above four sources can be chosen to clock the

RTC and the LCD, whatever the system clock.

● Startup clock: After reset, the microcontroller restarts by default with an internal

2 MHz clock (HSI/8). The prescaler ratio and clock source can be changed by the
application program as soon as the code execution starts.

● Clock security system (CSS): This feature can be enabled by software. If a HSE clock

failure occurs, the system clock is automatically switched to HSI.

● Configurable main clock output (CCO): This outputs an external clock for use by the

application.

16/109 Doc ID 023337 Rev 1

STM8L052R8 Functional overview

HSE OSC

1-16 MHz

HSI RC
16 MHz

LSI RC
38 kH z

LSE OSC

32 768 k

H

z

HSI

LSI

RTC

prescaler

/1;2;4;8;16;32;64

PCLK

to peripherals

RTCCLK/2

to LCD

to IWDG

SYSCLK

HSE

LSI
LSE

OSC_OUT

OSC32_OUT

OSC_IN

OSC32_IN

clock output

CCO

prescaler

/1;2;4;8;16;32;64

HSI
LSI
HSE
LSE

CCO

to core and

memory

SYSCLK
Presc aler

/1;2;4;8;16;32;64;128

IWDGCLK

RTCSEL[3:0]

LSE

CLKBEEPSEL[1:0]

to BEEP

BEEPCLK

MS30324V1

CSS

configurable

.

/ 2

Peripheral

Clock enable (20 bits)

to RTC

RTCCLK

clock enable (1 bit)

LCDCLK

to LCD

SYSCLK

Halt

clock enable (1 bit)

LCD peripheral

RTCCLK

LCD peripheral

CSS_LSE

Figure 2. High density value line STM8L05xxx clock tree diagram

1. The HSE clock source can be either an external crystal/ceramic resonator or an external source (HSE

bypass). Refer to Section HSE clock in the STM8L15x and STM8L16x reference manual (RM0031).

2. The LSE clock source can be either an external crystal/ceramic resonator or a external source (LSE

bypass). Refer to Section LSE clock in the STM8L15x and STM8L16x reference manual (RM0031).

3.5 Low power real-time clock

The real-time clock (RTC) is an independent binary coded decimal (BCD) timer/counter.

Six byte locations contain the second, minute, hour (12/24 hour), week day, date, month,
year, in BCD (binary coded decimal) format. Correction for 28, 29 (leap year), 30, and 31
day months are made automatically.The subsecond field can also be read in binary format.

The calendar can be corrected from 1 to 32767 RTC clock pulses. This allows to make a
synchronization to a master clock.

The RTC offers a digital calibration which allows an accuracy of +/-0.5ppm.

It provides a programmable alarm and programmable periodic interrupts with wakeup from
Halt capability.

● Periodic wakeup time using the 32.768 kHz LSE with the lowest resolution (of 61 µs) is

from min. 122 µs to max. 3.9 s. With a different resolution, the wakeup time can reach
36 hours.

● Periodic alarms based on the calendar can also be generated from every second to

A clock security system detects a failure on LSE, and can provide an interrupt with wakeup
capability. The RTC clock can automatically switch to LSI in case of LSE failure.

The RTC also provides 3 anti-tamper detection pins. This detection embeds aprogrammable
filter and can wakeup the MCU.

every year.

Doc ID 023337 Rev 1 17/109

Functional overview STM8L052R8

3.6 LCD (Liquid crystal display)

The LCD is only available on STM8L052xx devices.

The liquid crystal display drives up to 8 common terminals and up to 24 segment terminals
to drive up to 192 pixels. It can also be configured to drive up to 4 common and 28 segments
(up to 112 pixels).

● Internal step-up converter to guarantee contrast control whatever V

● Static 1/2, 1/3, 1/4, 1/8 duty supported.

● Static 1/2, 1/3, 1/4 bias supported.

● Phase inversion to reduce power consumption and EMI.

● Up to 8 pixels which can be programmed to blink.

● The LCD controller can operate in Halt mode.

DD

.

Note: Unnecessary segments and common pins can be used as general I/O pins.

3.7 Memories

The high density value line STM8L05xxx devices have the following main features:

● 4 Kbytes of RAM

● The non-volatile memory is divided into three arrays:

– 64 Kbytes of high density embedded Flash program memory

– 256 bytes of data EEPROM

–Option bytes

The EEPROM embeds the error correction code (ECC) feature. It supports the read-while­write (RWW): it is possible to execute the code from the program matrix while
programming/erasing the data matrix.

The option byte protects part of the Flash program memory from write and readout piracy.

3.8 DMA

A 4-channel direct memory access controller (DMA1) offers a memory-to-memory and
peripherals-from/to-memory transfer capability. The 4 channels are shared between the
following IPs with DMA capability: ADC1, I2C1, SPI1, SPI 2, USART1, USART2, USART3
and the five timers.

18/109 Doc ID 023337 Rev 1

STM8L052R8 Functional overview

3.9 Analog-to-digital converter

● 12-bit analog-to-digital converter (ADC1) with 28 channels (including 4 fast channels),

temperature sensor and internal reference voltage

● Conversion time down to 1 µs with f

● Programmable resolution

● Programmable sampling time

● Single and continuous mode of conversion

● Scan capability: automatic conversion performed on a selected group of analog inputs

● Analog watchdog: interrupt generation when the converted voltage is outside the

SYSCLK

= 16 MHz

programmed threshold

● Triggered by timer

Note: ADC1 can be served by DMA1.

3.10 System configuration controller and routing interface

The system configuration controller provides the capability to remap some alternate
functions on different I/O ports. TIM4 and ADC1 DMA channels can also be remapped.

The highly flexible routing interface allows application software to control the routing of
different I/Os to the TIM1 timer input captures. It also controls the routing of internal analog
signals to ADC1 and the internal reference voltage V

3.11 Timers

The high density value line STM8L05xxx devices contain one advanced control timer
(TIM1), three 16-bit general purpose timers (TIM2, TIM3 and TIM5) and one 8-bit basic
timer (TIM4).

All the timers can be served by DMA1.

Ta bl e 2 compares the features of the advanced control, general-purpose and basic timers.

Table 2. Timer feature comparison

Timer

TIM1

TIM2

TIM3

TIM5

TIM4 8-bit up

Counter

resolution

16-bit up/down

Counter

type

Prescaler factor

Any integer

from 1 to 65536

Any power of 2

from 1 to 128

Any power of 2

from 1 to 32768

DMA1

request

generation

Ye s

.

REFINT

Capture/compare

channels

3 + 1 3

2

0

Complementary

outputs

None

Doc ID 023337 Rev 1 19/109

Functional overview STM8L052R8

3.11.1 TIM1 - 16-bit advanced control timer

This is a high-end timer designed for a wide range of control applications. With its
complementary outputs, dead-time control and center-aligned PWM capability, the field of
applications is extended to motor control, lighting and half-bridge driver.

● 16-bit up, down and up/down autoreload counter with 16-bit prescaler

● 3 independent capture/compare channels (CAPCOM) configurable as input capture,

output compare, PWM generation (edge and center aligned mode) and single pulse
mode output

● 1 additional capture/compare channel which is not connected to an external I/O

● Synchronization module to control the timer with external signals

● Break input to force timer outputs into a defined state

● 3 complementary outputs with adjustable dead time

● Encoder mode

● Interrupt capability on various events (capture, compare, overflow, break, trigger)

3.11.2 16-bit general purpose timers

● 16-bit autoreload (AR) up/down-counter

● 7-bit prescaler adjustable to fixed power of 2 ratios (1…128)

● 2 individually configurable capture/compare channels

● PWM mode

● Interrupt capability on various events (capture, compare, overflow, break, trigger)

● Synchronization with other timers or external signals (external clock, reset, trigger and

enable)

3.11.3 8-bit basic timer

The 8-bit timer consists of an 8-bit up auto-reload counter driven by a programmable
prescaler. It can be used for timebase generation with interrupt generation on timer overflow.

3.12 Watchdog timers

The watchdog system is based on two independent timers providing maximum security to
the applications.

3.12.1 Window watchdog timer

The window watchdog (WWDG) is used to detect the occurrence of a software fault, usually
generated by external interferences or by unexpected logical conditions, which cause the
application program to abandon its normal sequence.

3.12.2 Independent watchdog timer

The independent watchdog peripheral (IWDG) can be used to resolve processor
malfunctions due to hardware or software failures.

It is clocked by the internal LSI RC clock source, and thus stays active even in case of a
CPU clock failure.

20/109 Doc ID 023337 Rev 1

STM8L052R8 Functional overview

3.13 Beeper

The beeper function outputs a signal on the BEEP pin for sound generation. The signal is in
the range of 1, 2 or 4 kHz.

3.14 Communication interfaces

3.14.1 SPI

The serial peripheral interfaces (SPI1 and SPI2) provide half/ full duplex synchronous serial
communication with external devices.

● Maximum speed: 8 Mbit/s (f

● Full duplex synchronous transfers

● Simplex synchronous transfers on 2 lines with a possible bidirectional data line

● Master or slave operation - selectable by hardware or software

● Hardware CRC calculation

● Slave/master selection input pin

SYSCLK

Note: SPI1 and SPI2 can be served by the DMA1 Controller.

/2) both for master and slave

3.14.2 I²C

The I2C bus interface (I2C1) provides multi-master capability, and controls all I²C bus­specific sequencing, protocol, arbitration and timing.

● Master, slave and multi-master capability

● Standard mode up to 100 kHz and fast speed modes up to 400 kHz

● 7-bit and 10-bit addressing modes

● SMBus 2.0 and PMBus support

● Hardware CRC calculation

Note: I

2

C1 can be served by the DMA1 Controller.

3.14.3 USART

The USART interfaces (USART1, USART2 and USART3) allow full duplex, asynchronous
communications with external devices requiring an industry standard NRZ asynchronous
serial data format. It offers a very wide range of baud rates.

● 1 Mbit/s full duplex SCI

● SPI1 emulation

● High precision baud rate generator

● Smartcard emulation

● IrDA SIR encoder decoder

● Single wire half duplex mode

Note: USART1, USART2 and USART3 can be served by the DMA1 Controller.

Doc ID 023337 Rev 1 21/109

Functional overview STM8L052R8

3.15 Infrared (IR) interface

The high density value line STM8L05xxx devices contain an infrared interface which can be
used with an IR LED for remote control functions. Two timer output compare channels are
used to generate the infrared remote control signals.

3.16 Development support

Development tools

Development tools for the STM8 microcontrollers include:

● The STice emulation system offering tracing and code profiling

● The STVD high-level language debugger including C compiler, assembler and

integrated development environment

● The STVP Flash programming software

The STM8 also comes with starter kits, evaluation boards and low-cost in-circuit
debugging/programming tools.

Single wire data interface (SWIM) and debug module

The debug module with its single wire data interface (SWIM) permits non-intrusive real-time
in-circuit debugging and fast memory programming.

The Single wire interface is used for direct access to the debugging module and memory
programming. The interface can be activated in all device operation modes.

The non-intrusive debugging module features a performance close to a full-featured
emulator. Beside memory and peripherals, CPU operation can also be monitored in real­time by means of shadow registers.

Bootloader

A bootloader is available to reprogram the Flash memory using the USART1, USART2,

USART3 (USARTs in asynchronous mode), SPI1 or SPI2 interfaces. The reference
document for the bootloader is UM0560: STM8 bootloader user manual.

The bootloader is used to download application software into the device memories,
including RAM, program and data memory, using standard serial interfaces. It is a
complementary solution to programming via the SWIM debugging interface.

22/109 Doc ID 023337 Rev 1

STM8L052R8 Pin description

12

21

1

2

3

4

5

6

7

8

9

10

11

NRST/PA1

PA2
PA3
PA4

VLCD

PE0

PE1

PD1

PD2

PD3

PE3

PD0

PE5

PE4

V

DD1

V

DDA

V

REF+

PE2

PB2

PC0

PC1

V

DD3

V

SS3

PC2

PC3

PC4

PC5

PC6

PC7

PE6

PE7

PB3

PB4

PB5

PB6

PB7

PF0

PD4

PD5

PD6

PD7

PA0

PA5

14

15

16

17

18

19

20

13

PA6
PA7

V

SSA/VREF-

V

SS1

PG1

PG0

PG2

PG3

PB1

PB0

PF1

PF4

PF5

PF6

PF7

PG4

PG5

PG6

PG7

V

SS2

V

DD2

5051525354555758596061626364 56 49

32 31 30 28 27 26 25 24 23 22 29

41

48

47

46

45

44

43

42

39

38

37

36

35

34

33

40

ai17835

4 Pin description

Figure 3. STM8L052R8 64-pin LQFP64 package pinout

Doc ID 023337 Rev 1 23/109

Pin description STM8L052R8

Table 3. Legend/abbreviation for Tabl e 4

Typ e I= input, O = output, S = power supply

FT Five-volt tolerant

Level

Port and control
configuration

Reset state

Table 4. High density value line STM8L05xxx pin description

TT 3.6 V tolerant

Output HS = high sink/source (20 mA)

Input float = floating, wpu = weak pull-up

Output T = true open drain, OD = open drain, PP = push pull

Bold X (pin state after reset release).
Unless otherwise specified, the pin state is the same during the reset phase (i.e.
“under reset”) and after internal reset release (i.e. at reset state).

Pin

number

LQFP64

2 NRST/PA1

PA2/OSC_IN/

3

[USART1_TX]
[SPI1_MISO]

PA3/OSC_OUT/[USART1_

4

RX]

PA4/TIM2_BKIN/

5

[TIM2_ETR]

LCD_COM0/ADC1_IN2

PA5/TIM3_BKIN/

6

[TIM3_ETR]

LCD_COM1/ADC1_IN1

Pin name

(1)

(8)

/[SPI1_MOSI]

(8)

(8)

(8)

(8)

Input Output

Type

I/O level

wpu

floating

OD

PP

Default alternate function

(after reset)

Main function

Ext. interrupt

High sink/source

I/O X HS X X Reset PA 1

HSE oscillator input /

/

I/O X X X HS X X Port A2

[USART1 transmit] / [SPI1
master in- slave out]

HSE oscillator output /

(8)

I/O X X X HS X X Port A3

[USART1 receive]/ [SPI1
master out/slave in]/

Timer 2 - break input
/[Timer 2 - trigger]/

/

I/O FT

(2)

XXXHSXXPort A4

LCD COM 0 / ADC1 input 2

Timer 3 - break input

/

I/O FT

(2)

XXXHSXXPort A5

/[Timer 3 - trigger]/
LCD_COM 1 / ADC1 input
1

PA 6/ [ADC1_TRIG]/

7

LCD_COM2/ADC1_IN0

PA7/LCD_SEG0

8

/TIM5_CH1

(3)

PB0

31

/TIM2_CH1/

LCD_SEG10/ADC1_IN18

PB1/TIM3_CH1/

32

LCD_SEG11/

(2)

I/O FT

I/O FT

I/O FT

I/O FT

(2)

XXXHSXXPort A6

(2)

XXXHSXXPort A7

(2)

XXXHSXXPort B0

(2)

XXXHSXXPort B1

ADC1_IN17

24/109 Doc ID 023337 Rev 1

[ADC1 - trigger] /
LCD_COM2 /
ADC1 input 0

LCD segment 0/ TIM5
channel 1

Timer 2 - channel 1 / LCD
segment 10 / ADC1_IN18

Timer 3 - channel 1 / LCD
segment 11 / ADC1_IN17

STM8L052R8 Pin description

Table 4. High density value line STM8L05xxx pin description (continued)

Pin

number

LQFP64

33

34

35

36

37

38

53 PC0

54 PC1

57

Pin name

PB2/ TIM2_CH2/
LCD_SEG12/
ADC1_IN16

PB3/TIM2_ETR/
LCD_SEG13/
ADC1_IN15

PB4

(3)

/[SPI1_NSS]

(8)

/
LCD_SEG14/
ADC1_IN14

PB5/[SPI1_SCK]

(8)

/
LCD_SEG15/
ADC1_IN13

(8)

PB6/[SPI1_MOSI]

/
LCD_SEG16/
ADC1_IN12

PB7/[SPI1_MISO]

(8)

/
LCD_SEG17/
ADC1_IN11

(2)

/I2C1_SDA I/O FT

(2)

/I2C1_SCL I/O FT

PC2/USART1_RX/
LCD_SEG22/ADC1_IN6/
VREFINT

Typ e

I/O FT

I/O FT

I/O FT

I/O FT

I/O FT

I/O FT

I/O FT

Input Output

I/O level

wpu

floating

OD

Ext. interrupt

High sink/source

(2)

XXXHSXXPort B2

(2)

XXXHSXXPort B3

(2)X(3)X(3)

(2)

XXXHSXXPort B5

(2)

XXXHSXXPort B6

(2)

XXXHSXXPort B7

(2)

XXT

(2)

XXT

(2)

XXXHSXXPort C2

XHSX XPort B4

(4)

(4)

Default alternate function

PP

(after reset)

Main function

Timer 2 - channel 2 / LCD
segment 12 / ADC1_IN16

Timer 2 - trigger / LCD
segment 13 /ADC1_IN15

[SPI1 master/slave select] /
LCD segment 14 /
ADC1_IN14

[SPI1 clock] / LCD segment
15 / ADC1_IN13

[SPI1 master out/slave in]/
LCD segment 16 /
ADC1_IN12

[SPI1 master in- slave out]

/LCD segment 17 /
ADC1_IN11

Port C0 I2C1 data

Port C1 I2C1 clock

USART1 receive /
LCD segment 22 /
ADC1_IN6 /Internal voltage
reference output

PC3/USART1_TX/

58

LCD_SEG23/

I/O FT

ADC1_IN5

PC4/USART1_CK/

59

I2C1_SMB/CCO/

I/O FT

ADC1_IN4

PC5/OSC32_IN

60

/[SPI1_NSS]

[USART1_TX]

PC6/OSC32_OUT/

61

[SPI1_SCK]
[USART1_RX]

(8)

(8)

(8)

/

(8)

/

I/O FT

I/O FT

62 PC7/ADC1_IN3 I/O FT

(2)

XXXHSXXPort C3

USART1 transmit /
LCD segment 23 /
ADC1_IN5

USART1 synchronous

(2)

XXXHSXXPort C4

clock / I2C1_SMB /
Configurable clock output /
ADC1_IN4

(2)

XXXHSXXPort C5

LSE oscillator input / [SPI1

master/slave select] /
[USART1 transmit]

(2)

XXXHSXXPort C6

LSE oscillator output /

[SPI1 clock] / [USART1
receive]

(2)

XXXHSXXPort C7 ADC1_IN3

Doc ID 023337 Rev 1 25/109

Pin description STM8L052R8

Table 4. High density value line STM8L05xxx pin description (continued)

Pin

number

LQFP64

25

26

27

28

45

46

47

Pin name

PD0/TIM3_CH2/

[ADC1_TRIG]

(8)

/

LCD_SEG7/ADC1_IN22/

PD1/TIM3_ETR/
LCD_COM3/
ADC1_IN21

PD2/TIM1_CH1
/LCD_SEG8/
ADC1_IN20

PD3/ TIM1_ETR/
LCD_SEG9/ADC1_IN19

PD4/TIM1_CH2
/LCD_SEG18/
ADC1_IN10

PD5/TIM1_CH3
/LCD_SEG19/
ADC1_IN9

PD6/TIM1_BKIN
/LCD_SEG20/
ADC1_IN8/RTC_CALIB/
/VREFINT

Typ e

I/O FT

I/O FT

I/O FT

I/O FT

I/O FT

I/O FT

I/O FT

Input Output

I/O level

wpu

floating

OD

Ext. interrupt

High sink/source

(2)

XXXHSXXPort D0

(2)

XXXHSXXPort D1

(2)

XXXHSXXPort D2

(2)

XXXHSXXPort D3

(2)

XXXHSXXPort D4

(2)

XXXHSXXPort D5

(2)

XXXHSXXPort D6

PP

Main function

Default alternate function

(after reset)

Timer 3 - channel 2 /
[ADC1_Trigger] / LCD
segment 7 / ADC1_IN22

Timer 3 - trigger /
LCD_COM3 / ADC1_IN21

Timer 1 - channel 1 / LCD
segment 8 / ADC1_IN20

Timer 1 - trigger / LCD
segment 9 / ADC1_IN19

Timer 1 - channel 2 / LCD
segment 18 / ADC1_IN10

Timer 1 - channel 3 / LCD
segment 19 / ADC1_IN9

Timer 1 - break input / LCD
segment 20 / ADC1_IN8 /
RTC calibration / Internal
voltage reference output

PD7/TIM1_CH1N
/LCD_SEG21/

48

ADC1_IN7/RTC_ALARM/V

I/O FT

(2)

XXXHSXXPort D7

REFINT

(2)

49 PG4/SPI2_NSS I/O FT

50 PG5/SPI2_SCK I/O FT

51 PG6/SPI2_MOSI I/O FT

52 PG7/SPI2_MISO I/O FT

(2)

PE0

19

20

/LCD_SEG1/TIM5_C

H2/RTC_TAMP1

PE1/TIM1_CH2N/
LCD_SEG2/RTC_TAMP2

I/O FT

I/O FT

X XXHSXXPort G4

(2)

X XXHSXXPort G5 SPI2 clock

(2)

X XXHSXXPort G6

(2)

X XXHSXXPort G7

(2)

XXXHSXXPort E0

(2)

XXXHSXXPort E1

26/109 Doc ID 023337 Rev 1

Timer 1 - inverted channel
1/ LCD segment 21 /
ADC1_IN7 / RTC alarm /
Internal voltage reference
output

SPI2
master/slave select

SPI2
master out- slaìve in

SPI2
master in- slave out

LCD segment 1/Timer 5
channel 2/RTC tamper 1

Timer 1 - inverted channel
2 / LCD segment 2/
RTC tamper 2

STM8L052R8 Pin description

Table 4. High density value line STM8L05xxx pin description (continued)

Pin

number

Pin name

LQFP64

PE2/TIM1_CH3N/

21

LCD_SEG3/RTC_TAMP3

PE3/LCD_SEG4

22

/USART2_RX

PE4/LCD_SEG5

23

/USART2_TX

PE5/LCD_SEG6/

24

ADC1_IN23/USART2_CK

63 PE6/PVD_IN/TIM5_BKIN I/O FT

PE7

64

/TIM5_ETR

Typ e

I/O FT

I/O FT

I/O FT

I/O FT

I/O FT

Input Output

Default alternate function

I/O level

wpu

floating

OD

PP

Main function

(after reset)

Ext. interrupt

High sink/source

(2)

XXXHSXXPort E2

Timer 1 - inverted channel
3 / LCD segment 3/
RTC tamper 3

(2)

XXXHSXXPort E3

(2)

XXXHSXXPort E4

(2)

XXXHSXXPort E5

LCD segment 4
/USART2 receive

LCD segment 5
/USART2 transmit

LCD segment 6 /
ADC1_IN23/USART2
synchronous clock

(2)

XXXHSXXPort E6

(2)

XXXHSXXPort E7 TIM5 trigger

PVD_IN
/TIM5 break input

PF0/ADC1_IN24

39

/[USART3_TX]

PF1/ADC1_IN25/

40

[USART3_RX]

PF4/LCD_SEG36

41

/LCD_COM4

PF5/LCD_SEG37/

42

LCD_COM5

PF6/LCD_SEG38/

43

LCD_COM6

PF7/LCD_SEG39/

44

LCD_COM7

(5)

(5)

(5)

(5)

I/O X X X HS X X Port F0

I/O X XXHSXXPort F1

(2)

I/O FT

I/O FT

I/O FT

I/O FT

X XXHSXXPort F4

(2)

X XXHSXXPort F5

(2)

X XXHSXXPort F6

(2)

X XXHSXXPort F7

ADC1_IN24/
[USART3 transmit]

ADC1_IN25/
[USART3 receive]

LCD_SEG36/
LCD COM4

LCD_SEG37/
LCD COM5

LCD_SEG38/
LCD COM6

LCD_SEG39/
LCD COM7

(5)

(5)

(5)

(5)

18 VLCD S LCD booster external capacitor

11 V

DD1

10 V

SS1

12 V

DDA

13 V

REF+

PG0/USART3_RX/

14

[TIM2_BKIN]

PG1/USART3_TX/

15

[TIM3_BKIN]

S Digital power supply

I/O ground

S Analog supply voltage

S ADC1 positive voltage reference

I/O FT

I/O FT

(2)

X XXHSXXPort G0

(2)

X XXHSXXPort G1

USART3 receive /

[Timer 2 - break input]

USART3 transmit /

[Timer 3 -break input]

Doc ID 023337 Rev 1 27/109

Pin description STM8L052R8

Table 4. High density value line STM8L05xxx pin description (continued)

Pin

number

LQFP64

Pin name

Typ e

Input Output

I/O level

wpu

floating

OD

PP

Main function

Default alternate function

(after reset)

Ext. interrupt

High sink/source

16 PG2/USART3_CK I/O FT

17 PG3[TIM3_ETR] I/O FT

9V

SSA/VREF-

55 V

DD2

56 V

SS2

(6)

PA 0

1

/[USART1_CK]

SWIM/BEEP/IR_TIM

(8)

(7)

S

S IOs supply voltage

S IOs ground voltage

/

I/O X X X

(2)

X XXHSXXPort G2

(2)

X XXHSXXPort G3 [Timer 3 - trigger]

Analog ground voltage /
ADC1 negative voltage reference

HS

XXPort A0

USART 3 synchronous
clock

[USART1 synchronous

(8)

clock]

/ SWIM input and

output /Beep output
/ Infrared Timer output

29 V

DD3

30 V

SS3

1. At power-up, the PA1/NRST pin is a reset input pin with pull-up. To be used as a general purpose pin (PA1), it can be
configured only as output open-drain or push-pull, not as a general purpose input. Refer to Section Configuring NRST/PA1
pin as general purpose output in the STM8L15x and STM8L16x reference manual (RM0031).

2. In the 5 V tolerant I/Os, protection diode to V

3. A pull-up is applied to PB0 and PB4 during the reset phase. These two pins are input floating after reset release.

4. In the open-drain output column, ‘T’ defines a true open-drain I/O (P-buffer, weak pull-up and protection diode to V
not implemented).

5. SEG/COM multiplexing available on medium+ and high density devices. SEG signals are available by default (see
reference manual for details).

6. The PA0 pin is in input pull-up during the reset phase and after reset release.

7. High Sink LED driver capability available on PA0.

8. [ ] Alternate function remapping option (if the same alternate function is shown twice, it indicates an exclusive choice not
aduplication of the function).

S IOs supply voltage

S IOs ground voltage

is not implemented.

DD

DD

are

28/109 Doc ID 023337 Rev 1

STM8L052R8 Pin description

4.1 System configuration options

As shown in Table 4: High density value line STM8L05xxx pin description, some alternate
functions can be remapped on different I/O ports by programming one of the two remapping
registers described in the “ Routing interface (RI) and system configuration controller”
section in the STM8L15x and STM8L16x reference manual (RM0031).

Doc ID 023337 Rev 1 29/109

Memory and register map STM8L052R8

GPIO and peripheral registers

0x00 0000

Reserved

High density

(64 Kbytes)

Reset and interrupt vectors

0x00 1000

0x00 10FF

0x00 07FF

RAM (4 Kbytes)

(1)

(513 bytes)

(1)

0x00 1100

Data EEPROM

0x00 4800

0x00 48FF

0x00 4900

0x00 7FFF

0x00 8000

0x00 FFFF

0x00 0800

0x00 0FFF

0x00 47FF

0x00 7EFF

0x00 8080

0x00 807F

0x00 7F00

Reserved

including

Stack

(256 bytes)

Option bytes

0x00 4FFF
0x00 5000

0x00 57FF
0x00 5800

Reserved

0x00 5FFF

Boot ROM

0x00 6000

0x00 67FF

(2 Kbytes)

0x00 6800

Reserved

CPU/SWIM/Debug/ITC

Registers

0x00 5000

GPIO Ports

0x00 5050

Flash

0x00 50C0

ITC-EXTI

0x00 50D3

RST

0x00 50E0

CLK

0x00 50F0

WWDG

0x00 5210

IWDG

0x00 5230

BEEP

0x00 5250

RTC

0x00 5280

SPI1

0x00 52E0

I2C1

0x00 52FF

USART1

TIM2

TIM3

TIM1

TIM4

IRTIM

ADC1

0x00 5070

DMA1

SYSCFG

SPI2

USART2

0x00 509D

0x00 50A0

0x00 50B0

0x00 5140

0x00 5200

0x00 5300

0x00 5340

0x00 5380

0x00 53F0

0x00 5430

0x00 5440

Flash program memory

WFE

0x00 50A6

0x00 50B2

PWR

Reserved

Reserved

0x00 53C0

Reserved

RI

LCD

USART3

0x00 53E0

0x00 5400

0x00 5444

TIM5

0x00 52B0

5 Memory and register map

5.1 Memory mapping

The memory map is shown in Figure 4.

Figure 4. Memory map

1. Table 5 lists the boundary addresses for each memory size. The top of the stack is at the RAM end
address.

2. Refer to Table 7 for an overview of hardware register mapping, to Table 6 for details on I/O port hardware
registers, and to Table 8 for information on CPU/SWIM/debug module controller registers.

30/109 Doc ID 023337 Rev 1

STM8L052R8 Memory and register map

Table 5. Flash and RAM boundary addresses

Memory area Size Start address End address

RAM 4 Kbytes 0x00 0000 0x00 0FFF

Flash program memory 64 Kbytes 0x00 8000 0x01 7FFF

5.2 Register map

Table 6. I/O port hardware register map

0x00 5000

0x00 5001 PA_IDR Port A input pin value register 0xXX

0x00 5002 PA_DDR Port A data direction register 0x00

0x00 5003 PA_CR1 Port A control register 1 0x01

0x00 5004 PA_CR2 Port A control register 2 0x00

0x00 5005

0x00 5006 PB_IDR Port B input pin value register 0xXX

0x00 5007 PB_DDR Port B data direction register 0x00

0x00 5008 PB_CR1 Port B control register 1 0x00

Address Block Register label Register name

PA_ODR Port A data output latch register 0x00

Por t A

PB_ODR Port B data output latch register 0x00

Por t B

Reset

status

0x00 5009 PB_CR2 Port B control register 2 0x00

0x00 500A

PC_ODR Port C data output latch register 0x00

0x00 500B PC_IDR Port C input pin value register 0xXX

0x00 500C PC_DDR Port C data direction register 0x00

Por t C

0x00 500D PC_CR1 Port C control register 1 0x00

0x00 500E PC_CR2 Port C control register 2 0x00

0x00 500F

PD_ODR Port D data output latch register 0x00

0x00 5010 PD_IDR Port D input pin value register 0xXX

0x00 5011 PD_DDR Port D data direction register 0x00

Por t D

0x00 5012 PD_CR1 Port D control register 1 0x00

0x00 5013 PD_CR2 Port D control register 2 0x00

0x00 5014

PE_ODR Port E data output latch register 0x00

0x00 5015 PE_IDR Port E input pin value register 0xXX

0x00 5016 PE_DDR Port E data direction register 0x00

Por t E

0x00 5017 PE_CR1 Port E control register 1 0x00

0x00 5018 PE_CR2 Port E control register 2 0x00

Doc ID 023337 Rev 1 31/109

Memory and register map STM8L052R8

Table 6. I/O port hardware register map (continued)

Address Block Register label Register name

0x00 5019

PF_ODR Port F data output latch register 0x00

0x00 501A PF_IDR Port F input pin value register 0xXX

0x00 501B PF_DDR Port F data direction register 0x00

Por t F

0x00 501C PF_CR1 Port F control register 1 0x00

0x00 501D PF_CR2 Port F control register 2 0x00

0x00 501E

PG_ODR Port F data output latch register 0x00

0x00 501F PG_IDR Port G input pin value register 0xXX

0x00 5020 PG_DDR Port G data direction register 0x00

Por t G

0x00 5021 PG_CR1 Port G control register 1 0x00

0x00 5022 PG_CR2 Port G control register 2 0x00

0x00 5023 to

0x00 502C

Table 7. General hardware register map

Reserved area (10 bytes)

Address Block Register label Register name

Reset

status

Reset

status

0x00 502E to

0x00 5049

0x00 5050

FLASH_CR1 Flash control register 1 0x00

Reserved area (27 bytes)

0x00 5051 FLASH_CR2 Flash control register 2 0x00

0x00 5052 FLASH _PUKR

Flash

Flash program memory unprotection key

register

0x00

0x00 5053 FLASH _DUKR Data EEPROM unprotection key register 0x00

0x00 5054 FLASH _IAPSR

0x00 5055 to

0x00 506F

Flash in-application programming status

register

Reserved area (27 bytes)

0x00

32/109 Doc ID 023337 Rev 1

STM8L052R8 Memory and register map

Table 7. General hardware register map (continued)

Address Block Register label Register name

0x00 5070

0x00 5071 DMA1_GIR1 DMA1 global interrupt register 1 0x00

0x00 5072 to

0x00 5074

0x00 5075 DMA1_C0CR DMA1 channel 0 configuration register 0x00

0x00 5076 DMA1_C0SPR DMA1 channel 0 status & priority register 0x00

0x00 5077 DMA1_C0NDTR

0x00 5078 DMA1_C0PARH

0x00 5079 DMA1_C0PARL

0x00 507A Reserved area (1 byte)

0x00 507B DMA1_C0M0ARH

0x00 507C DMA1_C0M0ARL

0x00 507D
0x00 507E

DMA1

DMA1_GCSR

DMA1 global configuration & status

register

Reserved area (3 bytes)

DMA1 number of data to transfer register

(channel 0)

DMA1 peripheral address high register

(channel 0)

DMA1 peripheral address low register

(channel 0)

DMA1 memory 0 address high register

(channel 0)

DMA1 memory 0 address low register

(channel 0)

Reserved area (2 bytes)

Reset

status

0xFC

0x00

0x52

0x00

0x00

0x00

0x00 507F DMA1_C1CR DMA1 channel 1 configuration register 0x00

0x00 5080 DMA1_C1SPR DMA1 channel 1 status & priority register 0x00

0x00 5081 DMA1_C1NDTR

0x00 5082 DMA1_C1PARH

0x00 5083 DMA1_C1PARL

DMA1 number of data to transfer register

(channel 1)

DMA1 peripheral address high register

(channel 1)

DMA1 peripheral address low register

(channel 1)

0x00

0x52

0x00

Doc ID 023337 Rev 1 33/109

Memory and register map STM8L052R8

Table 7. General hardware register map (continued)

Address Block Register label Register name

0x00 5084

0x00 5085 DMA1_C1M0ARH

0x00 5086 DMA1_C1M0ARL

0x00 5087
0x00 5088

0x00 5089 DMA1_C2CR DMA1 channel 2 configuration register 0x00

0x00 508A DMA1_C2SPR DMA1 channel 2 status & priority register 0x00

0x00 508B DMA1_C2NDTR

0x00 508C DMA1_C2PARH

0x00 508D DMA1_C2PARL

0x00 508E Reserved area (1 byte)

0x00 508F DMA1_C2M0ARH

DMA1

0x00 5090 DMA1_C2M0ARL

Reserved area (1 byte)

DMA1 memory 0 address high register

(channel 1)

DMA1 memory 0 address low register

(channel 1)

Reserved area (2 bytes)

DMA1 number of data to transfer register

(channel 2)

DMA1 peripheral address high register

(channel 2)

DMA1 peripheral address low register

(channel 2)

DMA1 memory 0 address high register

(channel 2)

DMA1 memory 0 address low register

(channel 2)

Reset

status

0x00

0x00

0x00

0x52

0x00

0x00

0x00

0x00 5091
0x00 5092

0x00 5093 DMA1_C3CR DMA1 channel 3 configuration register 0x00

0x00 5094 DMA1_C3SPR DMA1 channel 3 status & priority register 0x00

0x00 5095 DMA1_C3NDTR

0x00 5096

0x00 5097

0x00 5098 Reserved area (1 byte)

0x00 5099 DMA1_C3M0ARH

0x00 509A DMA1_C3M0ARL

0x00 509B to

0x00 509C

DMA1_C3PARH_

C3M1ARH

DMA1_C3PARL_

C3M1ARL

Reserved area (2 bytes)

DMA1 number of data to transfer register

(channel 3)

DMA1 peripheral address high register

(channel 3)

DMA1 peripheral address low register

(channel 3)

DMA1 memory 0 address high register

(channel 3)

DMA1 memory 0 address low register

(channel 3)

Reserved area (2 bytes)

0x00

0x40

0x00

0x00

0x00

34/109 Doc ID 023337 Rev 1

STM8L052R8 Memory and register map

Table 7. General hardware register map (continued)

Address Block Register label Register name

0x00 509D

0x00 509E SYSCFG_RMPCR1 Remapping register 1 0x00

0x00 509F SYSCFG_RMPCR2 Remapping register 2 0x00

0x00 50A0

0x00 50A1 EXTI_CR2 External interrupt control register 2 0x00

0x00 50A2 EXTI_CR3 External interrupt control register 3 0x00

0x00 50A3 EXTI_SR1 External interrupt status register 1 0x00

0x00 50A4 EXTI_SR2 External interrupt status register 2 0x00

0x00 50A5 EXTI_CONF1 External interrupt port select register 1 0x00

0x00 50A6

0x00 50A7 WFE_CR2 WFE control register 2 0x00

0x00 50A8 WFE_CR3 WFE control register 3 0x00

0x00 50A9 WFE_CR4 WFE control register 4 0x00

0x00 50AA

0x00 50AB EXTI_CONF2 External interrupt port select register 2 0x00

0x00 50A9 to

0x00 50AF

SYSCFG
SYSCFG

ITC - EXTI

WFE

ITC - EXTI

SYSCFG_RMPCR3 Remapping register 3 0x00

EXTI_CR1 External interrupt control register 1 0x00

WFE_CR1 WFE control register 1 0x00

EXTI_CR4 External interrupt control register 4 0x00

Reserved area (7 bytes)

Reset

status

0x00 50B0

RST

0x00 50B1 RST_SR Reset status register 0x01

0x00 50B2

PWR

0x00 50B3 PWR_CSR2 Power control and status register 2 0x00

0x00 50B4 to

0x00 50BF

RST_CR Reset control register 0x00

PWR_CSR1 Power control and status register 1 0x00

Reserved area (12 bytes)

Doc ID 023337 Rev 1 35/109

Memory and register map STM8L052R8

Table 7. General hardware register map (continued)

Address Block Register label Register name

0x00 50C0

0x00 50C1 CLK_CRTCR Clock RTC register 0x00

0x00 50C2 CLK_ICKR Internal clock control register 0x11

0x00 50C3 CLK_PCKENR1 Peripheral clock gating register 1 0x00

0x00 50C4 CLK_PCKENR2 Peripheral clock gating register 2 0x00

0x00 50C5 CLK_CCOR Configurable clock control register 0x00

0x00 50C6 CLK_ECKR External clock control register 0x00

0x00 50C7 CLK_SCSR System clock status register 0x01

0x00 50C8 CLK_SWR System clock switch register 0x01

0x00 50C9 CLK_SWCR Clock switch control register 0xX0

0x00 50CA CLK_CSSR Clock security system register 0x00

0x00 50CB CLK_CBEEPR Clock BEEP register 0x00

0x00 50CC CLK_HSICALR HSI calibration register 0xXX

0x00 50CD CLK_HSITRIMR HSI clock calibration trimming register 0x00

0x00 50CE CLK_HSIUNLCKR HSI unlock register 0x00

0x00 50CF CLK_REGCSR Main regulator control status register 0bxx11100x

0x00 50D0 CLK_PCKENR3 Peripheral clock gating register 3 0x00

CLK

CLK_CKDIVR Clock master divider register 0x03

Reset

status

(1)

0x00 50D1 to

0x00 50D2

0x00 50D3

0x00 50D4 WWDG_WR WWDR window register 0x7F

0x00 50D5 to

00 50DF

0x00 50E0

0x00 50E1 IWDG_PR IWDG prescaler register 0x00

0x00 50E2 IWDG_RLR IWDG reload register 0xFF

0x00 50E3 to

0x00 50EF

0x00 50F0

0x00 50F1
0x00 50F2

0x00 50F3 BEEP_CSR2 BEEP control/status register 2 0x1F

0x00 50F4 to

0x00 513F

WWDG

IWDG

BEEP

WWDG_CR WWDG control register 0x7F

IWDG_KR IWDG key register 0xXX

BEEP_CSR1 BEEP control/status register 1 0x00

Reserved area (2 bytes)

Reserved area (11 bytes)

Reserved area (13 bytes)

Reserved area (2 bytes)

Reserved area (76 bytes)

36/109 Doc ID 023337 Rev 1

STM8L052R8 Memory and register map

Table 7. General hardware register map (continued)

Address Block Register label Register name

0x00 5140

RTC_TR1 Time register 1 0x00

Reset

status

0x00 5141 RTC_TR2 Time register 2 0x00

0x00 5142 RTC_TR3 Time register 3 0x00

0x00 5143 Reserved area (1 byte)

0x00 5144 RTC_DR1 Date register 1 0x01

0x00 5145 RTC_DR2 Date register 2 0x21

0x00 5146 RTC_DR3 Date register 3 0x00

0x00 5147 Reserved area (1 byte)

0x00 5148 RTC_CR1 Control register 1 0x00

0x00 5149 RTC_CR2 Control register 2 0x00

0x00 514A RTC_CR3 Control register 3 0x00

0x00 514B Reserved area (1 byte)

0x00 514C RTC_ISR1 Initialization and status register 1 0x01

0x00 514D RTC_ISR2 Initialization and Status register 2 0x00

0x00 514E
0x00 514F

0x00 5150 RTC_SPRERH

RTC

0x00 5151 RTC_SPRERL

0x00 5152 RTC_APRER

(1)

(1)

(1)

Reserved area (2 bytes)

Synchronous prescaler register high 0x00

Synchronous prescaler register low 0xFF

Asynchronous prescaler register 0x7F

0x00 5153 Reserved area (1 byte)

(1)

(1)

Wakeup timer register high 0xFF

Wakeup timer register low 0xFF

0x00 5154 RTC_WUTRH

0x00 5155 RTC_WUTRL

0x00 5156 Reserved area (1 bytes)

(1)

(1)

(1)

(1)

(1)

(1)

(1)

(1)

0x00 5157 RTC_SSRL Subsecond register low 0x00

0x00 5158 RTC_SSRH Subsecond register high 0x00

0x00 5159 RTC_WPR Write protection register 0x00

0x00 515A RTC_SHIFTRH Shift register high 0x00

0x00 515B RTC_SHIFTRL Shift register low 0x00

0x00 515C RTC_ALRMAR1 Alarm A register 1 0x00

0x00 515D RTC_ALRMAR2 Alarm A register 2 0x00

0x00 515E RTC_ALRMAR3 Alarm A register 3 0x00

0x00 515F RTC_ALRMAR4 Alarm A register 4 0x00

0x00 5160 to

0x00 5163

Reserved area (4 bytes)

Doc ID 023337 Rev 1 37/109

(1)

(1)

(1)

(1)

Memory and register map STM8L052R8

Table 7. General hardware register map (continued)

Address Block Register label Register name

0x00 5164

0x00 5165 RTC_ALRMASSRL Alarm A subsecond register low 0x00

RTC

0x00 5166

0x00 5167 to

0x00 5169

0x00 516A

RTC_ALRMASSRH Alarm A subsecond register high 0x00

RTC_ALRMASSMS

KR

Alarm A masking register 0x00

Reserved area (3 bytes)

RTC_CALRH Calibration register high 0x00

Reset

status

0x00 516B RTC_CALRL Calibration register low 0x00

RTC

0x00 516C RTC_TCR1 Tamper control register 1 0x00

0x00 516D RTC_TCR2 Tamper control register 2 0x00

0x00 516E to

0x00 518A

Reserved area

0x00 5190 CSSLSE CSSLSE_CSR CSS on LSE control and status register 0x00

0x00 519A to

0x00 51FF

0x00 5200

SPI1_CR1 SPI1 control register 1 0x00

Reserved area

0x00 5201 SPI1_CR2 SPI1 control register 2 0x00

(1)

(1)

(1)

(1)

(1)

(1)

(1)

(1)

0x00 5202 SPI1_ICR SPI1 interrupt control register 0x00

0x00 5203 SPI1_SR SPI1 status register 0x02

SPI1

0x00 5204 SPI1_DR SPI1 data register 0x00

0x00 5205 SPI1_CRCPR SPI1 CRC polynomial register 0x07

0x00 5206 SPI1_RXCRCR SPI1 Rx CRC register 0x00

0x00 5207 SPI1_TXCRCR SPI1 Tx CRC register 0x00

0x00 5208 to

0x00 520F

Reserved area (8 bytes)

38/109 Doc ID 023337 Rev 1

STM8L052R8 Memory and register map

Table 7. General hardware register map (continued)

Address Block Register label Register name

0x00 5210

0x00 5211 I2C1_CR2 I2C1 control register 2 0x00

0x00 5212 I2C1_FREQR I2C1 frequency register 0x00

0x00 5213 I2C1_OARL I2C1 own address register low 0x00

0x00 5214 I2C1_OARH I2C1 own address register high 0x00

0x00 5215 I2C1_OARH I2C1 own address register for dual mode 0x00

0x00 5216 I2C1_DR I2C1 data register 0x00

0x00 5217 I2C1_SR1 I2C1 status register 1 0x00

I2C1

0x00 5218 I2C1_SR2 I2C1 status register 2 0x00

0x00 5219 I2C1_SR3 I2C1 status register 3 0x0x

0x00 521A I2C1_ITR I2C1 interrupt control register 0x00

0x00 521B I2C1_CCRL I2C1 clock control register low 0x00

0x00 521C I2C1_CCRH I2C1 clock control register high 0x00

0x00 521D I2C1_TRISER I2C1 TRISE register 0x02

0x00 521E I2C1_PECR I2C1 packet error checking register 0x00

0x00 521F to

0x00 522F

I2C1_CR1 I2C1 control register 1 0x00

Reserved area (17 bytes)

Reset

status

0x00 5230

0x00 5231 USART1_DR USART1 data register 0xXX

0x00 5232 USART1_BRR1 USART1 baud rate register 1 0x00

0x00 5233 USART1_BRR2 USART1 baud rate register 2 0x00

0x00 5234 USART1_CR1 USART1 control register 1 0x00

0x00 5235 USART1_CR2 USART1 control register 2 0x00

0x00 5236 USART1_CR3 USART1 control register 3 0x00

0x00 5237 USART1_CR4 USART1 control register 4 0x00

0x00 5238 USART1_CR5 USART1 control register 5 0x00

0x00 5239 USART1_GTR USART1 guard time register 0x00

0x00 523A USART1_PSCR USART1 prescaler register 0x00

0x00 523B to

0x00 524F

USART1

USART1_SR USART1 status register 0xC0

Reserved area (21 bytes)

Doc ID 023337 Rev 1 39/109

Memory and register map STM8L052R8

Table 7. General hardware register map (continued)

Address Block Register label Register name

0x00 5250

0x00 5251 TIM2_CR2 TIM2 control register 2 0x00

0x00 5252 TIM2_SMCR TIM2 Slave mode control register 0x00

0x00 5253 TIM2_ETR TIM2 external trigger register 0x00

0x00 5254 TIM2_DER TIM2 DMA1 request enable register 0x00

0x00 5255 TIM2_IER TIM2 interrupt enable register 0x00

0x00 5256 TIM2_SR1 TIM2 status register 1 0x00

0x00 5257 TIM2_SR2 TIM2 status register 2 0x00

0x00 5258 TIM2_EGR TIM2 event generation register 0x00

0x00 5259 TIM2_CCMR1 TIM2 capture/compare mode register 1 0x00

0x00 525A TIM2_CCMR2 TIM2 capture/compare mode register 2 0x00

0x00 525B TIM2_CCER1 TIM2 capture/compare enable register 1 0x00

0x00 525C TIM2_CNTRH TIM2 counter high 0x00

0x00 525D TIM2_CNTRL TIM2 counter low 0x00

0x00 525E TIM2_PSCR TIM2 prescaler register 0x00

0x00 525F TIM2_ARRH TIM2 auto-reload register high 0xFF

0x00 5260 TIM2_ARRL TIM2 auto-reload register low 0xFF

TIM2

TIM2_CR1 TIM2 control register 1 0x00

Reset

status

0x00 5261 TIM2_CCR1H TIM2 capture/compare register 1 high 0x00

0x00 5262 TIM2_CCR1L TIM2 capture/compare register 1 low 0x00

0x00 5263 TIM2_CCR2H TIM2 capture/compare register 2 high 0x00

0x00 5264 TIM2_CCR2L TIM2 capture/compare register 2 low 0x00

0x00 5265 TIM2_BKR TIM2 break register 0x00

0x00 5266 TIM2_OISR TIM2 output idle state register 0x00

0x00 5267 to

0x00 527F

Reserved area (25 bytes)

40/109 Doc ID 023337 Rev 1

STM8L052R8 Memory and register map

Table 7. General hardware register map (continued)

Address Block Register label Register name

0x00 5280

0x00 5281 TIM3_CR2 TIM3 control register 2 0x00

0x00 5282 TIM3_SMCR TIM3 Slave mode control register 0x00

0x00 5283 TIM3_ETR TIM3 external trigger register 0x00

0x00 5284 TIM3_DER TIM3 DMA1 request enable register 0x00

0x00 5285 TIM3_IER TIM3 interrupt enable register 0x00

0x00 5286 TIM3_SR1 TIM3 status register 1 0x00

0x00 5287 TIM3_SR2 TIM3 status register 2 0x00

0x00 5288 TIM3_EGR TIM3 event generation register 0x00

0x00 5289 TIM3_CCMR1 TIM3 Capture/Compare mode register 1 0x00

0x00 528A TIM3_CCMR2 TIM3 Capture/Compare mode register 2 0x00

0x00 528B TIM3_CCER1 TIM3 Capture/Compare enable register 1 0x00

0x00 528C TIM3_CNTRH TIM3 counter high 0x00

0x00 528D TIM3_CNTRL TIM3 counter low 0x00

0x00 528E TIM3_PSCR TIM3 prescaler register 0x00

0x00 528F TIM3_ARRH TIM3 Auto-reload register high 0xFF

0x00 5290 TIM3_ARRL TIM3 Auto-reload register low 0xFF

TIM3

TIM3_CR1 TIM3 control register 1 0x00

Reset

status

0x00 5291 TIM3_CCR1H TIM3 Capture/Compare register 1 high 0x00

0x00 5292 TIM3_CCR1L TIM3 Capture/Compare register 1 low 0x00

0x00 5293 TIM3_CCR2H TIM3 Capture/Compare register 2 high 0x00

0x00 5294 TIM3_CCR2L TIM3 Capture/Compare register 2 low 0x00

0x00 5295 TIM3_BKR TIM3 break register 0x00

0x00 5296 TIM3_OISR TIM3 output idle state register 0x00

0x00 5297 to

0x00 52AF

Reserved area (25 bytes)

Doc ID 023337 Rev 1 41/109

Memory and register map STM8L052R8

Table 7. General hardware register map (continued)

Address Block Register label Register name

0x00 52B0

0x00 52B1 TIM1_CR2 TIM1 control register 2 0x00

0x00 52B2 TIM1_SMCR TIM1 Slave mode control register 0x00

0x00 52B3 TIM1_ETR TIM1 external trigger register 0x00

0x00 52B4 TIM1_DER TIM1 DMA1 request enable register 0x00

0x00 52B5 TIM1_IER TIM1 Interrupt enable register 0x00

0x00 52B6 TIM1_SR1 TIM1 status register 1 0x00

0x00 52B7 TIM1_SR2 TIM1 status register 2 0x00

0x00 52B8 TIM1_EGR TIM1 event generation register 0x00

0x00 52B9 TIM1_CCMR1 TIM1 Capture/Compare mode register 1 0x00

0x00 52BA TIM1_CCMR2 TIM1 Capture/Compare mode register 2 0x00

0x00 52BB TIM1_CCMR3 TIM1 Capture/Compare mode register 3 0x00

0x00 52BC TIM1_CCMR4 TIM1 Capture/Compare mode register 4 0x00

0x00 52BD TIM1_CCER1 TIM1 Capture/Compare enable register 1 0x00

0x00 52BE TIM1_CCER2 TIM1 Capture/Compare enable register 2 0x00

0x00 52BF TIM1_CNTRH TIM1 counter high 0x00

0x00 52C0 TIM1_CNTRL TIM1 counter low 0x00

TIM1

0x00 52C1 TIM1_PSCRH TIM1 prescaler register high 0x00

0x00 52C2 TIM1_PSCRL TIM1 prescaler register low 0x00

0x00 52C3 TIM1_ARRH TIM1 Auto-reload register high 0xFF

TIM1_CR1 TIM1 control register 1 0x00

Reset

status

0x00 52C4 TIM1_ARRL TIM1 Auto-reload register low 0xFF

0x00 52C5 TIM1_RCR TIM1 Repetition counter register 0x00

0x00 52C6 TIM1_CCR1H TIM1 Capture/Compare register 1 high 0x00

0x00 52C7 TIM1_CCR1L TIM1 Capture/Compare register 1 low 0x00

0x00 52C8 TIM1_CCR2H TIM1 Capture/Compare register 2 high 0x00

0x00 52C9 TIM1_CCR2L TIM1 Capture/Compare register 2 low 0x00

0x00 52CA TIM1_CCR3H TIM1 Capture/Compare register 3 high 0x00

0x00 52CB TIM1_CCR3L TIM1 Capture/Compare register 3 low 0x00

0x00 52CC TIM1_CCR4H TIM1 Capture/Compare register 4 high 0x00

0x00 52CD TIM1_CCR4L TIM1 Capture/Compare register 4 low 0x00

0x00 52CE TIM1_BKR TIM1 break register 0x00

0x00 52CF TIM1_DTR TIM1 dead-time register 0x00

0x00 52D0 TIM1_OISR TIM1 output idle state register 0x00

0x00 52D1 TIM1_DCR1 DMA1 control register 1 0x00

42/109 Doc ID 023337 Rev 1

STM8L052R8 Memory and register map

Table 7. General hardware register map (continued)

Address Block Register label Register name

0x00 52D2

TIM1

0x00 52D3 TIM1_DMA1R TIM1 DMA1 address for burst mode 0x00

0x00 52D4 to

0x00 52DF

0x00 52E0

0x00 52E1 TIM4_CR2 TIM4 control register 2 0x00

0x00 52E2 TIM4_SMCR TIM4 Slave mode control register 0x00

0x00 52E3 TIM4_DER TIM4 DMA1 request enable register 0x00

0x00 52E4 TIM4_IER TIM4 Interrupt enable register 0x00

TIM4

0x00 52E5 TIM4_SR1 TIM4 status register 1 0x00

0x00 52E6 TIM4_EGR TIM4 Event generation register 0x00

0x00 52E7 TIM4_CNTR TIM4 counter 0x00

0x00 52E8 TIM4_PSCR TIM4 prescaler register 0x00

0x00 52E9 TIM4_ARR TIM4 Auto-reload register 0x00

0x00 52EA to

0x00 52FE

0x00 52FF IRTIM IR_CR Infrared control register 0x00

TIM1_DCR2 TIM1 DMA1 control register 2 0x00

Reserved area (12 bytes)

TIM4_CR1 TIM4 control register 1 0x00

Reserved area (21 bytes)

Reset

status

0x00 5300

0x00 5301 TIM5_CR2 TIM5 control register 2 0x00

0x00 5302 TIM5_SMCR TIM5 Slave mode control register 0x00

0x00 5303 TIM5_ETR TIM5 external trigger register 0x00

0x00 5304 TIM5_DER TIM5 DMA1 request enable register 0x00

0x00 5305 TIM5_IER TIM5 interrupt enable register 0x00

0x00 5306 TIM5_SR1 TIM5 status register 1 0x00

0x00 5307 TIM5_SR2 TIM5 status register 2 0x00

0x00 5308 TIM5_EGR TIM5 event generation register 0x00

0x00 5309 TIM5_CCMR1 TIM5 Capture/Compare mode register 1 0x00

0x00 530A TIM5_CCMR2 TIM5 Capture/Compare mode register 2 0x00

0x00 530B TIM5_CCER1 TIM5 Capture/Compare enable register 1 0x00

0x00 530C TIM5_CNTRH TIM5 counter high 0x00

0x00 530D TIM5_CNTRL TIM5 counter low 0x00

0x00 530E TIM5_PSCR TIM5 prescaler register 0x00

0x00 530F TIM5_ARRH TIM5 Auto-reload register high 0xFF

0x00 5310 TIM5_ARRL TIM5 Auto-reload register low 0xFF

TIM5

TIM5_CR1 TIM5 control register 1 0x00

Doc ID 023337 Rev 1 43/109

Memory and register map STM8L052R8

Table 7. General hardware register map (continued)

Address Block Register label Register name

0x00 5311

0x00 5312 TIM5_CCR1L TIM5 Capture/Compare register 1 low 0x00

0x00 5313 TIM5_CCR2H TIM5 Capture/Compare register 2 high 0x00

TIM5

0x00 5314 TIM5_CCR2L TIM5 Capture/Compare register 2 low 0x00

0x00 5315 TIM5_BKR TIM5 break register 0x00

0x00 5316 TIM5_OISR TIM5 output idle state register 0x00

0x00 5317

to

0x00 533F

0x00 5340

0x00 5341 ADC1_CR2 ADC1 configuration register 2 0x00

0x00 5342 ADC1_CR3 ADC1 configuration register 3 0x1F

0x00 5343 ADC1_SR ADC1 status register 0x00

0x00 5344 ADC1_DRH ADC1 data register high 0x00

0x00 5345 ADC1_DRL ADC1 data register low 0x00

0x00 5346 ADC1_HTRH ADC1 high threshold register high 0x0F

0x00 5347 ADC1_HTRL ADC1 high threshold register low 0xFF

TIM5_CCR1H TIM5 Capture/Compare register 1 high 0x00

Reserved area

ADC1_CR1 ADC1 configuration register 1 0x00

Reset

status

0x00 5348 ADC1_LTRH ADC1 low threshold register high 0x00

0x00 5349 ADC1_LTRL ADC1 low threshold register low 0x00

0x00 534A ADC1_SQR1 ADC1 channel sequence 1 register 0x00

0x00 534B ADC1_SQR2 ADC1 channel sequence 2 register 0x00

0x00 534C ADC1_SQR3 ADC1 channel sequence 3 register 0x00

0x00 534D ADC1_SQR4 ADC1 channel sequence 4 register 0x00

0x00 534E ADC1_TRIGR1 ADC1 trigger disable 1 0x00

0x00 534F ADC1_TRIGR2 ADC1 trigger disable 2 0x00

0x00 5350 ADC1_TRIGR3 ADC1 trigger disable 3 0x00

0x00 5351 ADC1_TRIGR4 ADC1 trigger disable 4 0x00

0x00 5352 to

0x00 53BF

ADC1

Reserved area (110 bytes)

44/109 Doc ID 023337 Rev 1

STM8L052R8 Memory and register map

Table 7. General hardware register map (continued)

Address Block Register label Register name

0x00 53C0

0x00 53C1 SPI2_CR2 SPI2 control register 2 0x00

0x00 53C2 SPI2_ICR SPI2 interrupt control register 0x00

0x00 53C3 SPI2_SR SPI2 status register 0x02

0x00 53C4 SPI2_DR SPI2 data register 0x00

0x00 53C5 SPI2_CRCPR SPI2 CRC polynomial register 0x07

0x00 53C6 SPI2_RXCRCR SPI2 Rx CRC register 0x00

0x00 53C7 SPI2_TXCRCR SPI2 Tx CRC register 0x00

0x00 53C8 to

0x00 53DF

0x00 53E0

0x00 53E1 USART2_DR USART2 data register 0xXX

0x00 53E2 USART2_BRR1 USART2 baud rate register 1 0x00

0x00 53E3 USART2_BRR2 USART2 baud rate register 2 0x00

0x00 53E4 USART2_CR1 USART2 control register 1 0x00

0x00 53E5 USART2_CR2 USART2 control register 2 0x00

0x00 53E6 USART2_CR3 USART2 control register 3 0x00

SPI2

USART2

SPI2_CR1 SPI2 control register 1 0x00

Reserved area

USART2_SR USART2 status register 0xC0

Reset

status

0x00 53E7 USART2_CR4 USART2 control register 4 0x00

0x00 53E8 USART2_CR5 USART2 control register 5 0x00

0x00 53E9 USART2_GTR USART2 guard time register 0x00

0x00 53EA USART2_PSCR USART2 prescaler register 0x00

0x00 53EB to

0x00 53EF

0x00 53F0

0x00 53F1 USART3_DR USART3 data register 0xXX

0x00 53F2 USART3_BRR1 USART3 baud rate register 1 0x00

0x00 53F3 USART3_BRR2 USART3 baud rate register 2 0x00

0x00 53F4 USART3_CR1 USART3 control register 1 0x00

0x00 53F5 USART3_CR2 USART3 control register 2 0x00

0x00 53F6 USART3_CR3 USART3 control register 3 0x00

0x00 53F7 USART3_CR4 USART3 control register 4 0x00

0x00 53F8 USART3_CR5 USART3 control register 5 0x00

0x00 53F9 USART3_GTR USART3 guard time register 0x00

0x00 53FA USART3_PSCR USART3 prescaler register 0x00

USART3

USART3_SR USART3 status register 0xC0

Reserved area

Doc ID 023337 Rev 1 45/109

Memory and register map STM8L052R8

Table 7. General hardware register map (continued)

Address Block Register label Register name

0x00 53FB to

0x00 53FF

0x00 5400

0x00 5401 LCD_CR2 LCD control register 2 0x00

0x00 5402 LCD_CR3 LCD control register 3 0x00

0x00 5403 LCD_FRQ LCD frequency selection register 0x00

LCD

0x00 5404 LCD_PM0 LCD Port mask register 0 0x00

0x00 5405 LCD_PM1 LCD Port mask register 1 0x00

0x00 5406 LCD_PM2 LCD Port mask register 2 0x00

0x00 5407 Reserved area

0x00 5408 LCD_PM4 LCD Port mask register 4 0x00

0x00 5409 to

0x00 540B

0x00 540C LCD_RAM0 LCD display memory 0 0x00

0x00 540D LCD_RAM1 LCD display memory 1 0x00

0x00 540E LCD_RAM2 LCD display memory 2 0x00

0x00 540F LCD_RAM3 LCD display memory 3 0x00

LCD_CR1 LCD control register 1 0x00

Reserved area

Reserved area (3 bytes)

Reset

status

0x00 5410 LCD_RAM4 LCD display memory 4 0x00

0x00 5411 LCD_RAM5 LCD display memory 5 0x00

0x00 5412 LCD_RAM6 LCD display memory 6 0x00

0x00 5413 LCD_RAM7 LCD display memory 7 0x00

0x00 5414 LCD_RAM8 LCD display memory 8 0x00

0x00 5415 LCD_RAM9 LCD display memory 9 0x00

0x00 5416 LCD_RAM10 LCD display memory 10 0x00

0x00 5417 LCD_RAM11 LCD display memory 11 0x00

0x00 5418 LCD_RAM12 LCD display memory 12 0x00

0x00 5419 LCD_RAM13 LCD display memory 13 0x00

0x00 541A Reserved area

0x00 541B LCD_RAM15 LCD display memory 15 0x00

0x00 541C Reserved area

0x00 541D LCD_RAM17 LCD display memory 17 0x00

0x00 541E Reserved area

0x00 541F LCD_RAM19 LCD display memory 19 0x00

0x00 5420 Reserved area

0x00 5421 LCD_RAM21 LCD display memory 21 0x00

LCD

46/109 Doc ID 023337 Rev 1

STM8L052R8 Memory and register map

Table 7. General hardware register map (continued)

Address Block Register label Register name

0x00 5422 to

0x00 542E

Reserved area

Reset

status

0x00 542F LCD LCD_CR4 LCD control register 4 0x00

0x00 5430

Reserved area (1 byte) 0x00

0x00 5431 RI_ICR1 Timer input capture routing register 1 0x00

0x00 5432 RI_ICR2 Timer input capture routing register 2 0x00

0x00 5433 RI_IOIR1 I/O input register 1 0xXX

0x00 5434 RI_IOIR2 I/O input register 2 0xXX

0x00 5435 RI_IOIR3 I/O input register 3 0xXX

0x00 5436 RI_IOCMR1 I/O control mode register 1 0x00

0x00 5437 RI_IOCMR2 I/O control mode register 2 0x00

RI

0x00 5438 RI_IOCMR3 I/O control mode register 3 0x00

0x00 5439 RI_IOSR1 I/O switch register 1 0x00

0x00 543A RI_IOSR2 I/O switch register 2 0x00

0x00 543B RI_IOSR3 I/O switch register 3 0x00

0x00 543C RI_IOGCR I/O group control register 0x3F

0x00 543D RI_ASCR1 Analog switch register 1 0x00

0x00 543E RI_ASCR2 Analog switch register 2 0x00

0x00 543F RI_RCR Resistor control register 1 0x00

0x00 5440 to

0x00 5444

1. These registers are not impacted by a system reset. They are reset at power-on.

Reserved area (5 bytes)

Doc ID 023337 Rev 1 47/109

Memory and register map STM8L052R8

Table 8. CPU/SWIM/debug module/interrupt controller registers

Address Block Register Label Register Name

0x00 7F00

0x00 7F01 PCE Program counter extended 0x00

0x00 7F02 PCH Program counter high 0x00

0x00 7F03 PCL Program counter low 0x00

0x00 7F04 XH X index register high 0x00

(1)

0x00 7F05 XL X index register low 0x00

0x00 7F06 YH Y index register high 0x00

0x00 7F07 YL Y index register low 0x00

0x00 7F08 SPH Stack pointer high 0x03

0x00 7F09 SPL Stack pointer low 0xFF

0x00 7F0A CCR Condition code register 0x28

0x00 7F0B to

0x00 7F5F

0x00 7F60 CFG_GCR Global configuration register 0x00

0x00 7F70

0x00 7F71 ITC_SPR2 Interrupt Software priority register 2 0xFF

0x00 7F72 ITC_SPR3 Interrupt Software priority register 3 0xFF

CPU

CPU

A Accumulator 0x00

Reserved area (85 bytes)

ITC_SPR1 Interrupt Software priority register 1 0xFF

Reset

Status

0x00 7F73 ITC_SPR4 Interrupt Software priority register 4 0xFF

0x00 7F74 ITC_SPR5 Interrupt Software priority register 5 0xFF

0x00 7F75 ITC_SPR6 Interrupt Software priority register 6 0xFF

0x00 7F76 ITC_SPR7 Interrupt Software priority register 7 0xFF

0x00 7F77 ITC_SPR8 Interrupt Software priority register 8 0xFF

0x00 7F78 to

0x00 7F79

0x00 7F80 SWIM SWIM_CSR SWIM control status register 0x00

0x00 7F81 to

0x00 7F8F

ITC-SPR

Reserved area (2 bytes)

Reserved area (15 bytes)

48/109 Doc ID 023337 Rev 1

STM8L052R8 Memory and register map

Table 8. CPU/SWIM/debug module/interrupt controller registers (continued)

Address Block Register Label Register Name

0x00 7F90

0x00 7F91 DM_BK1RH DM breakpoint 1 register high byte 0xFF

0x00 7F92 DM_BK1RL DM breakpoint 1 register low byte 0xFF

0x00 7F93 DM_BK2RE DM breakpoint 2 register extended byte 0xFF

0x00 7F94 DM_BK2RH DM breakpoint 2 register high byte 0xFF

0x00 7F95 DM_BK2RL DM breakpoint 2 register low byte 0xFF

0x00 7F96 DM_CR1 DM Debug module control register 1 0x00

0x00 7F97 DM_CR2 DM Debug module control register 2 0x00

0x00 7F98 DM_CSR1 DM Debug module control/status register 1 0x10

0x00 7F99 DM_CSR2 DM Debug module control/status register 2 0x00

0x00 7F9A DM_ENFCTR DM enable function register 0xFF

0x00 7F9B to

0x00 7F9F

1. Accessible by debug module only

DM

DM_BK1RE DM breakpoint 1 register extended byte 0xFF

Reserved area (5 bytes)

Reset

Status

Doc ID 023337 Rev 1 49/109

Interrupt vector mapping STM8L052R8

6 Interrupt vector mapping

Table 9. Interrupt mapping

IRQ

No.

Source

block

Description

Wakeup

from Halt

mode

Wakeup

from

Active-

halt mode

Wakeup

from Wait

(WFI

mode)

from Wait

RESET Reset Yes Yes Yes Yes 0x00 8000

TRAP Software interrupt - - - - 0x00 8004

0TLI

(2)

External Top level Interrupt - - - - 0x00 8008

1 FLASH EOP/WR_PG_DIS - - Yes Yes

2 DMA1 0/1 DMA1 channels 0/1 - - Yes Yes

3 DMA1 2/3 DMA1 channels 2/3 - - Yes Yes

4

5

RTC/LSE_

CSS

EXTI E/F/

(3)

PVD

RTC alarminterrupt/LSE
CSS interrupt

PortE/F interrupt/PVD
interrupt

Yes Yes Yes Yes 0x00 8018

Ye s Ye s Ye s Ye s

6 EXTIB/G External interrupt port B/G Yes Yes Yes Yes

7 EXTID/H External interrupt port D Yes Yes Yes Yes

8 EXTI0 External interrupt 0 Yes Yes Yes Yes

9 EXTI1 External interrupt 1 Yes Yes Yes Yes

10 EXTI2 External interrupt 2 Yes Yes Yes Yes

11 EXTI3 External interrupt 3 Yes Yes Yes Yes

12 EXTI4 External interrupt 4 Yes Yes Yes Yes

13 EXTI5 External interrupt 5 Yes Yes Yes Yes

14 EXTI6 External interrupt 6 Yes Yes Yes Yes

15 EXTI7 External interrupt 7 Yes Yes Yes Yes

Wakeup

(WFE

(1)

mode)

(5)

(5)

(5)

(5)

(5)

(5)

(5)

(5)

(5)

(5)

(5)

(5)

(5)

(5)

Vector

address

0x00 800C

0x00 8010

0x00 8014

0x00 801C

0x00 8020

0x00 8024

0x00 8028

0x00 802C

0x00 8030

0x00 8034

0x00 8038

0x00 803C

0x00 8040

0x00 8044

16 LCD LCD interrupt - - Yes Yes 0x00 8048

17 CLK/TIM1

system clock switch/
CSS interrupt/

--YesYes

(5)

0x00 804C

TIM 1 break

18 ADC1 ACD1 Yes Yes Yes Yes

(5)

0x00 8050

TIM2 update/overflow/
trigger/break

19 TIM2/USART2

USART2 transmission
complete/transmit data

--YesYes

(5)

0x00 8054

register empty
interrupt

20 TIM2/USART2

capture/
compare/USART2 interrupt

--YesYes

(5)

0x00 8058

50/109 Doc ID 023337 Rev 1

STM8L052R8 Interrupt vector mapping

Table 9. Interrupt mapping (continued)

IRQ

No.

Source

block

Description

Wakeup

from Halt

mode

Wakeup

from

Active-

halt mode

Wakeup

from Wait

(WFI

mode)

Wakeup

from Wait

mode)

TIM3 update/overflow/
trigger/break USART3
transmission

21 TIM3/USART3

complete/transmit data

--YesYes

register empty
interrupt

TIM3
capture/compareUSART3
Receive register

22 TIM3/USART3

data full/overrun/idle line

--YesYes

detected/parity error/
interrupt

23 TIM1

Update /overflow/trigger/
COM

---Yes

24 TIM1 Capture/compare - - - Yes

25 TIM4

TIM4 update/overflow/
trigger

--YesYes

26 SPI1 End of Transfer Yes Yes Yes Yes

(WFE

(5)

(5)

(5)

(5)

(5)

(5)

(1)

Vector

address

0x00 805C

0x00 8060

0x00 8064

0x00 8068

0x00 806C

0x00 8070

USART1 transmission
complete/transmit data

27 USART1/TIM5

register empty/

--YesYes

(5)

0x00 8074

TIM5 update/overflow/
trigger/break

USART1 received data

28 USART1/TIM5

ready/overrun error/
idle line detected/parity

--YesYes

(5)

0x00 8078
error/TIM5
capture/compare

29 I

1. The Low power wait mode is entered when executing a WFE instruction in Low power run mode.

2. The TLI interrupt is the logic OR between TIM2 overflow interrupt, and TIM4 overflow interrupts.

3. The interrupt from PVD is logically OR-ed with Port E and F interrupts. Register EXTI_CONF allows to select between Port

4. The device is woken up from Halt or Active-halt mode only when the address received matches the interface address.

5. In WFE mode, this interrupt is served if it has been previously enabled. After processing the interrupt, the processor goes

2

C1/SPI2 I2C1 interrupt

E and Port F interrupt (see External interrupt port select register (EXTI_CONF) in the RM0031).

back to WFE mode. When this interrupt is configured as a wakeup event, the CPU wakes up and resumes processing.

(4)

/ S P I 2 Ye s Yes Ye s Ye s

(5)

0x00 807C

Doc ID 023337 Rev 1 51/109

Option bytes STM8L052R8

7 Option bytes

Option bytes contain configurations for device hardware features as well as the memory
protection of the device. They are stored in a dedicated memory block.

All option bytes can be modified in ICP mode (with SWIM) by accessing the EEPROM
address. See Tabl e 1 0 for details on option byte addresses.

The option bytes can also be modified ‘on the fly’ by the application in IAP mode, except for
the ROP, UBC and PCODESIZE values which can only be taken into account when they are
modified in ICP mode (with the SWIM).

Refer to the STM8Lxx Flash programming manual (PM0054) and STM8 SWIM and Debug
Manual (UM0320) for information on SWIM programming procedures.

Table 10. Option byte addresses

Option

Address Option name

Read-out

00 4800

00 4802

00 4807 PCODESIZE OPT2 PCODE[7:0] 0x00

00 4808

00 4809

00 480A

00 480B Bootloader

00 480C 0x00

protection

(ROP)

UBC (User

Boot code size)

Independent

watchdog

option

Number of

stabilization

clock cycles for

HSE and LSE

oscillators

Brownout reset

(BOR)

option bytes

(OPTBL)

byte

No.

OPT0 ROP[7:0] 0x00

OPT1 UBC[7:0] 0x00

OPT3

[3:0]

OPT4 Reserved LSECNT[1:0] HSECNT[1:0] 0x00

OPT5

[3:0]

OPTBL

[15:0]

7654 3 2 1 0

Reserved

Reserved BOR_TH

Option bits Factory

default
setting

WWDG

_HALT

OPTBL[15:0]

WWDG

_HW

IWDG

_HALT

IWDG

_HW

BOR_

ON

0x00

0x01

0x00

52/ Doc ID 023337 Rev 1

STM8L052R8 Option bytes

Table 11. Option byte description

Option

byte no.

OPT0

OPT1

OPT2

OPT3

OPT4

Option description

ROP[7:0] Memory readout protection (ROP)

0xAA: Disable readout protection (write access via SWIM protocol)
Refer to Readout protection section in the STM8L reference manual (RM0031).

UBC[7:0] Size of the user boot code area

UBC[7:0] Size of the user boot code area
0x00: No UBC
0x01: Page 0 reserved for the UBC and write protected.

...
0xFF: Page 0 to 254 reserved for the UBC and write-protected.
Refer to User boot code section in the STM8L reference manual (RM0031).

PCODESIZE[7:0] Size of the proprietary code area

0x00: No proprietary code area
0x01: Page 0 reserved for the proprietary code and read/write protected.
...
0xFF: Page 0 to 254 reserved for the proprietary code and read/write protected.
Refer to Proprietary code area (PCODE) section in the STM8L reference manual

(RM0031) for more details.

IWDG_HW: Independent watchdog

0: Independent watchdog activated by software
1: Independent watchdog activated by hardware

IWDG_HALT: Independent watchdog off in Halt/Active-halt

0: Independent watchdog continues running in Halt/Active-halt mode
1: Independent watchdog stopped in Halt/Active-halt mode

WWDG_HW: Window watchdog

0: Window watchdog activated by software
1: Window watchdog activated by hardware

WWDG_HALT: Window window watchdog reset on Halt/Active-halt

0: Window watchdog stopped in Halt mode
1: Window watchdog generates a reset when MCU enters Halt mode

HSECNT: Number of HSE oscillator stabilization clock cycles

0x00 - 1 clock cycle
0x01 - 16 clock cycles
0x10 - 512 clock cycles
0x11 - 4096 clock cycles

LSECNT: Number of LSE oscillator stabilization clock cycles

0x00 - 1 clock cycle
0x01 - 16 clock cycles
0x10 - 512 clock cycles
0x11 - 4096 clock cycles

Doc ID 023337 Rev 1 53/

Option bytes STM8L052R8

Table 11. Option byte description (continued)

Option

byte no.

OPT5

OPTBL

Option description

BOR_ON:

0: Brownout reset off
1: Brownout reset on

BOR_TH[3:1]: Brownout reset thresholds. Refer to Ta bl e 1 6 for details on the thresholds
according to the value of BOR_TH bits.

OPTBL[15:0]:
This option is checked by the boot ROM code after reset. Depending on the content of

addresses 00 480B, 00 480C and 0x8000 (reset vector) the CPU jumps to the
bootloader or to the reset vector.

Refer to the UM0560 bootloader user manual for more details.

54/ Doc ID 023337 Rev 1

STM8L052R8 Electrical parameters

50 pF

STM8L PIN

8 Electrical parameters

8.1 Parameter conditions

Unless otherwise specified, all voltages are referred to VSS.

8.1.1 Minimum and maximum values

Unless otherwise specified the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at T
the selected temperature range).

Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean±3Σ).

8.1.2 Typical values

= 25 °C and TA = TA max (given by

A

Unless otherwise specified, typical data are based on TA = 25 °C, V
only as design guidelines and are not tested.

Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated

8.1.3 Typical curves

Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.

8.1.4 Loading capacitor

The loading conditions used for pin parameter measurement are shown in Figure 5.

Figure 5. Pin loading conditions

(mean±2Σ).

= 3 V. They are given

DD

Doc ID 023337 Rev 1 55/103

Electrical parameters STM8L052R8

V

IN

STM8L PIN

8.1.5 Pin input voltage

The input voltage measurement on a pin of the device is described in Figure 6.

Figure 6. Pin input voltage

8.2 Absolute maximum ratings

Stresses above those listed as “absolute maximum ratings” may cause permanent damage
to the device. This is a stress rating only and functional operation of the device under these
conditions is not implied. Exposure to maximum rating conditions for extended periods may
affect device reliability.

Table 12. Voltage characteristics

Symbol Ratings Min Max Unit

- V

V

DD

SS

(2)

V

IN

External supply voltage
(including V

DDA

(1)

)

Input voltage on true open-drain pins
(PC0 and PC1)

Input voltage on five-volt tolerant (FT)
pins

Input voltage on any other pin

- 0.3 4.0

V

- 0.3 VDD + 4.0

SS

- 0.3 V

V

SS

- 0.3 4.0

V

SS

DD

+ 4.0

see Absolute maximum

V

ESD

Electrostatic discharge voltage

ratings (electrical sensitivity)

on page 102

1. All power (V
be connected to the external power supply.

2. VIN maximum must always be respected. Refer to Table 13. for maximum allowed injected current values.

DD1

, V

DD2

, V

DD3

, V

DD4

, V

) and ground (V

DDA

SS1

, V

SS2

, V

SS3

, V

SS4

, V

) pins must always

SSA

V

56/103 Doc ID 023337 Rev 1

STM8L052R8 Electrical parameters

Table 13. Current characteristics

Symbol Ratings Max. Unit

I

VDD

I

VSS

I

IO

Total current into V

Total current out of V

Output current sunk by IR_TIM pin
(with high sink LED driver capability)

power line (source) 80

DD

ground line (sink) 80

SS

80

Output current sunk by any other I/O and control pin 25

Output current sourced by any I/Os and control pin - 25

Injected current on true open-drain pins (PC0 and PC1)

INJ(PIN)

INJ(PIN)

Injected current on five-volt tolerant (FT) pins

Injected current on any other pin

Total injected current (sum of all I/O and control pins)

(2)

I

ΣI

1. Positive injection is not possible on these I/Os. A negative injection is induced by VIN<VSS. I
never be exceeded. Refer to Table 12. for maximum allowed input voltage values.

2. A positive injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS. I
never be exceeded. Refer to Table 12. for maximum allowed input voltage values.

3. When several inputs are submitted to a current injection, the maximum ΣI
positive and negative injected currents (instantaneous values).

Table 14. Thermal characteristics

(1)

(1)

(3)

is the absolute sum of the

INJ(PIN)

- 5 / +0

- 5 / +0

- 5 / +5

± 25

INJ(PIN)

INJ(PIN)

must

Symbol Ratings Value Unit

mA

must

T

STG

T

J

Storage temperature range -65 to +150

° C

Maximum junction temperature 150

Doc ID 023337 Rev 1 57/103

Electrical parameters STM8L052R8

8.3 Operating conditions

Subject to general operating conditions for VDD and TA.

8.3.1 General operating conditions

Table 15. General operating conditions

Symbol Parameter Conditions Min. Max. Unit

System clock

f

SYSCLK

1. f

2. To calculate P

3. T

(1)

frequency

V

DD

V

DDA

(2)

P

D

T

A

T

J

SYSCLK

characteristics” table.

Jmax

Standard operating
voltage

Analog operating
voltage

Power dissipation at

= 85 °C

T

A

Temperature range 1.8 V ≤ V

Junction temperature
range

= f

CPU

), use the formula P

Dmax(TA

is given by the test limit. Above this value the product behavior is not guaranteed.

Dmax

1.8 V ≤ V

Must be at the same

potential as V

-40 °C ≤ T

=(T

-TA)/ΘJA with T

Jmax

< 3.6 V 0 16 MHz

DD

DD

LQFP64 288 mW

< 3.6 V -40 85

DD

< 85 °C -40 105

A

Jmax

1.8 3.6 V

1.8 3.6 V

in this table and Θ

in “Thermal

JA

(3)

°C

58/103 Doc ID 023337 Rev 1

STM8L052R8 Electrical parameters

8.3.2 Embedded reset and power control block characteristics

Table 16. Embedded reset and power control block characteristics

Symbol Parameter Conditions Min.

t

VDD

VDD rise time rate

V

fall time rate

DD

BOR detector
enabled

BOR detector
disabled

BOR detector
enabled

BOR detector
disabled

rising

V

DD

(1)

0

(1)

0

(1)

20

Reset below voltage functional range

BOR detector
enabled

t

TEMP

Reset release delay

V

DD

rising

BOR detector
disabled

V

V

V

V

V

V

V

POR

PDR

BOR0

BOR1

BOR2

BOR3

BOR4

Power-on reset threshold Rising edge 1.3

Power-down reset threshold Falling edge 1.3

Brown-out reset threshold 0
(BOR_TH[2:0]=000)

Brown-out reset threshold 1
(BOR_TH[2:0]=001)

Brown-out reset threshold 2
(BOR_TH[2:0]=010)

Brown-out reset threshold 3
(BOR_TH[2:0]=011)

Brown-out reset threshold 4
(BOR_TH[2:0]=100)

Falling edge 1.67 1.7 1.74

Rising edge 1.69 1.75 1.80

Falling edge 1.87 1.93 1.97

Rising edge 1.96 2.04 2.07

Falling edge 2.22 2.3 2.35

Rising edge 2.31 2.41 2.44

Falling edge 2.45 2.55 2.60

Rising edge 2.54 2.66 2.7

Falling edge 2.68 2.80 2.85

Rising edge 2.78 2.90 2.95

(2)

(2)

Typ.

Max. Unit

∞

(1)

1

∞

3

1

1.5 1.65

1.5 1.65

(1)

(1)

µs/V

ms/V

µs/V

ms

V

Doc ID 023337 Rev 1 59/103

Electrical parameters STM8L052R8

Table 16. Embedded reset and power control block characteristics (continued)

Symbol Parameter Conditions Min.

Typ.

Max. Unit

V

V

V

V

V

V

V

PVD0

PVD1

PVD2

PVD3

PVD4

PVD5

PVD6

PVD threshold 0

PVD threshold 1

PVD threshold 2

PVD threshold 3

PVD threshold 4

PVD threshold 5

PVD threshold 6

Vhyst Hysteresis voltage

Falling edge 1.80 1.84 1.88

Rising edge 1.88 1.94 1.99

Falling edge 1.98 2.04 2.09

Rising edge 2.08 2.14 2.18

Falling edge 2.2 2.24 2.28

Rising edge 2.28 2.34 2.38

Falling edge 2.39 2.44 2.48

Rising edge 2.47 2.54 2.58

Falling edge 2.57 2.64 2.69

Rising edge 2.68 2.74 2.79

Falling edge 2.77 2.83 2.88

Rising edge 2.87 2.94 2.99

Falling edge 2.97 3.05 3.09

Rising edge 3.08 3.15 3.20

BOR0 threshold 40

All BOR and PVD
thresholds

100

excepting BOR0

V

mV

1. Data guaranteed by design, not tested in production.

2. Data based on characterization results, not tested in production.

60/103 Doc ID 023337 Rev 1

STM8L052R8 Electrical parameters

VDD/V

DDA

PVD output

100 mV

hysteresis

V

PVD

V

BOR

hyster esi s

100 mV

IT enabled

BOR reset

(NRST)

POR/PDR reset

(NR ST)

PVD
BOR always active

POR/PDR (BOR not available)

ai17211b

POR

V

/

PDR

V

BOR/PDR reset
(NRST)

BOR disabled by option byte

(Note 1)

(Note 2)

(Note 3)

(Note 4)

Figure 7. Power supply thresholds

Doc ID 023337 Rev 1 61/103

Electrical parameters STM8L052R8

8.3.3 Supply current characteristics

Total current consumption

The MCU is placed under the following conditions:

● All I/O pins in input mode with a static value at V

● All peripherals are disabled except if explicitly mentioned.

In the following table, data are based on characterization results, unless otherwise specified.

or VSS (no load)

DD

Subject to general operating conditions for V

Table 17. Total current consumption in Run mode

Symbol Parameter

I

DD(RUN)

Supply
current in

run mode

All peripherals
OFF,
code executed
from RAM,

(2)

V

DD

to

3.6 V

from 1.8 V

Conditions

HSI RC osc.

(16 MHz)

(3)

HSE external
clock

(f

CPU=fHSE

(5)

)

LSI RC osc.
(typ. 38 kHz)

(1)

f

f

f

f

f

f

f

f

f

f

f

DD

= 125 kHz

CPU

= 1 MHz

CPU

= 4 MHz

CPU

= 8 MHz

CPU

= 16 MHz

CPU

= 125 kHz

CPU

= 1 MHz

CPU

= 4 MHz

CPU

= 8 MHz

CPU

= 16 MHz

CPU

= f

CPU

and TA.

LSI

Max.

Typ.

55°C 85 °C

0.22 0.28 0.39

0.32 0.38 0.49

0.59 0.65 0.76

0.93 0.99 1.1

1.62 1.68 1.79

0.21 0.25 0.35

0.3 0.34 0.44

0.57 0.61 0.71

0.95 0.99 1.09

1.73 1.77 1.87

0.029 0.035 0.039

Unit

(4)

mA

(4)

LSE external

= f

clock

f

CPU

(32.768 kHz)

62/103 Doc ID 023337 Rev 1

LSE

0.028 0.034 0.038

STM8L052R8 Electrical parameters

Table 17. Total current consumption in Run mode (continued)

Symbol Parameter

Conditions

(1)

Typ.

55°C 85 °C

Max.

f

I

DD(RUN)

Supply
current
in Run
mode

All peripherals
OFF, code
executed from
Flash,

from 1.8 V

V

DD

to 3.6 V

HSI RC

(6)

osc.

HSE external
clock

(f

CPU=fHSE

)

LSI RC osc.

(5)

CPU

f

CPU

f

CPU

f

CPU

f

CPU

f

CPU

f

CPU

f

CPU

f

CPU

f

CPU

f

CPU

= 125 kHz

= 1 MHz

= 4 MHz

= 8 MHz

= 16 MHz

= 125 kHz

= 1 MHz

= 4 MHz

= 8 MHz

= 16 MHz

= f

LSI

0.35 0.46 0.48

0.54 0.65 0.67

1.16 1.27 1.29

1.97 2.08 2.1

3.54 3.65 3.67

0.35 0.44 0.46

0.53 0.62 0.64

1.13 1.22 1.24

22.092.11

3.69 3.78 3.8

0.110 0.123 0.130

LSE external
clock

(32.768 kHz)

1. All peripherals OFF, VDD from 1.8 V to 3.6 V, HSI internal RC osc., f

2. CPU executing typical data processing

3. The run from RAM consumption can be approximated with the linear formula:
(run_from_RAM) = Freq. * 95 µA/MHz + 250 µA

I

DD

4. Tested in production.

5. Oscillator bypassed (HSEBYP = 1 in CLK_ECKCR). When configured for external crystal, the HSE consumption

6. The run from Flash consumption can be approximated with the linear formula:

7. Oscillator bypassed (LSEBYP = 1 in CLK_ECKCR). When configured for external crystal, the LSE consumption

) must be added. Refer to Table 28.

(I

DD HSE

(run_from_Flash) = Freq. * 200 µA/MHz + 330 µA

I

DD

) must be added. Refer to Table 29

(I

DD LSE

(7)

f

= f

CPU

CPU=fSYSCLK

LSE

0.100 0.101 0.104

Unit

mA

Doc ID 023337 Rev 1 63/103

Electrical parameters STM8L052R8

Figure 8. Typical I

2

1.8

1.6

1.4

1.2

1

0.8

0.6

IDD Run HSI 16MHz (mA)

0.4

0.2

0

1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6

DD(RUN)

from RAM vs. VDD (HSI clock source), f

VDD (V)

1. Typical current consumption measured with code executed from RAM.

Figure 9. Typical I

DD(RUN)

from Flash vs. V

(HSI clock source), f

DD

=16 MHz

CPU

25°C

85 °C

-40°C

= 16 MHz

CPU

1)

MS19109V2

1)

4

3.5

3

2.5

IDD Run HSI EEP 16MHz (m A)

2

1.5

1.8 2 2.2 2.4 2.6 2.8 3 3. 2 3.4 3.6

VDD (V)

1. Typical current consumption measured with code executed from Flash.

25°C

85°C

-

40°C

MS19112V2

64/103 Doc ID 023337 Rev 1

STM8L052R8 Electrical parameters

In the following table, data are based on characterization results, unless otherwise specified.

Table 18. Total current consumption in Wait mode

Symbol Parameter

Conditions

(1)

Typ

55°C

= 125 kHz

Max

f

CPU

f

= 1 MHz

CPU

f

f

f

f

f

f

f

f

f

f

f

f

f

f

f

f

f

f

f

f

f

f

= f

CPU

CPU

CPU

CPU

CPU

CPU

CPU

CPU

CPU

CPU

CPU

CPU

CPU

CPU

CPU

CPU

CPU

CPU

CPU

CPU

CPU

CPU

SYSCLK

= 4 MHz

= 8 MHz

= 16 MHz

= 125 kHz

= 1 MHz

= 4 MHz

= 8 MHz

= 16 MHz

= f

LSI

= f

LSE

= 125 kHz

= 1 MHz

= 4 MHz

= 8 MHz

= 16 MHz

= 125 kHz

= 1 MHz

= 4 MHz

= 8 MHz

= 16 MHz

= f

LSI

= f

LSE

HSI

CPU not
clocked,
all peripherals
OFF,
code executed
from RAM
with Flash in I

(2)

mode,

HSE external clock

DDQ

(f

CPU=fHSE

(4)

)

VDD from

1.8 V to 3.6 V

LSI

(5)

external clock

LSE
(32.768 kHz)

I

DD(Wait)

Supply
current in
Wait mode

HSI

CPU not
clocked,
all peripherals
OFF,
code executed
from Flash,

from

V

DD

1.8 V to 3.6 V

HSE
(f

CPU

HSE)

(4)

=

external clock

LSI

(5)

external clock

LSE
(32.768 kHz)

1. All peripherals OFF, VDD from 1.8 V to 3.6 V, HSI internal RC osc., f

2. Flash is configured in I

3. Tested in production.

4. Oscillator bypassed (HSEBYP = 1 in CLK_ECKCR). When configured for external crystal, the HSE consumption

) must be added. Refer to Table 28.

(I

DD HSE

mode in Wait mode by setting the EPM or WAITM bit in the Flash_CR1 register.

DDQ

CPU

0.21 0.29 0.33

0.25 0.33 0.37

0.32 0.4 0.44

0.42 0.496 0.54

0.66 0.736 0.78

0.19 0.21 0.3

0.2 0.23 0.32

0.27 0.3 0.39

0.37 0.4 0.49

0.63 0.66 0.75

0.028 0.037 0.039

0.027 0.035 0.038

0.27 0.36 0.42

0.29 0.38 0.44

0.37 0.46 0.52

0.45 0.55 0.61

0.69 0.79 0.85

0.23 0.29 0.32

0.24 0.31 0.34

0.32 0.39 0.42

0.42 0.49 0.51

0.7 0.77 0.79

0.037 0.085 0.105

0.036 0.082 0.095

Unit

85 °C

(3)

mA

(3)

mA

Doc ID 023337 Rev 1 65/103

Electrical parameters STM8L052R8

0.2

0.3

0.4

0.5

0.6

0.7

0.8

1.8 2 2.2 2.4 2. 6 2. 8 3 3.2 3. 4 3.6

DD

MS19108V2

5. Oscillator bypassed (LSEBYP = 1 in CLK_ECKCR). When configured for external crystal, the LSE consumption

) must be added. Refer to Table 29

(I

DD HSE

Figure 10. Typical I

DD(Wait)

0.8

0.7

0.6

0.5

0.4

IDD Wait HSI 16MHz (mA)

0.3

0.2

1.8 2 2.2 2.4 2. 6 2.8 3 3.2 3.4 3.6

from RAM vs. V

VDD (V)

(HSI clock source), f

DD

25°C

85°C

-

40°C

= 16 MHz

CPU

MS19113V2

1. Typical current consumption measured with code executed from RAM.

1)

Figure 11. Typical I

IDD Wfi HSI 16MHz EEON (mA)

1. Typical current consumption measured with code executed from Flash.

DD(Wait)

from Flash (HSI clock source), f

V

(V)

= 16 MHz

CPU

1)

25°C

85°C

-40°C

66/103 Doc ID 023337 Rev 1

STM8L052R8 Electrical parameters

In the following table, data are based on characterization results, unless otherwise specified.

Table 19. Total current consumption and timing in Low power run mode at V

= 1.8 V to

DD

3.6 V

Symbol

Parameter

Conditions

all peripherals OFF

LSI RC osc.
(at 38 kHz)

with TIM2 active

I

DD(LPR)

Supply current in Low
power run mode

all peripherals OFF

(3)

LSE

external
clock
(32.768 kHz)

with TIM2 active

1. No floating I/Os

2. Timer 2 clock enabled and counter running

3. Oscillator bypassed (LSEBYP = 1 in CLK_ECKCR). When configured for external crystal, the LSE consumption
) must be added. Refer to Table 29

(I

DD LSE

(1)

(2)

(2)

Typ. Max. Unit

= -40 °C

T

A

to 25 °C

T

= 55 °C 6.52 7.06

A

= 85 °C 7.68 8.7

T

A

T

= -40 °C

A

to 25 °C

T

= 55 °C 6.86 7.41

A

= 85 °C 9.71 10.81

T

A

TA = -40 °C
to 25 °C

T

= 55 °C 5.9 6.52

A

= 85 °C 6.14 6.8

T

A

TA = -40 °C
to 25 °C

T

= 55 °C 6.44 6.95

A

= 85 °C 6.7 7.65

T

A

5.86 6.38

6.2 6.73

5.42 5.94

5.87 6.48

μA

Doc ID 023337 Rev 1 67/103

Electrical parameters STM8L052R8

Figure 12. Typical I

0.02

0.015

0.01

IDD LpRun L SI all off (m A)

0.005

0

1.8 2 2. 2 2.4 2.6 2.8 3 3.2 3.4 3. 6

DD(LPR)

vs. V

(LSI clock source), all peripherals OFF

DD

VDD (V)

25°C

85°C

- 40°C

MS19110V2

68/103 Doc ID 023337 Rev 1

STM8L052R8 Electrical parameters

0

0.005

0.01

0.015

0.02

1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6

LpWfi ram LSI all o ff (m

VDD(V)

°C

0°C

.47

°C

In the following table, data are based on characterization results, unless otherwise specified.

Table 20. Total current consumption in Low power wait mode at V

Symbol

I

DD(LPW)

1. No floating I/Os.

2. Timer 2 clock enabled and counter is running.

3. Oscillator bypassed (LSEBYP = 1 in CLK_ECKCR). When configured for external crystal, the LSE consumption

(I

DD LSE

Parameter

LSI RC osc.
(at 38 kHz)

Supply current in
Low power wait
mode

LSE external

(3)

clock
(32.768 kHz)

) must be added. Refer to Table 29.

Conditions

all peripherals OFF

with TIM2 active

(2)

all peripherals OFF

with TIM2 active

(2)

= 1.8 V to 3.6 V

DD

(1)

= -40 °C to 25 °C

T

A

T

= 55 °C 3.38 3.78

A

= 85 °C 4.6 5.34

T

A

TA = -40 °C to 25 °C

T

= 55 °C 4.13 4.57

A

T

= 85 °C 5.29 6.08

A

TA = -40 °C to 25 °C

T

= 55 °C 2.58 3.07

A

= 85 °C 3.32 4.05

T

A

TA = -40 °C to 25 °C

= 55 °C 2.97 3.42

T

A

T

= 85 °C 3.69 4.55

A

Typ. Max. Unit

3.03 3.41

3.78 4.21

μA

2.46 2.89

2.88 3.29

Figure 13. Typical I

A)

IDD

DD(LPW)

vs. V

(LSI clock source), all peripherals OFF

DD

1. Typical current consumption measured with code executed from RAM.

(1)

25

85

-4

Doc ID 023337 Rev 1 69/103

Electrical parameters STM8L052R8

In the following table, data are based on characterization results, unless otherwise specified.

Table 21. Total current consumption and timing in Active-halt mode

Symbol

at V

= 1.8 V to 3.6 V

DD

Parameter

Conditions

(1)

Typ. Max. Unit

I

DD(AH)

I

DD(AH)

I

DD(WUFAH)

Supply current in
Active-halt mode

Supply current in
Active-halt mode

Supply current during
wakeup time from
Active-halt mode
(using HSI)

LSI RC
(at 38 kHz)

LSE external
clock
(32.768 kHz)

(6)

LCD OFF

(2)

LCD ON
(static duty/
external

(3)

)

V

LCD

LCD ON
(1/4 duty/
external

(4)

)

V

LCD

LCD ON
(1/4 duty/
internal

(5)

)

V

LCD

LCD OFF

(7)

LCD ON
(static duty/
external

(3)

V

)

LCD

LCD ON
(1/4 duty/
external

(4)

V

)

LCD

LCD ON
(1/4 duty/
internal

(5)

)

V

LCD

TA = -40 °C to 25 °C

T

= 55 °C 1.32 3.44

A

= 85 °C 1.63 3.87

T

A

TA = -40 °C to 25 °C

T

= 55 °C 1.64 3.8

A

= 85 °C 2.12 5.03

T

A

TA = -40 °C to 25 °C

T

= 55 °C 2.1 4.97

A

= 85 °C 2.6 6.14

T

A

TA = -40 °C to 25 °C

T

= 55 °C 4.39 10.32

A

= 85 °C 4.84 11.5

T

A

TA = -40 °C to 25 °C

T

= 55 °C 0.61 1.44

A

= 85 °C 0.91 2.27

T

A

TA = -40 °C to 25 °C

= 55 °C 1.05 2.55

T

A

= 85 °C 1.42 3.65

T

A

TA = -40 °C to 25 °C

= 55 °C 1.76 4.37

T

A

= 85 °C 2.14 5.23

T

A

TA = -40 °C to 25 °C

T

= 55 °C 3.89 9.15

A

= 85 °C 4.25 10.49

T

A

0.92 2.25

1.56 3.6

1.92 4.56

4.2 9.88

0.54 1.35

0.91 2.13

1.6 2.84

3.89 9.15

2.4 mA

μA

μA

Wakeup time from

(8)(9)

t

WU_HSI(AH)

Active-halt mode to
Run mode (using HSI)

Wakeup time from

(8)(9)

t

WU_LSI(AH)

Active-halt mode to
Run mode (using LSI)

70/103 Doc ID 023337 Rev 1

4.7 7 μs

150 μs

STM8L052R8 Electrical parameters

0

0.005

0.01

0.015

0.02

1.8 2 2.2 2.4 2. 6 2.8 3 3. 2 3.4 3. 6

AHalt (m

25°C

85°C

-40°C

MS19117V2

1. No floating I/O, unless otherwise specified.

2. RTC enabled. Clock source = LSI

3. RTC enabled, LCD enabled with external V

4. RTC enabled, LCD enabled with external V

5. LCD enabled with internal LCD booster V

connected.

6. Oscillator bypassed (LSEBYP = 1 in CLK_ECKCR). When configured for external crystal, the LSE consumption

(I

) must be added. Refer to Table 29

DD LSE

7. RTC enabled. Clock source = LSE

8. Wakeup time until start of interrupt vector fetch.

The first word of interrupt routine is fetched 4 CPU cycles after t

9. ULP=0 or ULP=1 and FWU=1 in the PWR_CSR2 register.

= 3 V, static duty, division ratio = 256, all pixels active, no LCD connected.

LCD

, 1/4 duty, 1/3 bias, division ratio = 64, all pixels active, no LCD connected.

LCD

= 3 V, 1/4 duty, 1/3 bias, division ratio = 64, all pixels active, no LCD

LCD

.

WU

Table 22. Typical current consumption in Active-halt mode, RTC clocked by LSE external crystal

Symbol Parameter Condition

(1)

Typ . Unit

LSE 1.2

= 1.8 V

V

I

DD(AH)

(2)

Supply current in Active-halt
mode

DD

V

DD

= 3 V

(3)

LSE/32

LSE 1.4

(3)

LSE/32

0.9

µA

1.1

LSE 1.6

V

= 3.6 V

DD

1. No floating I/O, unless otherwise specified.

2. Based on measurements on bench with 32.768 kHz external crystal oscillator.

3. RTC clock is LSE divided by 32.

Figure 14. Typical I

A)

DD(AH)

vs. V

(LSI clock source)

DD

LSE/32

(3)

1.3

IDD

Doc ID 023337 Rev 1 71/103

VDD(V)

Electrical parameters STM8L052R8

In the following table, data are based on characterization results, unless otherwise specified.

Table 23. Total current consumption and timing in Halt mode at V

Symbol

Parameter

Condition

(1)

= 1.8 to 3.6 V

DD

Typ. Max. Unit

Supply current in Halt mode

I

DD(Halt)

(Ultra low power ULP bit =1 in
the PWR_CSR2

register)

Supply current during wakeup

I

DD(WUHalt)

time from Halt mode (using
HSI)

t

WU_HSI(Halt)

t

WU_LSI(Halt)

(3)(4)

(3)(4)

1. TA = -40 to 85 °C, no floating I/O, unless otherwise specified

2. Tested in production

3. ULP=0 or ULP=1 and FWU=1 in the PWR_CSR2 register

4. Wakeup time until start of interrupt vector fetch.

The first word of interrupt routine is fetched 4 CPU cycles after t

Figure 15. Typical I

Wakeup time from Halt to Run
mode (using HSI)

Wakeup time from Halt mode
to Run mode (using LSI)

vs. V

0.02

0.02

0.018

0.018

0.016

0.016

DD(Halt)

DD

T

= -40 °C to 25 °C 400

A

= 55 °C 810 2400

T

A

TA = 85 °C 1600

2.4 mA

4.7 7 µs

150 µs

WU

(internal reference voltage OFF)

1600

4500

25°C

25°C

85°C

85°C

-40°C

(2)

nA

(2)

0.014

0.014

0.012

0.012

0.01

0.01

0.008

0.008

IDD Halt bgo ff (mA)

IDD Halt bgo ff (mA)

0.006

0.004

0.002

0

1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6

DD (V)

V

MS19119V2

72/103 Doc ID 023337 Rev 1

STM8L052R8 Electrical parameters

Current consumption of on-chip peripherals

Table 24. Peripheral current consumption

Symbol Parameter

I

DD(ALL)

I

DD(TIM1)

I

DD(TIM2)

I

DD(TIM3)

I

DD(TIM5)

I

DD(TIM4)

I

DD(USART1)

I

DD(USART2)

I

DD(USART3)

I

DD(SPI1)

I

DD(SPI2)

I

DD(I2C1)

I

DD(DMA1)

I

DD(WWDG)

I

DD(ADC1)

I

DD(PVD/BOR)

Peripherals ON

TIM1 supply current

TIM2 supply current

TIM3 supply current

TIM5 supply current

TIM4 timer supply current

USART1 supply current

USART2 supply current

USART3 supply current

SPI1 supply current

SPI2 supply current

I2C1 supply current

DMA1 supply current 3

WWDG supply current 1

ADC1 supply current

Power voltage detector and brownout Reset unit supply current

(5)

(1)

(2)

(2)

(2)

(2)

(2)

(3)

(3)

(3)

(3)

(3)

(3)

(4)

V

DD

Typ.

= 3.0 V

63

10

7

7

7

3

5

5

5

3

3

4

1500

2.6

Unit

µA/MHz

I

DD(BOR)

I

DD(IDWDG)

1. Peripherals listed above the I

SPI2, I2C1, DMA1, WWDG.

2. Data based on a differential I

CPU is in Wait mode in both cases. No IC/OC programmed, no I/O pins toggling. Not tested in production.

3. Data based on a differential I

the on-chip peripheral when clocked and not kept under reset. The CPU is in Wait mode in both cases. No I/O pins
toggling. Not tested in production.

4. Data based on a differential I

5. Including supply current of internal reference voltage.

Brownout Reset unit supply current

Independent watchdog supply current

parameter ON: TIM1, TIM2, TIM3, TIM4, TIM5, USART1, USART2, USART3, SPI1,

DD(ALL)

measurement between all peripherals OFF and a timer counter running at 16 MHz. The

DD

measurement between the on-chip peripheral in reset configuration and not clocked and

DD

measurement between ADC in reset configuration and continuous ADC conversion.

DD

(5)

including LSI supply
current

excluding LSI
supply current

2.4

0.45

0.05

Doc ID 023337 Rev 1 73/103

µA

Electrical parameters STM8L052R8

Table 25. Current consumption under external reset

Symbol Parameter Conditions Typ. Unit

V

= 1.8 V 48

I

DD(RST)

1. All pins except PA0, PB0 and PB4 are floating under reset. PA0, PB0 and PB4 are configured with pull-up under reset.

PB1, PB3 and PA5 must be tied externally under reset to avoid the consumption due to their schmitt trigger.

Supply current under

external reset

(1)

PB1/PB3/PA5 pins are
externally tied to V

DD

DD

= 3 V 80

DD

= 3.6 V 95

V

DD

8.3.4 Clock and timing characteristics

HSE external clock (HSEBYP = 1 in CLK_ECKCR)

Subject to general operating conditions for VDD and TA.

Table 26. HSE external clock characteristics

Symbol Parameter Conditions Min. Typ. Max. Unit

External clock source

f

HSE_ext

V

HSEH

V

HSEL

C

in(HSE)

I

LEAK_HSE

(1)

frequency

OSC_IN input pin high level
voltage

OSC_IN input pin low level
voltage

(1)

OSC_IN input capacitance 2.6 pF

OSC_IN input leakage
current

V

< V

IN

< V

DD

SS

116MHz

0.7 x V

V

SS

DD

V

DD

0.3 x V

DD

±1 µA

µAV

V

1. Guaranteed by design, not tested in production.

74/103 Doc ID 023337 Rev 1

STM8L052R8 Electrical parameters

LSE external clock (LSEBYP=1 in CLK_ECKCR)

Subject to general operating conditions for VDD and TA.

(2)

(2)

(1)

External clock source frequency 32.768 kHz

OSC32_IN input pin high level voltage 0.7 x V

OSC32_IN input pin low level voltage V

(1)

OSC32_IN input capacitance 0.6 pF

SS

DD

0.3 x V

OSC32_IN input leakage current ±1 µA

V

DD

V

DD

Table 27. LSE external clock characteristics

Symbol Parameter Min. Typ. Max. Unit

f

LSE_ext

V

LSEH

V

LSEL

C

in(LSE)

I

LEAK_LSE

1. Guaranteed by design, not tested in production.

2. Data based on characterization results, not tested in production.

HSE crystal/ceramic resonator oscillator

The HSE clock can be supplied with a 1 to 16 MHz crystal/ceramic resonator oscillator. All
the information given in this paragraph is based on characterization results with specified
typical external components. In the application, the resonator and the load capacitors have
to be placed as close as possible to the oscillator pins in order to minimize output distortion
and startup stabilization time. Refer to the crystal resonator manufacturer for more details
(frequency, package, accuracy...).

Table 28. HSE oscillator characteristics

Symbol Parameter Conditions Min. Typ. Max. Unit

f

HSE

R

(1)(2)

C

I

DD(HSE)

g

t

SU(HSE)

1. C=

2. The oscillator selection can be optimized in terms of supply current using a high quality resonator with small R

Refer to crystal manufacturer for more details

3. Guaranteed by design. Not tested in production.

4. t

SU(HSE)

value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer.

High speed external oscillator
frequency

Feedback resistor 200 kΩ

F

Recommended load capacitance

C = 20 pF,

f

= 16 MHz

HSE oscillator power consumption

OSC

C = 10 pF,

=16 MHz

f

OSC

Oscillator transconductance 3.5

m

(4)

Startup time VDD is stabilized 1 ms

C

=

C

is approximately equivalent to 2 x crystal C

L1

L2

is the startup time measured from the moment it is enabled (by software) to a stabilized 16 MHz oscillation. This

LOAD

.

116MHz

20 pF

2.5 (startup)

0.7 (stabilized)

2.5 (startup)

0.46 (stabilized)

(3)

value.

m

(3)

(3)

mA

mA/V

Doc ID 023337 Rev 1 75/103

Electrical parameters STM8L052R8

OSC_OUT

OSC_IN

f

HSE

to core

C

L1

C

L2

R

F

STM8

Resonator

Consumption

control

g

m

R

m

C

m

L

m

C

O

Resonator

g

mcrit

2 Π× f

HSE

×()

2

Rm× 2Co C+()

2

=

Figure 16. HSE oscillator circuit diagram

HSE oscillator critical g

Rm: Motional resistance (see crystal specification), Lm: Motional inductance (see crystal specification),

: Motional capacitance (see crystal specification), Co: Shunt capacitance (see crystal specification),

C

m

=C: Grounded external capacitance

C

L1=CL2

g

>> g

m

mcrit

formula

m

LSE crystal/ceramic resonator oscillator

The LSE clock can be supplied with a 32.768 kHz crystal/ceramic resonator oscillator. All
the information given in this paragraph is based on characterization results with specified
typical external components. In the application, the resonator and the load capacitors have
to be placed as close as possible to the oscillator pins in order to minimize output distortion
and startup stabilization time. Refer to the crystal resonator manufacturer for more details
(frequency, package, accuracy...).

Table 29. LSE oscillator characteristics

Symbol Parameter Conditions Min. Typ. Max. Unit

f

LSE

R

F

(1)(2)

C

I

DD(LSE)

g

m

t

SU(LSE)

1. C=

C

2. The oscillator selection can be optimized in terms of supply current using a high quality resonator with a small R

Refer to crystal manufacturer for more details.

3. Guaranteed by design. Not tested in production.

4. t

SU(LSE)

This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer.

Low speed external oscillator
frequency

32.768 kHz

Feedback resistor ΔV = 200 mV 1.2 MΩ

Recommended load capacitance

V

= 1.8 V 450

DD

LSE oscillator power consumption

Oscillator transconductance 3

(4)

Startup time VDD is stabilized 1 s

=

C

is approximately equivalent to 2 x crystal C

L1

L2

is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation.

= 3 V 600

DD

= 3.6 V 750

V

DD

.

LOAD

(3)

8pF

value.

m

nAV

µA/V

76/103 Doc ID 023337 Rev 1

STM8L052R8 Electrical parameters

OSC_OUT

OSC_IN

f

LSE

C

L1

C

L2

R

F

STM8

Resonator

Consumption

control

g

m

R

m

C

m

L

m

C

O

Resonator

Figure 17. LSE oscillator circuit diagram

Internal clock sources

Subject to general operating conditions for VDD, and TA.

High speed internal RC oscillator (HSI)

In the following table, data are based on characterization results, not tested in production,
unless otherwise specified.

Table 30. HSI oscillator characteristics

Symbol

Parameter

Conditions

(1)

Min. Typ. Max. Unit

f

HSI

ACC

TRIM

t

su(HSI)

I

DD(HSI)

Frequency VDD = 3.0 V 16 MHz

Accuracy of HSI
oscillator (factory

HSI

calibrated)

HSI user trimming

(3)

step

HSI oscillator setup
time (wakeup time)

HSI oscillator power
consumption

= 3.0 V, TA = 25 °C -1

V

DD

1.8 V ≤ V

-40 °C ≤ T

≤ 3.6 V,

DD

≤ 85 °C

A

Trimming code ≠ multiple of 16 0.4 0.7 %

Trimming code = multiple of 16 ± 1.5 %

(2)

-5 5 %

3.7 6

100 140

1

(2)

(4)

(4)

µA

1. VDD = 3.0 V, TA = -40 to 85 °C unless otherwise specified.

2. Tested in production.

3. The trimming step differs depending on the trimming code. It is usually negative on the codes which are multiples of 16

(0x00, 0x10, 0x20, 0x30...0xE0). Refer to the AN3101 “STM8L15x internal RC oscillator calibration” application note for
more details.

4. Guaranteed by design, not tested in production

%

µs

Doc ID 023337 Rev 1 77/103

Electrical parameters STM8L052R8

13.0

13.5

14.0

14.5

15.0

15.5

16.0

16.5

17.0

17.5

18.0

1.8 1.95 2.1 2.25 2.4 2.55 2.7 2.85 3 3.15 3.3 3.45 3.6

V

DD

[V]

HSI

frequency

[MHz]

-40°C
25°C
85°C

ai18218V3

Figure 18. Typical HSI frequency vs. V

DD

Low speed internal RC oscillator (LSI)

In the following table, data are based on characterization results, not tested in production.

Table 31. LSI oscillator characteristics

Symbol

Parameter

Conditions

(1)

Min. Typ. Max. Unit

f

t

su(LSI)

D

1. VDD = 1.8 V to 3.6 V, TA = -40 to 85 °C unless otherwise specified.

2. Guaranteed by Design, not tested in production.

3. This is a deviation for an individual part, once the initial frequency has been measured.

78/103 Doc ID 023337 Rev 1

Frequency 26 38 56 kHz

LSI

LSI oscillator wakeup time 200

LSI oscillator frequency
drift

(3)

(LSI)

(2)

µs

0 °C ≤ TA ≤ 85 °C -12 11 %

STM8L052R8 Electrical parameters

Figure 19. Typical LSI clock source frequency vs. V

0.04

0.038

0.036

0.034

RC32K Check (MHz)

0.032

0.03

1.8 2 2.2 2.4 2. 6 2.8 3 3. 2 3.4 3. 6

8.3.5 Memory characteristics

TA = -40 to 85 °C unless otherwise specified.

Table 32. RAM and hardware registers

DD

25°C

85°C

-40°C

VDD(V)

MS19116V2

Symbol Parameter Conditions Min. Typ. Max. Unit

V

RM

1. Minimum supply voltage without losing data stored in RAM (in Halt mode or under Reset) or in hardware
registers (only in Halt mode). Guaranteed by characterization, not tested in production.

Data retention mode

(1)

Halt mode (or Reset) 1.8 V

Doc ID 023337 Rev 1 79/103

Electrical parameters STM8L052R8

Flash memory

Table 33. Flash program and data EEPROM memory

Symbol Parameter Conditions Min. Typ.

V

Operating voltage

DD

(all modes, read/write/erase)

f

SYSCLK

= 16 MHz 1.8 3.6 V

Programming time for 1 or 128 bytes (block)
erase/write cycles (on programmed byte)

t

prog

Programming time for 1 to 128 bytes (block)
write cycles (on erased byte)

T

=+25 °C, VDD = 3.0 V

I

Programming/ erasing consumption

prog

Data retention (program memory) after 100
erase/write cycles at TA=−40 to +85 °C

(2)

t

RET

Data retention (data memory) after 100000
erase/write cycles at T

=−40 to +85 °C

A

Erase/write cycles (program memory)

(3)

N

RW

1. Data based on characterization results, not tested in production.

2. Conforming to JEDEC JESD22a117

3. The physical granularity of the memory is 4 bytes, so cycling is performed on 4 bytes even when a write/erase operation

4. Data based on characterization performed on the whole data memory.

Erase/write cycles (data memory)

addresses a single byte.

A

=+25 °C, VDD = 1.8 V

T

A

T

=+85 °C 30

RET

T

=+85 °C 30

RET

T

=−40 to +85 °C

A

100

100

(1)

(1)

(1)

(1)

(4)

Max.

(1)

6ms

3ms

0.7 mA

years

cycles

kcycles

Unit

80/103 Doc ID 023337 Rev 1

STM8L052R8 Electrical parameters

8.3.6 I/O current injection characteristics

As a general rule, current injection to the I/O pins, due to external voltage below VSS or
above V
in order to give an indication of the robustness of the microcontroller in cases when
abnormal injection accidentally happens, susceptibility tests are performed on a sample
basis during device characterization.

Functional susceptibility to I/O current injection

While a simple application is executed on the device, the device is stressed by injecting
current into the I/O pins programmed in floating input mode. While current is injected into the
I/O pin, one at a time, the device is checked for functional failures.

The failure is indicated by an out of range parameter: ADC error, out of spec current
injection on adjacent pins or other functional failure (for example reset, oscillator frequency
deviation, LCD levels, etc.).

The test results are given in the following table.

Table 34.

Symbol Description

(for standard pins) should be avoided during normal product operation. However,

DD

I/O current injection susceptibility

Functional susceptibility

Negative
injection

Positive

injection

Unit

Injected current on true open-drain pins -5 +0

I

INJ

Injected current on any other pin -5 +5

8.3.7 I/O port pin characteristics

General characteristics

Subject to general operating conditions for VDD and TA unless otherwise specified. All
unused pins must be kept at a fixed voltage: using the output mode of the I/O for example or
an external pull-up or pull-down resistor.

mAInjected current on all 5 V tolerant (FT) pins -5 +0

Doc ID 023337 Rev 1 81/103

Electrical parameters STM8L052R8

Table 35. I/O static characteristics

Symbol

V

IL

V

IH

V

hys

Parameter

Input low level voltage

Input high level voltage

(2)

(2)

Schmitt trigger voltage hysteresis

Conditions

(1)

Min.

Input voltage on true
open-drain pins (PC0

Vss-0.3

and PC1)

volt tolerant (FT) pins

Input voltage on any
other pin

Vss-0.3

Vss-0.3

Input voltage on true
open-drain pins (PC0
and PC1)

DD

< 2 V

0.70 x V

DD

with V

Input voltage on true
open-drain pins (PC0
and PC1)

DD

≥ 2 V

with V

Input voltage on five­volt tolerant (FT) pins
with V

Input voltage on five-

DD

< 2 V

0.70 x V

DD

volt tolerant (FT) pins

DD

≥ 2 V

0.70 x V

DD

with V

Input voltage on any
other pin

Standard I/Os 200

(3)

True open drain I/Os 200

Typ .

0.3 x V

0.3 x V

0.3 x V

VDD+0.3

Max. Unit

DD

VInput voltage on five-

DD

DD

5.2

5.5

V

5.2

5.5

mV

V

≤ VIN≤ V

SS

Standard I/Os

≤ VIN≤ V

V

I

Input leakage current

lkg

(4)

SS

True open drain I/Os

V

≤ VIN≤ V

SS

PA0 with high sink LED

DD

DD

DD

--50

- - 200

- - 200

driver capability

R

C

1. VDD = 3.0 V, TA = -40 to 85 °C unless otherwise specified.

2. Data based on characterization results, not tested in production.

3. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested.

4. The max. value may be exceeded if negative current is injected on adjacent pins.

5. Not tested in production.

6. R

Figure 23).

Weak pull-up equivalent resistor

PU

I/O pin capacitance 5 pF

IO

pull-up equivalent resistor based on a resistive transistor (corresponding I

PU

(2)(6)

V

IN=VSS

30 45 60 kΩ

current characteristics described in

PU

82/103 Doc ID 023337 Rev 1

(5)

(5)

nA

(5)

STM8L052R8 Electrical parameters

0

0.5

1

1.5

2

2.5

3

1.8 2.1 2.6 3.1 3.6

V

DD

[V]

V

IL

and V

IH

[V]

-40°C
25°C
85°C

ai18220V3

0

0.5

1

1.5

2

2.5

3

1.8 2.1 2.6 3.1 3.6

V

DD

[V]

V

IL

and V

IH

[V]

-40°C
25°C
85°C

ai18221V2

30

35

40

45

50

55

60

1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6

V

DD

[V]

Pull-Up resistance [k

Ω

]

-40°C
25°C
85°C

ai18222V2

Figure 20. Typical VIL and V

Figure 21. Typical V

and V

IL

vs. VDD (standard I/Os)

IH

vs. VDD (true open drain I/Os)

IH

Figure 22. Typical pull-up resistance R

vs. VDD with VIN=V

PU

SS

Doc ID 023337 Rev 1 83/103

Electrical parameters STM8L052R8

0

20

40

60

80

100

120

1.8 1.95 2.1 2.25 2.4 2.55 2.7 2.85 3 3.15 3.3 3.45 3.6
V

DD

[V]

Pull-Up current [μA]

-40°C
25°C
85°C

ai18223V2

Figure 23. Typical pull-up current Ipu vs. VDD with VIN=V

Output driving current

Subject to general operating conditions for V

Table 36. Output driving current (high sink ports)

and TA unless otherwise specified.

DD

SS

I/O

Symbol Parameter Conditions Min. Max. Unit

Type

= +2 mA,

I

IO

V

= 3.0 V

DD

I

= +2 mA,

(1)

V

OL

Output low level voltage for an I/O pin

Standard

(2)

V

OH

1. The IIO current sunk must always respect the absolute maximum rating specified in Table 13 and the sum
of IIO (I/O ports and control pins) must not exceed I

2. The IIO current sourced must always respect the absolute maximum rating specified in Table 13 and the
sum of IIO (I/O ports and control pins) must not exceed I

Output high level voltage for an I/O pin

.

VSS

VDD

IO

= 1.8 V

V

DD

I

= +10 mA,

IO

= 3.0 V

V

DD

= -2 mA,

I

IO

= 3.0 V

V

DD

I

= -1 mA,

IO

= 1.8 V

V

DD

I

= -10 mA,

IO

= 3.0 V

V

DD

.

V

-0.45

DD

-0.45

V

DD

V

DD

0.45 V

0.45 V

0.7 V

-0.7 V

V

V

84/103 Doc ID 023337 Rev 1

STM8L052R8 Electrical parameters

0

0.25

0.5

0.75

1

02468101214161820

I

OL

[mA]

V

OL

[V]

-40°C

25°C

85°C

ai18226V2

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0123 45678

I

OL

[mA]

V

OL

[V]

-40°C

25°C

85°C

ai18227V2

ai18228V2

0

0.1

0.2

0.3

0.4

0.5

01234567

I

OL

[mA]

V

OL

[V]

-40°C

25°C

85°C

0

0.1

0.2

0.3

0.4

0.5

01234567

I

OL

[mA]

V

OL

[V]

-40°C

25°C

85°C

BJ7

Table 37. Output driving current (true open drain ports)

I/O

Symbol Parameter Conditions Min. Max. Unit

Type

= +3 mA,

I

IO

= 3.0 V

V

(1)

V

OL

Output low level voltage for an I/O pin

Open drain

1. The IIO current sunk must always respect the absolute maximum rating specified in Table 13 and the sum
of IIO (I/O ports and control pins) must not exceed I

VSS

.

DD

= +1 mA,

I

IO

V

DD

= 1.8 V

0.45

V

0.45

Table 38. Output driving current (PA0 with high sink LED driver capability)

I/O

Symbol Parameter Conditions Min. Max. Unit

Type

= +20 mA,

I

(1)

V

IR

OL

1. The IIO current sunk must always respect the absolute maximum rating specified in Table 13 and the sum
of IIO (I/O ports and control pins) must not exceed I

Output low level voltage for an I/O pin

.

VSS

V

IO

DD

= 2.0 V

0.45 V

Figure 24. Typical VOL @ VDD = 3.0 V (high

sink ports)

Figure 26. Typical VOL @ VDD = 3.0 V (true

open drain ports)

Figure 25. Typical VOL @ VDD = 1.8 V (high

sink ports)

Figure 27. Typical VOL @ VDD = 1.8 V (true

open drain ports)

Doc ID 023337 Rev 1 85/103

Electrical parameters STM8L052R8

0

0.25

0.5

0.75

1

1.25

1.5

1.75

2

0 2 4 6 8 101214161820

I

OH

[mA]

V

DD

- V

OH

[V]

-40°C

25°C

85°C

ai12830V2

0

0.1

0.2

0.3

0.4

0.5

012345 67

I

OH

[mA]

V

DD

- V

OH

[V]

-40°C

25°C

85°C

BJ7

Figure 28. Typical V

DD - VOH

(high sink ports)

@ VDD = 3.0 V

Figure 29. Typical V

(high sink ports)

NRST pin

Subject to general operating conditions for VDD and TA unless otherwise specified.

Table 39. NRST pin characteristics

Symbol Parameter Conditions Min.

V

IL(NRST)

V

IH(NRST)

V

OL(NRST)

V

HYST

NRST input low level voltage

NRST input high level voltage

NRST output low level voltage

NRST input hysteresis

(3)

(1)

(1)

(1)

IOL = 2 mA
for 2.7 V ≤ V
V

I

= 1.5 mA

OL

DD

< 2.7 V

for V

DD

≤ 3.6

V

SS

1.4

10%V

(2)

DD - VOH

Typ .

DD

@ VDD = 1.8 V

Max. Unit

0.8

V

DD

0.4

V

mV

R

PU(NRST)

V

F(NRST)

V

NF(NRST)

NRST pull-up equivalent

(1)

resistor

NRST input filtered pulse

NRST input not filtered pulse

1. Data based on characterization results, not tested in production.

2. 200 mV min.

3. Data guaranteed by design, not tested in production.

86/103 Doc ID 023337 Rev 1

(3)

(3)

30 45 60 kΩ

50

ns

300

STM8L052R8 Electrical parameters

30

35

40

45

50

55

60

1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6
V

DD

[V]

Pull-up

resistance

[k

Ω

]

-40°C
25°C
85°C

ai18224V2

ai18225V2

0

20

40

60

80

100

120

1.8 1.95 2.1 2.25 2.4 2.55 2.7 2.85 3 3.15 3.3 3.45 3.6

V

DD

[V]

Pull-U

p current [ μA]

-40°C

25°C

85

°C

Figure 30. Typical NRST pull-up resistance RPU vs. VDD

Figure 31. Typical NRST pull-up current I

vs. VDD

pu

The reset network shown in Figure 32 protects the device against parasitic resets. The user
must ensure that the level on the NRST pin can go below the V

max. level specified in

IL

Ta bl e 3 9 . Otherwise the reset is not taken into account internally. For power consumption-

sensitive applications, the capacity of the external reset capacitor can be reduced to limit the
charge/discharge current. If the NRST signal is used to reset the external circuitry, the user
must pay attention to the charge/discharge time of the external capacitor to meet the reset
timing conditions of the external devices. The minimum recommended capacity is 10 nF.

Doc ID 023337 Rev 1 87/103

Electrical parameters STM8L052R8

EXTERNAL

RESET

CIRCUIT

STM8L

Filter

R

PU

V

DD

INTERNAL RESET

RSTIN

0.1 µF

Figure 32. Recommended NRST pin configuration

88/103 Doc ID 023337 Rev 1

STM8L052R8 Electrical parameters

8.3.8 Communication interfaces

SPI1 - Serial peripheral interface

Unless otherwise specified, the parameters given in Ta b le 4 0 are derived from tests
performed under ambient temperature, f
conditions summarized in Section 8.3.1. Refer to I/O port characteristics for more details on
the input/output alternate function characteristics (NSS, SCK, MOSI, MISO).

Table 40. SPI1 characteristics

Symbol Parameter Conditions

SYSCLK

frequency and VDD supply voltage

(1)

Min. Max. Unit

f

SCK

1/t

c(SCK)

t

r(SCK)

t

f(SCK)

t

su(NSS)

t

h(NSS)

t

w(SCKH)

t

w(SCKL)

t

su(MI)

t

su(SI)

t

h(MI)

t

h(SI)

t

a(SO)

t

dis(SO)

t

v(SO)

t

v(MO)

t

h(SO)

t

h(MO)

SPI1 clock frequency

Master mode 0 8

Slave mode 0 8

SPI1 clock rise and fall
time

(2)

NSS setup time Slave mode 4 x 1/f

(2)

NSS hold time Slave mode 80 -

(2)

SCK high and low time

(2)

(2)

Data input setup time

(2)

(2)

Data input hold time

(2)

(2)(3)

Data output access time Slave mode - 3x 1/f

(2)(4)

Data output disable time Slave mode 30 -

(2)

Data output valid time Slave mode (after enable edge) - 60

(2)

Data output valid time

(2)

Data output hold time

(2)

Capacitive load: C = 30 pF - 30 ns

Master mode,

MASTER

= 8 MHz, f

f

SCK

= 4 MHz

105 145

Master mode 30 -

Slave mode 3 -

Master mode 15 -

Slave mode 0 -

Master mode (after enable
edge)

Slave mode (after enable edge) 15 -

Master mode (after enable
edge)

MHz

SYSCLK

-

SYSCLK

-20

1-

1. Parameters are given by selecting 10 MHz I/O output frequency.

2. Values based on design simulation and/or characterization results, and not tested in production.

3. Min. time is for the minimum time to drive the output and max. time is for the maximum time to validate the data.

4. Min. time is for the minimum time to invalidate the output and max. time is for the maximum time to put the data in Hi-Z.

Doc ID 023337 Rev 1 89/103

Electrical parameters STM8L052R8

ai14134

SCK Input

CPHA=0

MOSI

INPUT

MISO

OUT PUT

CPHA=0

MS B O U T

MSB IN

BI T6 O UT

LSB IN

LSB OUT

CPOL=0

CPOL=1

BIT1 IN

NSS input

t

SU(NSS)

t

c(SCK)

t

h(NSS)

t

a(SO)

t

w(SCKH)

t

w(SCKL)

t

v(SO)

t

h(SO)

t

r(SCK)

t

f(SCK)

t

dis(SO)

t

su(SI)

t

h(SI)

ai14135

SCK Input

CPHA=1

MOSI

INPUT

MISO

OUT PUT

CPHA=1

MS B O U T

MSB IN

BI T6 O UT

LSB IN

LSB OUT

CPOL=0

CPOL=1

BIT1 IN

t

SU(NSS)

t

c(SCK)

t

h(NSS)

t

a(SO)

t

w(SCKH)

t

w(SCKL)

t

v(SO)

t

h(SO)

t

r(SCK)

t

f(SCK)

t

dis(SO)

t

su(SI)

t

h(SI)

NSS input

Figure 33. SPI1 timing diagram - slave mode and CPHA=0

Figure 34. SPI1 timing diagram - slave mode and CPHA=1

1. Measurement points are done at CMOS levels: 0.3V

and 0.7V

DD

DD

.

(1)

90/103 Doc ID 023337 Rev 1

STM8L052R8 Electrical parameters

ai14136

SCK Input

CPHA=0

MOSI

OUTUT

MISO

INP UT

CPHA=0

MSBIN

M SB OUT

BIT6 IN

LSB OUT

LSB IN

CPOL=0

CPOL=1

B I T1 OUT

NSS input

t

c(SCK)

t

w(SCKH)

t

w(SCKL)

t

r(SCK)

t

f(SCK)

t

h(MI)

High

SCK Input

CPHA=1

CPHA=1

CPOL=0

CPOL=1

t

su(MI)

t

v(MO)

t

h(MO)

Figure 35. SPI1 timing diagram - master mode

1. Measurement points are done at CMOS levels: 0.3V

and 0.7V

DD

(1)

DD

.

Doc ID 023337 Rev 1 91/103

Electrical parameters STM8L052R8

I2C - Inter IC control interface

Subject to general operating conditions for V

The STM8L I

2

C interface (I2C1) meets the requirements of the Standard I2C communication

DD

, f

SYSCLK

, and TA unless otherwise specified.

protocol described in the following table with the restriction mentioned below:

Refer to I/O port characteristics for more details on the input/output alternate function
characteristics (SDA and SCL).

Table 41. I2C characteristics

Max.

(1)

(2)

Symbol Parameter

t

w(SCLL)

t

w(SCLH)

t

su(SDA)

t

h(SDA)

t

r(SDA)

t

r(SCL)

t

f(SDA)

t

f(SCL)

t

h(STA)

t

su(STA)

t

su(STO)

t

w(STO:STA)

C

1. f

SYSCLK

Data based on standard I

2.

SCL clock low time 4.7 1.3

SCL clock high time 4.0 0.6

SDA setup time 250 100

SDA data hold time 0 0 900

SDA and SCL rise time 1000 300

SDA and SCL fall time 300 300

START condition hold time 4.0 0.6

Repeated START condition setup
time

STOP condition setup time 4.0 0.6 μs

STOP to START condition time (bus
free)

Capacitive load for each bus line 400 400 pF

b

must be at least equal to 8 MHz to achieve max fast I2C speed (400 kHz).

2

C protocol requirement, not tested in production.

Standard mode I2CFast mode I2C

Min.

(2)

Max.

(2)

Min.

(2)

4.7 0.6

4.7 1.3 μs

Unit

μs

ns

μs

Note: For speeds around 200 kHz, the achieved speed can have a ± 5% tolerance.

For other speed ranges, the achieved speed can have a

±

2% tolerance.

The above variations depend on the accuracy of the external components used.

92/103 Doc ID 023337 Rev 1

STM8L052R8 Electrical parameters

REPEATED START

START

STOP

START

t

f(SDA)

t

r(SDA)

t

su(SDA)th(SDA)

t

f(SCL)

t

r(SCL)

t

w(SCLL)

t

w(SCLH)

t

h(STA)

t

su(STO)

t

su(STA)tw(STO:STA)

SDA

SCL

4.7kΩ
SDA

STM8L

SCL

V

DD

100Ω

100Ω

V

DD

4.7kΩ

I2CBUS

2

Figure 36.

Typical application with I

C bus and timing diagram

1. Measurement points are done at CMOS levels: 0.3 x VDD and 0.7 x V

1)

DD

Doc ID 023337 Rev 1 93/103

Electrical parameters STM8L052R8

8.3.9 LCD controller

In the following table, data are guaranteed by Design, not tested in production.

Table 42. LCD characteristics

Symbol Parameter Min. Typ. Max. Unit

V

LCD

V

LCD0

V

LCD1

V

LCD2

V

LCD3

V

LCD4

V

LCD5

V

LCD6

V

LCD7

C

EXT

I

DD

(2)

R

HN

(3)

R

LN

V

33

V

34

V

23

V

12

V

13

V

14

V

0

1. LCD enabled with 3 V internal booster (LCD_CR1 = 0x08), 1/4 duty, 1/3 bias, division ratio= 64, all pixels
active, no LCD connected.

2. RHN is the total high value resistive network.

3. RLN is the total low value resistive network.

High value resistive network (low drive) 6.6 MΩ

Low value resistive network (high drive) 240 kΩ

Segment/Common higher level voltage V

Segment/Common 3/4 level voltage 3/4V

Segment/Common 2/3 level voltage 2/3V

Segment/Common 1/2 level voltage 1/2V

Segment/Common lowest level voltage 0

LCD external voltage 3.6

LCD internal reference voltage 0 2.6

LCD internal reference voltage 1 2.7

LCD internal reference voltage 2 2.8

LCD internal reference voltage 3 3.0

LCD internal reference voltage 4 3.1

LCD internal reference voltage 5 3.2

LCD internal reference voltage 6 3.4

LCD internal reference voltage 7 3.5

V

external capacitance 0.1 1 2 µF

LCD

Supply current

Supply current

(1)

at VDD = 1.8 V

(1)

at VDD = 3 V 3

Segment/Common 1/3 level voltage 1/3V

Segment/Common 1/4 level voltage 1/4V

3

LCDx

LCDx

LCDx

LCDx

LCDx

LCDx

V

µA

V

VLCD external capacitor

The application can achieve a stabilized LCD reference voltage by connecting an external
capacitor C

94/103 Doc ID 023337 Rev 1

EXT

to the V

LCD

pin. C

is specified in Ta bl e 4 2.

EXT

STM8L052R8 Electrical parameters

8.3.10 Embedded reference voltage

In the following table, data are based on characterization results, not tested in production,
unless otherwise specified.

Table 43. Reference voltage characteristics

Symbol Parameter Conditions Min. Typ. Max. Unit

I

REFINT

T

S_VREFINT

I

BUF

V

REFINT out

I

LPBUF

(1)(2)

(1)

(1)

Internal reference voltage

consumption

ADC sampling time when reading the

internal reference voltage

Internal reference voltage buffer

consumption (used for ADC)

Reference voltage output

Internal reference voltage low power

buffer consumption (used for

comparators or output)

REFOUT

C

REFOUT

t

VREFINT

t

BUFEN

(1)(4)

(1)

(1)(2)

I

Stability of V

STAB

VREFINT

STAB

VREFINT

1. Guaranteed by design, not tested in production

2. Defined when ADC output reaches its final value ±1/2LSB

3. Tested in production at V

4. To guarantee less than 1%

Stability of V

Stability of V

Buffer output current 1 µA

Reference voltage output load 50 pF

Internal reference voltage startup

time

Internal reference voltage buffer

startup time once enabled

over temperature -40 °C ≤ TA ≤ 85 °C 20 50 ppm/°C

REFINT

over temperature 0 °C ≤ TA ≤ 50 °C 20 ppm/°C

REFINT

after 1000 hours TBD ppm

REFINT

= 3 V ±10 mV.

DD

V

REFOUT

deviation

1.202

(3)

1.4 µA

510 µs

13.5 25 µA

1.242

1.224

(3)

V

730 1200 nA

23 ms

10 µs

Doc ID 023337 Rev 1 95/103

Electrical parameters STM8L052R8

8.3.11 12-bit ADC1 characteristics

In the following table, data are guaranteed by design, not tested in production.

Table 44. ADC1 characteristics

Symbol Parameter Conditions Min. Typ. Max. Unit

V

DDA

V

REF+

V

REF-

I

VDDA

I

VREF+

V

AIN

T

R

AIN

C

ADC

Analog supply voltage 1.8 3.6 V

Reference supply
voltage

Lower reference voltage

Current on the VDDA
input pin

2.4 V ≤ V

1.8 V≤ V

≤ 3.6 V

DDA

≤ 2.4 V V

DDA

2.4

V

DDA

DDA

V

SSA

1000 1450 µA

700

Current on the VREF+
input pin

400

(peak)

450

(average)

Conversion voltage
range

Temperature range -40 85 °C

A

(2)

0

V

REF+

on PF0/1/2/3 fast

External resistance on
V

AIN

channels

on all other channels

50

on PF0/1/2/3 fast

Internal sample and
hold capacitor

channels

16 pF

on all other channels

(3)

(1)

(1)

V

V

V

µA

µA

kΩ

≤ 3.6 V

DDA

≤ 2.4 V

DDA

channels

on all other

0.320 16 MHz

0.320 8 MHz

f

ADC

f

CONV

ADC sampling clock
frequency

12-bit conversion rate

2.4 V≤ V
without zooming

1.8 V≤ V

with zooming

V

on PF0/1/2/3 fast

AIN

V

AIN

channels

f

TRIG

t

LAT

External trigger
frequency

External trigger latency 3.5 1/f

96/103 Doc ID 023337 Rev 1

1

760

(3)(4)

(3)(4)

t

conv

MHz

kHz

1/f

ADC

SYSCLK

STM8L052R8 Electrical parameters

Table 44. ADC1 characteristics (continued)

Symbol Parameter Conditions Min. Typ. Max. Unit

V

PF0/1/2/3 fast

t

S

t

conv

t

WKUP

t

IDLE

t

VREFINT

Sampling time

12-bit conversion time

Wakeup time from OFF
state

Time before a new

(5)

conversion

Internal reference
voltage startup time

AIN

channels

< 2.4 V

V

DDA

PF0/1/2/3 fast

V

AIN

channels

DDA

≤ 3.6 V

DDA

< 2.4 V

≤ 3.6 V

DDA

2.4 V ≤ V

on slow channels

V

AIN

V

V

on slow channels

AIN

2.4 V ≤ V

16 MHz 1

0.43

0.22

0.86

0.41

(3)(4)

(3)(4)

(3)(4)

(3)(4)

12 + t

(3)

S

µs

µs

µs

µs

1/f

ADC

µs

3µs

∞ s

refer to

Ta bl e 4 3

ms

1. The current consumption through V

- one constant (max 300 µA)

- one variable (max 400 µA), only during sampling time + 2 first conversion pulses.
So, peak consumption is 300+400 = 700 µA and average consumption is 300 + [(4 sampling + 2) /16] x 400 = 450 µA at
1Msps

2. V

3. Minimum sampling and conversion time is reached for maximum R

4. Value obtained for continuous conversion on fast channel.

5. The time between 2 conversions, or between ADC ON and the first conversion must be lower than t

must be tied to ground.

REF-

is composed of two parameters:

REF

= 0.5 kΩ..

AIN

IDLE.

Doc ID 023337 Rev 1 97/103

Electrical parameters STM8L052R8

In the following three tables, data are guaranteed by characterization result, not tested in
production.

Table 45. ADC1 accuracy with V

Symbol Parameter Conditions Typ. Max. Unit

DNL Differential non linearity

INL Integral non linearity

TUE Total unadjusted error

Offset Offset error

Gain Gain error

= 3.3 V to 2.5 V

DDA

= 16 MHz 1 1.6

f

ADC

f

= 8 MHz 1 1.6

ADC

= 4 MHz 1 1.5

f

ADC

= 16 MHz 1.2 2

f

ADC

f

= 8 MHz 1.2 1.8

ADC

= 4 MHz 1.2 1.7

f

ADC

= 16 MHz 2.2 3.0

f

ADC

f

= 8 MHz 1.8 2.5

ADC

= 4 MHz 1.8 2.3

f

ADC

f

= 16 MHz 1.5 2

ADC

= 8 MHz 1 1.5

f

ADC

= 4 MHz 0.7 1.2

f

ADC

f

= 16 MHz

ADC

= 8 MHz

ADC

= 4 MHz

f

ADC

LSB

LSB

11.5f

Table 46. ADC1 accuracy with V

Symbol Parameter Typ. Max. Unit

DNL Differential non linearity 1 2 LSB

INL Integral non linearity 1.7 3 LSB

TUE Total unadjusted error 2 4 LSB

Offset Offset error 1 2 LSB

Gain Gain error 1.5 3 LSB

Table 47. ADC1 accuracy with V

Symbol Parameter Typ. Max. Unit

DNL Differential non linearity 1 2 LSB

INL Integral non linearity 2 3 LSB

TUE Total unadjusted error 3 5 LSB

Offset Offset error 2 3 LSB

Gain Gain error 2 3 LSB

= 2.4 V to 3.6 V

DDA

= V

DDA

REF+

= 1.8 V to 2.4 V

98/103 Doc ID 023337 Rev 1

STM8L052R8 Electrical parameters

E

O

E

G

1LSB

IDEAL

(1) Example of an actual transfer curve
(2) The ideal transfer curve
(3) End point correlation line

E

T

=Total Unadjusted Error: maximum deviation

between the actual and the ideal transfer curves.

E

O

=Offset Error: deviation between the first actual

transition and the first ideal one.

E

G

=Gain Error: deviation between the last ideal

transition and the last actual one.

E

D

=Differential Linearity Error: maximum deviation

between actual steps and the ideal one.

E

L

=Integral Linearity Error: maximum deviation
between any actual transition and the end point
correlation line.

4095

4094

4093

5

4

3

2

1

0

7

6

1234567

4093 4094 4095 4096

(1)

(2)

E

T

E

D

E

L

(3)

V

DDA

V

SSA

ai14395b

V

REF+

4096

(or depending on package)]

V

DDA

4096

[1LSB

IDEAL =

ai17090e

STM8L05xxx

V

DD

AINx

IL±50 nA

0.6 V

V

T

R

AIN

(1)

C

parasitic

V

AIN

0.6 V

V

T

R

ADC

C

ADC

(1)

12-bit

converter

Sample and hold ADC
converter

Figure 37. ADC1 accuracy characteristics

Figure 38. Typical connection diagram using the ADC

1. Refer to Ta b le 4 4 for the values of R

2. C

represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the

parasitic

pad capacitance (roughly 7 pF). A high C
this, f

should be reduced.

ADC

AIN

and C

parasitic

.

ADC

value will downgrade conversion accuracy. To remedy

General PCB design guidelines

Power supply decoupling should be performed as shown in Figure 39 or Figure 40,
depending on whether V

is connected to V

REF+

or not. Good quality ceramic 10 nF

DDA

capacitors should be used. They should be placed as close as possible to the chip.

Doc ID 023337 Rev 1 99/103

Electrical parameters STM8L052R8

V

REF+

S

STM8L

V

DDA

V

SSA/VREF-

1 μF // 10 nF

F

1 μF // 10 nF

Supply

External

reference

ai17031b

V

REF+/VDDA

STM8L

1 μF // 10 nF

V

REF–/VSSA

ai17032b

Supply

Figure 39. Power supply and reference decoupling (V

// 10 n

Figure 40. Power supply and reference decoupling (V

not connected to V

REF+

TM8L

connected to V

REF+

DDA

DDA

)

)

100/103 Doc ID 023337 Rev 1