ST STM8L052R8 User Manual

STM8L052R8

Value Line, 8-bit ultralow power MCU, 64-KB Flash, 256-byte data EEPROM, RTC, LCD, timers, USART, I2C, SPI, ADC

Datasheet − production data

Features

■Operating conditions

–Operating power supply: 1.8 V to 3.6 V

–Temperature range: -40 °C to 85 °C

■Low power features

–5 low power modes: Wait, Low power run (5.9 µA), Low power wait (3 µA), Active-halt with full RTC (1.4 µA), Halt (400 nA)

–Dynamic power consumption: 200 µA/MHz + 330 µA

–Ultra-low leakage per I/0: 50 nA

–Fast wakeup from Halt: 4.7 µs

■Advanced STM8 core

–Harvard architecture and 3-stage pipeline

–Max freq. 16 MHz, 16 CISC MIPS peak

–Up to 40 external interrupt sources

■Reset and supply management

–Low power, ultra-safe BOR reset with 5 programmable thresholds

–Ultra low power POR/PDR

–Programmable voltage detector (PVD)

■Clock management

–32 kHz and 1 to 16 MHz crystal oscillators

–Internal 16 MHz factory-trimmed RC

–38 kHz low consumption RC

–Clock security system

■Low power RTC

–BCD calendar with alarm interrupt

–Digital calibration with +/- 0.5ppm accuracy

–Advanced anti-tamper detection

■LCD: 8x24 or 4x28 w/ step-up converter

■Memories

–64 KB Flash program memory and

256 bytes data EEPROM with ECC, RWW

–Flexible write and read protection modes

–4 KB of RAM

LQFP64

■DMA

–4 channels supporting ADC, SPIs, I2C, USARTs, timers

–1 channel for memory-to-memory

■12-bit ADC up to 1 Msps/28 channels

–Internal reference voltage

■Timers

–Three 16-bit timers with 2 channels (used as IC, OC, PWM), quadrature encoder

–One 16-bit advanced control timer with 3 channels, supporting motor control

–One 8-bit timer with 7-bit prescaler

–2 watchdogs: 1 Window, 1 Independent

–Beeper timer with 1, 2 or 4 kHz frequencies

■Communication interfaces

–Two synchronous serial interfaces (SPI)

–Fast I2C 400 kHz SMBus and PMBus

–Three USARTs (ISO 7816 interface + IrDA)

■Up to 54 I/Os, all mappable on interrupt vectors

■Development support

–Fast on-chip programming and nonintrusive debugging with SWIM

–Bootloader using USART

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This is information on a product in full production.

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Contents	STM8L052R8

Contents

1	Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. 8
2	Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. 9
	2.1	Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	10
	2.2	Ultra low power continuum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	11
3	Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		12

3.1 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.2 Central processing unit STM8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.2.1 Advanced STM8 Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.2.2 Interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.3	Reset and supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		15
	3.3.1	Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	15
	3.3.2	Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	15
	3.3.3	Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	15
3.4	Clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		16
3.5	Low power real-time clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		17
3.6	LCD (Liquid crystal display) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		18
3.7	Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		18
3.8	DMA . .	. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	18
3.9	Analog-to-digital converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		19
3.10	System configuration controller and routing interface . . . . . . . . . . . . . . .		19
3.11	Timers .	. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	19
	3.11.1	TIM1 - 16-bit advanced control timer . . . . . . . . . . . . . . . . . . . . . . . . . . .	20
	3.11.2	16-bit general purpose timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	20
	3.11.3	8-bit basic timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	20
3.12	Watchdog timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		20

3.12.1 Window watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.12.2 Independent watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.13 Beeper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.14 Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.14.1 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.14.2 I²C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

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		3.14.3 USART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . 21
	3.15	Infrared (IR) interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . 22
	3.16	Development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . 22
4	Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. . . . 23

4.1 System configuration options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

5	Memory and register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			. 30
	5.1	Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		30
	5.2	Register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		31
6	Interrupt vector mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			50
7	Option bytes		. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	52
8	Electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			55
	8.1	Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		55
		8.1.1	Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 55
		8.1.2	Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 55
		8.1.3	Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 55
		8.1.4	Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 55
		8.1.5	Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 56
	8.2	Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		56
	8.3	Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		58
		8.3.1	General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 58
		8.3.2	Embedded reset and power control block characteristics . . . . . . . . . .	. 59
		8.3.3	Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 62
		8.3.4	Clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 74
		8.3.5	Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 79
		8.3.6	I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 81
		8.3.7	I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 81
		8.3.8	Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 89
		8.3.9	LCD controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 94
		8.3.10	Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 95
		8.3.11	12-bit ADC1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 96
		8.3.12	EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	101
	8.4	Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		103

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Contents		STM8L052R8
9	Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . 104
	9.1 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . 104
10	Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . 107
11	Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . 108

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STM8L052R8	List of tables

List of tables

Table 1. High density value line STM8L05xxx low power device features and

peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Table 2. Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 3. Legend/abbreviation for Table 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Table 4. High density value line STM8L05xxx pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Table 5. Flash and RAM boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 6. I/O port hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 7. General hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 8. CPU/SWIM/debug module/interrupt controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Table 9. Interrupt mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Table 10. Option byte addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Table 11. Option byte description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Table 12. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Table 13. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Table 14. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Table 15. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Table 16. Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 59 Table 17. Total current consumption in Run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Table 18. Total current consumption in Wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Table 19. Total current consumption and timing in Low power run mode at VDD = 1.8 V to

3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Table 20. Total current consumption in Low power wait mode at VDD = 1.8 V to 3.6 V . . . . . . . . . . 69 Table 21. Total current consumption and timing in Active-halt mode

at VDD = 1.8 V to 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Table 22. Typical current consumption in Active-halt mode, RTC clocked by LSE external crystal . . 71 Table 23. Total current consumption and timing in Halt mode at VDD = 1.8 to 3.6 V . . . . . . . . . . . . 72 Table 24. Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Table 25. Current consumption under external reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Table 26. HSE external clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Table 27. LSE external clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Table 28. HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Table 29. LSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Table 30. HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Table 31. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Table 32. RAM and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Table 33. Flash program and data EEPROM memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Table 34. I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Table 35. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Table 36. Output driving current (high sink ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Table 37. Output driving current (true open drain ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Table 38. Output driving current (PA0 with high sink LED driver capability). . . . . . . . . . . . . . . . . . . . 85 Table 39. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Table 40. SPI1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Table 41. I2C characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Table 42. LCD characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Table 43. Reference voltage characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Table 44. ADC1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Table 45. ADC1 accuracy with VDDA = 3.3 V to 2.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

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List of tables	STM8L052R8

Table 46. ADC1 accuracy with VDDA = 2.4 V to 3.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Table 47. ADC1 accuracy with VDDA = VREF+ = 1.8 V to 2.4 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Table 48. EMS data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

Table 49. EMI data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Table 50. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Table 51. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Table 52. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Table 53. LQFP64 – 10 x 10 mm, 64-pin low-profile quad flat package mechanical data . . . . . . . . 105 Table 54. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

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STM8L052R8	List of figures

List of figures

Figure 1.	High density value line STM8L05xxx device block diagram									. . . . . . . . . . . . . . . . . . . . .	. 12
Figure 2.	High density value line STM8L05xxx clock tree diagram								. . .	. . . . . . . . . . . . . . . . . . . . . .	17
Figure 3.	STM8L052R8 64-pin LQFP64 package pinout . . . .						. . .	.	. . .	. . . . . . . . . . . . . . . . . . . . . .	23
Figure 4.	Memory map . .		. . . . . . . . . . . . .		. .	. . . . . . . . . . . . .	. . .	.	. . .	. . . . . . . . . . . . . . . . . . . . . .	30
Figure 5.	Pin loading conditions . . . . . . . . .				. .	. . . . . . . . . . . . . .	. .	.	. . .	. . . . . . . . . . . . . . . . . . . . . .	55
Figure 6.	Pin input voltage . . . . . . . . . . . . .				. .	. . . . . . . . . . . . . .	. .	.	. . .	. . . . . . . . . . . . . . . . . . . . . .	56
Figure 7.	Power supply thresholds. . . . . . .				. .	. . . . . . . . . . . . . .	. .	.	. . .	. . . . . . . . . . . . . . . . . . . . . .	61
Figure 8.	Typical I		from RAM vs. V			(HSI clock source), f				=16 MHz 1) . . . . . . . . . . . . . . . .	. 64
		DD(RUN)		DD				CPU
Figure 9.	Typical I		from Flash vs. V			(HSI clock source), f				= 16 MHz 1) . . . . . . . . . . . . . . .	. 64
		DD(RUN)			DD				CPU
Figure 10.	Typical IDD(Wait) from RAM vs. VDD (HSI clock source), fCPU = 16 MHz 1) . . . . . . . . . . . . .										66
Figure 11.	Typical I		from Flash (HSI clock source), f				= 16 MHz 1) . . . . . . . . . . . . . . . . . . .				66
		DD(Wait)				CPU
Figure 12.	Typical IDD(LPR) vs. VDD (LSI clock source), all peripherals OFF . . . . . . . . . . . . . . . . . . . .										68
Figure 13.	Typical IDD(LPW) vs. VDD (LSI clock source), all peripherals OFF (1) . . . . . . . . . . . . . . . . .										69
Figure 14.	Typical IDD(AH) vs. VDD (LSI clock source) . . . . . . .						. .	.	. . .	. . . . . . . . . . . . . . . . . . . . . .	71
Figure 15.	Typical IDD(Halt) vs. VDD (internal reference voltage OFF) . .									. . . . . . . . . . . . . . . . . . . . . .	72
Figure 16.	HSE oscillator circuit diagram . . .				. .	. . . . . . . . . . . . . .	. .	.	. . .	. . . . . . . . . . . . . . . . . . . . . .	76
Figure 17.	LSE oscillator circuit diagram . . .				. .	. . . . . . . . . . . . . .	. .	.	. . .	. . . . . . . . . . . . . . . . . . . . . .	77
Figure 18.	Typical HSI frequency vs. VDD . .				. .	. . . . . . . . . . . . . .	. .	.	. . .	. . . . . . . . . . . . . . . . . . . . . .	78
Figure 19.	Typical LSI clock source frequency vs. VDD . . . . . . .						. .	.	. . .	. . . . . . . . . . . . . . . . . . . . . .	79
Figure 20.	Typical VIL and VIH vs. VDD (standard I/Os) . . . . . . .						. .	.	. . .	. . . . . . . . . . . . . . . . . . . . . .	83
Figure 21.	Typical VIL and VIH vs. VDD (true open drain I/Os). .						. .	.	. . .	. . . . . . . . . . . . . . . . . . . . . .	83
Figure 22.	Typical pull-up resistance RPU vs. VDD with VIN=VSS. .							.	. . .	. . . . . . . . . . . . . . . . . . . . . .	83
Figure 23.	Typical pull-up current Ipu vs. VDD with VIN=VSS . . .						. .	.	. . .	. . . . . . . . . . . . . . . . . . . . . .	84
Figure 24.	Typical VOL @ VDD = 3.0 V (high sink ports) . . . . . .						. .	.	. . .	. . . . . . . . . . . . . . . . . . . . . .	85
Figure 25.	Typical VOL @ VDD = 1.8 V (high sink ports) . . . . . .						. .	.	. . .	. . . . . . . . . . . . . . . . . . . . . .	85
Figure 26.	Typical VOL @ VDD = 3.0 V (true open drain ports) .						. .	.	. . .	. . . . . . . . . . . . . . . . . . . . . .	85
Figure 27.	Typical VOL @ VDD = 1.8 V (true open drain ports) .						. .	.	. . .	. . . . . . . . . . . . . . . . . . . . . .	85
Figure 28.	Typical VDD - VOH @ VDD = 3.0 V (high sink ports).						. .	.	. . .	. . . . . . . . . . . . . . . . . . . . . .	86
Figure 29.	Typical VDD - VOH @ VDD = 1.8 V (high sink ports).						. .	.	. . .	. . . . . . . . . . . . . . . . . . . . . .	86
Figure 30.	Typical NRST pull-up resistance RPU vs. VDD . . . . . .						. .	.	. . .	. . . . . . . . . . . . . . . . . . . . . .	87
Figure 31.	Typical NRST pull-up current Ipu vs. VDD . . . . . . . . .						. .	.	. . .	. . . . . . . . . . . . . . . . . . . . . .	87
Figure 32.	Recommended NRST pin configuration . . . . . . . . . . .						. .	.	. . .	. . . . . . . . . . . . . . . . . . . . . .	88
Figure 33.	SPI1 timing diagram - slave mode and CPHA=0 . . . .						. .	.	. . .	. . . . . . . . . . . . . . . . . . . . . .	90
Figure 34.	SPI1 timing diagram - slave mode and CPHA=1(1) . .						. .	.	. . .	. . . . . . . . . . . . . . . . . . . . . .	90
Figure 35.	SPI1 timing diagram - master mode(1) . . . . . . . . . . . .						. .	.	. . .	. . . . . . . . . . . . . . . . . . . . . .	91
Figure 36.	Typical application with I2C bus and timing diagram 1) .							.	. . .	. . . . . . . . . . . . . . . . . . . . . .	93
Figure 37.	ADC1 accuracy characteristics . .				. .	. . . . . . . . . . . . . .	. .	.	. . .	. . . . . . . . . . . . . . . . . . . . . .	99
Figure 38.	Typical connection diagram using the ADC . . . . . . . .						. .	.	. . .	. . . . . . . . . . . . . . . . . . . . . .	99
Figure 39.	Power supply and reference decoupling (VREF+ not connected to VDDA). . . . . . . . . . . . .										100
Figure 40.	Power supply and reference decoupling (VREF+ connected to VDDA) . . . . . . . . . . . . . .										100
Figure 41.	LQFP64 – 10 x 10 mm, 64 pin low-profile quad flat package outline . . . . . . . . . . . . . . . .										105
Figure 42.	Recommended footprint . . . . . . .				. .	. . . . . . . . . . . . . .	. .	.	. . .	. . . . . . . . . . . . . . . . . . . . .	106
Figure 43.	Ordering information scheme . . .				. .	. . . . . . . . . . . . . .	. .	.	. . .	. . . . . . . . . . . . . . . . . . . . .	107

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Introduction	STM8L052R8

1 Introduction

This document describes the features, pinout, mechanical data and ordering information of the high density value line STM8L052R8 microcontroller with a Flash memory density of 64 Kbytes.

For further details on the whole STMicroelectronics high density family please refer to

Section 2.2: Ultra low power continuum.

For detailed information on device operation and registers, refer to the reference manual (RM0031).

For information on to the Flash program memory and data EEPROM, refer to the programming manual (PM0054).

For information on the debug module and SWIM (single wire interface module), refer to the STM8 SWIM communication protocol and debug module user manual (UM0470).

For information on the STM8 core, refer to the STM8 CPU programming manual (PM0044).

High density value line devices provide the following benefits:

●Integrated system

–64 Kbytes of high density embedded Flash program memory

–256 bytes of data EEPROM

–4 Kbytes of RAM

–Internal high speed and low-power low speed RC

–Embedded reset

●Ultra low power consumption

–1 µA in Active-halt mode

–Clock gated system and optimized power management

–Capability to execute from RAM for Low power wait mode and low power run mode

●Advanced features

–Up to 16 MIPS at 16 MHz CPU clock frequency

–Direct memory access (DMA) for memory-to-memory or peripheral-to-memory access

●Short development cycles

–Application scalability across a common family product architecture with compatible pinout, memory map and modular peripherals

–Wide choice of development tools

These features make the value line STM8L05xxx ultra low power microcontroller family suitable for a wide range of consumer and mass market applications.

Refer to Table 1: High density value line STM8L05xxx low power device features and peripheral counts and Section 3: Functional overview for an overview of the complete range of peripherals proposed in this family.

Figure 1 shows the block diagram of the high density value line STM8L05xxx family.

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2 Description

The high density value line STM8L05xxx devices are members of the STM8L ultra low power 8-bit family.

The value line STM8L05xxx ultra low power family features the enhanced STM8 CPU core providing increased processing power (up to 16 MIPS at 16 MHz) while maintaining the advantages of a CISC architecture with improved code density, a 24-bit linear addressing space and an optimized architecture for low power operations.

The family includes an integrated debug module with a hardware interface (SWIM) which allows non-intrusive In-application debugging and ultra-fast Flash programming.

High density value line STM8L05xxx microcontrollers feature embedded data EEPROM and low-power, low-voltage, single-supply program Flash memory.

All devices offer 12-bit ADC, real-time clock, four 16-bit timers, one 8-bit timer as well as standard communication interface such as two SPIs, I2C, three USARTs and 8x24 or 4x28segment LCD. The 8x24 or 4x 28-segment LCD is available on the high density value line STM8L05xxx.

The STM8L05xxx family operates from 1.8 V to 3.6 V and is available in the -40 to +85 °C temperature range.

The modular design of the peripheral set allows the same peripherals to be found in different ST microcontroller families including 32-bit families. This makes any transition to a different family very easy, and simplified even more by the use of a common set of development tools.

All value line STM8L ultra low power products are based on the same architecture with the same memory mapping and a coherent pinout.

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Description	STM8L052R8

2.1Device overview

Table 1.	High density value line STM8L05xxx low power device features and
	peripheral counts
	Features		STM8L052R8
Flash (Kbytes)			64
Data EEPROM (bytes)			256
RAM (Kbytes)			4
LCD			8x24 or 4x28
		Basic	1
			(8-bit)
Timers		General purpose	3
			(16-bit)
		Advanced control	1
			(16-bit)
		SPI	2
Communication
		I2C	1
interfaces
		USART	3
GPIOs			54(1)
12-bit synchronized ADC			1
(number of channels)			(28)
			RTC, window watchdog, independent watchdog,
Others			16-MHz and 38-kHz internal RC,
			1- to 16-MHz and 32-kHz external oscillator
CPU frequency			16 MHz
Operating voltage			1.8 V to 3.6 V
Operating temperature			-40 to +85 °C
Package			LQFP64

1.The number of GPIOs given in this table includes the NRST/PA1 pin but the application can use the NRST/PA1 pin as general purpose output only (PA1).

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2.2Ultra low power continuum

The ultra low power value line STM8L05xxx and STM8L15xxx are fully pin-to-pin, software and feature compatible. Besides the full compatibility within the STM8L family, the devices are part of STMicroelectronics microcontrollers ultra low power strategy which also includes STM8L101xx and STM32L15xxx. The STM8L and STM32L families allow a continuum of performance, peripherals, system architecture, and features.

They are all based on STMicroelectronics 0.13 µm ultra-low leakage process.

Note: 1 The STM8L05xxx is pin-to-pin compatible with STM8L101xx devices.

2The STM32L family is pin-to-pin compatible with the general purpose STM32F family. Please refer to STM32L15x documentation for more information on these devices.

Performance

All families incorporate highly energy-efficient cores with both Harvard architecture and pipelined execution: advanced STM8 core for STM8L families and ARM Cortex™-M3 core for STM32L family. In addition specific care for the design architecture has been taken to optimize the mA/DMIPS and mA/MHz ratios.

This allows the ultra low power performance to range from 5 up to 33.3 DMIPs.

Shared peripherals

STM8L05x, STM8L15x and STM32L15xx share identical peripherals which ensure a very easy migration from one family to another:

●Analog peripheral: ADC1

●Digital peripherals: RTC and some communication interfaces

Common system strategy

To offer flexibility and optimize performance, the STM8L and STM32L devices use a common architecture:

●Same power supply range from 1.8 to 3.6 V

●Architecture optimized to reach ultra-low consumption both in low power modes and Run mode

●Fast startup strategy from low power modes

●Flexible system clock

●Ultra-safe reset: same reset strategy for both STM8L and STM32L including power-on reset, power-down reset, brownout reset and programmable voltage detector

Features

ST ultra low power continuum also lies in feature compatibility:

●More than 10 packages with pin count from 20 to 100 pins and size down to 3 x 3 mm

●Memory density ranging from 4 to 128 Kbytes

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Functional overview	STM8L052R8

3 Functional overview

Figure 1. High density value line STM8L05xxx device block diagram

OSC_IN,	1-16 MHz oscillator			@VDD
OSC_OUT			VDD18	Power	VDD=1.8 V
	16 MHz internal RC	Clock			to 3.6 V
OSC32_IN,		controller		VOLT. REG.	VSS
	32 kHz oscillator		Clocks
OSC32_OUT		and CSS
	38 kHz internal RC		to core and
			peripherals		NRST
				RESET
	Interrupt controller
	STM8 Core			POR/PDR
SWIM	Debug module			BOR
	(SWIM)
				PVD	PVD_IN
3 channels	16-bit Timer 1
2 channels	16-bit Timer 2			up to
2 channels	16-bit Timer 3			64-Kbyte
	8-bit Timer 4	ses		Program memory
				256 bytes
2 channels	16-bit Timer 5	b u		Data EEPROM
IR_TIM	Infrared interface	at a		up to
	DMA1 (4 channels)	d d		4-Kbyte RAM
		an
SCL, SDA,					PA[7:0]
	I²C1	t rol		Port A
SMB
SPI1_MOSI, SPI1_MISO,		n		Port B	PB[7:0]
	SPI1	, co
SPI1_SCK, SPI1_NSS					PC[7:0]
SPI2_MOSI, SPI2_MISO,	SPI2	ress		Port C
SPI2_SCK, SPI2_NSS					PD[7:0]
		d		Port D
USART1_RX, USART1_TX,	USART1	A d
USART1_CK				Port E	PE[7:0]
USART2_RX, USART2_TX,	USART2
USART2_CK				Port F	PF[7:0]
USART3_RX, USART3_TX,
	USART3
USART3_CK				Port G	PG[7:0]

VDDA, VSSA

@VDDA/VSSA

Beeper

BEEP

ADC1_INx

12-bit ADC1

ALARM, CALIB,

VREF+

RTC

TAMP1/2/3

VREF-

IWDG

(38 kHz clock)

VREFINT out	Internal reference	WWDG
	voltage
		LCD driver	SEGx, COMx
		Y PS Y
VLCD = 2.5 to 3.6 V	LCD booster
			MS30323V1

1.Legend:

ADC: Analog-to-digital converter BOR: Brownout reset

DMA: Direct memory access

I²C: Inter-integrated circuit multimaster interface LCD: Liquid crystal display

POR/PDR: Power on reset / power down reset RTC: Real-time clock

SPI: Serial peripheral interface SWIM: Single wire interface module

USART: Universal synchronous asynchronous receiver transmitter WWDG: Window watchdog

IWDG: independent watchdog

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3.1Low power modes

The high density value line STM8L05xxx devices support five low power modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources:

●Wait mode: The CPU clock is stopped, but selected peripherals keep running. An internal or external interrupt, event or a Reset can be used to exit the microcontroller from Wait mode (WFE or WFI mode).

●Low power run mode: The CPU and the selected peripherals are running. Execution is done from RAM with a low speed oscillator (LSI or LSE). Flash memory and data EEPROM are stopped and the voltage regulator is configured in ultra low power mode. The microcontroller enters Low power run mode by software and can exit from this mode by software or by a reset.

All interrupts must be masked. They cannot be used to exit the microcontroller from this mode.

●Low power wait mode: This mode is entered when executing a Wait for event in Low power run mode. It is similar to Low power run mode except that the CPU clock is stopped. The wakeup from this mode is triggered by a Reset or by an internal or external event (peripheral event generated by the timers, serial interfaces, DMA controller (DMA1) and I/O ports). When the wakeup is triggered by an event, the system goes back to Low power run mode.

All interrupts must be masked. They cannot be used to exit the microcontroller from this mode.

●Active-halt mode: CPU and peripheral clocks are stopped, except RTC. The wakeup can be triggered by RTC interrupts, external interrupts or reset.

●Halt mode: CPU and peripheral clocks are stopped, the device remains powered on. The wakeup is triggered by an external interrupt or reset. A few peripherals have also a wakeup from Halt capability. Switching off the internal reference voltage reduces power consumption. Through software configuration it is also possible to wake up the device without waiting for the internal reference voltage wakeup time to have a fast wakeup time of 5 µs.

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Functional overview	STM8L052R8

3.2Central processing unit STM8

3.2.1Advanced STM8 Core

The 8-bit STM8 core is designed for code efficiency and performance with an Harvard architecture and a 3-stage pipeline.

It contains 6 internal registers which are directly addressable in each execution context, 20 addressing modes including indexed indirect and relative addressing, and 80 instructions.

Architecture and registers

●Harvard architecture

●3-stage pipeline

●32-bit wide program memory bus - single cycle fetching most instructions

●X and Y 16-bit index registers - enabling indexed addressing modes with or without offset and read-modify-write type data manipulations

●8-bit accumulator

●24-bit program counter - 16-Mbyte linear memory space

●16-bit stack pointer - access to a 64-Kbyte level stack

●8-bit condition code register - 7 condition flags for the result of the last instruction

Addressing

●20 addressing modes

●Indexed indirect addressing mode for lookup tables located anywhere in the address space

●Stack pointer relative addressing mode for local variables and parameter passing

Instruction set

●80 instructions with 2-byte average instruction size

●Standard data movement and logic/arithmetic functions

●8-bit by 8-bit multiplication

●16-bit by 8-bit and 16-bit by 16-bit division

●Bit manipulation

●Data transfer between stack and accumulator (push/pop) with direct stack access

●Data transfer using the X and Y registers or direct memory-to-memory transfers

3.2.2Interrupt controller

The high density value line STM8L05xxx devices feature a nested vectored interrupt controller:

●Nested interrupts with 3 software priority levels

●32 interrupt vectors with hardware priority

●Up to 40 external interrupt sources on 11 vectors

●Trap and reset interrupts

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3.3Reset and supply management

3.3.1Power supply scheme

The device requires a 1.8 V to 3.6 V operating supply voltage (VDD). The external power supply pins must be connected as follows:

●VSS1, VDD1, VSS2, VDD2, VSS3, VDD3 = 1.8 to 3.6 V: external power supply for I/Os and for the internal regulator. Provided externally through VDD pins, the corresponding ground pin is VSS. VSS1/VSS2/VSS3/VSS4 and VDD1/VDD2/VDD3 must not be left unconnected.

●VSSA ; VDDA = 1.8 to 3.6 V: external power supplies for analog peripherals. VDDA and VSSA must be connected to VDD and VSS, respectively.

●VREF+ ; VREF- (for ADC1): external reference voltage for ADC1. Must be provided externally through VREF+ and VREF- pin.

3.3.2Power supply supervisor

The device has an integrated ZEROPOWER power-on reset (POR)/power-down reset (PDR), coupled with a brownout reset (BOR) circuitry that ensures proper operation starting from 1.8 V. After the 1.8 V BOR threshold is reached, the option byte loading process starts, either to confirm or modify default thresholds, or to disable BOR permanently.

Five BOR thresholds are available through option bytes, starting from 1.8 V to 3 V. To reduce the power consumption in Halt mode, it is possible to automatically switch off the internal reference voltage (and consequently the BOR) in Halt mode. The device remains

under reset when VDD is below a specified threshold, VPOR/PDR or VBOR, without the need for any external reset circuit.

The device features an embedded programmable voltage detector (PVD) that monitors the VDD/VDDA power supply and compares it to the VPVD threshold. This PVD offers 7 different levels between 1.85 V and 3.05 V, chosen by software, with a step around 200 mV. An interrupt can be generated when VDD/VDDA drops below the VPVD threshold and/or when VDD/VDDA is higher than the VPVD threshold. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state. The PVD is enabled by software.

3.3.3Voltage regulator

The high density value line STM8L05xxx embeds an internal voltage regulator for generating the 1.8 V power supply for the core and peripherals.

This regulator has two different modes:

●Main voltage regulator mode (MVR) for Run, Wait for interrupt (WFI) and Wait for event (WFE) modes

●Low power voltage regulator mode (LPVR) for Halt, Active-halt, Low power run and Low power wait modes

When entering Halt or Active-halt modes, the system automatically switches from the MVR to the LPVR in order to reduce current consumption.

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3.4Clock management

The clock controller distributes the system clock (SYSCLK) coming from different oscillators to the core and the peripherals. It also manages clock gating for low power modes and ensures clock robustness.

Features

●Clock prescaler: To get the best compromise between speed and current consumption the clock frequency to the CPU and peripherals can be adjusted by a programmable prescaler.

●Safe clock switching: Clock sources can be changed safely on the fly in run mode through a configuration register.

●Clock management: To reduce power consumption, the clock controller can stop the clock to the core, individual peripherals or memory.

●System clock sources: 4 different clock sources can be used to drive the system clock:

–1-16 MHz High speed external crystal (HSE)

–16 MHz High speed internal RC oscillator (HSI)

–32.768 kHz Low speed external crystal (LSE)

–38 kHz Low speed internal RC (LSI)

●RTC and LCD clock sources: The above four sources can be chosen to clock the RTC and the LCD, whatever the system clock.

●Startup clock: After reset, the microcontroller restarts by default with an internal 2 MHz clock (HSI/8). The prescaler ratio and clock source can be changed by the application program as soon as the code execution starts.

●Clock security system (CSS): This feature can be enabled by software. If a HSE clock failure occurs, the system clock is automatically switched to HSI.

●Configurable main clock output (CCO): This outputs an external clock for use by the application.

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Figure 2. High density value line STM8L05xxx clock tree diagram

		CSS
OSC_OUT	HSE OSC		HSE		SYSCLK to core and
OSC_IN	1-16 MHz		HSI	SYSCLK
						memory
	HSI RC		LSI	Prescaler
	16 MHz			/1;2;4;8;16;32;64;128		PCLK
			LSE
					Peripheral	to peripherals
					Clock enable (20 bits)
			LSE		BEEPCLK	to BEEP
	LSI RC		LSI	CLKBEEPSEL[1:0]	IWDGCLK	to IWDG
	38 kHz
					RTCCLK	to RTC
			RTCSEL[3:0]	LCD peripheral
			RTC	clock enable (1 bit)
				RTCCLK	RTCCLK/2	to LCD
			prescaler
				/ 2
OSC32_OUT	LSE OSC		/1;2;4;8;16;32;64
OSC32_IN	32.768 kHz	CSS_LSE
				Halt
				SYSCLK	LCDCLK	to LCD
	configurable		HSI
		CCO			LCD peripheral
	clock output		LSI
CCO		prescaler			clock enable (1 bit)
		/1;2;4;8;16;32;64	HSE
			LSE
						MS30324V1

1.The HSE clock source can be either an external crystal/ceramic resonator or an external source (HSE bypass). Refer to Section HSE clock in the STM8L15x and STM8L16x reference manual (RM0031).

2.The LSE clock source can be either an external crystal/ceramic resonator or a external source (LSE bypass). Refer to Section LSE clock in the STM8L15x and STM8L16x reference manual (RM0031).

3.5Low power real-time clock

The real-time clock (RTC) is an independent binary coded decimal (BCD) timer/counter.

Six byte locations contain the second, minute, hour (12/24 hour), week day, date, month, year, in BCD (binary coded decimal) format. Correction for 28, 29 (leap year), 30, and 31 day months are made automatically.The subsecond field can also be read in binary format.

The calendar can be corrected from 1 to 32767 RTC clock pulses. This allows to make a synchronization to a master clock.

The RTC offers a digital calibration which allows an accuracy of +/-0.5ppm.

It provides a programmable alarm and programmable periodic interrupts with wakeup from Halt capability.

●Periodic wakeup time using the 32.768 kHz LSE with the lowest resolution (of 61 µs) is from min. 122 µs to max. 3.9 s. With a different resolution, the wakeup time can reach 36 hours.

●Periodic alarms based on the calendar can also be generated from every second to every year.

A clock security system detects a failure on LSE, and can provide an interrupt with wakeup capability. The RTC clock can automatically switch to LSI in case of LSE failure.

The RTC also provides 3 anti-tamper detection pins. This detection embeds aprogrammable filter and can wakeup the MCU.

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3.6LCD (Liquid crystal display)

The LCD is only available on STM8L052xx devices.

The liquid crystal display drives up to 8 common terminals and up to 24 segment terminals to drive up to 192 pixels. It can also be configured to drive up to 4 common and 28 segments (up to 112 pixels).

●Internal step-up converter to guarantee contrast control whatever VDD.

●Static 1/2, 1/3, 1/4, 1/8 duty supported.

●Static 1/2, 1/3, 1/4 bias supported.

●Phase inversion to reduce power consumption and EMI.

●Up to 8 pixels which can be programmed to blink.

●The LCD controller can operate in Halt mode.

Note:

Unnecessary segments and common pins can be used as general I/O pins.

3.7Memories

The high density value line STM8L05xxx devices have the following main features:

●4 Kbytes of RAM

●The non-volatile memory is divided into three arrays:

–64 Kbytes of high density embedded Flash program memory

–256 bytes of data EEPROM

–Option bytes

The EEPROM embeds the error correction code (ECC) feature. It supports the read-while- write (RWW): it is possible to execute the code from the program matrix while programming/erasing the data matrix.

The option byte protects part of the Flash program memory from write and readout piracy.

3.8DMA

A 4-channel direct memory access controller (DMA1) offers a memory-to-memory and peripherals-from/to-memory transfer capability. The 4 channels are shared between the following IPs with DMA capability: ADC1, I2C1, SPI1, SPI 2, USART1, USART2, USART3 and the five timers.

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3.9Analog-to-digital converter

●12-bit analog-to-digital converter (ADC1) with 28 channels (including 4 fast channels), temperature sensor and internal reference voltage

●Conversion time down to 1 µs with fSYSCLK= 16 MHz

●Programmable resolution

●Programmable sampling time

●Single and continuous mode of conversion

●Scan capability: automatic conversion performed on a selected group of analog inputs

●Analog watchdog: interrupt generation when the converted voltage is outside the programmed threshold

●Triggered by timer

Note:

ADC1 can be served by DMA1.

3.10System configuration controller and routing interface

The system configuration controller provides the capability to remap some alternate functions on different I/O ports. TIM4 and ADC1 DMA channels can also be remapped.

The highly flexible routing interface allows application software to control the routing of different I/Os to the TIM1 timer input captures. It also controls the routing of internal analog signals to ADC1 and the internal reference voltage VREFINT.

3.11Timers

The high density value line STM8L05xxx devices contain one advanced control timer (TIM1), three 16-bit general purpose timers (TIM2, TIM3 and TIM5) and one 8-bit basic timer (TIM4).

All the timers can be served by DMA1.

Table 2 compares the features of the advanced control, general-purpose and basic timers.

Table 2.		Timer feature comparison
		Counter	Counter		DMA1	Capture/compare	Complementary
Timer				Prescaler factor	request
	resolution		type			channels	outputs
					generation
TIM1				Any integer		3 + 1	3
				from 1 to 65536
TIM2		16-bit	up/down
				Any power of 2
TIM3					Yes	2
				from 1 to 128
							None
TIM5
TIM4		8-bit	up	Any power of 2		0
				from 1 to 32768

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Functional overview	STM8L052R8

3.11.1TIM1 - 16-bit advanced control timer

This is a high-end timer designed for a wide range of control applications. With its complementary outputs, dead-time control and center-aligned PWM capability, the field of applications is extended to motor control, lighting and half-bridge driver.

●16-bit up, down and up/down autoreload counter with 16-bit prescaler

●3 independent capture/compare channels (CAPCOM) configurable as input capture, output compare, PWM generation (edge and center aligned mode) and single pulse mode output

●1 additional capture/compare channel which is not connected to an external I/O

●Synchronization module to control the timer with external signals

●Break input to force timer outputs into a defined state

●3 complementary outputs with adjustable dead time

●Encoder mode

●Interrupt capability on various events (capture, compare, overflow, break, trigger)

3.11.216-bit general purpose timers

●16-bit autoreload (AR) up/down-counter

●7-bit prescaler adjustable to fixed power of 2 ratios (1…128)

●2 individually configurable capture/compare channels

●PWM mode

●Interrupt capability on various events (capture, compare, overflow, break, trigger)

●Synchronization with other timers or external signals (external clock, reset, trigger and enable)

3.11.38-bit basic timer

The 8-bit timer consists of an 8-bit up auto-reload counter driven by a programmable prescaler. It can be used for timebase generation with interrupt generation on timer overflow.

3.12Watchdog timers

The watchdog system is based on two independent timers providing maximum security to the applications.

3.12.1Window watchdog timer

The window watchdog (WWDG) is used to detect the occurrence of a software fault, usually generated by external interferences or by unexpected logical conditions, which cause the application program to abandon its normal sequence.

3.12.2Independent watchdog timer

The independent watchdog peripheral (IWDG) can be used to resolve processor malfunctions due to hardware or software failures.

It is clocked by the internal LSI RC clock source, and thus stays active even in case of a CPU clock failure.

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STM8L052R8	Functional overview

3.13Beeper

The beeper function outputs a signal on the BEEP pin for sound generation. The signal is in the range of 1, 2 or 4 kHz.

3.14Communication interfaces

3.14.1SPI

The serial peripheral interfaces (SPI1 and SPI2) provide half/ full duplex synchronous serial communication with external devices.

●Maximum speed: 8 Mbit/s (fSYSCLK/2) both for master and slave

●Full duplex synchronous transfers

●Simplex synchronous transfers on 2 lines with a possible bidirectional data line

●Master or slave operation - selectable by hardware or software

●Hardware CRC calculation

●Slave/master selection input pin

Note:

SPI1 and SPI2 can be served by the DMA1 Controller.

3.14.2I²C

The I2C bus interface (I2C1) provides multi-master capability, and controls all I²C busspecific sequencing, protocol, arbitration and timing.

	● Master, slave and multi-master capability
	● Standard mode up to 100 kHz and fast speed modes up to 400 kHz
	● 7-bit and 10-bit addressing modes
	● SMBus 2.0 and PMBus support
	● Hardware CRC calculation
Note:	I2C1 can be served by the DMA1 Controller.

3.14.3	USART
	The USART interfaces (USART1, USART2 and USART3) allow full duplex, asynchronous
	communications with external devices requiring an industry standard NRZ asynchronous
	serial data format. It offers a very wide range of baud rates.
	● 1 Mbit/s full duplex SCI
	●	SPI1 emulation
	● High precision baud rate generator
	●	Smartcard emulation
	● IrDA SIR encoder decoder
	● Single wire half duplex mode
Note:	USART1, USART2 and USART3 can be served by the DMA1 Controller.

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Functional overview	STM8L052R8

3.15Infrared (IR) interface

The high density value line STM8L05xxx devices contain an infrared interface which can be used with an IR LED for remote control functions. Two timer output compare channels are used to generate the infrared remote control signals.

3.16Development support

Development tools

Development tools for the STM8 microcontrollers include:

●The STice emulation system offering tracing and code profiling

●The STVD high-level language debugger including C compiler, assembler and integrated development environment

●The STVP Flash programming software

The STM8 also comes with starter kits, evaluation boards and low-cost in-circuit debugging/programming tools.

Single wire data interface (SWIM) and debug module

The debug module with its single wire data interface (SWIM) permits non-intrusive real-time in-circuit debugging and fast memory programming.

The Single wire interface is used for direct access to the debugging module and memory programming. The interface can be activated in all device operation modes.

The non-intrusive debugging module features a performance close to a full-featured emulator. Beside memory and peripherals, CPU operation can also be monitored in realtime by means of shadow registers.

Bootloader

A bootloader is available to reprogram the Flash memory using the USART1, USART2,

USART3 (USARTs in asynchronous mode), SPI1 or SPI2 interfaces. The reference document for the bootloader is UM0560: STM8 bootloader user manual.

The bootloader is used to download application software into the device memories, including RAM, program and data memory, using standard serial interfaces. It is a complementary solution to programming via the SWIM debugging interface.

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STM8L052R8	Pin description

4 Pin description

Figure 3. STM8L052R8 64-pin LQFP64 package pinout

PE7

PE6 PC7 PC6

PC5 PC4 PC3

PC2

SS2

DD2

PC1

PC0 PG7 PG6

PG5

PG4

V

V

PA0

64 63 62 61 60 59 58

57 56 55 54 53 52 51 50 49

PD7

1

48

NRST/PA1

2

47

PD6

PA2

3

46

PD5

PA3

4

45

PD4

PA4

5

44

PF7

PA5

6

43

PF6

PA6

7

42

PF5

PA7

8

41

PF4

VSSA/VREF-

9

40

PF1

VSS1

10

39

PF0

VDD1

11

38

PB7

VDDA

12

37

PB6

VREF+

13

36

PB5

PG0

14

35

PB4

PG1

15

34

PB3

PG2

16

33

PB2

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

PG3

VLCD PE0 PE1

PE2 PE3 PE4

PE5

PD0

PD1

PD2

PD3 V VSS3

PB0

PB1

DD3

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Pin description				STM8L052R8
	Table 3.	Legend/abbreviation for Table 4
	Type		I= input, O = output, S = power supply
			FT	Five-volt tolerant
	Level
			TT	3.6 V tolerant
			Output	HS = high sink/source (20 mA)
	Port and control		Input	float = floating, wpu = weak pull-up
	configuration		Output	T = true open drain, OD = open drain, PP = push pull
			Bold X (pin state after reset release).
	Reset state		Unless otherwise specified, the pin state is the same during the reset phase (i.e.
			“under reset”) and after internal reset release (i.e. at reset state).

Table 4.

High density value line STM8L05xxx pin description

Pin

Input

Output

number

functionMain (afterreset)

Type

levelI/O

LQFP64

Pin name

floating

wpu

interruptExt.

sink/sourceHigh

OD

PP

Default alternate function

2

NRST/PA1(1)

I/O

X

HS

X

X

Reset

PA1

PA2/OSC_IN/

HSE oscillator input /

3

[USART1_TX](8)/

I/O

X

X

X

HS

X

X

Port A2

[USART1 transmit] / [SPI1

[SPI1_MISO] (8)

master inslave out]

PA3/OSC_OUT/[USART1_

HSE oscillator output /

4

I/O

X

X

X

HS

X

X

Port A3

[USART1 receive]/ [SPI1

RX](8)/[SPI1_MOSI](8)

master out/slave in]/

PA4/TIM2_BKIN/

Timer 2 - break input

5

[TIM2_ETR](8)/

I/O

FT(2)

X

X

X

HS

X

X

Port A4

/[Timer 2 - trigger]/

LCD_COM0/ADC1_IN2

LCD COM 0 / ADC1 input 2

PA5/TIM3_BKIN/

Timer 3 - break input

/[Timer 3 - trigger]/

6

[TIM3_ETR](8)/

I/O

FT(2)

X

X

X

HS

X

X

Port A5

LCD_COM 1 / ADC1 input

LCD_COM1/ADC1_IN1

1

PA6/[ADC1_TRIG]/

FT(2)

[ADC1 - trigger] /

7

I/O

X

X

X

HS

X

X

Port A6

LCD_COM2 /

LCD_COM2/ADC1_IN0

ADC1 input 0

8

PA7/LCD_SEG0(2)

I/O

FT(2)

X

X

X

HS

X

X

Port A7

LCD segment 0/ TIM5

/TIM5_CH1

channel 1

31

PB0(3)/TIM2_CH1/

I/O

FT(2)

X

X

X

HS

X

X

Port B0

Timer 2 - channel 1 / LCD

LCD_SEG10/ADC1_IN18

segment 10 / ADC1_IN18

PB1/TIM3_CH1/

FT(2)

Timer 3 - channel 1 / LCD

32

LCD_SEG11/

I/O

X

X

X

HS

X

X

Port B1

segment 11 / ADC1_IN17

ADC1_IN17

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STM8L052R8

Pin description

Table 4.

High density value line STM8L05xxx pin description (continued)

Pin

Input

Output

number

functionMain (afterreset)

Type

levelI/O

LQFP64

Pin name

floating

wpu

interruptExt.

sink/sourceHigh

OD

PP

Default alternate function

PB2/ TIM2_CH2/

FT(2)

Timer 2 - channel 2 / LCD

33

LCD_SEG12/

I/O

X

X

X

HS

X

X

Port B2

segment 12 / ADC1_IN16

ADC1_IN16

PB3/TIM2_ETR/

FT(2)

Timer 2 - trigger / LCD

34

LCD_SEG13/

I/O

X

X

X

HS

X

X

Port B3

segment 13 /ADC1_IN15

ADC1_IN15

PB4(3)/[SPI1_NSS](8)/

FT(2)

X(3)

X(3)

[SPI1 master/slave select] /

35

LCD_SEG14/

I/O

X

HS

X

X

Port B4

LCD segment 14 /

ADC1_IN14

ADC1_IN14

PB5/[SPI1_SCK](8)/

FT(2)

[SPI1 clock] / LCD segment

36

LCD_SEG15/

I/O

X

X

X

HS

X

X

Port B5

15 / ADC1_IN13

ADC1_IN13

PB6/[SPI1_MOSI](8)/

FT(2)

[SPI1 master out/slave in]/

37

LCD_SEG16/

I/O

X

X

X

HS

X

X

Port B6

LCD segment 16 /

ADC1_IN12

ADC1_IN12

PB7/[SPI1_MISO](8)/

FT(2)

[SPI1 master inslave out]

38

LCD_SEG17/

I/O

X

X

X

HS

X

X

Port B7

/LCD segment 17 /

ADC1_IN11

ADC1_IN11

53

PC0(2)/I2C1_SDA

I/O

FT(2)

X

X

T(4)

Port C0

I2C1 data

54

PC1(2)/I2C1_SCL

I/O

FT(2)

X

X

T(4)

Port C1

I2C1 clock

PC2/USART1_RX/

USART1 receive /

FT(2)

LCD segment 22 /

57

LCD_SEG22/ADC1_IN6/

I/O

X

X

X

HS

X

X

Port C2

ADC1_IN6 /Internal voltage

VREFINT

reference output

PC3/USART1_TX/

FT(2)

USART1 transmit /

58

LCD_SEG23/

I/O

X

X

X

HS

X

X

Port C3

LCD segment 23 /

ADC1_IN5

ADC1_IN5

PC4/USART1_CK/

USART1 synchronous

FT(2)

clock / I2C1_SMB /

59

I2C1_SMB/CCO/

I/O

X

X

X

HS

X

X

Port C4

Configurable clock output /

ADC1_IN4

ADC1_IN4

PC5/OSC32_IN

LSE oscillator input / [SPI1

60

/[SPI1_NSS](8)/

I/O

FT(2)

X

X

X

HS

X

X

Port C5

master/slave select] /

[USART1_TX](8)

[USART1 transmit]

PC6/OSC32_OUT/

LSE oscillator output /

61

[SPI1_SCK](8)/

I/O

FT(2)

X

X

X

HS

X

X

Port C6

[SPI1 clock] / [USART1

[USART1_RX](8)

receive]

62

PC7/ADC1_IN3

I/O

FT(2)

X

X

X

HS

X

X

Port C7

ADC1_IN3

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Pin description

STM8L052R8

Table 4.

High density value line STM8L05xxx pin description (continued)

Pin

Input

Output

number

functionMain (afterreset)

Type

levelI/O

LQFP64

Pin name

floating

wpu

interruptExt.

sink/sourceHigh

OD

PP

Default alternate function

PD0/TIM3_CH2/

Timer 3 - channel 2 /

25

[ADC1_TRIG](8)/

I/O

FT(2)

X

X

X

HS

X

X

Port D0

[ADC1_Trigger] / LCD

LCD_SEG7/ADC1_IN22/

segment 7 / ADC1_IN22

PD1/TIM3_ETR/

FT(2)

Timer 3 - trigger /

26

LCD_COM3/

I/O

X

X

X

HS

X

X

Port D1

LCD_COM3 / ADC1_IN21

ADC1_IN21

PD2/TIM1_CH1

FT(2)

Timer 1 - channel 1 / LCD

27

/LCD_SEG8/

I/O

X

X

X

HS

X

X

Port D2

segment 8 / ADC1_IN20

ADC1_IN20

28

PD3/ TIM1_ETR/

I/O

FT(2)

X

X

X

HS

X

X

Port D3

Timer 1 - trigger / LCD

LCD_SEG9/ADC1_IN19

segment 9 / ADC1_IN19

PD4/TIM1_CH2

FT(2)

Timer 1 - channel 2 / LCD

45

/LCD_SEG18/

I/O

X

X

X

HS

X

X

Port D4

segment 18 / ADC1_IN10

ADC1_IN10

PD5/TIM1_CH3

FT(2)

Timer 1 - channel 3 / LCD

46

/LCD_SEG19/

I/O

X

X

X

HS

X

X

Port D5

segment 19 / ADC1_IN9

ADC1_IN9

PD6/TIM1_BKIN

Timer 1 - break input / LCD

47

/LCD_SEG20/

I/O

FT(2)

X

X

X

HS

X

X

Port D6

segment 20 / ADC1_IN8 /

ADC1_IN8/RTC_CALIB/

RTC calibration / Internal

/VREFINT

voltage reference output

PD7/TIM1_CH1N

Timer 1 - inverted channel

1/ LCD segment 21 /

/LCD_SEG21/

FT(2)

48

I/O

X

X

X

HS

X

X

Port D7

ADC1_IN7 / RTC alarm /

ADC1_IN7/RTC_ALARM/V

Internal voltage reference

REFINT

output

49

PG4/SPI2_NSS

I/O

FT(2)

X

X

X

HS

X

X

Port G4

SPI2

master/slave select

50

PG5/SPI2_SCK

I/O

FT(2)

X

X

X

HS

X

X

Port G5

SPI2 clock

51

PG6/SPI2_MOSI

I/O

FT(2)

X

X

X

HS

X

X

Port G6

SPI2

master outslaìve in

52

PG7/SPI2_MISO

I/O

FT(2)

X

X

X

HS

X

X

Port G7

SPI2

master inslave out

19

PE0(2)/LCD_SEG1/TIM5_C

I/O

FT(2)

X

X

X

HS

X

X

Port E0

LCD segment 1/Timer 5

H2/RTC_TAMP1

channel 2/RTC tamper 1

PE1/TIM1_CH2N/

FT(2)

Timer 1 - inverted channel

20

I/O

X

X

X

HS

X

X

Port E1

2 / LCD segment 2/

LCD_SEG2/RTC_TAMP2

RTC tamper 2

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STM8L052R8

Pin description

Table 4.

High density value line STM8L05xxx pin description (continued)

Pin

Input

Output

number

functionMain (afterreset)

Type

levelI/O

LQFP64

Pin name

floating

wpu

interruptExt.

sink/sourceHigh

OD

PP

Default alternate function

PE2/TIM1_CH3N/

FT(2)

Timer 1 - inverted channel

21

I/O

X

X

X

HS

X

X

Port E2

3 / LCD segment 3/

LCD_SEG3/RTC_TAMP3

RTC tamper 3

22

PE3/LCD_SEG4

I/O

FT(2)

X

X

X

HS

X

X

Port E3

LCD segment 4

/USART2_RX

/USART2 receive

23

PE4/LCD_SEG5

I/O

FT(2)

X

X

X

HS

X

X

Port E4

LCD segment 5

/USART2_TX

/USART2 transmit

PE5/LCD_SEG6/

FT(2)

LCD segment 6 /

24

I/O

X

X

X

HS

X

X

Port E5

ADC1_IN23/USART2

ADC1_IN23/USART2_CK

synchronous clock

(2)

X

X

X

HS

X

X

Port E6

PVD_IN

63

PE6/PVD_IN/TIM5_BKIN

I/O

FT

/TIM5 break input

64

PE7

I/O

FT(2)

X

X

X

HS

X

X

Port E7

TIM5 trigger

/TIM5_ETR

39

PF0/ADC1_IN24

I/O

X

X

X

HS

X

X

Port F0

ADC1_IN24/

/[USART3_TX]

[USART3 transmit]

40

PF1/ADC1_IN25/

I/O

X

X

X

HS

X

X

Port F1

ADC1_IN25/

[USART3_RX]

[USART3 receive]

41

PF4/LCD_SEG36

I/O

FT(2)

X

X

X

HS

X

X

Port F4

LCD_SEG36/

/LCD_COM4(5)

LCD COM4(5)

42

PF5/LCD_SEG37/

I/O

FT(2)

X

X

X

HS

X

X

Port F5

LCD_SEG37/

LCD_COM5(5)

LCD COM5(5)

43

PF6/LCD_SEG38/

I/O

FT(2)

X

X

X

HS

X

X

Port F6

LCD_SEG38/

LCD_COM6(5)

LCD COM6(5)

44

PF7/LCD_SEG39/

I/O

FT(2)

X

X

X

HS

X

X

Port F7

LCD_SEG39/

LCD_COM7(5)

LCD COM7(5)

18

VLCD

S

LCD booster external capacitor

11

VDD1

S

Digital power supply

10

VSS1

I/O ground

12

VDDA

S

Analog supply voltage

13

VREF+

S

ADC1 positive voltage reference

14

PG0/USART3_RX/

(2)

X

X

X

HS

X

X

Port G0

USART3 receive /

[TIM2_BKIN]

I/O

FT

[Timer 2 - break input]

15

PG1/USART3_TX/

I/O

FT(2)

X

X

X

HS

X

X

Port G1

USART3 transmit /

[TIM3_BKIN]

[Timer 3 -break input]

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Pin description

STM8L052R8

Table 4.

High density value line STM8L05xxx pin description (continued)

Pin

Input

Output

number

functionMain (afterreset)

Type

levelI/O

LQFP64

Pin name

floating

wpu

interruptExt.

sink/sourceHigh

OD

PP

Default alternate function

16

PG2/USART3_CK

I/O

FT(2)

X

X

X

HS

X

X

Port G2

USART 3 synchronous

clock

17

PG3[TIM3_ETR]

I/O

FT(2)

X

X

X

HS

X

X

Port G3

[Timer 3 - trigger]

9

VSSA/VREF-

S

Analog ground voltage /

ADC1 negative voltage reference

55

VDD2

S

IOs supply voltage

56

VSS2

S

IOs ground voltage

PA0(6)/[USART1_CK](8)/

[USART1 synchronous

1

I/O

X

X

X

HS

X

X

Port A0

clock](8) / SWIM input and

SWIM/BEEP/IR_TIM (7)

output /Beep output

/ Infrared Timer output

29

VDD3

S

IOs supply voltage

30

VSS3

S

IOs ground voltage

1.At power-up, the PA1/NRST pin is a reset input pin with pull-up. To be used as a general purpose pin (PA1), it can be configured only as output open-drain or push-pull, not as a general purpose input. Refer to Section Configuring NRST/PA1 pin as general purpose output in the STM8L15x and STM8L16x reference manual (RM0031).

2.In the 5 V tolerant I/Os, protection diode to VDD is not implemented.

3.A pull-up is applied to PB0 and PB4 during the reset phase. These two pins are input floating after reset release.

4.In the open-drain output column, ‘T’ defines a true open-drain I/O (P-buffer, weak pull-up and protection diode to VDD are not implemented).

5.SEG/COM multiplexing available on medium+ and high density devices. SEG signals are available by default (see reference manual for details).

6.The PA0 pin is in input pull-up during the reset phase and after reset release.

7.High Sink LED driver capability available on PA0.

8.[ ] Alternate function remapping option (if the same alternate function is shown twice, it indicates an exclusive choice not aduplication of the function).

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STM8L052R8	Pin description

4.1System configuration options

As shown in Table 4: High density value line STM8L05xxx pin description, some alternate functions can be remapped on different I/O ports by programming one of the two remapping registers described in the “ Routing interface (RI) and system configuration controller” section in the STM8L15x and STM8L16x reference manual (RM0031).

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Memory and register map	STM8L052R8

5 Memory and register map

5.1Memory mapping

The memory map is shown in Figure 4.

Figure 4. Memory map

0x00 0000

0x00 07FF

0x00 0800

0x00 0FFF

0x00 1000

0x00 10FF

0x00 1100

0x00 47FF

0x00 4800

0x00 48FF

0x00 4900

0x00 4FFF

0x00 5000

0x00 57FF

0x00 5800

0x00 5FFF

0x00 6000

0x00 67FF

0x00 6800

0x00 7EFF

0x00 7F00

0x00 7FFF

0x00 8000

0x00 807F

0x00 8080

0x00 FFFF

RAM (4 Kbytes) (1) including

Stack (513 bytes) (1)

Reserved

Data EEPROM

(256 bytes)

Reserved

Option bytes

Reserved

GPIO and peripheral registers

Reserved

Boot ROM

(2 Kbytes)

Reserved

CPU/SWIM/Debug/ITC

Registers

Reset and interrupt vectors

High density Flash program memory

(64 Kbytes)

0x00 5000

GPIO Ports

0x00 5050

Flash

0x00 5070

DMA1

0x00 509D

SYSCFG

0x00 50A0

ITC-EXTI

0x00 50A6

WFE

0x00 50B0

RST

0x00 50B2

PWR

0x00 50C0

CLK

0x00 50D3

WWDG

0x00 50E0

IWDG

0x00 50F0

BEEP

0x00 5140

RTC

0x00 5200

SPI1

0x00 5210

I2C1

0x00 5230

USART1

0x00 5250

TIM2

0x00 5280

TIM3

0x00 52B0

TIM1

0x00 52E0

TIM4

0x00 52FF

IRTIM

0x00 5300

TIM5

0x00 5340

ADC1

0x00 5380

Reserved

0x00 53C0

SPI2

0x00 53E0

USART2

0x00 53F0

USART3

0x00 5400

LCD

0x00 5430

RI

0x00 5440

Reserved

0x00 5444

1.Table 5 lists the boundary addresses for each memory size. The top of the stack is at the RAM end address.

2.Refer to Table 7 for an overview of hardware register mapping, to Table 6 for details on I/O port hardware registers, and to Table 8 for information on CPU/SWIM/debug module controller registers.

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