ST STM6513 User Manual
Reset
STM6513
Dual push-button Smart
TM
with dual reset outputs and user-selectable setup delay
Features
■ Dual Smart Reset push-button inputs with
user-selectable extended reset setup delay (by
three-state input logic): t
■ Capacitor-adjustable reset pulse duration
(t
)
REC1
■ Power-on reset
■ Dual reset output (RST1 is active-high, push-
pull type, RST2
■ Factory-programmable thresholds to monitor
V
in the range of 1.575 to 4.625 V typ.
CC
■ Operating voltage 1.0 V (active-low output
is active-low, open-drain)
valid) to 5.5 V
■ Low supply current 3 µA
■ Operating temperature: industrial grade –40 °C
to +85 °C
■ TDFN8 package: 2 mm x 2 mm x 0.75 mm
■ RoHS compliant
= 2, 6, 10 s (min.)
SRC
TDFN8 (DG)
2 mm x 2 mm
Applications
■ Mobile phones, smartphones
■ e-books
■ MP3 players
■ Games
■ Portable navigation devices
■ Any application that requires delayed reset
push-button(s) response for improved system
stability.
June 2010 Doc ID 16490 Rev 2 1/29
www.st.com
1
Contents STM6513
Contents
1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3 Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.1 Power supply (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.2 Ground (V
3.3 Smart Reset inputs (SR0
3.4 User-programmable Smart Reset delay (TSR pin) . . . . . . . . . . . . . . . . . . 8
3.5 Reset outputs (RST1, RST2
3.6 Adjustable output reset timeout period input pin (TREC
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
SS
, SR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
) . . . . . . . . . . . 8
ADJ
4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5 Typical operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
6 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
7 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
8 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
9 Package footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
10 Tape and reel information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
11 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
12 Package marking information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
13 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
2/29 Doc ID 16490 Rev 2
STM6513 List of tables
List of tables
Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 2. t
Table 3. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 4. Operating and measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 5. DC and AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 6. Possible V
Table 7. TDFN – 8-lead 2 x 2 x 0.75 mm, 0.5 mm package mechanical data . . . . . . . . . . . . . . . . . 21
Table 8. Parameter for landing pattern - TDFN – 8-lead 2 x 2 mm package . . . . . . . . . . . . . . . . . . 22
Table 9. Carrier tape dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 10. Reel dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 11. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 12. Package marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 13. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
programmed by an ideal external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
REC1
voltage thresholds. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
CC
Doc ID 16490 Rev 2 3/29
List of figures STM6513
List of figures
Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 2. Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 3. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 4. Typical application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 5. Timing waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 6. Smart Reset delay t
TSR = V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
SS
Figure 7. Output reset timeout period t
(t
option E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 8. Supply current I
Figure 9. Reset voltage V
REC
CC
RST
(threshold option S, 2.925 V typ.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 10. Input leakage current, TSR pin, logic low vs. temperature and supply voltage V
Figure 11. Input leakage current, TSR pin, logic high vs. temperature and supply voltage V
Figure 12. AC testing input/output waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 13. TDFN - 8-lead, 2 x 2 x 0.75 mm, 0.5 mm pitch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 14. Landing pattern - TDFN – 8-lead 2 x 2 mm without thermal pad . . . . . . . . . . . . . . . . . . . . 22
Figure 15. Carrier tape . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 16. Reel dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 17. Tape trailer/leader. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 18. Pin 1 orientation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 19. Package marking area, top view. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
vs. temperature and supply voltage VCC,
SRC
vs. temperature and supply voltage VCC
REC2
vs. temperature and supply voltage VCC . . . . . . . . . . . . . . . . . . . . . . . 13
(falling) vs. temperature
. . . . . . 14
CC
. . . . . 15
CC
4/29 Doc ID 16490 Rev 2
STM6513 Description
1 Description
The STM6513 has two separate delayed Smart Reset inputs (SR0, SR1) which when taken
low simultaneously provide three user-selectable delayed Smart Reset setup time (t
options of 2 s, 6 s and 10 s. These are selected through a three-state TSR input pin: when
connected to ground, t
t
= 10 s (all the times are minimum). There are two reset outputs, both going active
SRC
= 2 s; when left open, t
SRC
= 6 s; when connected to VCC,
SRC
simultaneously after both the Smart Reset inputs were held active for the selected t
delay time. The first reset output, RST1, is active-high, push-pull; the second reset output,
RST2
, is active-low, open-drain requiring an external pull-up resistor. The duration of the
output reset pulses is independently programmable: t
external capacitor C
360 ms typ. Additionally, the V
tREC
), t
is factory-programmed to 210 ms (typ.), with the option of
REC2
is monitored and if it drops below the selected V
CC
threshold, both the reset outputs go active and remain so while V
threshold, plus the defined duration of the reset pulse t
is user-programmable (by
REC1
is below the V
CC
on each output.
REC
Smart Reset devices
The Smart Reset device family STM65xx provides a useful feature that ensures inadvertent
short reset push-button closures do not cause system resets. This is done by implementing
extended Smart Reset input delay (t
). Once the valid Smart Reset input levels and setup
SRC
delay are met, the device generates an output reset pulse with user-programmable timeout
period (t
REC
).
The Smart Reset inputs can be also connected to the applications interrupt to allow the
control of both the interrupt pin and the hard reset functions. If the push-buttons are closed
for a short time, the processor is only interrupted. If the system still does not respond
properly, holding the push-buttons for the extended setup time (t
) causes hard reset of
SRC
the processor through the reset outputs. The Smart Reset feature helps significantly
increase system stability.
SRC
RST
RST
SRC
)
The STM65xx family of Smart Reset devices consists of low current microprocessor reset
circuits targeted at applications such as MP3 players, navigation, smartphones or mobile
phones; generally any application that requires delayed reset push-button(s) response for
improved system stability. The STM65xx devices feature single or dual Smart Reset inputs
(SR). The delayed Smart Reset setup time (t
) options of 2 s, 6 s and 10 s
SRC
(all min.) are adjustable by an external capacitor on the SRC pin or selectable by three-state
logic. The delayed setup period ignores switch closures shorter than t
, thus preventing
SRC
unwanted resets.
The STM65xx devices have active-low (optionally active-high) open-drain reset (RST
)
output(s) with or without internal pull-up resistor or push-pull as output options, with factoryprogrammed or capacitor-adjustable or push-buttons defined output reset pulse duration,
with or without power-on reset function.
Some devices also have an undervoltage monitoring feature: the reset output is also
asserted when the monitored supply voltage V
reset output remains asserted for the reset timeout period (t
drops below the specified threshold. The
CC
) after the monitored supply
REC
voltage goes above the specified threshold.
Doc ID 16490 Rev 2 5/29
Description STM6513
Figure 1. Logic diagram
V
CC
SR1
TREC
ADJ
SR0
TSR
STM6513
V
SS
RST1
RST2
AM00372
Figure 2. Pin connections
RST1
V
SS
SR1
RST2
1
2
STM
6513
3
4
8
V
CC
7
SR0
TREC
6
5
ADJ
TSR
AM00373
6/29 Doc ID 16490 Rev 2
STM6513 Device overview
2 Device overview
Table 1. Signal names
Symbol Input/output Description
RST1 Output First reset output, active-high, push-pull.
R
ST2 Output Second reset output, active-low, open-drain.
S
R0 Input Primary push-button Smart Reset input. Active-low.
S
R1 Input Secondary push-button Smart Reset input. Active-low.
A Three-state Smart Reset input delay setup control. When connected
TSR Input
TREC
ADJ
Input
to ground, t
V
, t
CC
SRC
intended to be either permanently grounded, permanently connected
to V
or permanently left open. If left open, for improved system glitch
CC
immunity it is strongly recommended to connect a 0.1 µF decoupling
ceramic capacitor between the TSR and V
Input pin for t
external capacitor C
programmed.
= 2 s; when left open, t
SRC
= 6 s; when connected to
SRC
= 10 s (all times are minimum). TSR is a DC-type input,
pins.
SS
reset pulse duration adjustment. Connect an
REC1
to this pin to determine t
tREC
REC1
; t
REC2
is factory-
Positive supply voltage input. Power supply for the device and an input
V
CC
Supply
for the monitored supply voltage. A 0.1 µF decoupling ceramic
capacitor is recommended to be connected between V
and VSS
CC
pins.
V
SS
Supply Ground
Doc ID 16490 Rev 2 7/29
Pin descriptions STM6513
3 Pin descriptions
3.1 Power supply (VCC)
This pin is used to provide the power to the Smart Reset device and to monitor the power
supply. A 0.1 µF decoupling ceramic capacitor is recommended to be connected between
V
and VSS pins.
CC
3.2 Ground (VSS)
This is the ground for the device and all supplies.
3.3 Smart Reset inputs (SR0, SR1)
Push-button Smart Reset inputs. Both inputs need to be held active at the same time for at
least t
the unused one permanently to V
to activate the reset outputs. When only one Smart Reset input is used, connect
SRC
SS
.
3.4 User-programmable Smart Reset delay (TSR pin)
Used to allow the user to program the setup time before the push-buttons action is validated
by reset output. Controlled by different voltage levels on the TSR pin: when connected to
ground, t
(all times are minimum). TSR is a DC-type input, intended to be either permanently
grounded, permanently connected to V
system glitch immunity it is strongly recommended to connect a 0.1 µF decoupling ceramic
capacitor between the TSR and V
= 2 s; when left open, t
SRC
= 6 s; when connected to VCC, t
SRC
or permanently left open. If left open, for improved
CC
pins.
SS
SRC
= 10 s
3.5 Reset outputs (RST1, RST2)
Reset outputs, RST1 active-high, push-pull type, RST2 active-low, open-drain.
3.6 Adjustable output reset timeout period input pin (TREC
The output reset timeout period (t
capacitor C
Ta bl e 2 . Refer also to Ta bl e 5.
to the TREC
tREC
ADJ
) on RST1 is adjustable by connecting an external
REC1
pin. Calculated t
REC
and C
examples are given in
tREC
ADJ
)
8/29 Doc ID 16490 Rev 2
STM6513 Pin descriptions
Table 2. t
C
value (µF)
tREC
programmed by an ideal external capacitor
REC1
(ms)
(1)(2)
t
REC1
Min. Typ. Max.
Closest common
value (µF)
C
tREC
0.001 10 15 20 0.001
0.002 20 30 40 0.0022
0.01 100 150 200 0.01
0.014 140 210 280 0.015
0.028 280 420 560 0.027
0.056 560 840 1120 0.056
0.112 1120 1680 2240 0.12
1. At 25 ° C. Example calculations based on an ideal capacitor. During application design and component
selection it should be considered that the current flowing into the external t
(C
) is on the order of 100 nA, therefore a low-leakage capacitor (ceramic or film capacitor) should be
tREC
used and placed as close as possible to the TREC
environment should be ensured to prevent t
value of C
2. In case of repeated activations of the internal t
intervals to fully discharge C
is 0.001 µF.
tREC
, so that the next t
tREC
REC
pin. Also an adequate low-leakage PCB
ADJ
accuracy from being affected. A recommended minimum
timer, an interval of 10 ms min. is needed between t
REC
is as specified.
REC1
programming capacitor
REC
REC
Doc ID 16490 Rev 2 9/29
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