Figure 10.Input leakage current, TSR pin, logic low vs. temperature and supply voltage V
Figure 11.Input leakage current, TSR pin, logic high vs. temperature and supply voltage V
vs. temperature and supply voltage VCC . . . . . . . . . . . . . . . . . . . . . . . 13
(falling) vs. temperature
. . . . . . 14
CC
. . . . . 15
CC
4/29Doc ID 16490 Rev 2
STM6513Description
1 Description
The STM6513 has two separate delayed Smart Reset inputs (SR0, SR1) which when taken
low simultaneously provide three user-selectable delayed Smart Reset setup time (t
options of 2 s, 6 s and 10 s. These are selected through a three-state TSR input pin: when
connected to ground, t
t
= 10 s (all the times are minimum). There are two reset outputs, both going active
SRC
= 2 s; when left open, t
SRC
= 6 s; when connected to VCC,
SRC
simultaneously after both the Smart Reset inputs were held active for the selected t
delay time. The first reset output, RST1, is active-high, push-pull; the second reset output,
RST2
, is active-low, open-drain requiring an external pull-up resistor. The duration of the
output reset pulses is independently programmable: t
external capacitor C
360 ms typ. Additionally, the V
tREC
), t
is factory-programmed to 210 ms (typ.), with the option of
REC2
is monitored and if it drops below the selected V
CC
threshold, both the reset outputs go active and remain so while V
threshold, plus the defined duration of the reset pulse t
is user-programmable (by
REC1
is below the V
CC
on each output.
REC
Smart Reset devices
The Smart Reset device family STM65xx provides a useful feature that ensures inadvertent
short reset push-button closures do not cause system resets. This is done by implementing
extended Smart Reset input delay (t
). Once the valid Smart Reset input levels and setup
SRC
delay are met, the device generates an output reset pulse with user-programmable timeout
period (t
REC
).
The Smart Reset inputs can be also connected to the applications interrupt to allow the
control of both the interrupt pin and the hard reset functions. If the push-buttons are closed
for a short time, the processor is only interrupted. If the system still does not respond
properly, holding the push-buttons for the extended setup time (t
) causes hard reset of
SRC
the processor through the reset outputs. The Smart Reset feature helps significantly
increase system stability.
SRC
RST
RST
SRC
)
The STM65xx family of Smart Reset devices consists of low current microprocessor reset
circuits targeted at applications such as MP3 players, navigation, smartphones or mobile
phones; generally any application that requires delayed reset push-button(s) response for
improved system stability. The STM65xx devices feature single or dual Smart Reset inputs
(SR). The delayed Smart Reset setup time (t
) options of 2 s, 6 s and 10 s
SRC
(all min.) are adjustable by an external capacitor on the SRC pin or selectable by three-state
logic. The delayed setup period ignores switch closures shorter than t
, thus preventing
SRC
unwanted resets.
The STM65xx devices have active-low (optionally active-high) open-drain reset (RST
)
output(s) with or without internal pull-up resistor or push-pull as output options, with factoryprogrammed or capacitor-adjustable or push-buttons defined output reset pulse duration,
with or without power-on reset function.
Some devices also have an undervoltage monitoring feature: the reset output is also
asserted when the monitored supply voltage V
reset output remains asserted for the reset timeout period (t
A Three-state Smart Reset input delay setup control. When connected
TSRInput
TREC
ADJ
Input
to ground, t
V
, t
CC
SRC
intended to be either permanently grounded, permanently connected
to V
or permanently left open. If left open, for improved system glitch
CC
immunity it is strongly recommended to connect a 0.1 µF decoupling
ceramic capacitor between the TSR and V
Input pin for t
external capacitor C
programmed.
= 2 s; when left open, t
SRC
= 6 s; when connected to
SRC
= 10 s (all times are minimum). TSR is a DC-type input,
pins.
SS
reset pulse duration adjustment. Connect an
REC1
to this pin to determine t
tREC
REC1
; t
REC2
is factory-
Positive supply voltage input. Power supply for the device and an input
V
CC
Supply
for the monitored supply voltage. A 0.1 µF decoupling ceramic
capacitor is recommended to be connected between V
and VSS
CC
pins.
V
SS
SupplyGround
Doc ID 16490 Rev 27/29
Pin descriptionsSTM6513
3 Pin descriptions
3.1 Power supply (VCC)
This pin is used to provide the power to the Smart Reset device and to monitor the power
supply. A 0.1 µF decoupling ceramic capacitor is recommended to be connected between
V
and VSS pins.
CC
3.2 Ground (VSS)
This is the ground for the device and all supplies.
3.3 Smart Reset inputs (SR0, SR1)
Push-button Smart Reset inputs. Both inputs need to be held active at the same time for at
least t
the unused one permanently to V
to activate the reset outputs. When only one Smart Reset input is used, connect
SRC
SS
.
3.4 User-programmable Smart Reset delay (TSR pin)
Used to allow the user to program the setup time before the push-buttons action is validated
by reset output. Controlled by different voltage levels on the TSR pin: when connected to
ground, t
(all times are minimum). TSR is a DC-type input, intended to be either permanently
grounded, permanently connected to V
system glitch immunity it is strongly recommended to connect a 0.1 µF decoupling ceramic
capacitor between the TSR and V
= 2 s; when left open, t
SRC
= 6 s; when connected to VCC, t
SRC
or permanently left open. If left open, for improved
3.6 Adjustable output reset timeout period input pin (TREC
The output reset timeout period (t
capacitor C
Ta bl e 2 . Refer also to Ta bl e 5.
to the TREC
tREC
ADJ
) on RST1 is adjustable by connecting an external
REC1
pin. Calculated t
REC
and C
examples are given in
tREC
ADJ
)
8/29Doc ID 16490 Rev 2
STM6513Pin descriptions
Table 2.t
C
value (µF)
tREC
programmed by an ideal external capacitor
REC1
(ms)
(1)(2)
t
REC1
Min.Typ.Max.
Closest common
value (µF)
C
tREC
0.0011015200.001
0.002203040 0.0022
0.01100150200 0.01
0.014140210280 0.015
0.028280420560 0.027
0.0565608401120 0.056
0.112112016802240 0.12
1. At 25 ° C. Example calculations based on an ideal capacitor. During application design and component
selection it should be considered that the current flowing into the external t
(C
) is on the order of 100 nA, therefore a low-leakage capacitor (ceramic or film capacitor) should be
tREC
used and placed as close as possible to the TREC
environment should be ensured to prevent t
value of C
2. In case of repeated activations of the internal t
intervals to fully discharge C
is 0.001 µF.
tREC
, so that the next t
tREC
REC
pin. Also an adequate low-leakage PCB
ADJ
accuracy from being affected. A recommended minimum
timer, an interval of 10 ms min. is needed between t
REC
is as specified.
REC1
programming capacitor
REC
REC
Doc ID 16490 Rev 29/29
Block diagramSTM6513
4 Block diagram
Figure 3.Block diagram
SR1
SR0
TSR
V
SR logic
Three-state
selector
CC
V
REF
t
REC2
+
–
I
REF
t
SRC
t
REC1
Oscillator
TREC
ADJ
RST2
RST1
AM00374V2
10/29Doc ID 16490 Rev 2
STM6513Block diagram
STM6513 hookup with RST1 and RST2, bridging the PS_hold reset pulse during the
microprocessor reset initiated by the STM6513 Smart Reset device:
Figure 4.Typical application diagram
V
CC
PMU
LD00
LD07
Seq.
logic
V
REG
...
(PU resistor)
MCU
RST_n
POWER
KEY
C
tREC
TREC
TSR
ADJ
PWR
SW
V
STM6513
PS_hold
REG
Figure 5.Timing waveforms
POR initiated
SR0, SR1
RST1 (PP)
RST2 (OD)
SR0
SR1
100 kΩ
RST
PS_hold
GPIO1GPIOn
Forces PS_hold
high during
reset period
Smart Reset™ initiated
t
SRC
KEYn
KEY1
AM00375a
RST2 (OD)
Factory programmed
RST1 (PP)
by C
tREC
t
REC1
t
REC2
(~1 s)
(210 ms)
t
REC1
t
REC2
(~1 s)
(210 ms)
AM00376V2
Doc ID 16490 Rev 211/29
Typical operating characteristicsSTM6513
5 Typical operating characteristics
Figure 6.Smart Reset delay t
t
SRC
TSR = V
[s]
–60–40–20020406080100120140
SS
3
2.9
2.8
2.7
2.6
2.5
2.4
2.3
2.2
2.1
2
vs. temperature and supply voltage VCC,
SRC
Temperature [˚C]
5.5 V3.3 V
AM00632
12/29Doc ID 16490 Rev 2
STM6513Typical operating characteristics
Figure 7.Output reset timeout period t
V
(t
option E)
REC
280
260
240
220
200
180
160
140
t
REC2
CC
[ms]
–60–40–20020406080100120140
vs. temperature and supply voltage
REC2
Temperature [˚C]
5.5 V3.3 V
AM00633
Figure 8.Supply current I
I
[µA]
CC
–60–40–20020406080100120140
vs. temperature and supply voltage V
CC
6
5
4
3
2
1
0
Temperature [˚C]
5.5 V3.3 V
CC
AM00634
Doc ID 16490 Rev 213/29
Typical operating characteristicsSTM6513
Figure 9.Reset voltage V
(threshold option S, 2.925 V typ.)
V
,
falling [V]
RST
–60–40–20020406080100120140
(falling) vs. temperature
RST
2.96
2.95
2.94
2.93
2.92
2.91
2.9
2.89
Temperature [˚C]
AM00635
Figure 10. Input leakage current, TSR pin, logic low vs. temperature and supply
I
LI(TSR), LO
voltage V
[µA]
CC
10
8
6
4
2
–60–40–20020406080100120140
0
–2
–4
–6
–8
–10
Temperature [˚C]
5.5 V3.3 V2 V
14/29Doc ID 16490 Rev 2
AM00636
STM6513Typical operating characteristics
Figure 11. Input leakage current, TSR pin, logic high vs. temperature and supply
voltage V
CC
10
8
6
4
2
I
LI(TSR ), HI
[µA]
–60–40–20020406080100120140
0
–2
–4
–6
–8
–10
Temperature [˚C]
5.5 V3.3 V2 V
AM00637
Doc ID 16490 Rev 215/29
Maximum ratingSTM6513
6 Maximum rating
Stressing the device above the rating listed in the Table 3: Absolute maximum ratings may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the Operating sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability. Refer also to the STMicroelectronics SURE
Program and other relevant quality documents.
Table 3.Absolute maximum ratings
SymbolParameterValueUnit
T
STG
T
SLD
θ
JA
V
IO
V
CC
1. Reflow at peak temperature of 260 °C. The time above 255 °C must not exceed 30 s.
2. For RST1 –0.3 to VCC +0.3 V only.
Storage temperature (VCC off)–55 to +150 °C
(1)
Lead solder temperature for 10 seconds260 °C
Thermal resistance (junction to ambient) TDFN8149.0°C/W
Input or output voltage–0.3 to 5.5
Supply voltage–0.3 to 7V
(2)
V
16/29Doc ID 16490 Rev 2
STM6513DC and AC parameters
7 DC and AC parameters
This section summarizes the operating measurement conditions, and the DC and AC
characteristics of the device. The parameters in the Table 5: DC and AC characteristics that
follow, are derived from tests performed under the Measurement Conditions summarized in
Table 4.: Operating and measurement conditions. Designers should check that the
operating conditions in their circuit match the operating conditions when relying on the
quoted parameters.
Table 4.Operating and measurement conditions
ParameterValueUnit
V
supply voltage1.0 to 5.5V
CC
Ambient operating temperature (T
Input rise and fall times≤
Input pulse voltages0.2 to 0.8 V
Input and output timing ref. voltages0.3 to 0.7 V
Figure 12. AC testing input/output waveforms
)–40 to +85°C
A
5ns
CC
CC
V
V
0.8 V
0.2 V
CC
CC
0.7 V
0.3 V
CC
CC
AM00478
Doc ID 16490 Rev 217/29
DC and AC parametersSTM6513
Table 5.DC and AC characteristics
SymbolParameterTest conditions
Reset output valid - active-low1.05.5V
V
V
V
V
Supply voltage range
CC
Supply current (VCC)
I
CC
Reset output voltage
OL
low
Reset output voltage
OH
high, RST1
Fixed voltage trip
point for V
RST
monitoring (refer to
Ta b le 6 )
CC
Reset output valid - active-high1.25.5V
V
= 3.0 V, TSR left open
CC
V
= 5.0 V, TSR left open46µA
CC
V
≥
4.5 V, sinking 3.2 mA0.3V
CC
V
≥
3.3 V, sinking 2.5 mA0.3V
CC
V
≥
1.0 V, sinking 0.1 mA0.3V
CC
V
≥
4.5 V, I
CC
V
≥
CC
V
≥
CC
2.7 V, I
1.2 V, I
SOURCE
SOURCE
SOURCE
–40 to +85 °CV
25 °CV
L, M0.5%
HYST
Hysteresis of V
RST
T, S, R, Z, Y, W, V1%
V
(1)
(3)
Min.Typ.
= 0.8 mA0.8 V
= 0.5 mA0.8 V
= 0.05 mA0.8 V
–2.5%V
RST
–2.0%V
RST
CC
CC
CC
(2)
Max.Units
35µA
V
V
V
V
RST
RST
+2.5%V
RST
V
+2.0%V
RST
t
REC2
t
REC1
V
to reset delay
CC
(4)
Output reset timeout
period on RST2
,
factory-programmed
User-adjustable
output reset timeout
period on RST1
Refer to Ta bl e 2 .
VCC falling from (V
to (V
- 100 mV) at 10 mV/µs
RST
+ 100 mV)
RST
20µs
Option E140210280ms
Option F240360480ms
10 000 x
C
tREC
(µF)
15 000 x
C
tREC
(µF)
20 000 x
C
tREC
(µF)
ms
18/29Doc ID 16490 Rev 2
STM6513DC and AC parameters
Table 5.DC and AC characteristics (continued)
SymbolParameterTest conditions
Smart Reset inputs (SRx)
(1)
Min.Typ.
(2)
Max.Units
22.53s
1012.515s
V
–0.30.3 V
SS
0.7 V
CC
t
SRC
t
SRC
V
V
Smart Reset delay
SR0, SR1 input
IL
voltage low
SR0, SR1 input
IH
voltage high
Input glitch
immunity
(5)
TSR = V
SS
TSR = floating67.59s
TSR = V
Corresponds to the actual t
CC
SRC
Input leakage
I
LI(SR)
current (SR0
, SR1
–11µA
pins)
I
LI(TSR)
1. Valid for ambient operating temperature: TA = –40 to +85 °C; VCC = 1.0 V to 5.5 V (except where noted).
2. Typical value is at 25 °C and V
3. For devices with V
4. Guaranteed by design.
5. Input glitch immunity is equal to t
Table 6.Possible VCC voltage thresholds
Input leakage
current (TSR pin)
< 3.0 V.
RST
= 3.3 V unless otherwise noted.
CC
(when both SR inputs are low), otherwise infinite.
SRC
–57µA
CC
5.5V
V
s
VCC monitoring
threshold V
RST
Typ.
±2.5% (–40 °C to +85 °C)±2.0% (25 °C)
Unit
Min.Max.Min.Max.
L (falling)4.6254.5094.7414.5334.718V
M (falling)4.3754.2664.4844.2884.463V
T (falling)3.0752.9983.1523.0143.137V
S (falling)2.9252.8522.9982.8672.984V
R (falling)2.6252.5592.6912.5732.678V
Z (falling)2.3132.2552.3712.2672.359V
Y (falling)2.1882.1332.2432.1442.232V
W (falling)1.6651.6231.7071.6321.698V
V (falling)1.5751.5361.6141.5441.607V
Doc ID 16490 Rev 219/29
Package mechanical dataSTM6513
8 Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK
®
packages, depending on their level of environmental compliance. ECOPACK®
®
is an ST trademark.
Figure 13. TDFN - 8-lead, 2 x 2 x 0.75 mm, 0.5 mm pitch
PIN 1 INDEX AREA
0.10 C
0.10
C
A
0.08 C
PIN 1 INDEX AREA
D
2x
0.10 C
2x
TOP VIEW
SIDE VIEW
e
1
A
B
E
C
A1
SEATING
PLANE
b
4
0.10 C A B
Pin#1 I D
8
BOTTOM VIEW
20/29Doc ID 16490 Rev 2
L
5
TDFN-8L
STM6513Package mechanical data
Table 7.TDFN – 8-lead 2 x 2 x 0.75 mm, 0.5 mm package mechanical data
Dimension (mm)Dimension (inches)
Symbol
Min.Nom.Max.Min.Nom.Max.
A0.700.750.800.0280.0300.031
A10.000.020.050.0000.0010.002
b0.150.200.250.0060.0080.010
D
BSC
E
BSC
1.92.002.10.0750.0790.083
1.92.002.10.0750.0790.083
e0.500.020
L0.450.550.650.0180.0220.026
Doc ID 16490 Rev 221/29
Package footprintSTM6513
9 Package footprint
Figure 14. Landing pattern - TDFN – 8-lead 2 x 2 mm without thermal pad
D
P
E1E
L
b
Table 8.Parameter for landing pattern - TDFN – 8-lead 2 x 2 mm package
2All dimensions are in mm, unless otherwise noted.
User direction of feed
AM00442
Doc ID 16490 Rev 225/29
Part numberingSTM6513
11 Part numbering
Table 11.Ordering information scheme
Example:STM6513VEIEDG6F
Device type
STM6513
Reset (V
monitoring threshold) voltage V
CC
RST
L = 4.625 V (typ., falling)
M = 4.375 V
T = 3.075 V
S = 2.925 V
R = 2.625 V
Z = 2.313 V
Y = 2.188 V
W = 1.665 V
V = 1.575 V
Smart Reset setup delay (t
presence of internal input pull-up on all Smart Reset inputs (SR0
SRC
);
, SR1)
E = 2 or 6 or 10 s min., user-programmed (three-state); no input pull-up
Outputs type
I = RST1 active-high, push-pull, RST2
Reset timeout period (t
E = t
F = t
user-programmable (external capacitor), t
REC1
user-programmable (external capacitor), t
REC1
REC
)
active-low, open-drain, no pull-up
factory-programmed (210 ms typ.)
REC2
factory-programmed (360 ms typ.)
REC2
Package
DG = TDFN8 - 2 x 2 x 0.75 mm, 0.5 mm pitch
Temperature range
6 = –40 °C to +85 °C
Shipping method
F = ECOPACK
®
package, tape and reel
For other options, voltage threshold values etc. or for more information on any aspect of this device,
please contact the ST sales office nearest you.
26/29Doc ID 16490 Rev 2
STM6513Package marking information
12 Package marking information
Table 12.Package marking
Full part number
STM6513VEIEDG6FTSRAL, NPUVAH, PPC
STM6513SEIEDG6FTSRAL, NPUSAH, PPC
STM6513REIEDG6FTSRAL, NPURAH, PPC
Smart
t
SRC
delay
control
inputs type
Reset
V
RST
RST1
output
type
t
REC1
programming
tREC
tREC
tREC
RST2 output
type
t
REC2
option
Topmark
AL, OD, NPUE9AH
AL, OD, NPUE9SH
AL, OD, NPUE9RH
Note:AL = active-low, AH = active-high; PP = push-pull, OD = open-drain, PU = internal pull-up
resistor, NPU = no internal pull-up resistor.
Figure 19. Package marking area, top view
A
BC
D
E
Topmark
A = dot (pin 1 reference)
B = assembly plant (P)
C = assembly year (Y, 0-9): 9 = 2009 etc.
D = assembly work week (WW, 01 to 52): 20 = WW20 etc.
E = marking area (topmark)
AM00479
Doc ID 16490 Rev 227/29
Revision historySTM6513
13 Revision history
Table 13.Document revision history
DateRevisionChanges
22-Oct-20091Initial release.
Updated title, Features, Applications, replaced “smart reset” by
21-Jun-20102
“Smart Reset™” and “Smart Reset”, updated Section 1, Ta bl e 1 ,
Section 3, Ta bl e 2 , Figure 3, Figure 5, Figure 6, Ta b l e 3 , Ta bl e 5 to
Ta b le 8 , Ta b le 1 1 and Ta b le 1 2 .
28/29Doc ID 16490 Rev 2
STM6513
y
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