ST STM6315 User Manual

STM6315

Open drain microprocessor reset

Features

■ Low supply current of 1.5µA (typ)

■ ±1.8% reset threshold accuracy (25°C)

■ Guaranteed RST assertion down to

V

= 1.0V

CC

■ Open drain RST output can exceed V

■

Power supply transient immunity

■ Operating temperature: –40 to +125°C

■ Available in SOT143-4 package.

CC

SOT143-4 (W1)

March 2007 Rev 5 1/21

www.st.com

1

Contents STM6315

Contents

1 Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.1 Reset output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.2 Manual reset input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.3 Negative-going V

2.4 Valid RST

output down to VCC = 0V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

transients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

CC

3 Typical operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

4 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

5 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

6 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

7 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2/21

STM6315 List of tables

List of tables

Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Table 2. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Table 3. Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Table 4. DC and AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 5. SOT143-4 – 4-lead small outline transistor package mechanical data . . . . . . . . . . . . . . . . 17

Table 6. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 7. Marking description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 8. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3/21

List of figures STM6315

List of figures

Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 2. SOT143-4 connections (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 3. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 4. Hardware hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 5. Reset timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 6. Manual reset timing diagram, switch bounce/debounce. . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 7. Supply current vs. supply voltage, V
Figure 8. Supply current vs. temperature (no load), V
Figure 9. RST

Figure 10. Normalized reset time-out period vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 11. Normalized reset threshold vs. temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 12. Max. transient duration not causing reset pulse vs. reset threshold Overdrive . . . . . . . . . 11

Figure 13. AC testing input/output waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 14. SOT143-4 – 4-lead small outline transistor package outline . . . . . . . . . . . . . . . . . . . . . . . 17

output voltage vs. output current, VCC = 4.25V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

= 2.63V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

RST

= 2.63V . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

RST

4/21

STM6315 Summary description

1 Summary description

The STM6315 Microprocessor Reset Circuit is a low power supervisory device used to
monitor power supplies. It performs a single function: asserting a reset signal whenever the
V

supply voltage drops below a preset value and keeping it asserted until VCC has risen

CC

above the preset threshold for a minimum period of time (t
reset input (MR

). The open drain RST output can be pulled up to a voltage higher than VCC,

but less than 6V.

The STM6315 comes with standard factory-trimmed reset thresholds of 2.63V, 2.93V,

3.08V, 4.38V, and 4.63V. The STM6315 is available in the SOT143-4 package.

Figure 1. Logic diagram

V

CC

). It also provides a manual

rec

STM6315

V

SS

Table 1. Signal names

Symbol Description

V

CC

MR

RST

V

SS

Supply voltage

Manual reset input

Active-low open drain reset output

Ground

MR

Figure 2. SOT143-4 connections (top view)

V

SS

1

RST

AI11162

V

4

CC

RST

2

5/21

3

MR

AI11163

Summary description STM6315

Figure 3. Block diagram

V

V

CC

RST

COMPARE

t

rec

Generator

RST

MR

Figure 4. Hardware hookup

V

CC

Manual

Reset

DEBOUNCE

V

CC

10k

STM6315 MCU

MR

(1)

RST

V

SS

RESET
Input

AI11164

V

CC

V

SS

1. Open drain RST output requires external pull-up resistor.

6/21

AI11165

STM6315 Operation

2 Operation

2.1 Reset output

The STM6315 Microprocessor Reset Circuit has an active-low, open drain reset output. This
output structure will sink current when RST
to any supply voltage up to 6V (see Figure 4 on page 6). Select a resistor value large
enough to register a logic low, and small enough to register a logic high while supplying all
input current and leakage paths connected to the reset output line. A 10k pull-up is sufficient
in most applications.

is asserted. Connect a pull-up resistor from RST

The STM6315 asserts a reset signal to the MCU whenever V
threshold (V

Figure 6 on page 8). RST

During power-up, (once V
for the reset time-out period, t

If V

drops below the reset threshold, RST goes low. Each time RST is asserted, it stays

CC

), or when the manual reset input (MR) is taken low (see Figure 5 and

RST

is guaranteed valid down to VCC = 1.0V.

exceeds the reset threshold) an internal timer keeps RST low

CC

. After this interval, RST returns high.

rec

low for at least the reset time-out period. Any time V
internal timer clears. The reset timer starts when V

2.2 Manual reset input

A logic low on MR asserts RST. RST remains asserted while MR is low, and for t
returns high. The MR

input has an internal pull-up resistor 63kΩ (typ), allowing it to be left

open if not used.

This input can be driven with TTL/CMOS-logic levels or with open drain/collector outputs.
Connect a standard open push-button switch from MR
function (see Figure 4 on page 6); external debounce circuitry is not required. If the device is
used in a noisy environment, connect a 0.1µF capacitor from MR
additional noise immunity.

2.3 Negative-going VCC transients

goes below the reset

CC

goes below the reset threshold, the

CC

returns above the reset threshold.

CC

rec

to VSS to create a manual reset

to VSS to provide

after it

The STM6315 is relatively immune to negative-going VCC transients (glitches). Figure 12 on

page 11 shows typical transient duration versus reset comparator overdrive (for which the

STM6315 will NOT generate a reset pulse). The graph was generated using a negative
pulse applied to V

, starting at 0.5V above the actual reset threshold and ending below it

CC

by the magnitude indicated (Reset Threshold Overdrive). The graph indicates the maximum
pulse width a negative V

transient can have without causing a reset pulse. As the

CC

magnitude of the transient increases (further below the threshold), the maximum allowable
pulse width decreases. Any combination of duration and overdrive which lies under the
curve will NOT generate a reset signal (see Figure 12). A 0.1µF bypass capacitor mounted
as close as possible to the V

pin provides additional transient immunity.

CC

7/21