ST STM32W108HB, STM32W108CC, STM32W108CB, STM32W108CZ User Manual

STM32W108HB STM32W108CC

STM32W108CB STM32W108CZ

High-performance, IEEE 802.15.4 wireless system-on-chip with up to 256 Kbytes of embedded Flash memory

Features

■Complete system-on-chip

–32-bit ARM® Cortex™-M3 processor

–2.4 GHz IEEE 802.15.4 transceiver & lower MAC

–128/192/256-Kbyte Flash, 8/12/16-Kbyte RAM memory

–AES128 encryption accelerator

–Flexible ADC, SPI/UART/I2C serial communications, and general-purpose timers

–24 highly configurable GPIOs with Schmitt trigger inputs

■Industry-leading ARM® Cortex™-M3 processor

–Leading 32-bit processing performance

–Highly efficient Thumb®-2 instruction set

–Operation at 6, 12 or 24 MHz

–Flexible nested vectored interrupt controller

■Low power consumption, advanced management

–Receive current (w/ CPU): 27 mA

–Transmit current (w/ CPU, +3 dBm TX): 31 mA

–Low deep sleep current, with retained RAM and GPIO: 400 nA/800 nA with/without sleep timer

–Low-frequency internal RC oscillator for low-power sleep timing

–High-frequency internal RC oscillator for fast (100 µs) processor start-up from sleep

■Exceptional RF performance

–Normal mode link budget up to 102 dB; configurable up to 107 dB

–-99 dBm normal RX sensitivity; configurable to -100 dBm (1% PER, 20 byte packet)

–+3 dB normal mode output power; configurable up to +8 dBm

Datasheet −production data

VFQFPN48	VFQFPN40
(7 x 7 mm)	(6 x 6 mm)

UFQFPN48 (7 x 7 mm)

–Robust WiFi and Bluetooth coexistence

■Innovative network and processor debug

–Non-intrusive hardware packet trace

–Serial wire/JTAG interface

–Standard ARM debug capabilities: Flash patch & breakpoint; data watchpoint & trace; instrumentation trace macrocell

■Application flexibility

–Single voltage operation: 2.1-3.6 V with internal 1.8 V and 1.25 V regulators

–Optional 32.768 kHz crystal for higher timer accuracy

–Low external component count with single 24 MHz crystal

–Support for external power amplifier

–Small 7x7 mm 48-pin VFQFPN package or 6x6 mm 40-pin VFQFPN package

Applications

■Smart energy

■Building automation and control

■Home automation and control

■Security and monitoring

■ZigBee® Pro wireless sensor networking

■RF4CE products and remote controls

■6LoWPAN and custom protocols

March 2012

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This is information on a product in full production.

www.st.com

Contents	STM32W108HB STM32W108CC STM32W108CB STM32W108CZ

Contents

1	Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		10
	1.1	Development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	11
	1.2	Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	12

1.2.1 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 1.2.2 ARM® Cortex™-M3 core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2	Documentation conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		14
3	Pinout and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		15
4	Embedded memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		27
	4.1	Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	29
	4.2	Random-access memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	29

4.2.1 Direct memory access (DMA) to RAM . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4.2.2 RAM memory protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

4.3 Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

5	Radio frequency module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	32
	5.1 Receive (Rx) path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	32

5.1.1 Rx baseband . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.1.2 RSSI and CCA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

5.2	Transmit (Tx) path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		32
	5.2.1	Tx baseband . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	33
	5.2.2	TX_ACTIVE and nTX_ACTIVE signals . . . . . . . . . . . . . . . . . . . . . . . . .	33

5.3 Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.4 Integrated MAC module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.5 Packet trace interface (PTI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.6 Random number generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

6	System modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	35
	6.1 Power domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	36

6.1.1 Internally regulated power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.1.2 Externally regulated power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

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6.2 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

6.2.1 Reset sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 6.2.2 Reset recording . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 6.2.3 Reset generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 6.2.4 Reset register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

6.3 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

6.3.1 High-frequency internal RC oscillator (OSCHF) . . . . . . . . . . . . . . . . . . 42 6.3.2 High-frequency crystal oscillator (OSC24M) . . . . . . . . . . . . . . . . . . . . . 42 6.3.3 Low-frequency internal RC oscillator (OSCRC) . . . . . . . . . . . . . . . . . . . 42 6.3.4 Low-frequency crystal oscillator (OSC32K) . . . . . . . . . . . . . . . . . . . . . . 42 6.3.5 Clock switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 6.3.6 Clock switching registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

6.4 System timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

6.4.1 Watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 6.4.2 Sleep timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 6.4.3 Event timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

6.4.4Slow timers (Watchdog and Sleeptimer) control and status registers . . 45

6.5 Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

6.5.1 Wake sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 6.5.2 Basic sleep modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 6.5.3 Further options for deep sleep . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 6.5.4 Use of debugger with sleep modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

6.6 Security accelerator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

7	Integrated voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		56
8	General-purpose input/outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		58
	8.1	Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	59

8.1.1 GPIO ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 8.1.2 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 8.1.3 Forced functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 8.1.4 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 8.1.5 nBOOTMODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 8.1.6 GPIO modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 8.1.7 Wake monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

8.2 External interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

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8.3 Debug control and status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 8.4 GPIO alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 8.5 General-purpose input / output (GPIO) registers . . . . . . . . . . . . . . . . . . . 67

8.5.1 Port x configuration register (Low) (GPIO_PxCFGL) . . . . . . . . . . . . . . . 67 8.5.2 Port x configuration register (High) (GPIO_PxCFGH) . . . . . . . . . . . . . . 67 8.5.3 Port x input data register (GPIO_PxIN) . . . . . . . . . . . . . . . . . . . . . . . . . 68 8.5.4 Port x output data register (GPIO_PxOUT) . . . . . . . . . . . . . . . . . . . . . . 69 8.5.5 Port x output clear register (GPIO_PxCLR) . . . . . . . . . . . . . . . . . . . . . . 69 8.5.6 Port x output set register (GPIO_PxSET) . . . . . . . . . . . . . . . . . . . . . . . 70 8.5.7 Port x wakeup monitor register (GPIO_PxWAKE) . . . . . . . . . . . . . . . . . 71 8.5.8 GPIO wakeup filtering register (GPIO_WAKEFILT) . . . . . . . . . . . . . . . . 71 8.5.9 Interrupt x select register (GPIO_IRQxSEL) . . . . . . . . . . . . . . . . . . . . . 72 8.5.10 GPIO interrupt x configuration register (GPIO_INTCFGx) . . . . . . . . . . . 73 8.5.11 GPIO interrupt flag register (INT_GPIOFLAG) . . . . . . . . . . . . . . . . . . . 73 8.5.12 GPIO debug configuration register (GPIO_DBGCFG) . . . . . . . . . . . . . . 74 8.5.13 GPIO debug status register (GPIO_DBGSTAT) . . . . . . . . . . . . . . . . . . . 75

9	Serial interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		76
	9.1	Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	76
	9.2	Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	77
	9.3	SPI master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	78

9.3.1 Setup and configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 9.3.2 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 9.3.3 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

9.4 SPI slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

82

9.4.1 Setup and configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 9.4.2 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 9.4.3 DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 9.4.4 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

9.5 Inter-integrated circuit interfaces (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

9.5.1 Setup and configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 9.5.2 Constructing frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 9.5.3 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

9.6	Universal asynchronous receiver / transmitter (UART) . . . . . . . . . . . . . .		89
	9.6.1	Setup and configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	90
	9.6.2	FIFOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	91

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9.6.3	RTS/CTS flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . 92
9.6.4	DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . 93
9.6.5	Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . 93

9.7 Direct memory access (DMA) channels . . . . . . . . . . . . . . . . . . . . . . . . . . 93 9.8 Serial controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

9.8.1 Serial mode register (SCx_MODE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 9.8.2 Serial controller interrupt flag register (INT_SCxFLAG) . . . . . . . . . . . . 95 9.8.3 Serial controller interrupt configuration register (INT_SCxCFG) . . . . . . 96 9.8.4 Serial controller interrupt mode register (SCx_INTMODE) . . . . . . . . . . 97

9.9 SPI master mode registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

9.9.1 Serial data register (SCx_DATA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 9.9.2 SPI configuration register (SCx_SPICFG) . . . . . . . . . . . . . . . . . . . . . . . 98 9.9.3 SPI status register (SCx_SPISTAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 9.9.4 Serial clock linear prescaler register (SCx_RATELIN) . . . . . . . . . . . . . . 99 9.9.5 Serial clock exponential prescaler register (SCx_RATEEXP) . . . . . . . 100

9.10 SPI slave mode registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 9.11 Inter-integrated circuit (I2C) interface registers . . . . . . . . . . . . . . . . . . . 100

9.11.1 I2C status register (SCx_TWISTAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 9.11.2 I2C control 1 register (SCx_TWICTRL1) . . . . . . . . . . . . . . . . . . . . . . . 101 9.11.3 I2C control 2 register (SCx_TWICTRL2) . . . . . . . . . . . . . . . . . . . . . . . 101

9.12 Universal asynchronous receiver / transmitter (UART) registers . . . . . . 102

9.12.1 UART status register (SC1_UARTSTAT) . . . . . . . . . . . . . . . . . . . . . . . 102 9.12.2 UART configuration register (SC1_UARTCFG) . . . . . . . . . . . . . . . . . . 103 9.12.3 UART baud rate period register (SC1_UARTPER) . . . . . . . . . . . . . . . 104 9.12.4 UART baud rate fractional period register (SC1_UARTFRAC) . . . . . . 104

9.13 DMA channel registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

9.13.1	Serial DMA control register (SCx_DMACTRL) . . . . . . . . . . . . . . . . . .	105
9.13.2	Serial DMA status register (SCx_DMASTAT) . . . . . . . . . . . . . . . . . . .	106
9.13.3	Transmit DMA begin address register A (SCx_TXBEGA) . . . . . . . . . .	107
9.13.4	Transmit DMA begin address register B (SCx_TXBEGB) . . . . . . . . . .	107
9.13.5	Transmit DMA end address register A (SCx_TXENDA) . . . . . . . . . . .	108
9.13.6	Transmit DMA end address register B (SCx_TXENDB) . . . . . . . . . . .	108
9.13.7	Transmit DMA count register (SCx_TXCNT) . . . . . . . . . . . . . . . . . . . .	109
9.13.8	Receive DMA begin address register A (SCx_RXBEGA) . . . . . . . . . .	110
9.13.9	Receive DMA begin address register B (SCx_RXBEGB) . . . . . . . . . .	110
9.13.10	Receive DMA end address register A (SCx_RXENDA) . . . . . . . . . . . .	111

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		9.13.11	Receive DMA end address register B (SCx_RXENDB) . . . . . . . . . . .	. 111
		9.13.12	Receive DMA count register A (SCx_RXCNTA) . . . . . . . . . . . . . . . . .	112
		9.13.13	Receive DMA count register B (SCx_RXCNTB) . . . . . . . . . . . . . . . . .	112
		9.13.14	Saved receive DMA count register (SCx_RXCNTSAVED) . . . . . . . . .	113
		9.13.15	DMA first receive error register A (SCx_RXERRA) . . . . . . . . . . . . . . .	114
		9.13.16	DMA first receive error register B (SCx_RXERRB) . . . . . . . . . . . . . . .	114
10	General-purpose timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			115
	10.1	Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		117
		10.1.1	Time-base unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	117
		10.1.2	Counter modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	119
		10.1.3	Clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	125
		10.1.4	Capture/compare channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	128
		10.1.5	Input capture mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	130
		10.1.6	PWM input mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	131
		10.1.7	Forced output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	132
		10.1.8	Output compare mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	132
		10.1.9	PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	133
		10.1.10	One-pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	136
		10.1.11	Encoder interface mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	138
		10.1.12	Timer input XOR function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	140
		10.1.13	Timers and external trigger synchronization . . . . . . . . . . . . . . . . . . . .	141
		10.1.14	Timer synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	145
		10.1.15	Timer signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	150
	10.2	Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		151
	10.3 General-purpose timer (1 and 2) registers . . . . . . . . . . . . . . . . . . . . . . .			151
		10.3.1	Timer x control register 1 (TIMx_CR1) . . . . . . . . . . . . . . . . . . . . . . . .	151
		10.3.2	Timer x control register 2 (TIMx_CR2) . . . . . . . . . . . . . . . . . . . . . . . .	153
		10.3.3	Timer x slave mode control register (TIMx_SMCR) . . . . . . . . . . . . . . .	154
		10.3.4	Timer x event generation register (TIMx_EGR) . . . . . . . . . . . . . . . . . .	156
		10.3.5	Timer x capture/compare mode register 1 (TIMx_CCMR1) . . . . . . . . .	157
		10.3.6	Timer x capture/compare mode register 2 (TIMx_CCMR2) . . . . . . . . .	160
		10.3.7	Timer x capture/compare enable register (TIMx_CCER) . . . . . . . . . . .	163
		10.3.8	Timer x counter register (TIMx_CNT) . . . . . . . . . . . . . . . . . . . . . . . . .	164
		10.3.9	Timer x prescaler register (TIMx_PSC) . . . . . . . . . . . . . . . . . . . . . . . .	165
		10.3.10	Timer x auto-reload register (TIMx_ARR) . . . . . . . . . . . . . . . . . . . . . .	165
		10.3.11	Timer x capture/compare 1 register (TIMx_CCR1) . . . . . . . . . . . . . . .	166

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	10.3.12 Timer x capture/compare 2 register (TIMx_CCR2) . . . . . . . . . .	. . . . . 166
	10.3.13 Timer x capture/compare 3 register (TIMx_CCR3) . . . . . . . . . . .	. . . . 167
	10.3.14 Timer x capture/compare 4 register (TIMx_CCR4) . . . . . . . . . . .	. . . . 167
	10.3.15 Timer 1 option register (TIM1_OR) . . . . . . . . . . . . . . . . . . . . . . .	. . . . 168
	10.3.16 Timer 2 option register (TIM2_OR) . . . . . . . . . . . . . . . . . . . . . . .	. . . . 169
	10.3.17 Timer x interrupt configuration register (INT_TIMxCFG) . . . . . . .	. . . . 170
	10.3.18 Timer x interrupt flag register (INT_TIMxFLAG) . . . . . . . . . . . . .	. . . . 170
	10.3.19 Timer x missed interrupt register (INT_TIMxMISS) . . . . . . . . . . .	. . . . 171
11	Analog-to-digital converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . 172
	11.1 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . 173

11.1.1 Setup and configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 11.1.2 GPIO usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 11.1.3 Voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 11.1.4 Offset/gain correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 11.1.5 DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 11.1.6 ADC configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 11.1.7 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 11.1.8 Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178

11.2 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 11.3 Analog-to-digital converter (ADC) registers . . . . . . . . . . . . . . . . . . . . . . 180

11.3.1	ADC configuration register (ADC_CFG) . . . . . . . . . . . . . . . . . . . . . . .	180
11.3.2	ADC offset register (ADC_OFFSET) . . . . . . . . . . . . . . . . . . . . . . . . . .	181
11.3.3	ADC gain register (ADC_GAIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	181
11.3.4	ADC DMA configuration register (ADC_DMACFG) . . . . . . . . . . . . . . .	182
11.3.5	ADC DMA status register (ADC_DMASTAT) . . . . . . . . . . . . . . . . . . . .	182
11.3.6	ADC DMA begin address register (ADC_DMABEG) . . . . . . . . . . . . . .	183
11.3.7	ADC DMA buffer size register (ADC_DMASIZE) . . . . . . . . . . . . . . . . .	183
11.3.8	ADC DMA current address register (ADC_DMACUR) . . . . . . . . . . . . .	184
11.3.9	ADC DMA count register (ADC_DMACNT) . . . . . . . . . . . . . . . . . . . . .	184
11.3.10	ADC interrupt flag register (INT_ADCFLAG) . . . . . . . . . . . . . . . . . . . .	185
11.3.11	ADC interrupt configuration register (INT_ADCCFG) . . . . . . . . . . . . .	185

12 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186

12.1 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 186

12.1.1 Non-maskable interrupt (NMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 12.1.2 Faults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189

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12.2	Event manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	189
12.3	Nested vectored interrupt controller (NVIC) interrupts . . . . . . . . . . . . . .	193
	12.3.1 Top-level set interrupts configuration register (INT_CFGSET) . . . . . .	193
	12.3.2 Top-level clear interrupts configuration register (INT_CFGCLR) . . . . .	194
	12.3.3 Top-level set interrupts pending register (INT_PENDSET) . . . . . . . . .	195
	12.3.4 Top-level clear interrupts pending register (INT_PENDCLR) . . . . . . . .	196
	12.3.5 Top-level active interrupts register (INT_ACTIVE) . . . . . . . . . . . . . . . .	197
	12.3.6 Top-level missed interrupts register (INT_MISS) . . . . . . . . . . . . . . . . .	198
	12.3.7 Auxiliary fault status register (SCS_AFSR) . . . . . . . . . . . . . . . . . . . . .	199

13	Debug support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		200
	13.1	STM32W108 JTAG TAP connection . . . . . . . . . . . . . . . . . . . . . . . . . . . .	201
14	Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		202
	14.1	Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	202

14.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 14.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 14.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 14.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 14.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202

14.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 14.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204

14.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 14.3.2 Operating conditions at power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 14.3.3 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 205

14.4 ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 14.5 Clock frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211

14.5.1 High frequency internal clock characteristics . . . . . . . . . . . . . . . . . . . . 211 14.5.2 High frequency external clock characteristics . . . . . . . . . . . . . . . . . . . 211 14.5.3 Low frequency internal clock characteristics . . . . . . . . . . . . . . . . . . . . 212 14.5.4 Low frequency external clock characteristics . . . . . . . . . . . . . . . . . . . . 212

14.6 DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 14.7 Digital I/O specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 14.8 Non-RF system electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . 219 14.9 RF electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219

14.9.1 Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219

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14.9.2 Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220

14.9.3 Synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221

15	Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	222
16	Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	227
17	Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	228

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Description	STM32W108HB STM32W108CC STM32W108CB STM32W108CZ

1 Description

The STM32W108 is a fully integrated System-on-Chip that integrates a 2.4 GHz, IEEE 802.15.4-compliant transceiver, 32-bit ARM® Cortex™-M3 microprocessor, Flash and RAM memory, and peripherals of use to designers of 802.15.4-based systems.

Figure 1. STM32W108 block diagram

					Data SRAM	ProgramFlash
					8 kBytes	128 kBytes
				TX_ACTIVE	12 kBytes	192 kBytes
	PA select				16 kBytes	256 kBytes
RF_TX_ALT_P,N	PA	SYNTH	DAC
				MAC	ARM CORTEX-M3®	2nd level
	PA				CPU with NVIC	Interrupt
				+
					and MPU	controller
RF_P,N	LNA	IF	ADC	Baseband
				PacketTracesniffer	CPU debug
BIAS_R	Bias					Encryption
					TPIU/ITM/
				General	FPB/DWT	acclerator
OSCA
	HF crystal	Internal HF	Calibration	purpose	Always
				timers
OSCB	OSC	RC-OSC	ADC		Powered
						Serial	SWCLK,
					Domain
				GPIO		Wire and	JTCK
VREG_OUT	Regulator			registers	Watchdog	JTAG
			General			debug
nRESET	POR		Purpose	UART/
			ADC
	LF crystal	Internal LF		SPI/I2C	Chip	Sleep
					manager	timer
	OSC	RC-OSC

GPIO multiplexor swtich

PA[7:0], PB[7:0], PC[7:0]

!I

The transceiver utilizes an efficient architecture that exceeds the dynamic range requirements imposed by the IEEE 802.15.4-2003 standard by over 15 dB. The integrated receive channel filtering allows for robust co-existence with other communication standards in the 2.4 GHz spectrum, such as IEEE 802.11 and Bluetooth. The integrated regulator, VCO, loop filter, and power amplifier keep the external component count low. An optional high performance radio mode (boost mode) is software-selectable to boost dynamic range.

The integrated 32-bit ARM® Cortex™-M3 microprocessor is highly optimized for high performance, low power consumption, and efficient memory utilization. Including an integrated MPU, it supports two different modes of operation: Privileged mode and Unprivileged mode. This architecture could be used to separate the networking stack from the application code and prevent unwanted modification of restricted areas of memory and registers resulting in increased stability and reliability of deployed solutions.

The STM32W108 has 128/192/256 Kbytes of embedded Flash memory and 8/12/16 Kbytes of integrated RAM for data and program storage. The STM32W108 HAL software employs an effective wear-leveling algorithm that optimizes the lifetime of the embedded Flash.

To maintain the strict timing requirements imposed by the ZigBee and IEEE 802.15.4-2003 standards, the STM32W108 integrates a number of MAC functions into the hardware. The MAC hardware handles automatic ACK transmission and reception, automatic backoff delay, and clear channel assessment for transmission, as well as automatic filtering of

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received packets. A packet trace interface is also integrated with the MAC, allowing complete, non-intrusive capture of all packets to and from the STM32W108.

The STM32W108 offers a number of advanced power management features that enable long battery life. A high-frequency internal RC oscillator allows the processor core to begin code execution quickly upon waking. Various deep sleep modes are available with less than 1 µA power consumption while retaining RAM contents. To support user-defined applications, on-chip peripherals include UART, SPI, I2C, ADC and general-purpose timers, as well as up to 24 GPIOs. Additionally, an integrated voltage regulator, power-on-reset circuit, and sleep timer are available.

1.1Development tools

The STM32W108 implements both the ARM Serial Wire and JTAG debug interfaces. These interfaces provide real time, non-intrusive programming and debugging capabilities. Serial Wire and JTAG provide the same functionality, but are mutually exclusive. The Serial Wire interface uses two pins; the JTAG interface uses five. Serial Wire is preferred, since it uses fewer pins.

The STM32W108 also integrates the standard ARM system debug components: Flash Patch and Breakpoint (FPB), Data Watchpoint and Trace (DWT), and Instrumentation Trace Macrocell (DWT).

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1.2Overview

1.2.1Functional description

The STM32W108 radio receiver is a low-IF, super-heterodyne receiver. The architecture has been chosen to optimize co-existence with other devices in the 2.4 GHz band (namely, WIFI and Bluetooth), and to minimize power consumption. The receiver uses differential signal paths to reduce sensitivity to noise interference. Following RF amplification, the signal is downconverted by an image-rejecting mixer, filtered, and then digitized by an ADC.

The radio transmitter uses an efficient architecture in which the data stream directly modulates the VCO frequency. An integrated power amplifier (PA) provides the output power. Digital logic controls Tx path and output power calibration. If the STM32W108 is to be used with an external PA, use the TX_ACTIVE or nTX_ACTIVE signal to control the timing of the external switching logic.

The integrated 4.8 GHz VCO and loop filter minimize off-chip circuitry. Only a 24 MHz crystal with its loading capacitors is required to establish the PLL local oscillator signal.

The MAC interfaces the on-chip RAM to the Rx and Tx baseband modules. The MAC provides hardware-based IEEE 802.15.4 packet-level filtering. It supplies an accurate symbol time base that minimizes the synchronization effort of the software stack and meets the protocol timing requirements. In addition, it provides timer and synchronization assistance for the IEEE 802.15.4 CSMA-CA algorithm.

The STM32W108 integrates an ARM® Cortex-M3 microprocessor, revision r1p1. This industry-leading core provides 32 bit performance and is very power efficient. It has excellent code density using the ARM® Thumb 2 instruction set. The processor can be operated at 12 MHz or 24 MHz when using the crystal oscillator, or at 6 MHz or 12 MHz when using the integrated high frequency RC oscillator.

The STM32W108 has 128/192/256 Kbytes of Flash memory, 8/12/16 Kbytes of SRAM onchip, and the ARM configurable memory protection unit (MPU).

The STM32W108 contains 24 GPIO pins shared with other peripheral or alternate functions. Because of flexible routing within the STM32W108, external devices can use the alternate functions on a variety of different GPIOs. The integrated Serial Controller SC1 can be configured for SPI (master or slave), I2C (master-only), or UART operation, and the Serial Controller SC2 can be configured for SPI (master or slave) or I2C (master-only) operation.

The STM32W108 has a general purpose ADC which can sample analog signals from six GPIO pins in single-ended or differential modes. It can also sample the regulated supply VDD_PADSA, the voltage reference VREF, and GND. The ADC has two selectable voltage ranges: 0 V to 1.2 V (normal) and 0.1 V to 0.1 V below the high voltage supply (high). The ADC has a DMA mode to capture samples and automatically transfer them into RAM. The integrated voltage reference for the ADC, VREF, can be made available to external circuitry. An external voltage reference can also be driven into the ADC.

The STM32W108 contains four oscillators: a high frequency 24 MHz external crystal oscillator, a high frequency 12 MHz internal RC oscillator, an optional low frequency 32.768 kHz external crystal oscillator, and a 10 kHz internal RC oscillator.

The STM32W108 has an ultra low power, deep sleep state with a choice of clocking modes. The sleep timer can be clocked with either the external 32.768 kHz crystal oscillator or with a 1 kHz clock derived from the internal 10 kHz RC oscillator. Alternatively, all clocks can be disabled for the lowest power mode. In the lowest power mode, only external events on

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	GPIO pins will wake up the chip. The STM32W108 has a fast startup time (typically 100 µs)
	from deep sleep to the execution of the first ARM® Cortex-M3 instruction.
	The STM32W108 contains three power domains. The always-on high voltage supply powers
	the GPIO pads and critical chip functions. Regulated low voltage supplies power the rest of
	the chip. The low voltage supplies are be disabled during deep sleep to reduce power
	consumption. Integrated voltage regulators generate regulated 1.25 V and 1.8 V voltages
	from an unregulated supply voltage. The 1.8 V regulator output is decoupled and routed
	externally to supply analog blocks, RAM, and Flash memories. The 1.25 V regulator output
	is decoupled externally and supplies the core logic.
	The digital section of the receiver uses a coherent demodulator to generate symbols for the
	hardware-based MAC. The digital receiver also contains the analog radio calibration
	routines and controls the gain within the receiver path.
	In addition to 2 general-purpose timers, the STM32W108 also contains a watchdog timer to
	ensure protection against software crashes and CPU lockup, a 32-bit sleep timer dedicated
	to system timing and waking from sleep at specific times and an ARM® standard system
	event timer in the NVIC.
	The STM32W108 integrates hardware support for a Packet Trace module, which allows
	robust packet-based debug.
Note:	The STM32W108 is not pin-compatible with the previous generation chip, the SN250,
	except for the RF section of the chip. Pins 1-11 and 45-48 are compatible, to ease migration
	to the STM32W108.
1.2.2	ARM® Cortex™-M3 core
	The STM32W108 integrates the ARM® Cortex™-M3 microprocessor, revision r1p1,

developed by ARM Ltd, making the STM32W108 a true system-on-a-chip solution. The ARM® Cortex-M3 is an advanced 32-bit modified Harvard architecture processor that has separate internal program and data buses, but presents a unified program and data address space to software. The word width is 32 bits for both the program and data sides. The ARM® Cortex-M3 allows unaligned word and half-word data accesses to support efficientlypacked data structures.

The ARM® Cortex-M3 clock speed is configurable to 6 MHz, 12 MHz, or 24 MHz. For normal operation 12 MHz is preferred over 24 MHz due to its lower power consumption. The 6 MHz operation can only be used when radio operations are not required since the radio requires an accurate 12 MHz clock.

The ARM® Cortex-M3 in the STM32W108 has also been enhanced to support two separate memory protection levels. Basic protection is available without using the MPU, but the usual operation uses the MPU. The MPU protects unimplemented areas of the memory map to prevent common software bugs from interfering with software operation. The architecture could also separate the networking stack from the application code using a fine granularity RAM protection module. Errant writes are captured and details are reported to the developer to assist in tracking down and fixing issues.

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Documentation conventions	STM32W108HB STM32W108CC STM32W108CB STM32W108CZ

2 Documentation conventions

	Table 1.	Description of abbreviations used for bitfield access
	Abbreviation		Description(1)
	Read/Write (rw)		Software can read and write to these bits.
	Read-only (r)		Software can only read these bits.
	Write only (w)		Software can only write to this bit. Reading returns the reset value.
	Read/Write in (MPU)		Software can read and write to these bits only in Privileged mode. For
			more information, please refer to RAM memory protection on page 30
	Privileged mode only (rws)
			and Memory protection unit on page 31.

1.The conditions under which the hardware (core) sets or clears this field are explained in details in the bitfield description, as well as the events that may be generated by writing to the bit.

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3 Pinout and pin description

Figure 2. 48-pin VFQFPN pinout

CASO

CBSO

YNTHS VDD

PRE VDD

CORE VDD

KSTIM1M TIM2CLK, ADC0, PB5,

TIM1C1 IRQ6, ADC1, PB6,

TIM1C2 IRQC, ADC2, PB7,

TRACEDATA1 IRQDn, T,SJR PC0,

MEM VDD

TRACEDATA0 WO,S ,3ADC PC1,

SPAD VDD

	48	47	46	45	44	43	42	41	40	39	38	37
VDD_24MHZ	1											36
VDD_VCO	2											35
RF_P	3											34
RF_N	4											33
VDD_RF	5											32
RF_TX_ALT_P	6											31
RF_TX_ALT_N	7											30
VDD_IF	8											29
BIAS_R	9											28
VDD_PADSA	10											27
PC5, TX_ACTIVE	11											26
nRESET	12						Ground pad on back
												25
	13	14	15	16	17	18	19	20	21	22	23	24
	ACTIVE nTX 2B,3CSO PC6,	EXT 23CSO 2A,3CSO PC7,	OUT VREG	SPAD VDD	CORE VDD	EN REG TIM1C4, PA7,	CLKSC1S ,SC1nCTS ,3TIM2C ,3PB	ELSSC1nS ,SC1nRTS TIM2C4, PB4,	ISC2MOS TIM2C1, PA0,	OSC2MIS DA,SC2S ,3TIM2C PA1,	SPAD VDD	CLKSC2S CL,SC2S TIM2C4, PA2,

PB0, VREF, IRQA, TRACECLK, TIM1CLK, TIM2MSK PC4, JTMS, SWDIO

PC3, JTDI

PC2, JTDO, SWO

SWCLK, JTCK

PB2, SC1MISO, SC1MOSI, SC1SCL, SC1RXD, TIM2C2 PB1, SC1MISO, SC1MOSI, SC1SDA, SC1TXD, TIM2C1 PA6, TIM1C3

VDD_PADS

PA5, ADC5, PTI_DATA, nBOOTMODE, TRACEDATA3

PA4, ADC4, PTI_EN, TRACEDATA2

PA3, SC2nSSEL, TRACECLK, TIM2C2

Ai15261

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Pinout and pin description	STM32W108HB STM32W108CC STM32W108CB STM32W108CZ

Figure 3. 40-pin VFQFPN pinout

	24MHZ VDD	CASO	CBSO	PRE VDD	CORE VDD	TIM1C1 IRQ6, ADC1, PB6,	TIM1C2 IRQC, ADC2, PB7,	TRACEDATA1 IRQDn, T,SJR PC0,	MEM VDD	TRACEDATA0 WO,S ,3ADC PC1,
	40	39	38	37	36	35	34	33	32	31
VDD_VCO	1										30	PC4, JTMS, SWDIO
RF_P	2										29	PC3, JTDI
RF_N	3										28	PC2, JTDO, SWO
VDD_RF	4										27	SWCLK, JTCK
RF_TX_ALT_P	5										26	PB2, SC1MISO, SC1MOSI, SC1SCL, SC1RXD, TIM2C2
RF_TX_ALT_N	6										25	PB1, SC1MISO, SC1MOSI, SC1SDA, SC1TXD, TIM2C1
VDD_IF	7										24	VDD_PADS
BIAS_R	8										23	PA5, ADC5, PTI_DATA, nBOOTMODE, TRACEDATA3
VDD_PADSA	9										22	PA4, ADC4, PTI_EN, TRACEDATA2
PC5, TX_ACTIVE	10					Ground pad on back					21	PA3, SC2nSSEL, TRACECLK, TIM2C2
	11	12	13	14	15	16	17	18	19	20
	ETSnRE	OUT VREG	SPAD VDD	CORE VDD	,3TIM2C ,3PB	TIM2C4, PB4,	TIM2C1, PA0,	,3TIM2C PA1,	SPAD VDD	TIM2C4, PA2,
					CLKSC1S ,SC1nCTS	ELSSC1nS ,SC1nRTS	ISC2MOS	OSC2MIS DA,SC2S		CLKSC2S CL,SC2S		Ai15260

Table 2.	Pin descriptions
48-Pin	40-Pin
Package	Package	Signal	Direction	Description
Pin no.	Pin no.
1	40	VDD_24MHZ	Power	1.8V high-frequency oscillator supply
2	1	VDD_VCO	Power	1.8V VCO supply
3	2	RF_P	I/O	Differential (with RF_N) receiver input/transmitter output
4	3	RF_N	I/O	Differential (with RF_P) receiver input/transmitter output
5	4	VDD_RF	Power	1.8V RF supply (LNA and PA)
6	5	RF_TX_ALT_P	O	Differential (with RF_TX_ALT_N) transmitter output (optional)
7	6	RF_TX_ALT_N	O	Differential (with RF_TX_ALT_P) transmitter output (optional)
8	7	VDD_IF	Power	1.8V IF supply (mixers and filters)
9	8	BIAS_R	I	Bias setting resistor

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STM32W108HB STM32W108CC STM32W108CB STM32W108CZ					Pinout and pin description
Table 2.	Pin descriptions (continued)
48-Pin	40-Pin
Package	Package	Signal	Direction	Description
Pin no.	Pin no.
10	9	VDD_PADSA	Power	Analog pad supply (1.8V)
		PC5	I/O	Digital I/O
11	10			Logic-level control for external Rx/Tx switch. The
		TX_ACTIVE	O	STM32W108 baseband controls TX_ACTIVE and drives it
				high (VDD_PADS) when in Tx mode.
				Select alternate output function with GPIO_PCCFGH[7:4]
12	11	nRESET	I	Active low chip reset (internal pull-up)
		PC6	I/O	Digital I/O
		OSC32B	I/O	32.768 kHz crystal oscillator
13				Select analog function with GPIO_PCCFGH[11:8]
		nTX_ACTIVE	O	Inverted TX_ACTIVE signal (see PC5)
				Select alternate output function with GPIO_PCCFGH[11:8]
		PC7	I/O	Digital I/O
14		OSC32A	I/O	32.768 kHz crystal oscillator.
				Select analog function with GPIO_PCCFGH[15:12]
		OSC32_EXT	I	Digital 32 kHz clock input source
15	12	VREG_OUT	Power	Regulator output (1.8 V while awake, 0 V during deep sleep)
16	13	VDD_PADS	Power	Pads supply (2.1-3.6 V)
17	14	VDD_CORE	Power	1.25 V digital core supply decoupling
			I/O
		PA7	High	Digital I/O. Disable REG_EN with GPIO_DBGCFG[4]
			current
				Timer 1 Channel 4 output
18			O	Enable timer output with TIM1_CCER
				Select alternate output function with GPIO_PACFGH[15:12]
		TIM1_CH4
				Disable REG_EN with GPIO_DBGCFG[4]
			I	Timer 1 Channel 4 input. (Cannot be remapped.)
		REG_EN	O	External regulator open drain output. (Enabled after reset.)

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Pinout and pin description			STM32W108HB STM32W108CC STM32W108CB STM32W108CZ
Table 2.	Pin descriptions (continued)
48-Pin	40-Pin
Package	Package	Signal	Direction	Description
Pin no.	Pin no.
		PB3	I/O	Digital I/O
				Timer 2 channel 3 output
		TIM2_CH3	O	Enable remap with TIM2_OR[6]
				Enable timer output in TIM2_CCER
		(see Pin 22)
				Select alternate output function with GPIO_PBCFGL[15:12]
			I	Timer 2 channel 3 input. Enable remap with TIM2_OR[6].
				UART CTS handshake of Serial Controller 1
		UART_CTS	I	Enable with SC1_UARTCFG[5]
19	15			Select UART with SC1_MODE
				SPI master clock of Serial Controller 1
				Either disable timer output in TIM2_CCER or disable remap
			O	with TIM2_OR[6]
				Enable master with SC1_SPICFG[4]
		SC1SCLK		Select SPI with SC1_MODE
				Select alternate output function with GPIO_PBCFGL[15:12]
				SPI slave clock of Serial Controller 1
			I	Enable slave with SC1_SPICFG[4]
				Select SPI with SC1_MODE
		PB4	I/O	Digital I/O
				Timer 2 channel 4 output
		TIM2_CH4	O	Enable remap with TIM2_OR[7]
				Enable timer output in TIM2_CCER
		(see also
				Select alternate output function with GPIO_PBCFGH[3:0]
		Pin 24)
			I	Timer 2 channel 4 input. Enable remap with TIM2_OR[7].
20	16			UART RTS handshake of Serial Controller 1
				Either disable timer output in TIM2_CCER or disable remap
		UART_RTS	O	with TIM2_OR[7]
				Enable with SC1_UARTCFG[5]
				Select UART with SC1_MODE
				Select alternate output function with GPIO_PBCFGH[3:0]
				SPI slave select of Serial Controller 1
		SC1nSSEL	I	Enable slave with SC1_SPICFG[4]
				Select SPI with SC1_MODE

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STM32W108HB STM32W108CC STM32W108CB STM32W108CZ					Pinout and pin description
Table 2.	Pin descriptions (continued)
48-Pin	40-Pin
Package	Package	Signal	Direction	Description
Pin no.	Pin no.
		PA0	I/O	Digital I/O
				Timer 2 channel 1 output
		TIM2_CH1	O	Disable remap with TIM2_OR[4]
				Enable timer output in TIM2_CCER
		(see also
				Select alternate output function with GPIO_PACFGL[3:0]
		Pin 30)
			I	Timer 2 channel 1 input. Disable remap with TIM2_OR[4].
21	17			SPI master data out of Serial Controller 2
				Either disable timer output in TIM2_CCER or enable remap
			O	with TIM2_OR[4]
				Enable master with SC2_SPICFG[4]
		SC2MOSI		Select SPI with SC2_MODE
				Select alternate output function with GPIO_PACFGL[3:0]
				SPI slave data in of Serial Controller 2
			I	Enable slave with SC2_SPICFG[4]
				Select SPI with SC2_MODE
		PA1	I/O	Digital I/O
				Timer 2 channel 3 output
		TIM2_CH3	O	Disable remap with TIM2_OR[6]
				Enable timer output in TIM2_CCER
		(see also
				Select alternate output function with GPIO_PACFGL[7:4]
		Pin 19)
			I	Timer 2 channel 3 input. Disable remap with TIM2_OR[6].
				I2C data of Serial Controller 2
				Either disable timer output in TIM2_CCER or enable remap
		SC2SDA	I/O	with TIM2_OR[6]
				Select I2C with SC2_MODE
22	18
				Select alternate open-drain output function with
				GPIO_PACFGL[7:4]
				SPI slave data out of Serial Controller 2
				Either disable timer output in TIM2_CCER or enable remap
			O	with TIM2_OR[6]
				Enable slave with SC2_SPICFG[4]
		SC2MISO		Select SPI with SC2_MODE
				Select alternate output function with GPIO_PACFGL[7:4]
				SPI master data in of Serial Controller 2
			I	Enable slave with SC2_SPICFG[4]
				Select SPI with SC2_MODE
23	19	VDD_PADS	Power	Pads supply (2.1-3.6V)

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Pinout and pin description			STM32W108HB STM32W108CC STM32W108CB STM32W108CZ
Table 2.	Pin descriptions (continued)
48-Pin	40-Pin
Package	Package	Signal	Direction	Description
Pin no.	Pin no.
		PA2	I/O	Digital I/O
				Timer 2 channel 4 output
		TIM2_CH4	O	Disable remap with TIM2_OR[7]
				Enable timer output in TIM2_CCER
		(see also
				Select alternate output function with GPIO_PACFGL[11:8]
		Pin 20)
			I	Timer 2 channel 4 input. Disable remap with TIM2_OR[7].
				I2C clock of Serial Controller 2
				Either disable timer output in TIM2_CCER or enable remap
		SC2SCL	I/O	with TIM2_OR[7]
				Select I2C with SC2_MODE
24	20
				Select alternate open-drain output function with
				GPIO_PACFGL[11:8]
				SPI master clock of Serial Controller 2
				Either disable timer output in TIM2_CCER or enable remap
			O	with TIM2_OR[7]
				Enable master with SC2_SPICFG[4]
		SC2SCLK		Select SPI with SC2_MODE
				Select alternate output function with GPIO_PACFGL[11:8]
				SPI slave clock of Serial Controller 2
			I	Enable slave with SC2_SPICFG[4]
				Select SPI with SC2_MODE
		PA3	I/O	Digital I/O
				SPI slave select of Serial Controller 2
		SC2nSSEL	I	Enable slave with SC2_SPICFG[4]
				Select SPI with SC2_MODE
				Synchronous CPU trace clock
		TRACECLK		Either disable timer output in TIM2_CCER or enable remap
25	21	(see also Pin	O	with TIM2_OR[5]
		36)		Enable trace interface in ARM core
				Select alternate output function with GPIO_PACFGL[15:12]
				Timer 2 channel 2 output
		TIM2_CH2	O	Disable remap with TIM2_OR[5]
				Enable timer output in TIM2_CCER
		(see also Pin
				Select alternate output function with GPIO_PACFGL[15:12]
		31)
			I	Timer 2 channel 2 input. Disable remap with TIM2_OR[5].

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STM32W108HB STM32W108CC STM32W108CB STM32W108CZ					Pinout and pin description
Table 2.	Pin descriptions (continued)
48-Pin	40-Pin
Package	Package	Signal	Direction		Description
Pin no.	Pin no.
		PA4	I/O	Digital I/O
		ADC4	Analog	ADC Input 4. Select analog function with
				GPIO_PACFGH[3:0].
				Frame signal of Packet Trace Interface (PTI).
26	22	PTI_EN	O	Disable trace interface in ARM core.
				Select alternate output function with GPIO_PACFGH[3:0].
				Synchronous CPU trace data bit 2.
		TRACEDATA2	O	Select 4-wire synchronous trace interface in ARM core.
				Enable trace interface in ARM core.
				Select alternate output function with GPIO_PACFGH[3:0].
		PA5	I/O	Digital I/O
		ADC5	Analog	ADC Input 5. Select analog function with
				GPIO_PACFGH[7:4].
				Data signal of Packet Trace Interface (PTI).
		PTI_DATA	O	Disable trace interface in ARM core.
				Select alternate output function with GPIO_PACFGH[7:4].
27	23
				Embedded serial bootloader activation out of reset.
		nBOOTMODE	I	Signal is active during and immediately after a reset on NRST.
				See Section 6.2: Resets on page 37 for details.
				Synchronous CPU trace data bit 3.
		TRACEDATA3	O	Select 4-wire synchronous trace interface in ARM core.
				Enable trace interface in ARM core.
				Select alternate output function with GPIO_PACFGH[7:4]
28	24	VDD_PADS	Power	Pads supply (2.1-3.6 V)
			I/O
		PA6	High	Digital I/O
			current
29				Timer 1 channel 3 output
		TIM1_CH3	O	Enable timer output in TIM1_CCER
				Select alternate output function with GPIO_PACFGH[11:8]
			I	Timer 1 channel 3 input (Cannot be remapped.)

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Pinout and pin description			STM32W108HB STM32W108CC STM32W108CB STM32W108CZ
Table 2.	Pin descriptions (continued)
48-Pin	40-Pin
Package	Package	Signal	Direction	Description
Pin no.	Pin no.
		PB1	I/O	Digital I/O
				SPI slave data out of Serial Controller 1
				Either disable timer output in TIM2_CCER or disable remap
		SC1MISO	O	with TIM2_OR[4]
				Select SPI with SC1_MODE
				Select slave with SC1_SPICR
				Select alternate output function with GPIO_PBCFGL[7:4]
				SPI master data out of Serial Controller 1
				Either disable timer output in TIM2_CCER or disable remap
		SC1MOSI	O	with TIM2_OR[4]
				Select SPI with SC1_MODE
				Select master with SC1_SPICR
				Select alternate output function with GPIO_PBCFGL[7:4]
				I2C data of Serial Controller 1
30	25			Either disable timer output in TIM2_CCER,
		SC1SDA	I/O	or disable remap with TIM2_OR[4]
				Select I2C with SC1_MODE
				Select alternate open-drain output function with
				GPIO_PBCFGL[7:4]
				UART transmit data of Serial Controller 1
				Either disable timer output in TIM2_CCER or disable remap
		SC1TXD	O	with TIM2_OR[4]
				Select UART with SC1_MODE
				Select alternate output function with GPIO_PBCFGL[7:4]
				Timer 2 channel 1 output
		TIM2_CH1	O	Enable remap with TIM2_OR[4]
				Enable timer output in TIM2_CCER
		(see also
				Select alternate output function with GPIO_PACFGL[7:4]
		Pin 21)
			I	Timer 2 channel 1 input. Disable remap with TIM2_OR[4].

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STM32W108HB STM32W108CC STM32W108CB STM32W108CZ					Pinout and pin description
Table 2.	Pin descriptions (continued)
48-Pin	40-Pin
Package	Package	Signal	Direction	Description
Pin no.	Pin no.
		PB2	I/O	Digital I/O
				SPI master data in of Serial Controller 1
		SC1MISO	I	Select SPI with SC1_MODE
				Select master with SC1_SPICR
				SPI slave data in of Serial Controller 1
		SC1MOSI	I	Select SPI with SC1_MODE
				Select slave with SC1_SPICR
				I2C clock of Serial Controller 1
				Either disable timer output in TIM2_CCER,
31	26	SC1SCL	I/O	or disable remap with TIM2_OR[5]
				Select I2C with SC1_MODE
				Select alternate open-drain output function with
				GPIO_PBCFGL[11:8]
		SC1RXD	I	UART receive data of Serial Controller 1
				Select UART with SC1_MODE
				Timer 2 channel 2 output
		TIM2_CH2	O	Enable remap with TIM2_OR[5]
				Enable timer output in TIM2_CCER
		(see also Pin
				Select alternate output function with GPIO_PBCFGL[11:8]
		25)
			I	Timer 2 channel 2 input. Enable remap with TIM2_OR[5].
				Serial Wire clock input/output with debugger
		SWCLK	I/O	Selected when in Serial Wire mode (see JTMS description,
				Pin 35)
32	27
				JTAG clock input from debugger
		JTCK	I	Selected when in JTAG mode (default mode, see JTMS
				description, Pin 35)
				Internal pull-down is enabled
		PC2	I/O	Digital I/O
				Enable with GPIO_DBGCFG[5]
				JTAG data out to debugger
		JTDO	O	Selected when in JTAG mode (default mode, see JTMS
				description, Pin 35)
33	28
				Serial Wire Output asynchronous trace output to debugger
				Select asynchronous trace interface in ARM core
		SWO	O	Enable trace interface in ARM core
				Select alternate output function with GPIO_PCCFGL[11:8]
				Enable Serial Wire mode (see JTMS description, Pin 35)
				Internal pull-up is enabled

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Pinout and pin description			STM32W108HB STM32W108CC STM32W108CB STM32W108CZ
Table 2.	Pin descriptions (continued)
48-Pin	40-Pin
Package	Package	Signal	Direction	Description
Pin no.	Pin no.
				Digital I/O
		PC3	I/O	Either Enable with GPIO_DBGCFG[5],
				or enable Serial Wire mode (see JTMS description)
34	29
				JTAG data in from debugger
		JTDI	I	Selected when in JTAG mode (default mode, see JTMS
				description, Pin 35)
				Internal pull-up is enabled
		PC4	I/O	Digital I/O
				Enable with GPIO_DBGCFG[5]
				JTAG mode select from debugger
				Selected when in JTAG mode (default mode)
		JTMS	I	JTAG mode is enabled after power-up or by forcing NRST low
				Select Serial Wire mode using the ARM-defined protocol
35	30			through a debugger
				Internal pull-up is enabled
				Serial Wire bidirectional data to/from debugger
				Enable Serial Wire mode (see JTMS description)
		SWDIO	I/O	Select Serial Wire mode using the ARM-defined protocol
				through a debugger
				Internal pull-up is enabled
		PB0	I/O	Digital I/O
		VREF	Analog O	ADC reference output.
				Enable analog function with GPIO_PBCFGL[3:0].
				ADC reference input.
		VREF	Analog I	Enable analog function with GPIO_PBCFGL[3:0].
				Enable reference output with an ST system function.
36
		IRQA	I	External interrupt source A.
		TRACECLK		Synchronous CPU trace clock.
		(see also Pin	O	Enable trace interface in ARM core.
		25)		Select alternate output function with GPIO_PBCFGL[3:0].
		TIM1CLK	I	Timer 1 external clock input.
		TIM2MSK	I	Timer 2 external clock mask input.
37		VDD_PADS	Power	Pads supply (2.1 to 3.6 V).

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	STM32W108HB STM32W108CC STM32W108CB STM32W108CZ					Pinout and pin description
	Table 2.	Pin descriptions (continued)
	48-Pin	40-Pin
	Package	Package	Signal	Direction	Description
	Pin no.	Pin no.
			PC1	I/O	Digital I/O
			ADC3	Analog	ADC Input 3
					Enable analog function with GPIO_PCCFGL[7:4]
			SWO		Serial Wire Output asynchronous trace output to debugger
					Select asynchronous trace interface in ARM core
			(see also Pin	O
	38	31			Enable trace interface in ARM core
			33)
					Select alternate output function with GPIO_PCCFGL[7:4]
					Synchronous CPU trace data bit 0
					Select 1-, 2- or 4-wire synchronous trace interface in ARM
			TRACEDATA0	O	core
					Enable trace interface in ARM core
					Select alternate output function with GPIO_PCCFGL[7:4]
	39	32	VDD_MEM	Power	1.8 V supply (flash, RAM)
				I/O	Digital I/O
					Either enable with GPIO_DBGCFG[5],
			PC0	High
					or enable Serial Wire mode (see JTMS description, Pin 35)
				current
					and disable TRACEDATA1
					JTAG reset input from debugger
			JRST	I	Selected when in JTAG mode (default mode, see JTMS
	40	33			description) and TRACEDATA1 is disabled
					Internal pull-up is enabled
			IRQD (1)	I	Default external interrupt source D
					Synchronous CPU trace data bit 1
			TRACEDATA1	O	Select 2- or 4-wire synchronous trace interface in ARM core
					Enable trace interface in ARM core
					Select alternate output function with GPIO_PCCFGL[3:0]
				I/O
			PB7	High	Digital I/O
				current
			ADC2	Analog	ADC Input 2
					Enable analog function with GPIO_PBCFGH[15:12]
	41	34
			IRQC (1)	I	Default external interrupt source C
					Timer 1 channel 2 output
			TIM1_CH2	O	Enable timer output in TIM1_CCER
					Select alternate output function with GPIO_PBCFGH[15:12]
				I	Timer 1 channel 2 input (Cannot be remapped)

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	Pinout and pin description			STM32W108HB STM32W108CC STM32W108CB STM32W108CZ
	Table 2.	Pin descriptions (continued)
	48-Pin	40-Pin
	Package	Package	Signal	Direction	Description
	Pin no.	Pin no.
				I/O
			PB6	High	Digital I/O
				current
			ADC1	Analog	ADC Input 1
					Enable analog function with GPIO_PBCFGH[11:8]
	42	35
			IRQB	I	External interrupt source B
					Timer 1 channel 1 output
			TIM1_CH1	O	Enable timer output in TIM1_CCER
					Select alternate output function with GPIO_PBCFGH[11:8]
				I	Timer 1 channel 1 input (Cannot be remapped)
			PB5	I/O	Digital I/O
			ADC0	Analog	ADC Input 0
	43				Enable analog function with GPIO_PBCFGH[7:4]
			TIM2CLK	I	Timer 2 external clock input
			TIM1MSK	I	Timer 2 external clock mask input
	44	36	VDD_CORE	Power	1.25 V digital core supply decoupling
	45	37	VDD_PRE	Power	1.8 V prescaler supply
	46		VDD_SYNTH	Power	1.8 V synthesizer supply
	47	38	OSCB	I/O	24 MHz crystal oscillator or left open when using external
					clock input on OSCA
	48	39	OSCA	I/O	24 MHz crystal oscillator or external clock input
	49	41	GND	Ground	Ground supply pad in the bottom center of the package.

1.IRQC and IRQD external interrupts can be mapped to any digital I/O pin using the GPIO_IRQCSEL and GPIO_IRQDSEL registers.

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STM32W108HB STM32W108CC STM32W108CB STM32W108CZ	Embedded memory

4 Embedded memory

Figure 4. STM32W108xB memory mapping

	0xE00FFFFF	ROM table
	0xE00FF000
	0xE0042000	Not used
	0xE0041000	Not used
	0xE0040000	TPIU
	0xE003FFFF
		Not used
	0xE000F000
	0xE000E000	NVIC
	0xE0003000	Not used
	0xE0002000	FPB
	0xE0001000	DWT
	0xE0000000	ITM
	0x42002XXX
		Register bit band
		alias region
		mapped onto System
		interface
		(not used)
	0x42000000
	0x40000XXX
		Registers
		mapped onto System
	0x40000000	interface
	0x22002000	RAM bit band
		alias region
		mapped onto System
		interface
		(not used)
	0x22000000
	0x20001FFF
		RAM (8kB)
		mapped onto System
	0x20000000	interface
	0x080409FF
	0x08040800	Customer Info Block (0.5kB)
	0x080407FF	Fixed Info Block (2kB)
	0x08040000
	0x0801FFFF
		Main Flash Block (128kB)
		Upper mapping
		(Boot mode)
	0x08000000
	0x0001FFFF
		Main Flash Block (128kB)
		Lower mapping
	0x000007FF	(Normal Mode)
	0x00000000

Not used

Private periph bus (external)

Private periph bus (internal)

Not used

Not used

Peripheral

RAM

Flash

0xFFFFFFFF

0xE0000000

0xDFFFFFFF

0xA0000000

0x9FFFFFFF

0x60000000

0x5FFFFFFF

0x40000000

0x3FFFFFFF

0x20000000

0x1FFFFFFF

0x00000000

7		0

Optional boot mode maps Fixed Info Block to the start of memory

Fixed Info Block (2kB)

Ai15259

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Embedded memory	STM32W108HB STM32W108CC STM32W108CB STM32W108CZ

Figure 5. STM32W108CC and STM32W108CZ memory mapping

	X% &&&&&	2/--TABLE
	X% &&
	X%	.OTTUSED
	X%	.OTTUSED
	X%	40)5
	X% &&&&
		.OTTUSED
	X% &
	X% %	.6)#
	X%	.OTTUSED
	X%	&0"
	X%	$74
	X%	)4-
	X 888
		2EGISTERRBITBBAND
		ALIAS REGION
		MAPPED ONTO 3YSTEM
		INTERFACE
		NOT USED
	X
	X 888
		2EGISTERS
		MAPPED ONTO 3YSTEM
	X	INTERFACE
	X
		2!- BITTBAND
		ALIAS REGION
		MAPPED ONTO 3YSTEM
		INTERFACE
		NOT USED
	X

X &&&

X &&&

X

X &&&

X

X &&&

X

X &&

X

X &&&&

X &&&&

X

X &&&&

X &&&&

X &&

X

2!- K"

MAPPED ONTO 3YSTEMM

INTERFACE

&IXEDX)NFO "LOCK %XTENSIONK"

#USTOMER )NFOF"LOCKK K"

&IXEDX)NFO "LOCK K"

-AIN &LASH "LOCK

K"

5PPER MAPPING"OOTTMODE

-AIN &LASH "LOCKK K" ,OWERRMAPPING.ORMAL -ODE

X&&&&&&&&

.OTTUSED

0RIVATE PERIPH BUS EXTERNAL

0RIVATEAPERIPH BUS INTERNAL

X% X$&&&&&&&

.OTTUSED

X!

X &&&&&&&

.OTTUSED

X

X &&&&&&&

0ERIPHERAL

X

X &&&&&&&

2!-

X

X &&&&&&&

&LASH

X

/PTIONALLBOOT MODE MAPS &IXED )NFO "LOCK TO THE STARTTOF MEMORY

&IXEDD)NFO "LOCK K"

-3 6

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STM32W108HB STM32W108CC STM32W108CB STM32W108CZ	Embedded memory

4.1Flash memory

The STM32W108 provides Flash memory in four separate blocks as follows:

●Main Flash Block (MFB)

●Fixed Information Block (FIB)

●Fixed Information Block Extension (FIB-EXT)

●Customer Information Block (CIB)

The size of these blocks and associated page size is described in Table 3.

Table 3.	Flash memory
	STM32W108xB		STM32W108CC		STM32W108CZ		Unit
	Size	Page size	Size	Page size	Size	Page size
MFB	128	1	256	2	192	2	K Bytes
FIB	2	2	2	2	2	2	K Bytes
CIB	0.5	0.5	2	2	2	2	K Bytes
FIB-EXT	0	N/A	16	2	16	2	K Bytes
Total	130.5		276		212		K Bytes

The smallest erasable unit is one page and the smallest writable unit is an aligned 16-bit half-word. The flash is guaranteed to have 10k write/erase cycles. The flash cell has been qualified for a data retention time of >100 years at room temperature.

Flash may be programmed either through the Serial Wire/JTAG interface or through bootloader software. Programming flash through Serial Wire/JTAG requires the assistance of RAM-based utility code. Programming through a bootloader requires specific software for over-the-air loading or serial link loading. A simplified, serial-link-only bootloader is also available preprogrammed into the FIB.

4.2Random-access memory

The STM32W108 has 8/12/16 Kbytes of static RAM on-chip. The start of RAM is mapped to address 0x20000000. Although the ARM® Cortex-M3 allows bit band accesses to this address region, the standard MPU configuration does not permit use of the bit-band feature.

The RAM is physically connected to the AHB System bus and is therefore accessible to both the ARM® Cortex-M3 microprocessor and the debugger. The RAM can be accessed for both instruction and data fetches as bytes, half words, or words. The standard MPU configuration does not permit execution from the RAM, but for special purposes, such as programming the main flash block, the MPU may be disabled. To the bus, the RAM appears as 32-bit wide memory and in most situations has zero wait state read or write access. In the higher CPU clock mode the RAM requires two wait states. This is handled by hardware transparent to the user application with no configuration required.

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Embedded memory	STM32W108HB STM32W108CC STM32W108CB STM32W108CZ

4.2.1Direct memory access (DMA) to RAM

Several of the peripherals are equipped with DMA controllers allowing them to transfer data into and out of RAM autonomously. This applies to the radio (802.15.4 MAC), general purpose ADC, and both serial controllers. In the case of the serial controllers, the DMA is full duplex so that a read and a write to RAM may be requested at the same time. Thus there are six DMA channels in total.

The STM32W108 integrates a DMA arbiter that ensures fair access to the microprocessor as well as the peripherals through a fixed priority scheme appropriate to the memory bandwidth requirements of each master. The priority scheme is as follows, with the top peripheral being the highest priority:

1.General Purpose ADC

2.Serial Controller 2 Receive

3.Serial Controller 2 Transmit

4.MAC

5.Serial Controller 1 Receive

6.Serial Controller 1 Transmit

4.2.2RAM memory protection

The STM32W108 integrates two memory protection mechanisms. The first memory protection mechanism is through the ARM® Cortex-M3 Memory Protection Unit (MPU) described in the Memory Protection Unit section. The MPU may be used to protect any area of memory. MPU configuration is normally handled by software. The second memory protection mechanism is through a fine granularity RAM protection module. This allows segmentation of the RAM into blocks where any block can be marked as write protected. An attempt to write to a protected RAM block using a user mode write results in a bus error being signaled on the AHB System bus. A system mode write is allowed at any time and reads are allowed in either mode. The main purpose of this fine granularity RAM protection module is to notify the stack of erroneous writes to system areas of memory. RAM protection is configured using a group of registers that provide a bit map. Each bit in the map represents a 32-byte block of RAM for STM32W108xB and 64 bytes of RAM for STM32W108CC and STM32W108CZ. When the bit is set the block is write protected.

The fine granularity RAM memory protection mechanism is also available to the peripheral DMA controllers. A register bit is provided to enable the memory protection to include DMA writes to protected memory. If a DMA write is made to a protected location in RAM, a management interrupt is generated. At the same time the faulting address and the identification of the peripheral is captured for later debugging. Note that only peripherals capable of writing data to RAM, such as received packet data or a received serial port character, can generate this interrupt.

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