ST STM32W108C8 User Manual
High-performance, IEEE 802.15.4 wireless system-on-chip
VFQFPN48
(7 x 7 mm)
Features
■ Complete system-on-chip
– 32-bit ARM® Cortex™-M3 processor
– 2.4 GHz IEEE 802.15.4 transceiver & lower
MAC
– 8-Kbyte RAM and 64-Kbyte Flash memory
– AES128 encryption accelerator
– Flexible ADC, SPI/UART/I
communications, and general-purpose
timers
– 24 highly configurable GPIOs with Schmitt
trigger inputs
■ Industry-leading ARM® Cortex™-M3
processor
– Leading 32-bit processing performance
– Highly efficient Thumb®-2 instruction set
– Operation at 6, 12 or 24 MHz
– Flexible nested vectored interrupt controller
■ Low power consumption, advanced
management
– Receive current (w/ CPU): 27 mA
– Transmit current (w/ CPU, +3 dBm TX):
31 mA
– Low deep sleep current, with retained RAM
and GPIO: 400 nA/800 nA with/without
sleep timer
– Low-frequency internal RC oscillator for
low-power sleep timing
– High-frequency internal RC oscillator for
fast (100 µs) processor start-up from sleep
■ Exceptional RF performance
– Normal mode link budget up to 102 dB;
configurable up to 107 dB
– -99 dBm normal RX sensitivity;
configurable to -100 dBm (1% PER, 20
byte packet)
– +3 dB normal mode output power;
configurable up to +8 dBm
– Robust WiFi and Bluetooth coexistence
2
C serial
STM32W108C8
with 64-Kybte Flash memory
■ Innovative network and processor debug
– Non-intrusive hardware packet trace
– Serial wire/JTAG interface
– Standard ARM debug capabilities: Flash
patch and breakpoint; data watchpoint and
trace; instrumentation trace macrocell
■ Application flexibility
– Single voltage operation: 2.1-3.6 V with
internal 1.8 V and 1.25 V regulators
– Optional 32.768 kHz crystal for higher timer
accuracy
– Low external component count with single
24 MHz crystal
– Support for external power amplifier
– Small 7x7 mm 48-pin VFQFPN package
Applications
■ RF4CE products and remote controls
■ 6LoWPAN and custom protocols
■ 802.15.4 based network protocols (standard
and proprietary)
July 2011 Doc ID 018587 Rev 2 1/215
www.st.com
1
STM32W108C8
1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.1 Development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.2.1 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.2.2 ARM® Cortex™-M3 core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2 Documentation conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3 Pinout and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4 Embedded memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.1 Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.2 Random-access memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.2.1 Direct memory access (DMA) to RAM . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.2.2 RAM memory protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.3 Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5 Radio frequency module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.1 Receive (Rx) path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.1.1 Rx baseband . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.1.2 RSSI and CCA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.2 Transmit (Tx) path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.2.1 Tx baseband . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.2.2 TX_ACTIVE and nTX_ACTIVE signals . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.3 Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.4 Integrated MAC module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.5 Packet trace interface (PTI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.6 Random number generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6 System modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6.1 Power domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
6.1.1 Internally regulated power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
6.1.2 Externally regulated power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
6.2 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.2.1 Reset sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Watchdog reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
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6.3 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Software reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Option byte error. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Debug reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
JTAG reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Deep sleep reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
6.2.2 Reset recording . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6.2.3 Reset generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6.2.4 Reset register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Reset event source register (RESET_EVENT) . . . . . . . . . . . . . . . . . . . . . . . . . .36
6.3.1 High-frequency internal RC oscillator (OSCHF) . . . . . . . . . . . . . . . . . . 38
6.3.2 High-frequency crystal oscillator (OSC24M) . . . . . . . . . . . . . . . . . . . . . 39
6.3.3 Low-frequency internal RC oscillator (OSCRC) . . . . . . . . . . . . . . . . . . . 39
6.3.4 Low-frequency crystal oscillator (OSC32K) . . . . . . . . . . . . . . . . . . . . . . 39
6.3.5 Clock switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
6.3.6 Clock switching registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
XTAL or OSCHF main clock select register (OSC24M_CTRL) . . . . . . . . . . . . . .40
CPU clock source select register (CPU_CLK_SEL). . . . . . . . . . . . . . . . . . . . . . .40
6.4 System timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
6.4.1 Watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
6.4.2 Sleep timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
6.4.3 Event timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
6.4.4 Slow timers (Watchdog and Sleeptimer) control and status registers . . 42
Watchdog general control register (WDOG_CFG) . . . . . . . . . . . . . . . . . . . . . . . .42
Watchdog control register (WDOG_CTRL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Watchdog restart register (WDOG_RESTART) . . . . . . . . . . . . . . . . . . . . . . . . . .43
Sleep timer configuration register (SLEEPTMR_CFG). . . . . . . . . . . . . . . . . . . . .43
Sleep timer count high register (SLEEPTMR_CNTH) . . . . . . . . . . . . . . . . . . . . .43
Sleep timer count low register (SLEEPTMR_CNTL) . . . . . . . . . . . . . . . . . . . . . .44
Sleep timer compare A high register (SLEEPTMR_CMPAH). . . . . . . . . . . . . . . .44
Sleep timer compare A low register (SLEEPTMR_CMPAL). . . . . . . . . . . . . . . . .45
Sleep timer compare B high register (SLEEPTMR_CMPBH). . . . . . . . . . . . . . . .45
Sleep timer compare B low register (SLEEPTMR_CMPBL). . . . . . . . . . . . . . . . .46
Sleep timer interrupt source register (INT_SLEEPTMRFLAG). . . . . . . . . . . . . . .46
Sleep timer interrupt mask register (INT_SLEEPTMRCFG). . . . . . . . . . . . . . . . .47
Sleep timer clock source enables (SLEEPTMR_CLKEN) . . . . . . . . . . . . . . . . . .47
6.5 Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
6.5.1 Wake sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
6.5.2 Basic sleep modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
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6.5.3 Further options for deep sleep . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
6.5.4 Use of debugger with sleep modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
6.6 Security accelerator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
7 Integrated voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
8 General-purpose input/outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
8.1 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
8.1.1 GPIO ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
8.1.2 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
8.1.3 Forced functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
8.1.4 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
8.1.5 nBOOTMODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
8.1.6 GPIO modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Analog mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
Input mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
Output mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
Alternate output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
Alternate output SPI SCLK mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
8.1.7 Wake monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
8.2 External interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
8.3 Debug control and status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
8.4 GPIO alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
8.5 General-purpose input / output (GPIO) registers . . . . . . . . . . . . . . . . . . . 64
8.5.1 Port x configuration register (Low) (GPIO_PxCFGL) . . . . . . . . . . . . . . . 64
8.5.2 Port x configuration register (High) (GPIO_PxCFGH) . . . . . . . . . . . . . . 64
8.5.3 Port x input data register (GPIO_PxIN) . . . . . . . . . . . . . . . . . . . . . . . . . 65
8.5.4 Port x output data register (GPIO_PxOUT) . . . . . . . . . . . . . . . . . . . . . . 66
8.5.5 Port x output clear register (GPIO_PxCLR) . . . . . . . . . . . . . . . . . . . . . . 66
8.5.6 Port x output set register (GPIO_PxSET) . . . . . . . . . . . . . . . . . . . . . . . 67
8.5.7 Port x wakeup monitor register (GPIO_PxWAKE) . . . . . . . . . . . . . . . . . 67
8.5.8 GPIO wakeup filtering register (GPIO_WAKEFILT) . . . . . . . . . . . . . . . . 68
8.5.9 Interrupt x select register (GPIO_IRQxSEL) . . . . . . . . . . . . . . . . . . . . . 68
8.5.10 GPIO interrupt x configuration register (GPIO_INTCFGx) . . . . . . . . . . . 69
8.5.11 GPIO interrupt flag register (INT_GPIOFLAG) . . . . . . . . . . . . . . . . . . . 70
8.5.12 GPIO debug configuration register (GPIO_DBGCFG) . . . . . . . . . . . . . . 70
8.5.13 GPIO debug status register (GPIO_DBGSTAT) . . . . . . . . . . . . . . . . . . . 71
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9 Serial interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
9.1 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
9.2 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
9.3 SPI master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
9.3.1 Setup and configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
9.3.2 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
9.3.3 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
9.4 SPI slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
9.4.1 Setup and configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
9.4.2 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
9.4.3 DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
9.4.4 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
9.5 Inter-integrated circuit interfaces (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
9.5.1 Setup and configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
9.5.2 Constructing frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
9.5.3 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
9.6 Universal asynchronous receiver / transmitter (UART) . . . . . . . . . . . . . . 84
9.6.1 Setup and configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
9.6.2 FIFOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
9.6.3 RTS/CTS flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
9.6.4 DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
9.6.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
9.7 Direct memory access (DMA) channels . . . . . . . . . . . . . . . . . . . . . . . . . . 88
9.8 Serial controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
9.8.1 Serial mode register (SCx_MODE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
9.8.2 Serial controller interrupt flag register (INT_SCxFLAG) . . . . . . . . . . . . 90
9.8.3 Serial controller interrupt configuration register (INT_SCxCFG) . . . . . . 91
9.8.4 Serial controller interrupt mode register (SCx_INTMODE) . . . . . . . . . . 92
9.9 SPI master mode registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
9.9.1 Serial data register (SCx_DATA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
9.9.2 SPI configuration register (SCx_SPICFG) . . . . . . . . . . . . . . . . . . . . . . . 93
9.9.3 SPI status register (SCx_SPISTAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
9.9.4 Serial clock linear prescaler register (SCx_RATELIN) . . . . . . . . . . . . . . 94
9.9.5 Serial clock exponential prescaler register (SCx_RATEEXP) . . . . . . . . 95
9.10 SPI slave mode registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
9.11 Inter-integrated circuit (I2C) interface registers . . . . . . . . . . . . . . . . . . . . 95
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9.11.1 I2C status register (SCx_TWISTAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
9.11.2 I2C control 1 register (SCx_TWICTRL1) . . . . . . . . . . . . . . . . . . . . . . . . 96
9.11.3 I2C control 2 register (SCx_TWICTRL2) . . . . . . . . . . . . . . . . . . . . . . . . 96
9.12 Universal asynchronous receiver / transmitter (UART) registers . . . . . . . 97
9.12.1 UART status register (SC1_UARTSTAT) . . . . . . . . . . . . . . . . . . . . . . . . 97
9.12.2 UART configuration register (SC1_UARTCFG) . . . . . . . . . . . . . . . . . . . 98
9.12.3 UART baud rate period register (SC1_UARTPER) . . . . . . . . . . . . . . . . 99
9.12.4 UART baud rate fractional period register (SC1_UARTFRAC) . . . . . . . 99
9.13 DMA channel registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
9.13.1 Serial DMA control register (SCx_DMACTRL) . . . . . . . . . . . . . . . . . . 100
9.13.2 Serial DMA status register (SCx_DMASTAT) . . . . . . . . . . . . . . . . . . . 101
9.13.3 Transmit DMA begin address register A (SCx_TXBEGA) . . . . . . . . . . 102
9.13.4 Transmit DMA begin address register B (SCx_TXBEGB) . . . . . . . . . . 102
9.13.5 Transmit DMA end address register A (SCx_TXENDA) . . . . . . . . . . . 103
9.13.6 Transmit DMA end address register B (SCx_TXENDB) . . . . . . . . . . . 103
9.13.7 Transmit DMA count register (SCx_TXCNT) . . . . . . . . . . . . . . . . . . . . 103
9.13.8 Receive DMA begin address register A (SCx_RXBEGA) . . . . . . . . . . 104
9.13.9 Receive DMA begin address register B (SCx_RXBEGB) . . . . . . . . . . 104
9.13.10 Receive DMA end address register A (SCx_RXENDA) . . . . . . . . . . . . 105
9.13.11 Receive DMA end address register B (SCx_RXENDB) . . . . . . . . . . . . 105
9.13.12 Receive DMA count register A (SCx_RXCNTA) . . . . . . . . . . . . . . . . . 106
9.13.13 Receive DMA count register B (SCx_RXCNTB) . . . . . . . . . . . . . . . . . 106
9.13.14 Saved receive DMA count register (SCx_RXCNTSAVED) . . . . . . . . . 107
9.13.15 DMA first receive error register A (SCx_RXERRA) . . . . . . . . . . . . . . . 107
9.13.16 DMA first receive error register B (SCx_RXERRB) . . . . . . . . . . . . . . . 108
10 General-purpose timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
10.1 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
10.1.1 Time-base unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
10.1.2 Counter modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Up-counting mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
Down-counting mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114
Center-aligned mode (up/down counting) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
10.1.3 Clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Internal clock source (CK_INT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118
External clock source mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118
External clock source mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120
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STM32W108C8
10.1.4 Capture/compare channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
10.1.5 Input capture mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
10.1.6 PWM input mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
10.1.7 Forced output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
10.1.8 Output compare mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
10.1.9 PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
PWM edge-aligned mode: up-counting configuration. . . . . . . . . . . . . . . . . . . . .127
PWM edge-aligned mode: down-counting configuration . . . . . . . . . . . . . . . . . .127
PWM center-aligned mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127
10.1.10 One-pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
A special case: OCy fast enable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130
10.1.11 Encoder interface mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
10.1.12 Timer input XOR function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
10.1.13 Timers and external trigger synchronization . . . . . . . . . . . . . . . . . . . . 133
Slave mode: Reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133
Slave mode: Gated mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134
Slave mode: Trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134
Slave mode: External clock mode 2 + Trigger mode . . . . . . . . . . . . . . . . . . . . .135
10.1.14 Timer synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Using one timer as prescaler for the other timer . . . . . . . . . . . . . . . . . . . . . . . .136
Using one timer to enable the other timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137
Using one timer to start the other timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138
Starting both timers synchronously in response to an external trigger . . . . . . . . 139
10.1.15 Timer signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
10.2 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
10.3 General-purpose timer (1 and 2) registers . . . . . . . . . . . . . . . . . . . . . . . 142
10.3.1 Timer x control register 1 (TIMx_CR1) . . . . . . . . . . . . . . . . . . . . . . . . 142
10.3.2 Timer x control register 2 (TIMx_CR2) . . . . . . . . . . . . . . . . . . . . . . . . 143
10.3.3 Timer x slave mode control register (TIMx_SMCR) . . . . . . . . . . . . . . . 144
10.3.4 Timer x event generation register (TIMx_EGR) . . . . . . . . . . . . . . . . . . 146
10.3.5 Timer x capture/compare mode register 1 (TIMx_CCMR1) . . . . . . . . . 148
10.3.6 Timer x capture/compare mode register 2 (TIMx_CCMR2) . . . . . . . . . 150
10.3.7 Timer x capture/compare enable register (TIMx_CCER) . . . . . . . . . . . 153
10.3.8 Timer x counter register (TIMx_CNT) . . . . . . . . . . . . . . . . . . . . . . . . . 154
10.3.9 Timer x prescaler register (TIMx_PSC) . . . . . . . . . . . . . . . . . . . . . . . . 154
10.3.10 Timer x auto-reload register (TIMx_ARR) . . . . . . . . . . . . . . . . . . . . . . 155
10.3.11 Timer x capture/compare 1 register (TIMx_CCR1) . . . . . . . . . . . . . . . 155
10.3.12 Timer x capture/compare 2 register (TIMx_CCR2) . . . . . . . . . . . . . . . 156
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STM32W108C8
10.3.13 Timer x capture/compare 3 register (TIMx_CCR3) . . . . . . . . . . . . . . . 156
10.3.14 Timer x capture/compare 4 register (TIMx_CCR4) . . . . . . . . . . . . . . . 156
10.3.15 Timer 1 option register (TIM1_OR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
10.3.16 Timer 2 option register (TIM2_OR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
10.3.17 Timer x interrupt configuration register (INT_TIMxCFG) . . . . . . . . . . . 158
10.3.18 Timer x interrupt flag register (INT_TIMxFLAG) . . . . . . . . . . . . . . . . . 158
10.3.19 Timer x missed interrupt register (INT_TIMxMISS) . . . . . . . . . . . . . . . 159
11 Analog-to-digital converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
11.1 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
11.1.1 Setup and configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
11.1.2 GPIO usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
11.1.3 Voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
11.1.4 Offset/gain correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
11.1.5 DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
11.1.6 ADC configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163
Input range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .164
Sample time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .164
11.1.7 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
11.1.8 Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
11.2 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
11.3 Analog-to-digital converter (ADC) registers . . . . . . . . . . . . . . . . . . . . . . 168
11.3.1 ADC configuration register (ADC_CFG) . . . . . . . . . . . . . . . . . . . . . . . 168
11.3.2 ADC offset register (ADC_OFFSET) . . . . . . . . . . . . . . . . . . . . . . . . . . 169
11.3.3 ADC gain register (ADC_GAIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
11.3.4 ADC DMA configuration register (ADC_DMACFG) . . . . . . . . . . . . . . . 170
11.3.5 ADC DMA status register (ADC_DMASTAT) . . . . . . . . . . . . . . . . . . . . 170
11.3.6 ADC DMA begin address register (ADC_DMABEG) . . . . . . . . . . . . . . 171
11.3.7 ADC DMA buffer size register (ADC_DMASIZE) . . . . . . . . . . . . . . . . . 171
11.3.8 ADC DMA current address register (ADC_DMACUR) . . . . . . . . . . . . . 171
11.3.9 ADC DMA count register (ADC_DMACNT) . . . . . . . . . . . . . . . . . . . . . 172
11.3.10 ADC interrupt flag register (INT_ADCFLAG) . . . . . . . . . . . . . . . . . . . . 173
11.3.11 ADC interrupt configuration register (INT_ADCCFG) . . . . . . . . . . . . . 173
12 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
12.1 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 174
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12.1.1 Non-maskable interrupt (NMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
12.1.2 Faults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
12.2 Event manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
12.3 Nested vectored interrupt controller (NVIC) interrupts . . . . . . . . . . . . . . 181
12.3.1 Top-level set interrupts configuration register (INT_CFGSET) . . . . . . 181
12.3.2 Top-level clear interrupts configuration register (INT_CFGCLR) . . . . . 182
12.3.3 Top-level set interrupts pending register (INT_PENDSET) . . . . . . . . . 183
12.3.4 Top-level clear interrupts pending register (INT_PENDCLR) . . . . . . . . 184
12.3.5 Top-level active interrupts register (INT_ACTIVE) . . . . . . . . . . . . . . . . 185
12.3.6 Top-level missed interrupts register (INT_MISS) . . . . . . . . . . . . . . . . . 186
12.3.7 Auxiliary fault status register (SCS_AFSR) . . . . . . . . . . . . . . . . . . . . . 187
13 Debug support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
13.1 STM32W108 JTAG TAP connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
14 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
14.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
14.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
14.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
14.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
14.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
14.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
14.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
14.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
14.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
14.3.2 Operating conditions at power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
Power-on resets (POR HV and POR LV) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .192
NRST pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .193
14.3.3 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 193
Electrostatic discharge (ESD). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .193
Static latch-up. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .194
14.4 ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
14.5 Clock frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
14.5.1 High frequency internal clock characteristics . . . . . . . . . . . . . . . . . . . . 199
14.5.2 High frequency external clock characteristics . . . . . . . . . . . . . . . . . . . 199
14.5.3 Low frequency internal clock characteristics . . . . . . . . . . . . . . . . . . . . 199
14.5.4 Low frequency external clock characteristics . . . . . . . . . . . . . . . . . . . . 200
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14.6 DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
14.7 Digital I/O specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
14.8 Non-RF system electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . 206
14.9 RF electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
14.9.1 Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
14.9.2 Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
14.9.3 Synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
15 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
16 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
17 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
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STM32W108C8 Description
Packet sniffer
ADC
RF_P,N
Program
Flash
64 kBytes
Data
SRAM
8 kBytes
HF crystal
OSC
LF crystal
OSC
General
Purpose
ADC
Serial
Wire and
JTAG
debug
Internal LF
RC-OSC
GPIO multiplexor swtich
Chip
manager
Regulator
Bias
2ndlevel
Interrupt
controller
RF_TX_ALT_P,N
OSCA
OSCB
PA[7:0], PB[7:0], PC[7:0]
Encryption
acclerat or
IF
Always
Powered
Domain
ARM CORTEX-M3
®
CPU with NVIC
and MPU
VREG_OUT
Watchdog
PA se lect
LNA
PA
PA
DAC
MAC
+
Baseband
Sleep
timer
BIAS_R
POR
nRESET
General
purpose
timers
GPIO
regist ers
UART/
SPI/I
2
C
SYNTH
Inter nal H F
RC-OSC
TX_ACTIVE
SWCLK,
JTCK
Calibration
ADC
Packet Trace
CPU debug
TPIU/ITM/
FPB/DWT
-36
1 Description
The STM32W108C8 is a fully integrated System-on-Chip that integrates a 2.4 GHz, IEEE
802.15.4-compliant transceiver, 32-bit ARM® Cortex™-M3 microprocessor, Flash and RAM
memory, and peripherals of use to designers of 802.15.4-based systems.
Figure 1. STM32W108C8 block diagram
The transceiver utilizes an efficient architecture that exceeds the dynamic range
requirements imposed by the IEEE 802.15.4-2003 standard by over 15 dB. The integrated
receive channel filtering allows for robust co-existence with other communication standards
in the 2.4 GHz spectrum, such as IEEE 802.11 and Bluetooth. The integrated regulator,
VCO, loop filter, and power amplifier keep the external component count low. An optional
high performance radio mode (boost mode) is software-selectable to boost dynamic range.
The integrated 32-bit ARM® Cortex™-M3 microprocessor is highly optimized for high
performance, low power consumption, and efficient memory utilization. Including an
integrated MPU, it supports two different modes of operation: Privileged mode and
Unprivileged mode. This architecture could be used to separate the networking stack from
the application code and prevent unwanted modification of restricted areas of memory and
registers resulting in increased stability and reliability of deployed solutions.
The STM32W108C8 has 64 Kbytes of embedded Flash memory and 8 Kbytes of integrated
RAM for data and program storage. The STM32W108C8 HAL software employs an effective
wear-leveling algorithm that optimizes the lifetime of the embedded Flash.
To maintain the strict timing requirements imposed by the IEEE 802.15.4-2003 standards,
the STM32W108C8 integrates a number of MAC functions into the hardware. The MAC
hardware handles automatic ACK transmission and reception, automatic backoff delay, and
clear channel assessment for transmission, as well as automatic filtering of received
packets. A packet trace interface is also integrated with the MAC, allowing complete, nonintrusive capture of all packets to and from the STM32W108C8.
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Description STM32W108C8
The STM32W108C8 offers a number of advanced power management features that enable
long battery life. A high-frequency internal RC oscillator allows the processor core to begin
code execution quickly upon waking. Various deep sleep modes are available with less than
1 µA power consumption while retaining RAM contents. To support user-defined
applications, on-chip peripherals include UART, SPI, I
as well as up to 24 GPIOs. Additionally, an integrated voltage regulator, power-on-reset
circuit, and sleep timer are available.
2
C, ADC and general-purpose timers,
1.1 Development tools
The STM32W108C8 implements both the ARM Serial Wire and JTAG debug interfaces.
These interfaces provide real time, non-intrusive programming and debugging capabilities.
Serial Wire and JTAG provide the same functionality, but are mutually exclusive. The Serial
Wire interface uses two pins; the JTAG interface uses five. Serial Wire is preferred, since it
uses fewer pins.
The STM32W108C8 also integrates the standard ARM system debug components: Flash
Patch and Breakpoint (FPB), Data Watchpoint and Trace (DWT), and Instrumentation Trace
Macrocell (DWT).
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STM32W108C8 Description
1.2 Overview
1.2.1 Functional description
The STM32W108C8 radio receiver is a low-IF, super-heterodyne receiver. The architecture
has been chosen to optimize co-existence with other devices in the 2.4 GHz band (namely,
WIFI and Bluetooth), and to minimize power consumption. The receiver uses differential
signal paths to reduce sensitivity to noise interference. Following RF amplification, the signal
is downconverted by an image-rejecting mixer, filtered, and then digitized by an ADC.
The radio transmitter uses an efficient architecture in which the data stream directly
modulates the VCO frequency. An integrated power amplifier (PA) provides the output
power. Digital logic controls Tx path and output power calibration. If the STM32W108C8 is to
be used with an external PA, use the TX_ACTIVE or nTX_ACTIVE signal to control the
timing of the external switching logic.
The integrated 4.8 GHz VCO and loop filter minimize off-chip circuitry. Only a 24 MHz
crystal with its loading capacitors is required to establish the PLL local oscillator signal.
The MAC interfaces the on-chip RAM to the Rx and Tx baseband modules. The MAC
provides hardware-based IEEE 802.15.4 packet-level filtering. It supplies an accurate
symbol time base that minimizes the synchronization effort of the software stack and meets
the protocol timing requirements. In addition, it provides timer and synchronization
assistance for the IEEE 802.15.4 CSMA-CA algorithm.
The STM32W108C8 integrates an ARM® Cortex-M3 microprocessor, revision r1p1. This
industry-leading core provides 32 bit performance and is very power efficient. It has
excellent code density using the ARM® Thumb 2 instruction set. The processor can be
operated at 12 MHz or 24 MHz when using the crystal oscillator, or at 6 MHz or 12 MHz
when using the integrated high frequency RC oscillator.
The STM32W108C8 has 64 Kbytes of Flash memory, 8 Kbytes of SRAM on-chip, and the
ARM configurable memory protection unit (MPU).
The STM32W108C8 contains 24 GPIO pins shared with other peripheral or alternate
functions. Because of flexible routing within the STM32W108C8, external devices can use
the alternate functions on a variety of different GPIOs. The integrated Serial Controller SC1
can be configured for SPI (master or slave), I
Serial Controller SC2 can be configured for SPI (master or slave) or I
operation.
The STM32W108C8 has a general purpose ADC which can sample analog signals from six
GPIO pins in single-ended or differential modes. It can also sample the regulated supply
VDD_PADSA, the voltage reference VREF, and GND. The ADC has two selectable voltage
ranges: 0 V to 1.2 V (normal) and 0.1 V to 0.1 V below the high voltage supply (high). The
ADC has a DMA mode to capture samples and automatically transfer them into RAM. The
integrated voltage reference for the ADC, VREF, can be made available to external circuitry.
An external voltage reference can also be driven into the ADC.
The STM32W108C8 contains four oscillators: a high frequency 24 MHz external crystal
oscillator, a high frequency 12 MHz internal RC oscillator, an optional low frequency 32.768
kHz external crystal oscillator, and a 10 kHz internal RC oscillator.
2
C (master-only), or UART operation, and the
2
C (master-only)
The STM32W108C8 has an ultra low power, deep sleep state with a choice of clocking
modes. The sleep timer can be clocked with either the external 32.768 kHz crystal oscillator
or with a 1 kHz clock derived from the internal 10 kHz RC oscillator. Alternatively, all clocks
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Description STM32W108C8
can be disabled for the lowest power mode. In the lowest power mode, only external events
on GPIO pins will wake up the chip. The STM32W108C8 has a fast startup time (typically
100 µs) from deep sleep to the execution of the first ARM® Cortex-M3 instruction.
The STM32W108C8 contains three power domains. The always-on high voltage supply
powers the GPIO pads and critical chip functions. Regulated low voltage supplies power the
rest of the chip. The low voltage supplies are be disabled during deep sleep to reduce power
consumption. Integrated voltage regulators generate regulated 1.25 V and 1.8 V voltages
from an unregulated supply voltage. The 1.8 V regulator output is decoupled and routed
externally to supply analog blocks, RAM, and Flash memories. The 1.25 V regulator output
is decoupled externally and supplies the core logic.
The digital section of the receiver uses a coherent demodulator to generate symbols for the
hardware-based MAC. The digital receiver also contains the analog radio calibration
routines and controls the gain within the receiver path.
In addition to 2 general-purpose timers, the STM32W108C8 also contains a watchdog timer
to ensure protection against software crashes and CPU lockup, a 32-bit sleep timer
dedicated to system timing and waking from sleep at specific times and an ARM® standard
system event timer in the NVIC.
The STM32W108C8 integrates hardware support for a Packet Trace module, which allows
robust packet-based debug.
Note: The STM32W108C8 is not pin-compatible with the previous generation chip, the SN250,
except for the RF section of the chip. Pins 1-11 and 45-48 are compatible, to ease migration
to the STM32W108C8.
1.2.2 ARM® Cortex™-M3 core
The STM32W108C8 integrates the ARM® Cortex™-M3 microprocessor, revision r1p1,
developed by ARM Ltd, making the STM32W108C8 a true system-on-a-chip solution. The
ARM® Cortex-M3 is an advanced 32-bit modified Harvard architecture processor that has
separate internal program and data buses, but presents a unified program and data address
space to software. The word width is 32 bits for both the program and data sides. The
ARM® Cortex-M3 allows unaligned word and half-word data accesses to support efficientlypacked data structures.
The ARM® Cortex-M3 clock speed is configurable to 6 MHz, 12 MHz, or 24 MHz. For
normal operation 12 MHz is preferred over 24 MHz due to its lower power consumption. The
6 MHz operation can only be used when radio operations are not required since the radio
requires an accurate 12 MHz clock.
The ARM® Cortex-M3 in the STM32W108C8 has also been enhanced to support two
separate memory protection levels. Basic protection is available without using the MPU, but
the usual operation uses the MPU. The MPU protects unimplemented areas of the memory
map to prevent common software bugs from interfering with software operation. The
architecture could also separate the networking stack from the application code using a fine
granularity RAM protection module. Errant writes are captured and details are reported to
the developer to assist in tracking down and fixing issues.
13/215 Doc ID 018587 Rev 2
STM32W108C8 Documentation conventions
2 Documentation conventions
Table 1. Description of abbreviations used for bitfield access
Abbreviation Description
Read/Write (rw) Software can read and write to these bits.
Read-only (r) Software can only read these bits.
Write only (w) Software can only write to this bit. Reading returns the reset value.
Read/Write in (MPU)
Privileged mode only (rws)
1. The conditions under which the hardware (core) sets or clears this field are explained in details in the
bitfield description, as well as the events that may be generated by writing to the bit.
Software can read and write to these bits only in Privileged mode. For
more information, please refer to RAM memory protection on page 28
and Memory protection unit on page 28.
(1)
Doc ID 018587 Rev 2 14/215
Pinout and pin description STM32W108C8
Ai15261
Ground pad on back
VDD_24MHZ
RF_P
RF_N
VDD_RF
RF_TX_ALT_P
RF_TX_ALT_N
VDD_IF
BIAS_R
VDD_PADSA
PC5, TX_ACTIVE
VDD_PADS
PA1, TIM2C3, SC2SDA, SC2MISO
PA0, TIM2C1, SC2MOSI
PA7, TIM1C4, REG_EN
VDD_CORE
VREG_OUT
PC6, OSC32B, nTX_ACTIVE
VDD_PADS
PA2, TIM2C4, SC2SCL, SC2SCLK
PB0, VREF, IRQA, TRACECLK, TIM1CLK, TIM2MSK
PC4, JTMS, SWDIO
PC3, JTDI
PC2, JTDO, SWO
SWCLK, JTCK
VDD_PADS
PA5, ADC5, PTI_DATA, nBOOTMODE, TRACEDATA3
PA4, ADC4, PTI_EN, TRACEDATA2
PA 3, SC2nSSEL, TRACECLK, TIM2C2
PC1, ADC3, SWO, TRACEDATA0
VDD_MEM
PB7, ADC2, IRQC, TIM1C2
PB5, ADC0, TIM2CLK, TIM1MSK
VDD_CORE
VDD_PRE
OSCA
PC0, JRST, IRQDn, TRACEDATA1
OSCB
VDD_PADS
1
2
3
4
5
6
7
8
9
10
11
12
13 14 15 16 17 18 19 20 21 22
23 24
36
35
34
33
32
31
30
29
28
27
26
25
48 47 46 45 44 43 42 41 40 39
38 37
VDD_VCO
nRESET
PC7, OSC32A, OSC32_EXT
PB3, TIM2C3, SC1nCTS, SC1SCLK
PB4, TIM2C4, SC1nRTS, SC1nSSEL
PB1, SC1MISO, SC1MOSI, SC1SDA , SC1TXD, TIM2C1
PA6, TIM1C3
PB2, SC1MISO, SC1MOSI, SC1SCL, SC1RXD, TIM2C2
VDD_SYNTH
PB6, ADC1, IRQ6, TIM1C1
3 Pinout and pin description
Figure 2. 48-pin VFQFPN pinout
Table 2. Pin descriptions
Pin no. Signal Direction Description
1 VDD_24MHZ Power 1.8V high-frequency oscillator supply
2 VDD_VCO Power 1.8V VCO supply
3 RF_P I/O Differential (with RF_N) receiver input/transmitter output
4 RF_N I/O Differential (with RF_P) receiver input/transmitter output
5 VDD_RF Power 1.8V RF supply (LNA and PA)
6 RF_TX_ALT_P O Differential (with RF_TX_ALT_N) transmitter output (optional)
7 RF_TX_ALT_N O Differential (with RF_TX_ALT_P) transmitter output (optional)
8 VDD_IF Power 1.8V IF supply (mixers and filters)
15/215 Doc ID 018587 Rev 2
STM32W108C8 Pinout and pin description
Table 2. Pin descriptions (continued)
Pin no. Signal Direction Description
9 BIAS_R I Bias setting resistor
10 VDD_PADSA Power Analog pad supply (1.8V)
PC5 I/O Digital I/O
11
12 nRESET I Active low chip reset (internal pull-up)
13
14
TX_ACTIVE O
PC6 I/O Digital I/O
OSC32B I/O
nTX_ACTIVE O
PC7 I/O Digital I/O
OSC32A I/O
Logic-level control for external Rx/Tx switch. The STM32W108C8
baseband controls TX_ACTIVE and drives it high (VDD_PADS)
when in Tx mode.
Select alternate output function with GPIO_PCCFGH[7:4]
32.768 kHz crystal oscillator
Select analog function with GPIO_PCCFGH[11:8]
Inverted TX_ACTIVE signal (see PC5)
Select alternate output function with GPIO_PCCFGH[11:8]
32.768 kHz crystal oscillator.
Select analog function with GPIO_PCCFGH[15:12]
OSC32_EXT I Digital 32 kHz clock input source
15 VREG_OUT Power Regulator output (1.8 V while awake, 0 V during deep sleep)
16 VDD_PADS Power Pads supply (2.1-3.6 V)
17 VDD_CORE Power 1.25 V digital core supply decoupling
18
PA 7
TIM1_CH4
REG_EN O External regulator open drain output. (Enabled after reset.)
I/O
High current
O
I Timer 1 Channel 4 input. (Cannot be remapped.)
Digital I/O. Disable REG_EN with GPIO_DBGCFG[4]
Timer 1 Channel 4 output
Enable timer output with TIM1_CCER
Select alternate output function with GPIO_PACFGH[15:12]
Disable REG_EN with GPIO_DBGCFG[4]
Doc ID 018587 Rev 2 16/215
Pinout and pin description STM32W108C8
Table 2. Pin descriptions (continued)
Pin no. Signal Direction Description
PB3 I/O Digital I/O
Timer 2 channel 3 output
Enable remap with TIM2_OR[6]
Enable timer output in TIM2_CCER
Select alternate output function with GPIO_PBCFGL[15:12]
UART CTS handshake of Serial Controller 1
Enable with SC1_UARTCFG[5]
Select UART with SC1_MODE
SPI master clock of Serial Controller 1
Either disable timer output in TIM2_CCER or disable remap with
TIM2_OR[6]
Enable master with SC1_SPICFG[4]
Select SPI with SC1_MODE
Select alternate output function with GPIO_PBCFGL[15:12]
SPI slave clock of Serial Controller 1
Enable slave with SC1_SPICFG[4]
Select SPI with SC1_MODE
Timer 2 channel 4 output
Enable remap with TIM2_OR[7]
Enable timer output in TIM2_CCER
Select alternate output function with GPIO_PBCFGH[3:0]
19
TIM2_CH3
(see Pin 22)
UART_CTS I
SC1SCLK
PB4 I/O Digital I/O
TIM2_CH4
(see also Pin 24)
O
I Timer 2 channel 3 input. Enable remap with TIM2_OR[6].
O
I
O
20
UART_RTS O
SC1nSSEL I
I Timer 2 channel 4 input. Enable remap with TIM2_OR[7].
UART RTS handshake of Serial Controller 1
Either disable timer output in TIM2_CCER or disable remap with
TIM2_OR[7]
Enable with SC1_UARTCFG[5]
Select UART with SC1_MODE
Select alternate output function with GPIO_PBCFGH[3:0]
SPI slave select of Serial Controller 1
Enable slave with SC1_SPICFG[4]
Select SPI with SC1_MODE
17/215 Doc ID 018587 Rev 2
STM32W108C8 Pinout and pin description
Table 2. Pin descriptions (continued)
Pin no. Signal Direction Description
PA0 I/O Digital I/O
Timer 2 channel 1 output
TIM2_CH1
O
(see also Pin 30)
I Timer 2 channel 1 input. Disable remap with TIM2_OR[4].
21
O
SC2MOSI
I
PA1 I/O Digital I/O
TIM2_CH3
O
(see also Pin 19)
I Timer 2 channel 3 input. Disable remap with TIM2_OR[6].
SC2SDA I/O
22
O
SC2MISO
I
23 VDD_PADS Power Pads supply (2.1-3.6V)
Disable remap with TIM2_OR[4]
Enable timer output in TIM2_CCER
Select alternate output function with GPIO_PACFGL[3:0]
SPI master data out of Serial Controller 2
Either disable timer output in TIM2_CCER or enable remap with
TIM2_OR[4]
Enable master with SC2_SPICFG[4]
Select SPI with SC2_MODE
Select alternate output function with GPIO_PACFGL[3:0]
SPI slave data in of Serial Controller 2
Enable slave with SC2_SPICFG[4]
Select SPI with SC2_MODE
Timer 2 channel 3 output
Disable remap with TIM2_OR[6]
Enable timer output in TIM2_CCER
Select alternate output function with GPIO_PACFGL[7:4]
2
I
C data of Serial Controller 2
Either disable timer output in TIM2_CCER or enable remap with
TIM2_OR[6]
Select I
2
C with SC2_MODE
Select alternate open-drain output function with GPIO_PACFGL[7:4]
SPI slave data out of Serial Controller 2
Either disable timer output in TIM2_CCER or enable remap with
TIM2_OR[6]
Enable slave with SC2_SPICFG[4]
Select SPI with SC2_MODE
Select alternate output function with GPIO_PACFGL[7:4]
SPI master data in of Serial Controller 2
Enable slave with SC2_SPICFG[4]
Select SPI with SC2_MODE
Doc ID 018587 Rev 2 18/215
Pinout and pin description STM32W108C8
Table 2. Pin descriptions (continued)
Pin no. Signal Direction Description
PA2 I/O Digital I/O
Timer 2 channel 4 output
Disable remap with TIM2_OR[7]
Enable timer output in TIM2_CCER
Select alternate output function with GPIO_PACFGL[11:8]
2
I
C clock of Serial Controller 2
Either disable timer output in TIM2_CCER or enable remap with
TIM2_OR[7]
Select I
2
C with SC2_MODE
Select alternate open-drain output function with
GPIO_PACFGL[11:8]
SPI master clock of Serial Controller 2
Either disable timer output in TIM2_CCER or enable remap with
TIM2_OR[7]
Enable master with SC2_SPICFG[4]
Select SPI with SC2_MODE
Select alternate output function with GPIO_PACFGL[11:8]
SPI slave clock of Serial Controller 2
Enable slave with SC2_SPICFG[4]
Select SPI with SC2_MODE
24
TIM2_CH4
O
(see also Pin 20)
SC2SCL I/O
O
SC2SCLK
I Timer 2 channel 4 input. Disable remap with TIM2_OR[7].
I
25
PA3 I/O Digital I/O
SPI slave select of Serial Controller 2
SC2nSSEL I
Enable slave with SC2_SPICFG[4]
Select SPI with SC2_MODE
Synchronous CPU trace clock
TRACECLK
(see also Pin 36)
O
Either disable timer output in TIM2_CCER or enable remap with
TIM2_OR[5]
Enable trace interface in ARM core
Select alternate output function with GPIO_PACFGL[15:12]
Timer 2 channel 2 output
TIM2_CH2
(see also Pin 31)
O
Disable remap with TIM2_OR[5]
Enable timer output in TIM2_CCER
Select alternate output function with GPIO_PACFGL[15:12]
I Timer 2 channel 2 input. Disable remap with TIM2_OR[5].
19/215 Doc ID 018587 Rev 2
STM32W108C8 Pinout and pin description
Table 2. Pin descriptions (continued)
Pin no. Signal Direction Description
PA4 I/O Digital I/O
ADC4 Analog ADC Input 4. Select analog function with GPIO_PACFGH[3:0].
Frame signal of Packet Trace Interface (PTI).
26
PTI_EN O
TRACEDATA2 O
PA5 I/O Digital I/O
ADC5 Analog ADC Input 5. Select analog function with GPIO_PACFGH[7:4].
PTI_DATA O
27
nBOOTMODE I
Disable trace interface in ARM core.
Select alternate output function with GPIO_PACFGH[3:0].
Synchronous CPU trace data bit 2.
Select 4-wire synchronous trace interface in ARM core.
Enable trace interface in ARM core.
Select alternate output function with GPIO_PACFGH[3:0].
Data signal of Packet Trace Interface (PTI).
Disable trace interface in ARM core.
Select alternate output function with GPIO_PACFGH[7:4].
Embedded serial bootloader activation out of reset.
Signal is active during and immediately after a reset on NRST. See
Section 6.2: Resets on page 34 for details.
Synchronous CPU trace data bit 3.
TRACEDATA3 O
28 VDD_PADS Power Pads supply (2.1-3.6 V)
PA 6
29
TIM1_CH3
I/O
High current
O
I Timer 1 channel 3 input (Cannot be remapped.)
Select 4-wire synchronous trace interface in ARM core.
Enable trace interface in ARM core.
Select alternate output function with GPIO_PACFGH[7:4]
Digital I/O
Timer 1 channel 3 output
Enable timer output in TIM1_CCER
Select alternate output function with GPIO_PACFGH[11:8]
Doc ID 018587 Rev 2 20/215
Pinout and pin description STM32W108C8
Table 2. Pin descriptions (continued)
Pin no. Signal Direction Description
PB1 I/O Digital I/O
SPI slave data out of Serial Controller 1
Either disable timer output in TIM2_CCER or disable remap with
SC1MISO O
SC1MOSI O
30
SC1SDA I/O
SC1TXD O
TIM2_OR[4]
Select SPI with SC1_MODE
Select slave with SC1_SPICR
Select alternate output function with GPIO_PBCFGL[7:4]
SPI master data out of Serial Controller 1
Either disable timer output in TIM2_CCER or disable remap with
TIM2_OR[4]
Select SPI with SC1_MODE
Select master with SC1_SPICR
Select alternate output function with GPIO_PBCFGL[7:4]
2
I
C data of Serial Controller 1
Either disable timer output in TIM2_CCER,
or disable remap with TIM2_OR[4]
Select I
2
C with SC1_MODE
Select alternate open-drain output function with GPIO_PBCFGL[7:4]
UART transmit data of Serial Controller 1
Either disable timer output in TIM2_CCER or disable remap with
TIM2_OR[4]
Select UART with SC1_MODE
Select alternate output function with GPIO_PBCFGL[7:4]
TIM2_CH1
(see also Pin 21)
Timer 2 channel 1 output
O
Enable remap with TIM2_OR[4]
Enable timer output in TIM2_CCER
Select alternate output function with GPIO_PACFGL[7:4]
I Timer 2 channel 1 input. Disable remap with TIM2_OR[4].
21/215 Doc ID 018587 Rev 2
STM32W108C8 Pinout and pin description
Table 2. Pin descriptions (continued)
Pin no. Signal Direction Description
PB2 I/O Digital I/O
SPI master data in of Serial Controller 1
31
SC1MISO I
SC1MOSI I
SC1SCL I/O
Select SPI with SC1_MODE
Select master with SC1_SPICR
SPI slave data in of Serial Controller 1
Select SPI with SC1_MODE
Select slave with SC1_SPICR
2
I
C clock of Serial Controller 1
Either disable timer output in TIM2_CCER,
or disable remap with TIM2_OR[5]
Select I
2
C with SC1_MODE
Select alternate open-drain output function with
GPIO_PBCFGL[11:8]
32
33
34
SC1RXD I
TIM2_CH2
O
(see also Pin 25)
SWCLK I/O
JTCK I
PC2 I/O
JTDO O
SWO O
PC3 I/O
JTDI I
UART receive data of Serial Controller 1
Select UART with SC1_MODE
Timer 2 channel 2 output
Enable remap with TIM2_OR[5]
Enable timer output in TIM2_CCER
Select alternate output function with GPIO_PBCFGL[11:8]
I Timer 2 channel 2 input. Enable remap with TIM2_OR[5].
Serial Wire clock input/output with debugger
Selected when in Serial Wire mode (see JTMS description, Pin 35)
JTAG clock input from debugger
Selected when in JTAG mode (default mode, see JTMS description,
Pin 35)
Internal pull-down is enabled
Digital I/O
Enable with GPIO_DBGCFG[5]
JTAG data out to debugger
Selected when in JTAG mode (default mode, see JTMS description,
Pin 35)
Serial Wire Output asynchronous trace output to debugger
Select asynchronous trace interface in ARM core
Enable trace interface in ARM core
Select alternate output function with GPIO_PCCFGL[11:8]
Enable Serial Wire mode (see JTMS description, Pin 35)
Internal pull-up is enabled
Digital I/O
Either Enable with GPIO_DBGCFG[5],
or enable Serial Wire mode (see JTMS description)
JTAG data in from debugger
Selected when in JTAG mode (default mode, see JTMS description,
Pin 35)
Internal pull-up is enabled
Doc ID 018587 Rev 2 22/215
Pinout and pin description STM32W108C8
Table 2. Pin descriptions (continued)
Pin no. Signal Direction Description
35
36
PC4 I/O
JTMS I
SWDIO I/O
PB0 I/O Digital I/O
VREF Analog O
VREF Analog I
IRQA I External interrupt source A.
TRACECLK
(see also Pin 25)
TIM1CLK I Timer 1 external clock input.
TIM2MSK I Timer 2 external clock mask input.
O
Digital I/O
Enable with GPIO_DBGCFG[5]
JTAG mode select from debugger
Selected when in JTAG mode (default mode)
JTAG mode is enabled after power-up or by forcing NRST low
Select Serial Wire mode using the ARM-defined protocol through a
debugger
Internal pull-up is enabled
Serial Wire bidirectional data to/from debugger
Enable Serial Wire mode (see JTMS description)
Select Serial Wire mode using the ARM-defined protocol through a
debugger
Internal pull-up is enabled
ADC reference output.
Enable analog function with GPIO_PBCFGL[3:0].
ADC reference input.
Enable analog function with GPIO_PBCFGL[3:0].
Enable reference output with an ST system function.
Synchronous CPU trace clock.
Enable trace interface in ARM core.
Select alternate output function with GPIO_PBCFGL[3:0].
37 VDD_PADS Power Pads supply (2.1 to 3.6 V).
PC1 I/O Digital I/O
ADC3 Analog
38
39 VDD_MEM Power 1.8 V supply (flash, RAM)
23/215 Doc ID 018587 Rev 2
SWO
(see also Pin 33)
TRACEDATA0 O
O
ADC Input 3
Enable analog function with GPIO_PCCFGL[7:4]
Serial Wire Output asynchronous trace output to debugger
Select asynchronous trace interface in ARM core
Enable trace interface in ARM core
Select alternate output function with GPIO_PCCFGL[7:4]
Synchronous CPU trace data bit 0
Select 1-, 2- or 4-wire synchronous trace interface in ARM core
Enable trace interface in ARM core
Select alternate output function with GPIO_PCCFGL[7:4]
STM32W108C8 Pinout and pin description
Table 2. Pin descriptions (continued)
Pin no. Signal Direction Description
Digital I/O
40
PC0
I/O
High current
JRST I
(1)
IRQD
TRACEDATA1 O
I Default external interrupt source D
Either enable with GPIO_DBGCFG[5],
or enable Serial Wire mode (see JTMS description, Pin 35) and
disable TRACEDATA1
JTAG reset input from debugger
Selected when in JTAG mode (default mode, see JTMS description)
and TRACEDATA1 is disabled
Internal pull-up is enabled
Synchronous CPU trace data bit 1
Select 2- or 4-wire synchronous trace interface in ARM core
Enable trace interface in ARM core
Select alternate output function with GPIO_PCCFGL[3:0]
41
42
43
PB7
I/O
High current
ADC2 Analog
(1)
IRQC
I Default external interrupt source C
Digital I/O
ADC Input 2
Enable analog function with GPIO_PBCFGH[15:12]
Timer 1 channel 2 output
TIM1_CH2
O
Enable timer output in TIM1_CCER
Select alternate output function with GPIO_PBCFGH[15:12]
I Timer 1 channel 2 input (Cannot be remapped)
PB6
I/O
High current
ADC1 Analog
Digital I/O
ADC Input 1
Enable analog function with GPIO_PBCFGH[11:8]
IRQB I External interrupt source B
Timer 1 channel 1 output
TIM1_CH1
O
Enable timer output in TIM1_CCER
Select alternate output function with GPIO_PBCFGH[11:8]
I Timer 1 channel 1 input (Cannot be remapped)
PB5 I/O Digital I/O
ADC0 Analog
ADC Input 0
Enable analog function with GPIO_PBCFGH[7:4]
TIM2CLK I Timer 2 external clock input
TIM1MSK I Timer 2 external clock mask input
44 VDD_CORE Power 1.25 V digital core supply decoupling
45 VDD_PRE Power 1.8 V prescaler supply
46 VDD_SYNTH Power 1.8 V synthesizer supply
47 OSCB I/O
24 MHz crystal oscillator or left open when using external clock input
on OSCA
Doc ID 018587 Rev 2 24/215
Pinout and pin description STM32W108C8
Table 2. Pin descriptions (continued)
Pin no. Signal Direction Description
48 OSCA I/O 24 MHz crystal oscillator or external clock input
49 GND Ground Ground supply pad in the bottom center of the package.
1. IRQC and IRQD external interrupts can be mapped to any digital I/O pin using the using the GPIO_IRQCSEL and
GPIO_IRQDSEL registers.
25/215 Doc ID 018587 Rev 2
STM32W108C8 Embedded memory
-AIN&LASH"LOCK
,OWERMAPPING
.ORMAL-ODE
X
X&&&&
2!-K"
MAPPEDONTO3YSTEM
INTERFACE
X
X&&&
2!-BITBAND
ALIASREGION
MAPPEDONTO3YSTEM
INTERFACE
NOTUSED
X
X
&LASH
2!-
0ER IP HER AL
2EGISTERS
MAPPEDONTO3YSTEM
INTERFACE
2EGISTERBITBAND
ALIASREGION
MAPPEDONTO3YSTEM
INTERFACE
NOTUSED
X
X888
X
X888
.OTUSED
0RIVATEPERIPHBUSINTERNAL
.OTUSED
0RIVATEPERIPHBUSEXTERNAL
.OTUSED
.OTUSED
.OTUSED
X%
)4-
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X%
X%
X%
X%%
X%&
X%&&&&
X%
X%
X%
X%&&
X%&&&&&
X%
X
X
X
X
X!
X&&&&&&&&
X$&&&&&&&
X&&&&&&&
X&&&&&&&
X&&&&&&&
X&&&&&&&
&IXED)NFO"LOCKK"
#USTOMER)NFO"LOCKK"
X
X&&
X&&
X
-AIN&LASH"LOCKK"
5PPERMAPPING
"OOTMODE
X
X&&&&
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/PTIONALBOOT MODE
MAPS &IXED)NFO"LOCK
TO THESTARTOFMEMORY
X&&
.OTUSED
.OTUSED
K"
-36
4 Embedded memory
Figure 3. STM32W108C8 memory mapping
Doc ID 018587 Rev 2 26/215
Embedded memory STM32W108C8
4.1 Flash memory
The STM32W108C8 provides a total of 66.5 Kbytes of Flash memory in three separate
blocks:
● Main Flash Block (MFB)
● Fixed Information Block (FIB)
● Customer Information Block (CIB)
The MFB is divided into 641024-byte pages. The CIB is a single 512-byte page. The FIB is a
single 2048-byte page. The smallest erasable unit is one page and the smallest writable unit
is an aligned 16-bit half-word. The flash is rated to have a guaranteed 1,000 write/erase
cycles. The flash cell has been qualified for a data retention time of >100 years at room
temperature.
Flash may be programmed either through the Serial Wire/JTAG interface or through
bootloader software. Programming flash through Serial Wire/JTAG requires the assistance
of RAM-based utility code. Programming through a bootloader requires specific software for
over-the-air loading or serial link loading. A simplified, serial-link-only bootloader is also
available preprogrammed into the FIB.
4.2 Random-access memory
The STM32W108C8 has 8 Kbytes of static RAM on-chip. The start of RAM is mapped to
address 0x20000000. Although the ARM® Cortex-M3 allows bit band accesses to this
address region, the standard MPU configuration does not permit use of the bit-band feature.
The RAM is physically connected to the AHB System bus and is therefore accessible to both
the ARM® Cortex-M3 microprocessor and the debugger. The RAM can be accessed for
both instruction and data fetches as bytes, half words, or words. The standard MPU
configuration does not permit execution from the RAM, but for special purposes, such as
programming the main flash block, the MPU may be disabled. To the bus, the RAM appears
as 32-bit wide memory and in most situations has zero wait state read or write access. In
the higher CPU clock mode the RAM requires two wait states. This is handled by hardware
transparent to the user application with no configuration required.
4.2.1 Direct memory access (DMA) to RAM
Several of the peripherals are equipped with DMA controllers allowing them to transfer data
into and out of RAM autonomously. This applies to the radio (802.15.4 MAC), general
purpose ADC, and both serial controllers. In the case of the serial controllers, the DMA is full
duplex so that a read and a write to RAM may be requested at the same time. Thus there
are six DMA channels in total.
The STM32W108C8 integrates a DMA arbiter that ensures fair access to the
microprocessor as well as the peripherals through a fixed priority scheme appropriate to the
memory bandwidth requirements of each master. The priority scheme is as follows, with the
top peripheral being the highest priority:
1. General Purpose ADC
2. Serial Controller 2 Receive
3. Serial Controller 2 Transmit
4. MAC
5. Serial Controller 1 Receive
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STM32W108C8 Embedded memory
6. Serial Controller 1 Transmit
4.2.2 RAM memory protection
The STM32W108C8 integrates two memory protection mechanisms. The first memory
protection mechanism is through the ARM® Cortex-M3 Memory Protection Unit (MPU)
described in the Memory Protection Unit section. The MPU may be used to protect any area
of memory. MPU configuration is normally handled by software. The second memory
protection mechanism is through a fine granularity RAM protection module. This allows
segmentation of the RAM into 32-byte blocks where any block can be marked as write
protected. An attempt to write to a protected RAM block using a user mode write results in a
bus error being signaled on the AHB System bus. A system mode write is allowed at any
time and reads are allowed in either mode. The main purpose of this fine granularity RAM
protection module is to notify the stack of erroneous writes to system areas of memory. RAM
protection is configured using a group of registers that provide a bit map. Each bit in the map
represents a 32-byte block of RAM. When the bit is set the block is write protected.
The fine granularity RAM memory protection mechanism is also available to the peripheral
DMA controllers. A register bit is provided to enable the memory protection to include DMA
writes to protected memory. If a DMA write is made to a protected location in RAM, a
management interrupt is generated. At the same time the faulting address and the
identification of the peripheral is captured for later debugging. Note that only peripherals
capable of writing data to RAM, such as received packet data or a received serial port
character, can generate this interrupt.
4.3 Memory protection unit
The STM32W108C8 includes the ARM® Cortex-M3 Memory Protection Unit, or MPU. The
MPU controls access rights and characteristics of up to eight address regions, each of
which may be divided into eight equal sub-regions. Refer to the ARM® Cortex-M3 Technical
Reference Manual (DDI 0337A) for a detailed description of the MPU.
ST software configures the MPU in a standard configuration and application software should
not modify it. The configuration is designed for optimal detection of illegal instruction or data
accesses. If an illegal access is attempted, the MPU captures information about the access
type, the address being accessed, and the location of the offending software. This simplifies
software debugging and increases the reliability of deployed devices. As a consequence of
this MPU configuration, accessing RAM and register bit-band address alias regions is not
permitted, and generates a bus fault if attempted.
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Radio frequency module STM32W108C8
5 Radio frequency module
The radio module consists of an analog front end and digital baseband as shown in
Figure 1: STM32W108C8 block diagram.
5.1 Receive (Rx) path
The Rx path uses a low-IF, super-heterodyne receiver that rejects the image frequency
using complex mixing and polyphase filtering. In the analog domain, the input RF signal
from the antenna is first amplified and mixed down to a 4 MHz IF frequency. The mixers'
output is filtered, combined, and amplified before being sampled by a 12 Msps ADC. The
digitized signal is then demodulated in the digital baseband. The filtering within the Rx path
improves the STM32W108C8's co-existence with other 2.4 GHz transceivers such as IEEE
802.15.4, IEEE 802.11g, and Bluetooth radios. The digital baseband also provides gain
control of the Rx path, both to enable the reception of small and large wanted signals and to
tolerate large interferers.
5.1.1 Rx baseband
The STM32W108C8 Rx digital baseband implements a coherent demodulator for optimal
performance. The baseband demodulates the O-QPSK signal at the chip level and
synchronizes with the IEEE 802.15.4-defined preamble. An automatic gain control (AGC)
module adjusts the analog gain continuously every ¼ symbol until the preamble is detected.
Once detected, the gain is fixed for the remainder of the packet. The baseband despreads
the demodulated data into 4-bit symbols. These symbols are buffered and passed to the
hardware-based MAC module for packet assembly and filtering.
In addition, the Rx baseband provides the calibration and control interface to the analog Rx
modules, including the LNA, Rx baseband filter, and modulation modules. The ST RF
software driver includes calibration algorithms that use this interface to reduce the effects of
silicon process and temperature variation.
5.1.2 RSSI and CCA
The STM32W108C8 calculates the RSSI over every 8-symbol period as well as at the end
of a received packet. The linear range of RSSI is specified to be at least 40 dB over
temperature. At room temperature, the linear range is approximately 60 dB (-90 dBm to -30
dBm input signal).
The STM32W108C8 Rx baseband provides support for the IEEE 802.15.4-2003 RSSI CCA
method, Clear channel reports busy medium if RSSI exceeds its threshold.
5.2 Transmit (Tx) path
The STM32W108C8 Tx path produces an O-QPSK-modulated signal using the analog front
end and digital baseband. The area- and power-efficient Tx architecture uses a two-point
modulation scheme to modulate the RF signal generated by the synthesizer. The modulated
RF signal is fed to the integrated PA and then out of the STM32W108C8.
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