ST STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx, STM32F107xx Reference Manual

RM0034

Reference manual

STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx

and STM32F107xx advanced ARM-based 32-bit MCUs

Introduction

This reference manual targets application developers. It provides complete information on
how to use the STM32F101xx, STM32F102xx, STM32F103xx and
STM32F105xx/STM32F107xx microcontroller memory and peripherals. The STM32F101xx,
STM32F102xx, STM32F103xx and STM32F105xx/STM32F107xx will be referred to as
STM32F10xxx throughout the document, unless otherwise specified.

The STM32F10xxx is a family of microcontrollers with different memory sizes, packages and
peripherals.

For ordering information, mechanical and electrical device characteristics please refer to the
low-, medium- and high-density STM32F101xx and STM32F103xx datasheets, to the low-
and medium-density STM32F102xx datasheets and to the STM32F105xx/STM32F107xx
connectivity line datasheet.

For information on programming, erasing and protection of the internal Flash memory
please refer to the STM32F10xxx Flash programming manual.

For information on the ARM Cortex™-M3 core, please refer to the Cortex™-M3 Technical
Reference Manual.

Related documents

Available from www.arm.com:

■

Cortex™-M3 Technical Reference Manual, available from:

http://infocenter.arm.com/help/topic/com.arm.doc.ddi0337e/DDI0337E_cortex_m3_r1p1_trm.pdf

Available from www.st.com:

■

STM32F101xx STM32F103xx datasheets

■

STM32F10xxx Flash programming manual

March 2009 Rev 1 1/959

www.st.com

Contents RM0034

Contents

1 Documentation conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

1.1 List of abbreviations for registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

1.2 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

1.3 Peripheral availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

2 Memory and bus architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

2.1 System architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

2.2 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

2.3 Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

2.3.1 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

2.3.2 Bit banding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

2.3.3 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

2.4 Boot configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

3 CRC calculation unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

3.1 CRC introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

3.2 CRC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

3.3 CRC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

3.4 CRC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

3.4.1 Data register (CRC_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

3.4.2 Independent data register (CRC_IDR) . . . . . . . . . . . . . . . . . . . . . . . . . 50

3.4.3 Control register (CRC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

3.4.4 CRC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

4 Power control (PWR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

4.1 Power supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

4.1.1 Independent A/D converter supply and reference voltage . . . . . . . . . . . 52

4.1.2 Battery backup domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

4.1.3 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

4.2 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

4.2.1 Power on reset (POR)/power down reset (PDR) . . . . . . . . . . . . . . . . . . 53

4.2.2 Programmable voltage detector (PVD) . . . . . . . . . . . . . . . . . . . . . . . . . 54

4.3 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

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4.3.1 Slowing down system clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

4.3.2 Peripheral clock gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

4.3.3 Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

4.3.4 Stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

4.3.5 Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

4.3.6 Auto-wakeup (AWU) from low-power mode . . . . . . . . . . . . . . . . . . . . . . 60

4.4 Power control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

4.4.1 Power control register (PWR_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

4.4.2 Power control/status register (PWR_CSR) . . . . . . . . . . . . . . . . . . . . . . 62

4.4.3 PWR register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

5 Backup registers (BKP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

5.1 BKP introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

5.2 BKP main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

5.3 BKP functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

5.3.1 Tamper detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

5.3.2 RTC calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

5.4 BKP registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

5.4.1 Backup data register x (BKP_DRx) (x = 1 ..42) . . . . . . . . . . . . . . . . . . . 66

5.4.2 RTC clock calibration register (BKP_RTCCR) . . . . . . . . . . . . . . . . . . . . 66

5.4.3 Backup control register (BKP_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

5.4.4 Backup control/status register (BKP_CSR) . . . . . . . . . . . . . . . . . . . . . . 68

5.4.5 BKP register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

6 Low-, medium- and high-density reset and clock control (RCC) . . . . 72

6.1 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

6.1.1 System reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

6.1.2 Power reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

6.1.3 Backup domain reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

6.2 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

6.2.1 HSE clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

6.2.2 HSI clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

6.2.3 PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

6.2.4 LSE clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

6.2.5 LSI clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

6.2.6 System clock (SYSCLK) selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

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6.2.7 Clock security system (CSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

6.2.8 RTC clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

6.2.9 Watchdog clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

6.2.10 Clock-out capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

6.3 RCC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

6.3.1 Clock control register (RCC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

6.3.2 Clock configuration register (RCC_CFGR) . . . . . . . . . . . . . . . . . . . . . . 82

6.3.3 Clock interrupt register (RCC_CIR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

6.3.4 APB2 peripheral reset register (RCC_APB2RSTR) . . . . . . . . . . . . . . . 87

6.3.5 APB1 peripheral reset register (RCC_APB1RSTR) . . . . . . . . . . . . . . . 89

6.3.6 AHB peripheral clock enable register (RCC_AHBENR) . . . . . . . . . . . . 91

6.3.7 APB2 peripheral clock enable register (RCC_APB2ENR) . . . . . . . . . . . 93

6.3.8 APB1 peripheral clock enable register (RCC_APB1ENR) . . . . . . . . . . . 95

6.3.9 Backup domain control register (RCC_BDCR) . . . . . . . . . . . . . . . . . . . 97

6.3.10 Control/status register (RCC_CSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

6.3.11 RCC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

7 Connectivity line devices: reset and clock control (RCC) . . . . . . . . . 102

7.1 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

7.1.1 System reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

7.1.2 Power reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

7.1.3 Backup domain reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

7.2 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

7.2.1 HSE clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

7.2.2 HSI clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

7.2.3 PLLs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

7.2.4 LSE clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

7.2.5 LSI clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

7.2.6 System clock (SYSCLK) selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

7.2.7 Clock security system (CSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

7.2.8 RTC clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

7.2.9 Watchdog clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

7.2.10 Clock-out capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

7.3 RCC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

7.3.1 Clock control register (RCC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

7.3.2 Clock configuration register (RCC_CFGR) . . . . . . . . . . . . . . . . . . . . . 113

7.3.3 Clock interrupt register (RCC_CIR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

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7.3.4 APB2 peripheral reset register (RCC_APB2RSTR) . . . . . . . . . . . . . . 119

7.3.5 APB1 peripheral reset register (RCC_APB1RSTR) . . . . . . . . . . . . . . 120

7.3.6 AHB Peripheral Clock enable register (RCC_AHBENR) . . . . . . . . . . . 123

7.3.7 APB2 peripheral clock enable register (RCC_APB2ENR) . . . . . . . . . . 124

7.3.8 APB1 peripheral clock enable register (RCC_APB1ENR) . . . . . . . . . . 126

7.3.9 Backup domain control register (RCC_BDCR) . . . . . . . . . . . . . . . . . . 129

7.3.10 Control/status register (RCC_CSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

7.3.11 AHB Peripheral Clock reset register (RCC_AHBRSTR) . . . . . . . . . . . 132

7.3.12 Clock configuration register2 (RCC_CFGR2) . . . . . . . . . . . . . . . . . . . 133

7.3.13 RCC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

8 General-purpose and alternate-function I/Os (GPIOs and AFIOs) . . 137

8.1 GPIO functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

8.1.1 General-purpose I/O (GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

8.1.2 Atomic bit set or reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

8.1.3 External interrupt/wakeup lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

8.1.4 Alternate functions (AF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

8.1.5 Software remapping of I/O alternate functions . . . . . . . . . . . . . . . . . . 140

8.1.6 GPIO locking mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

8.1.7 Input configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

8.1.8 Output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

8.1.9 Alternate function configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

8.1.10 Analog input configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

8.2 GPIO registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

8.2.1 Port configuration register low (GPIOx_CRL) (x=A..G) . . . . . . . . . . . . 144

8.2.2 Port configuration register high (GPIOx_CRH) (x=A..G) . . . . . . . . . . . 145

8.2.3 Port input data register (GPIOx_IDR) (x=A..G) . . . . . . . . . . . . . . . . . . 145

8.2.4 Port output data register (GPIOx_ODR) (x=A..G) . . . . . . . . . . . . . . . . 146

8.2.5 Port bit set/reset register (GPIOx_BSRR) (x=A..G) . . . . . . . . . . . . . . . 146

8.2.6 Port bit reset register (GPIOx_BRR) (x=A..G) . . . . . . . . . . . . . . . . . . . 147

8.2.7 Port configuration lock register (GPIOx_LCKR) (x=A..G) . . . . . . . . . . 147

8.3 Alternate function I/O and debug configuration (AFIO) . . . . . . . . . . . . . 148

8.3.1 Using OSC32_IN/OSC32_OUT pins as GPIO ports PC14/PC15 . . . . 148

8.3.2 Using OSC_IN/OSC_OUT pins as GPIO ports PD0/PD1 . . . . . . . . . . 148

8.3.3 CAN1 alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

8.3.4 CAN2 alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

8.3.5 JTAG/SWD alternate function remapping . . . . . . . . . . . . . . . . . . . . . . 149

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Contents RM0034

8.3.6 ADC alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

8.3.7 Timer alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

8.3.8 USART Alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . 152

8.3.9 I2C 1 alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

8.3.10 SPI 1 alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

8.3.11 SPI 3 alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

8.3.12 Ethernet alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . 154

8.4 AFIO registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

8.4.1 Event control register (AFIO_EVCR) . . . . . . . . . . . . . . . . . . . . . . . . . . 154

8.4.2 AF remap and debug I/O configuration register (AFIO_MAPR) . . . . . . 155

8.4.3 External interrupt configuration register 1 (AFIO_EXTICR1) . . . . . . . . 158

8.4.4 External interrupt configuration register 2 (AFIO_EXTICR2) . . . . . . . . 159

8.4.5 External interrupt configuration register 3 (AFIO_EXTICR3) . . . . . . . . 159

8.4.6 External interrupt configuration register 4 (AFIO_EXTICR4) . . . . . . . . 160

8.5 GPIO and AFIO register maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160

9 Interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

9.1 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 162

9.1.1 SysTick calibration value register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

9.1.2 Interrupt and exception vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

9.2 External interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . . 167

9.2.1 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

9.2.2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

9.2.3 Wakeup event management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

9.2.4 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

9.2.5 External interrupt/event line mapping . . . . . . . . . . . . . . . . . . . . . . . . . 169

9.3 EXTI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

9.3.1 Interrupt mask register (EXTI_IMR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

9.3.2 Event mask register (EXTI_EMR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

9.3.3 Rising trigger selection register (EXTI_RTSR) . . . . . . . . . . . . . . . . . . 172

9.3.4 Falling trigger selection register (EXTI_FTSR) . . . . . . . . . . . . . . . . . . 172

9.3.5 Software interrupt event register (EXTI_SWIER) . . . . . . . . . . . . . . . . . 173

9.3.6 Pending register (EXTI_PR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

9.3.7 EXTI register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174

10 DMA controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

10.1 DMA introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

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10.2 DMA main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

10.3 DMA functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

10.3.1 DMA transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

10.3.2 Arbiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

10.3.3 DMA channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

10.3.4 Programmable data width, data alignment and endians . . . . . . . . . . . 179

10.3.5 Error management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180

10.3.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180

10.3.7 DMA request mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180

10.4 DMA registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184

10.4.1 DMA interrupt status register (DMA_ISR) . . . . . . . . . . . . . . . . . . . . . . 184

10.4.2 DMA interrupt flag clear register (DMA_IFCR) . . . . . . . . . . . . . . . . . . 185

10.4.3 DMA channel x configuration register (DMA_CCRx) (x = 1 ..7) . . . . . . 186

10.4.4 DMA channel x number of data register (DMA_CNDTRx) (x = 1 ..7) . 187

10.4.5 DMA channel x peripheral address register (DMA_CPARx) (x = 1 ..7) 188

10.4.6 DMA channel x memory address register (DMA_CMARx) (x = 1 ..7) . 188

10.4.7 DMA register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189

11 Analog-to-digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191

11.1 ADC introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191

11.2 ADC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191

11.3 ADC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192

11.3.1 ADC on-off control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194

11.3.2 ADC clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194

11.3.3 Channel selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194

11.3.4 Single conversion mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195

11.3.5 Continuous conversion mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195

11.3.6 Timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195

11.3.7 Analog watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196

11.3.8 Scan mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197

11.3.9 Injected channel management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197

11.3.10 Discontinuous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198

11.4 Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199

11.5 Data alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199

11.6 Channel-by-channel programmable sample time . . . . . . . . . . . . . . . . . . 200

11.7 Conversion on external trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200

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11.8 DMA request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202

11.9 Dual ADC mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203

11.9.1 Injected simultaneous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205

11.9.2 Regular simultaneous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205

11.9.3 Fast interleaved mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206

11.9.4 Slow interleaved mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206

11.9.5 Alternate trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207

11.9.6 Independent mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208

11.9.7 Combined regular/injected simultaneous mode . . . . . . . . . . . . . . . . . . 208

11.9.8 Combined regular simultaneous + alternate trigger mode . . . . . . . . . . 208

11.9.9 Combined injected simultaneous + interleaved . . . . . . . . . . . . . . . . . . 209

11.10 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210

11.11 ADC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211

11.12 ADC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212

11.12.1 ADC status register (ADC_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212

11.12.2 ADC control register 1 (ADC_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 213

11.12.3 ADC control register 2 (ADC_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . 215

11.12.4 ADC sample time register 1 (ADC_SMPR1) . . . . . . . . . . . . . . . . . . . . 218

11.12.5 ADC sample time register 2 (ADC_SMPR2) . . . . . . . . . . . . . . . . . . . . 219

11.12.6 ADC injected channel data offset register x (ADC_JOFRx)(x=1..4) . . 219

11.12.7 ADC watchdog high threshold register (ADC_HTR) . . . . . . . . . . . . . . 220

11.12.8 ADC watchdog low threshold register (ADC_LTR) . . . . . . . . . . . . . . . 220

11.12.9 ADC regular sequence register 1 (ADC_SQR1) . . . . . . . . . . . . . . . . . 220

11.12.10 ADC regular sequence register 2 (ADC_SQR2) . . . . . . . . . . . . . . . . . 221

11.12.11 ADC regular sequence register 3 (ADC_SQR3) . . . . . . . . . . . . . . . . . 222

11.12.12 ADC injected sequence register (ADC_JSQR) . . . . . . . . . . . . . . . . . . 222

11.12.13 ADC injected data register x (ADC_JDRx) (x= 1..4) . . . . . . . . . . . . . . 223

11.12.14 ADC regular data register (ADC_DR) . . . . . . . . . . . . . . . . . . . . . . . . . 223

11.12.15 ADC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224

12 Digital-to-analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226

12.1 DAC introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226

12.2 DAC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226

12.3 DAC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228

12.3.1 DAC channel enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228

12.3.2 DAC output buffer enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228

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12.3.3 DAC data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228

12.3.4 DAC conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229

12.3.5 DAC output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230

12.3.6 DAC trigger selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230

12.3.7 DMA request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231

12.3.8 Noise generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231

12.3.9 Triangle-wave generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232

12.4 Dual DAC channel conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233

12.4.1 Independent trigger without wave generation . . . . . . . . . . . . . . . . . . . 233

12.4.2 Independent trigger with same LFSR generation . . . . . . . . . . . . . . . . 234

12.4.3 Independent trigger with different LFSR generation . . . . . . . . . . . . . . 234

12.4.4 Independent trigger with same triangle generation . . . . . . . . . . . . . . . 234

12.4.5 Independent trigger with different triangle generation . . . . . . . . . . . . . 235

12.4.6 Simultaneous software start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235

12.4.7 Simultaneous trigger without wave generation . . . . . . . . . . . . . . . . . . 235

12.4.8 Simultaneous trigger with same LFSR generation . . . . . . . . . . . . . . . 236

12.4.9 Simultaneous trigger with different LFSR generation . . . . . . . . . . . . . 236

12.4.10 Simultaneous trigger with same triangle generation . . . . . . . . . . . . . . 236

12.4.11 Simultaneous trigger with different triangle generation . . . . . . . . . . . . 237

12.5 DAC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237

12.5.1 DAC control register (DAC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237

12.5.2 DAC software trigger register (DAC_SWTRIGR) . . . . . . . . . . . . . . . . . 240

12.5.3 DAC channel1 12-bit right-aligned data holding register

(DAC_DHR12R1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240

12.5.4 DAC channel1 12-bit left aligned data holding register

(DAC_DHR12L1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241

12.5.5 DAC channel1 8-bit right aligned data holding register

(DAC_DHR8R1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241

12.5.6 DAC channel2 12-bit right aligned data holding register

(DAC_DHR12R2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241

12.5.7 DAC channel2 12-bit left aligned data holding register

(DAC_DHR12L2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242

12.5.8 DAC channel2 8-bit right-aligned data holding register

(DAC_DHR8R2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242

12.5.9 Dual DAC 12-bit right-aligned data holding register

(DAC_DHR12RD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242

12.5.10 DUAL DAC 12-bit left aligned data holding register

(DAC_DHR12LD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243

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12.5.11 DUAL DAC 8-bit right aligned data holding register

(DAC_DHR8RD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243

12.5.12 DAC channel1 data output register (DAC_DOR1) . . . . . . . . . . . . . . . . 244

12.5.13 DAC channel2 data output register (DAC_DOR2) . . . . . . . . . . . . . . . . 244

12.5.14 DAC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245

13 Advanced-control timers (TIM1&TIM8) . . . . . . . . . . . . . . . . . . . . . . . . 246

13.1 TIM1&TIM8 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246

13.2 TIM1&TIM8 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246

13.3 TIM1&TIM8 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249

13.3.1 Time-base unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249

13.3.2 Counter modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250

13.3.3 Repetition counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258

13.3.4 Clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260

13.3.5 Capture/compare channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262

13.3.6 Input capture mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264

13.3.7 PWM input mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265

13.3.8 Forced output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266

13.3.9 Output compare mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267

13.3.10 PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268

13.3.11 Complementary outputs and dead-time insertion . . . . . . . . . . . . . . . . 271

13.3.12 Using the break function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272

13.3.13 Clearing the OCxREF signal on an external event . . . . . . . . . . . . . . . 275

13.3.14 6-step PWM generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276

13.3.15 One-pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277

13.3.16 Encoder interface mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278

13.3.17 Timer input XOR function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281

13.3.18 Interfacing with Hall sensors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281

13.3.19 TIMx and external trigger synchronization . . . . . . . . . . . . . . . . . . . . . . 283

13.3.20 Timer synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286

13.3.21 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286

13.4 TIM1&TIM8 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287

13.4.1 Control register 1 (TIMx_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287

13.4.2 Control register 2 (TIMx_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288

13.4.3 Slave mode control register (TIMx_SMCR) . . . . . . . . . . . . . . . . . . . . . 290

13.4.4 DMA/Interrupt enable register (TIMx_DIER) . . . . . . . . . . . . . . . . . . . . 292

13.4.5 Status register (TIMx_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294

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13.4.6 Event generation register (TIMx_EGR) . . . . . . . . . . . . . . . . . . . . . . . . 295

13.4.7 Capture/compare mode register 1 (TIMx_CCMR1) . . . . . . . . . . . . . . . 296

13.4.8 Capture/compare mode register 2 (TIMx_CCMR2) . . . . . . . . . . . . . . . 300

13.4.9 Capture/compare enable register (TIMx_CCER) . . . . . . . . . . . . . . . . . 301

13.4.10 Counter (TIMx_CNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304

13.4.11 Prescaler (TIMx_PSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304

13.4.12 Auto-reload register (TIMx_ARR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304

13.4.13 Repetition counter register (TIMx_RCR) . . . . . . . . . . . . . . . . . . . . . . . 305

13.4.14 Capture/compare register 1 (TIMx_CCR1) . . . . . . . . . . . . . . . . . . . . . 305

13.4.15 Capture/compare register 2 (TIMx_CCR2) . . . . . . . . . . . . . . . . . . . . . 306

13.4.16 Capture/compare register 3 (TIMx_CCR3) . . . . . . . . . . . . . . . . . . . . . 306

13.4.17 Capture/compare register 4 (TIMx_CCR4) . . . . . . . . . . . . . . . . . . . . . 307

13.4.18 Break and dead-time register (TIMx_BDTR) . . . . . . . . . . . . . . . . . . . . 307

13.4.19 DMA control register (TIMx_DCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309

13.4.20 DMA address for full transfer (TIMx_DMAR) . . . . . . . . . . . . . . . . . . . . 310

13.4.21 TIM1&TIM8 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310

14 General-purpose timer (TIMx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312

14.1 TIMx introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312

14.2 TIMx main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313

14.3 TIMx functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314

14.3.1 Time-base unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314

14.3.2 Counter modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316

14.3.3 Clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324

14.3.4 Capture/compare channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327

14.3.5 Input capture mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329

14.3.6 PWM input mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330

14.3.7 Forced output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330

14.3.8 Output compare mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331

14.3.9 PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332

14.3.10 One pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335

14.3.11 Clearing the OCxREF signal on an external event . . . . . . . . . . . . . . . 336

14.3.12 Encoder interface mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337

14.3.13 Timer input XOR function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339

14.3.14 Timers and external trigger synchronization . . . . . . . . . . . . . . . . . . . . 339

14.3.15 Timer synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342

14.3.16 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347

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14.4 TIMx registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348

14.4.1 Control register 1 (TIMx_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348

14.4.2 Control register 2 (TIMx_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349

14.4.3 Slave mode control register (TIMx_SMCR) . . . . . . . . . . . . . . . . . . . . . 350

14.4.4 DMA/Interrupt enable register (TIMx_DIER) . . . . . . . . . . . . . . . . . . . . 353

14.4.5 Status register (TIMx_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354

14.4.6 Event generation register (TIMx_EGR) . . . . . . . . . . . . . . . . . . . . . . . . 355

14.4.7 Capture/compare mode register 1 (TIMx_CCMR1) . . . . . . . . . . . . . . . 356

14.4.8 Capture/compare mode register 2 (TIMx_CCMR2) . . . . . . . . . . . . . . . 360

14.4.9 Capture/compare enable register (TIMx_CCER) . . . . . . . . . . . . . . . . . 361

14.4.10 Counter (TIMx_CNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362

14.4.11 Prescaler (TIMx_PSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363

14.4.12 Auto-reload register (TIMx_ARR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363

14.4.13 Capture/compare register 1 (TIMx_CCR1) . . . . . . . . . . . . . . . . . . . . . 363

14.4.14 Capture/compare register 2 (TIMx_CCR2) . . . . . . . . . . . . . . . . . . . . . 364

14.4.15 Capture/compare register 3 (TIMx_CCR3) . . . . . . . . . . . . . . . . . . . . . 364

14.4.16 Capture/compare register 4 (TIMx_CCR4) . . . . . . . . . . . . . . . . . . . . . 365

14.4.17 DMA control register (TIMx_DCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365

14.4.18 DMA address for full transfer (TIMx_DMAR) . . . . . . . . . . . . . . . . . . . . 366

14.4.19 TIMx register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366

15 Basic timers (TIM6&TIM7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368

15.1 TIM6&TIM7 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368

15.2 TIM6&TIM7 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368

15.3 TIM6&TIM7 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369

15.3.1 Time-base unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369

15.3.2 Counting mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371

15.3.3 Clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373

15.3.4 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374

15.4 TIM6&TIM7 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374

15.4.1 Control register 1 (TIMx_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374

15.4.2 Control register 2 (TIMx_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376

15.4.3 DMA/Interrupt enable register (TIMx_DIER) . . . . . . . . . . . . . . . . . . . . 376

15.4.4 Status register (TIMx_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377

15.4.5 Event generation register (TIMx_EGR) . . . . . . . . . . . . . . . . . . . . . . . . 377

15.4.6 Counter (TIMx_CNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377

15.4.7 Prescaler (TIMx_PSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378

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15.4.8 Auto-reload register (TIMx_ARR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378

15.4.9 TIM6&TIM7 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379

16 Real-time clock (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380

16.1 RTC introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380

16.2 RTC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381

16.3 RTC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381

16.3.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381

16.3.2 Resetting RTC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383

16.3.3 Reading RTC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383

16.3.4 Configuring RTC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383

16.3.5 RTC flag assertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384

16.4 RTC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385

16.4.1 RTC control register high (RTC_CRH) . . . . . . . . . . . . . . . . . . . . . . . . 385

16.4.2 RTC control register low (RTC_CRL) . . . . . . . . . . . . . . . . . . . . . . . . . . 386

16.4.3 RTC prescaler load register (RTC_PRLH / RTC_PRLL) . . . . . . . . . . . 387

16.4.4 RTC prescaler divider register (RTC_DIVH / RTC_DIVL) . . . . . . . . . . 388

16.4.5 RTC counter register (RTC_CNTH / RTC_CNTL) . . . . . . . . . . . . . . . . 389

16.4.6 RTC alarm register high (RTC_ALRH / RTC_ALRL) . . . . . . . . . . . . . . 390

16.4.7 RTC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391

17 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392

17.1 IWDG introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392

17.2 IWDG main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392

17.3 IWDG functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392

17.3.1 Hardware watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393

17.3.2 Register access protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393

17.3.3 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393

17.4 IWDG registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394

17.4.1 Key register (IWDG_KR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394

17.4.2 Prescaler register (IWDG_PR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394

17.4.3 Reload register (IWDG_RLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395

17.4.4 Status register (IWDG_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 396

17.4.5 IWDG register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 396

18 Window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397

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18.1 WWDG introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397

18.2 WWDG main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397

18.3 WWDG functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397

18.4 How to program the watchdog timeout . . . . . . . . . . . . . . . . . . . . . . . . . . 399

18.5 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400

18.6 Debug registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400

18.6.1 Control register (WWDG_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400

18.6.2 Configuration register (WWDG_CFR) . . . . . . . . . . . . . . . . . . . . . . . . . 400

18.6.3 Status register (WWDG_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401

18.6.4 WWDG register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401

19 Flexible static memory controller (FSMC) . . . . . . . . . . . . . . . . . . . . . 402

19.1 FSMC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402

19.2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 403

19.3 AHB interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 404

19.3.1 Supported memories and transactions . . . . . . . . . . . . . . . . . . . . . . . . 404

19.4 External device address mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405

19.4.1 NOR/PSRAM address mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405

19.4.2 NAND/PC Card address mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . 406

19.5 NOR Flash/PSRAM controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407

19.5.1 External memory interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 408

19.5.2 Supported memories and transactions . . . . . . . . . . . . . . . . . . . . . . . . 410

19.5.3 General timing rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411

19.5.4 NOR Flash/PSRAM controller timing diagrams . . . . . . . . . . . . . . . . . . 411

19.5.5 Synchronous burst transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 424

19.5.6 NOR/PSRAM controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 430

19.6 NAND Flash/PC Card controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435

19.6.1 External memory interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 436

19.6.2 NAND Flash / PC Card supported memories and transactions . . . . . . 438

19.6.3 Timing diagrams for NAND, ATA and PC Card . . . . . . . . . . . . . . . . . . 438

19.6.4 NAND Flash operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439

19.6.5 NAND Flash pre-wait functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . 440

19.6.6 Error correction code computation ECC (NAND Flash) . . . . . . . . . . . . 441

19.6.7 NAND Flash/PC Card controller registers . . . . . . . . . . . . . . . . . . . . . . 441

19.6.8 FSMC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 447

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20 Secure digital input/output interface (SDIO) . . . . . . . . . . . . . . . . . . . . 449

20.1 SDIO main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 449

20.2 SDIO bus topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450

20.3 SDIO functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 452

20.3.1 SDIO adapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453

20.3.2 SDIO AHB interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 463

20.4 Card functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 464

20.4.1 Card identification mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 464

20.4.2 Card reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 464

20.4.3 Operating voltage range validation . . . . . . . . . . . . . . . . . . . . . . . . . . . 464

20.4.4 Card identification process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 465

20.4.5 Block write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 466

20.4.6 Block read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 466

20.4.7 Stream access, stream write and stream read (MultiMediaCard only) 467

20.4.8 Erase: group erase and sector erase . . . . . . . . . . . . . . . . . . . . . . . . . . 468

20.4.9 Wide bus selection or deselection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 468

20.4.10 Protection management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 469

20.4.11 Card status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 472

20.4.12 SD status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 475

20.4.13 SD I/O mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 479

20.4.14 Commands and responses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 480

20.5 Response formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 483

20.5.1 R1 (normal response command) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 483

20.5.2 R1b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 484

20.5.3 R2 (CID, CSD register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 484

20.5.4 R3 (OCR register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 484

20.5.5 R4 (Fast I/O) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485

20.5.6 R4b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485

20.5.7 R5 (interrupt request) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 486

20.5.8 R6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 486

20.6 SDIO I/O card-specific operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 487

20.6.1 SDIO I/O read wait operation by SDIO_D2 signalling . . . . . . . . . . . . . 487

20.6.2 SDIO read wait operation by stopping SDIO_CK . . . . . . . . . . . . . . . . 487

20.6.3 SDIO suspend/resume operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 488

20.6.4 SDIO interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 488

20.7 CE-ATA specific operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 488

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20.7.1 Command completion signal disable . . . . . . . . . . . . . . . . . . . . . . . . . . 488

20.7.2 Command completion signal enable . . . . . . . . . . . . . . . . . . . . . . . . . . 488

20.7.3 CE-ATA interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 489

20.7.4 Aborting CMD61 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 489

20.8 HW flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 489

20.9 SDIO registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 489

20.9.1 SDIO power control register (SDIO_POWER) . . . . . . . . . . . . . . . . . . . 489

20.9.2 SDI clock control register (SDIO_CLKCR) . . . . . . . . . . . . . . . . . . . . . . 490

20.9.3 SDIO argument register (SDIO_ARG) . . . . . . . . . . . . . . . . . . . . . . . . . 491

20.9.4 SDIO command register (SDIO_CMD) . . . . . . . . . . . . . . . . . . . . . . . . 491

20.9.5 SDIO command response register (SDIO_RESPCMD) . . . . . . . . . . . 492

20.9.6 SDIO response 1..4 register (SDIO_RESPx) . . . . . . . . . . . . . . . . . . . 493

20.9.7 SDIO data timer register (SDIO_DTIMER) . . . . . . . . . . . . . . . . . . . . . 493

20.9.8 SDIO data length register (SDIO_DLEN) . . . . . . . . . . . . . . . . . . . . . . 494

20.9.9 SDIO data control register (SDIO_DCTRL) . . . . . . . . . . . . . . . . . . . . . 494

20.9.10 SDIO data counter register (SDIO_DCOUNT) . . . . . . . . . . . . . . . . . . 495

20.9.11 SDIO status register (SDIO_STA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 496

20.9.12 SDIO interrupt clear register (SDIO_ICR) . . . . . . . . . . . . . . . . . . . . . . 497

20.9.13 SDIO mask register (SDIO_MASK) . . . . . . . . . . . . . . . . . . . . . . . . . . . 499

20.9.14 SDIO FIFO counter register (SDIO_FIFOCNT) . . . . . . . . . . . . . . . . . . 501

20.9.15 SDIO data FIFO register (SDIO_FIFO) . . . . . . . . . . . . . . . . . . . . . . . . 502

20.9.16 SDIO register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 502

21 Universal serial bus full-speed device interface (USB) . . . . . . . . . . . 504

21.1 USB introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504

21.2 USB main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504

21.3 USB functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504

21.3.1 Description of USB blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 506

21.4 Programming considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 507

21.4.1 Generic USB device programming . . . . . . . . . . . . . . . . . . . . . . . . . . . 507

21.4.2 System and power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 508

21.4.3 Double-buffered endpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 514

21.4.4 Isochronous transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 516

21.4.5 Suspend/Resume events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 517

21.5 USB registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 519

21.5.1 Common registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 519

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21.5.2 Endpoint-specific registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 526

21.5.3 Buffer descriptor table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 529

21.5.4 USB register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 533

22 Controller area network (bxCAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 535

22.1 bxCAN introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 535

22.2 bxCAN main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 535

22.3 bxCAN general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 536

22.3.1 CAN 2.0B active core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 537

22.3.2 Control, status and configuration registers . . . . . . . . . . . . . . . . . . . . . 537

22.3.3 Tx mailboxes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 537

22.3.4 Acceptance filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 537

22.4 bxCAN operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 539

22.4.1 Initialization mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 540

22.4.2 Normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 540

22.4.3 Sleep mode (low power) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 540

22.5 Test mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 541

22.5.1 Silent mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 541

22.5.2 Loop back mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 542

22.5.3 Loop back combined with silent mode . . . . . . . . . . . . . . . . . . . . . . . . . 542

22.6 STM32F10xxx in Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 543

22.7 bxCAN functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 543

22.7.1 Transmission handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 543

22.7.2 Time triggered communication mode . . . . . . . . . . . . . . . . . . . . . . . . . 545

22.7.3 Reception handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 545

22.7.4 Identifier filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 546

22.7.5 Message storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 550

22.7.6 Error management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 552

22.7.7 Bit timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 552

22.8 bxCAN interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 554

22.9 CAN registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 556

22.9.1 Register access protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 556

22.9.2 CAN control and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 556

22.9.3 Mailbox registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 566

22.9.4 CAN filter registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 571

22.9.5 bxCAN register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 575

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23 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 578

23.1 SPI introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 578

23.2 SPI and I

23.2.1 SPI features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 579

23.2.2 I

23.3 SPI functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 581

23.3.1 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 581

23.3.2 SPI slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 585

23.3.3 SPI master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 585

23.3.4 Simplex communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 586

23.3.5 Status flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 587

23.3.6 CRC calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 587

23.3.7 SPI communication using DMA (direct memory addressing) . . . . . . . 588

23.3.8 Error flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 589

23.3.9 Disabling the SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 590

23.3.10 SPI interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 590

2

S main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 579

2

S features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 580

23.4 I2S functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 590

23.4.1 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 590

23.4.2 Supported audio protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 592

23.4.3 Clock generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 599

23.4.4 I

23.4.5 I

2

S master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 602

2

S slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 604

23.4.6 Status flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 605

23.4.7 Error flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 606

23.4.8 I

2

S interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 606

23.4.9 DMA features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 607

23.5 SPI and I2S registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 607

23.5.1 SPI control register 1 (SPI_CR1) (not used in I2S mode) . . . . . . . . . . 607

23.5.2 SPI control register 2 (SPI_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 609

23.5.3 SPI status register (SPI_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 610

23.5.4 SPI data register (SPI_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 611

23.5.5 SPI CRC polynomial register (SPI_CRCPR) (not used in I

mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 612

23.5.6 SPI Rx CRC register (SPI_RXCRCR) (not used in I

23.5.7 SPI Tx CRC register (SPI_TXCRCR) (not used in I

23.5.8 SPI_I

23.5.9 SPI_I

2

S configuration register (SPI_I2SCFGR) . . . . . . . . . . . . . . . . . . 613

2

S prescaler register (SPI_I2SPR) . . . . . . . . . . . . . . . . . . . . . . . 615

2

2

S

2

S mode) . . . . . . 612

S mode) . . . . . . . 613

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23.5.10 SPI register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 616

24 Inter-integrated circuit (I2C) interface . . . . . . . . . . . . . . . . . . . . . . . . . 617

24.1 I2C introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 617

24.2 I

24.3 I

24.4 I2C interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 632

24.5 I

24.6 I

2

C main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 617

2

C functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 618

24.3.1 Mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 618

24.3.2 I2C slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 620

24.3.3 I2C master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 623

24.3.4 Error conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 626

24.3.5 SDA/SCL line control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 628

24.3.6 SMBus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 628

24.3.7 DMA requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 630

24.3.8 Packet error checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 632

2

C debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 633

2

C registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 634

24.6.1 Control register 1 (I2C_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 634

24.6.2 Control register 2 (I2C_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 636

24.6.3 Own address register 1 (I2C_OAR1) . . . . . . . . . . . . . . . . . . . . . . . . . . 637

24.6.4 Own address register 2 (I2C_OAR2) . . . . . . . . . . . . . . . . . . . . . . . . . . 638

24.6.5 Data register (I2C_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 638

24.6.6 Status register 1 (I2C_SR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 639

24.6.7 Status register 2 (I2C_SR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 642

24.6.8 Clock control register (I2C_CCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 643

24.6.9 TRISE register (I2C_TRISE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 644

24.6.10 I2C register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 645

25 Universal synchronous asynchronous receiver

transmitter (USART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 646

25.1 USART introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 646

25.2 USART main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 646

25.3 USART functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 647

25.3.1 USART character description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 650

25.3.2 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 651

25.3.3 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 653

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25.3.4 Fractional baud rate generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 657

25.3.5 Multiprocessor communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 659

25.3.6 Parity control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 660

25.3.7 LIN (local interconnection network) mode . . . . . . . . . . . . . . . . . . . . . . 661

25.3.8 USART synchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 663

25.3.9 Single wire half duplex communication . . . . . . . . . . . . . . . . . . . . . . . . 665

25.3.10 Smartcard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 666

25.3.11 IrDA SIR ENDEC block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 668

25.3.12 Continuous communication using DMA . . . . . . . . . . . . . . . . . . . . . . . . 669

25.3.13 Hardware flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 671

25.4 USART interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 672

25.5 USART mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 673

25.6 USART registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 673

25.6.1 Status register (USART_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 674

25.6.2 Data register (USART_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 676

25.6.3 Baud rate register (USART_BRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 676

25.6.4 Control register 1 (USART_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 677

25.6.5 Control register 2 (USART_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 679

25.6.6 Control register 3 (USART_CR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 680

25.6.7 Guard time and prescaler register (USART_GTPR) . . . . . . . . . . . . . . 682

25.6.8 USART register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 683

26 USB on-the-go full-speed (OTG_FS) . . . . . . . . . . . . . . . . . . . . . . . . . . 684

26.1 OTG_FS introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 684

26.2 OTG_FS main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 684

26.2.1 General features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 685

26.2.2 Host-mode features: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 685

26.2.3 Device-mode features: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 686

26.3 OTG_FS functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 686

26.3.1 Host architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 686

26.3.2 Device architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 687

26.3.3 Core architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 687

26.4 SOF trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 693

26.5 OTG_FS interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 693

26.6 OTG_FS control and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 695

26.6.1 CSR memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 695

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26.6.2 OTG_FS global registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 700

26.6.3 Host-mode registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 720

26.6.4 Device-mode registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 730

26.6.5 OTG_FS power and clock gating control register

(OTG_FS_PCGCCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 750

26.6.6 OTG_FS register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 751

27 OTG_FS programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 767

27.1 Core initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 767

27.2 Host initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 767

27.3 Device initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 768

27.4 Host programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 769

27.4.1 Channel initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 769

27.4.2 Halting a channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 769

27.4.3 Operational model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 770

27.5 Device programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 786

27.5.1 Endpoint initialization on USB reset . . . . . . . . . . . . . . . . . . . . . . . . . . . 786

27.5.2 Endpoint initialization on enumeration completion . . . . . . . . . . . . . . . . 786

27.5.3 Endpoint initialization on SetAddress command . . . . . . . . . . . . . . . . . 787

27.5.4 Endpoint initialization on SetConfiguration/SetInterface command . . . 787

27.5.5 Endpoint activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 787

27.5.6 Endpoint deactivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 787

27.6 Operational model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 788

27.6.1 SETUP and OUT data transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 788

27.6.2 IN data transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 798

27.7 Worst case response time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 806

27.7.1 Choosing the value of TRDT in OTG_FS_GUSBCFG . . . . . . . . . . . . . 806

27.8 OTG programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 807

27.8.1 A-device session request protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . 808

27.8.2 B-device session request protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . 808

27.8.3 A-device host negotiation protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . 810

27.8.4 B-device host negotiation protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . 811

28 Ethernet (ETH): media access control (MAC) with

DMA controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 814

28.1 Ethernet introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 814

28.2 Ethernet main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 814

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Contents RM0034

28.2.1 MAC core features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 815

28.2.2 DMA features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 816

28.2.3 PTP features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 816

28.3 Ethernet pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 817

28.4 Ethernet functional description: SMI, MII and RMII . . . . . . . . . . . . . . . . 818

28.4.1 Station management interface: SMI . . . . . . . . . . . . . . . . . . . . . . . . . . . 818

28.4.2 Media-independent interface: MII . . . . . . . . . . . . . . . . . . . . . . . . . . . . 821

28.4.3 Reduced media-independent interface: RMII . . . . . . . . . . . . . . . . . . . 824

28.4.4 MII/RMII selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 825

28.5 Ethernet functional description: MAC 802.3 . . . . . . . . . . . . . . . . . . . . . . 826

28.5.1 MAC 802.3 frame format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 826

28.5.2 MAC frame transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 830

28.5.3 MAC frame reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 837

28.5.4 MAC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 842

28.5.5 MAC filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 843

28.5.6 MAC loopback mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 845

28.5.7 MAC management counters: MMC . . . . . . . . . . . . . . . . . . . . . . . . . . . 846

28.5.8 Power management: PMT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 846

28.5.9 Precision time protocol (IEEE1588 PTP) . . . . . . . . . . . . . . . . . . . . . . . 849

28.6 Ethernet functional description: DMA controller operation . . . . . . . . . . . 856

28.6.1 Initialization of a transfer using DMA . . . . . . . . . . . . . . . . . . . . . . . . . . 857

28.6.2 Host bus burst access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 857

28.6.3 Host data buffer alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 858

28.6.4 Buffer size calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 858

28.6.5 DMA arbiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 858

28.6.6 Error response to DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 859

28.6.7 Tx DMA configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 859

28.6.8 Rx DMA configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 871

28.6.9 DMA interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 880

28.7 Ethernet interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 881

28.8 Ethernet register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 882

28.8.1 MAC register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 882

28.8.2 MMC register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 897

28.8.3 IEEE 1588 time stamp registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 902

28.8.4 DMA register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 907

28.8.5 Ethernet register maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 921

22/959

RM0034 Contents

29 Device electronic signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 924

29.1 Memory size registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 924

29.1.1 Flash size register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 924

29.2 Unique device ID register (96 bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 925

30 Debug support (DBG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 927

30.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 927

30.2 Reference ARM documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 929

30.3 SWJ debug port (serial wire and JTAG) . . . . . . . . . . . . . . . . . . . . . . . . . 929

30.3.1 Mechanism to select the JTAG-DP or the SW-DP . . . . . . . . . . . . . . . . 929

30.4 Pinout and debug port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 930

30.4.1 SWJ debug port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 930

30.4.2 Flexible SWJ-DP pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 930

30.4.3 Internal pull-up and pull-down on JTAG pins . . . . . . . . . . . . . . . . . . . . 931

30.4.4 Using serial wire and releasing the unused debug pins as GPIOs . . . 932

30.5 STM32F10xxx JTAG TAP connection . . . . . . . . . . . . . . . . . . . . . . . . . . 932

30.6 ID codes and locking mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 933

30.6.1 MCU device ID code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 933

30.6.2 Boundary scan TAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 934

30.6.3 Cortex-M3 TAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 934

30.6.4 Cortex-M3 JEDEC-106 ID code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 935

30.7 JTAG debug port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 935

30.8 SW debug port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 937

30.8.1 SW protocol introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 937

30.8.2 SW protocol sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 937

30.8.3 SW-DP state machine (Reset, idle states, ID code) . . . . . . . . . . . . . . 938

30.8.4 DP and AP read/write accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 938

30.8.5 SW-DP registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 939

30.8.6 SW-AP registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 939

30.9 AHB-AP (AHB Access Port) - valid for both JTAG-DP or SW-DP . . . . . 940

30.10 Core debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 940

30.11 Capability of the debugger host to connect under system reset . . . . . . 941

30.12 FPB (Flash patch breakpoint) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 942

30.13 DWT (data watchpoint trigger) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 942

30.14 ITM (instrumentation trace macrocell) . . . . . . . . . . . . . . . . . . . . . . . . . . 942

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Contents RM0034

30.14.1 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 942

30.14.2 Timestamp packets, synchronization and overflow packets . . . . . . . . 943

30.15 MCU debug component (MCUDBG) . . . . . . . . . . . . . . . . . . . . . . . . . . . 944

30.15.1 Debug support for low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . 944

30.15.2 Debug support for timers, watchdog, bxCAN and I

30.15.3 Debug MCU configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 945

2

C . . . . . . . . . . . . . 945

30.16 TPIU (trace port interface unit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 947

30.16.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 947

30.16.2 TRACE pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 948

30.16.3 TPUI formatter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 950

30.16.4 TPUI frame synchronization packets . . . . . . . . . . . . . . . . . . . . . . . . . . 951

30.16.5 Emission of synchronization frame packet . . . . . . . . . . . . . . . . . . . . . . 951

30.16.6 Synchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 951

30.16.7 Asynchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 952

30.16.8 TRACECLKIN connection inside STM32F10xxx . . . . . . . . . . . . . . . . . 952

30.16.9 TPIU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 952

30.16.10 Example of configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 953

30.17 DBG register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 954

31 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 955

24/959

RM0034 List of tables

List of tables

Table 1. Register boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Table 2. Flash module organization (low-density devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 3. Flash module organization (medium-density devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 4. Flash module organization (high-density devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Table 5. Flash module organization (connectivity line devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Table 6. Boot modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table 7. CRC calculation unit register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Table 8. Low-power mode summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Table 9. Sleep-now. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Table 10. Sleep-on-exit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Table 11. Stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Table 12. Standby mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Table 13. PWR - register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Table 14. BKP register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Table 15. RCC - register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

Table 16. RCC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

Table 17. Port bit configuration table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

Table 18. Output MODE bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

Table 19. CAN1 alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

Table 20. CAN2 alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

Table 21. Debug interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

Table 22. Debug port mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

Table 23. ADC1 external trigger injected conversion alternate function remapping . . . . . . . . . . . . . 150

Table 24. ADC1 external trigger regular conversion alternate function remapping . . . . . . . . . . . . . 150

Table 25. ADC2 external trigger injected conversion alternate function remapping . . . . . . . . . . . . . 150

Table 26. ADC2 external trigger regular conversion alternate function remapping . . . . . . . . . . . . . 151

Table 27. Timer 5 alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

Table 28. Timer 4 alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

Table 29. Timer 3 alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

Table 30. Timer 2 alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

Table 31. Timer 1 alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

Table 32. USART3 remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

Table 33. USART2 remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

Table 34. USART1 remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

Table 35. I2C1 remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

Table 36. SPI1 remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

Table 37. SPI3 remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

Table 38. ETH remapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

Table 39. GPIO register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160

Table 40. AFIO register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

Table 41. Vector table for connectivity line devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

Table 42. Vector table for other STM32F10xxx devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

Table 43. External interrupt/event controller register map and reset values. . . . . . . . . . . . . . . . . . . 174

Table 45. DMA interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180

Table 46. Summary of DMA1 requests for each channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182

Table 47. Summary of DMA2 requests for each channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183

Table 48. DMA register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189

Table 49. ADC pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194

25/959

List of tables RM0034

Table 50. Analog watchdog channel selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196

Table 51. External trigger for regular channels for ADC1 and ADC2 . . . . . . . . . . . . . . . . . . . . . . . . 201

Table 52. External trigger for injected channels for ADC1 and ADC2 . . . . . . . . . . . . . . . . . . . . . . . 201

Table 53. External trigger for regular channels for ADC3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202

Table 54. External trigger for injected channels for ADC3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202

Table 55. ADC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211

Table 56. ADC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224

Table 57. DAC pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227

Table 58. External triggers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230

Table 59. DAC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245

Table 60. Counting direction versus encoder signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279

Table 61. TIMx Internal trigger connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292

Table 62. Output control bits for complementary OCx and OCxN channels with break feature. . . . 303

Table 63. TIM1&TIM8 register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310

Table 64. Counting direction versus encoder signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338

Table 65. TIMx Internal trigger connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352

Table 66. Output control bit for standard OCx channels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362

Table 67. TIMx register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366

Table 68. TIM6&TIM7 register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379

Table 69. RTC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391

Table 70. Watchdog timeout period (with 40 kHz input clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393

Table 71. IWDG register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 396

Table 72. WWDG register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401

Table 73. NOR/PSRAM bank selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405

Table 74. External memory address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 406

Table 75. Memory mapping and timing registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 406

Table 76. NAND bank selections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407

Table 77. Programmable NOR/PSRAM access parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 408

Table 78. Nonmuxed I/O NOR Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 408

Table 79. Muxed I/O NOR Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 409

Table 80. PSRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 409

Table 81. NOR Flash/PSRAM supported memories and transactions . . . . . . . . . . . . . . . . . . . . . . . 410

Table 82. FSMC_BCRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412

Table 83. FSMC_TCRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 413

Table 84. FSMC_BCRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414

Table 85. FSMC_TCRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415

Table 86. FSMC_BWTRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415

Table 87. FSMC_BCRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417

Table 88. FSMC_TCRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418

Table 89. FSMC_BWTRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418

Table 90. FSMC_BCRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 420

Table 91. FSMC_TCRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 420

Table 92. FSMC_BWTRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 420

Table 93. FSMC_BCRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 422

Table 94. FSMC_TCRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 422

Table 95. FSMC_BWTRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 422

Table 96. FSMC_BCRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 424

Table 97. FSMC_TCRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 424

Table 98. FSMC_BCRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 426

Table 99. FSMC_TCRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 427

Table 100. FSMC_BCRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 429

Table 101. FSMC_TCRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 429

26/959

RM0034 List of tables

Table 102. Programmable NAND/PC Card access parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 436

Table 103. 8-bit NAND Flash. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 436

Table 104. 16-bit NAND Flash. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437

Table 105. 16-bit PC Card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437

Table 106. Supported memories and transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 438

Table 107. ECC result relevant bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 447

Table 108. FSMC register map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 447

Table 109. SDIO I/O definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453

Table 110. Command format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457

Table 111. Short response format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458

Table 112. Long response format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458

Table 113. Command path status flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458

Table 114. Data token format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 461

Table 115. Transmit FIFO status flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 462

Table 116. Receive FIFO status flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 463

Table 117. Card status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 473

Table 118. SD status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 475

Table 119. Speed class code field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 477

Table 120. Performance move field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 477

Table 121. AU_SIZE field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 477

Table 122. Maximum AU size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 478

Table 123. Erase size field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 478

Table 124. Erase timeout field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 478

Table 125. Erase offset field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 479

Table 126. Block-oriented write commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 481

Table 127. Block-oriented write protection commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 482

Table 128. Erase commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 482

Table 129. I/O mode commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 482

Table 130. Lock card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 483

Table 131. Application-specific commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 483

Table 132. R1 response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 484

Table 133. R2 response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 484

Table 134. R3 response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485

Table 135. R4 response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485

Table 136. R4b response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485

Table 137. R5 response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 486

Table 138. R6 response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 486

Table 139. Response type and SDIO_RESPx registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 493

Table 140. SDIO register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 502

Table 141. Double-buffering buffer flag definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 515

Table 142. Bulk double-buffering memory buffers usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 515

Table 143. Isochronous memory buffers usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 517

Table 144. Resume event detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 518

Table 145. Reception status encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 529

Table 146. Endpoint type encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 529

Table 147. Endpoint kind meaning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 529

Table 148. Transmission status encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 529

Table 149. Definition of allocated buffer memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 532

Table 150. USB register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 533

Table 151. Transmit mailbox mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 551

Table 152. Receive mailbox mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 551

Table 153. bxCAN register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 575

27/959

List of tables RM0034

Table 154. SPI interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 590

Table 155. Audio-frequency precision using standard 8 MHz HSE (high-density

devices only). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 600

Table 156. Audio-frequency precision using standard 25 MHz and PLL3 (connectivity line

devices only). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 601

Table 157. Audio-frequency precision using standard 14.7456 MHz and PLL3 (connectivity line

devices only). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 602

Table 158. I

2

S interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 606

Table 159. SPI register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 616

Table 160. SMBus vs. I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 628

Table 161. I2C Interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 632

Table 162. I2C register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 645

Table 163. Noise detection from sampled data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 656

Table 164. Error calculation for programmed baud rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 658

Table 165. Frame formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 660

Table 166. USART interrupt requests. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 672

Table 167. USART mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 673

Table 168. USART register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 683

Table 169. Core global control and status registers (CSRs). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 696

Table 170. Host-mode control and status registers (CSRs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 697

Table 171. Device-mode control and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 698

Table 172. Data FIFO (DFIFO) access register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 700

Table 173. Power and clock gating control and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 700

Table 174. Minimum duration for soft disconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 732

Table 175. OTG_FS register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 751

Table 176. Ethernet pin configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 817

Table 177. Management frame format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 819

Table 178. Clock range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 821

Table 179. TX interface signal encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 823

Table 180. RX interface signal encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 823

Table 181. Frame statuses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 839

Table 182. Destination address filtering table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 844

Table 183. Source address filtering table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 845

Table 184. Receive descriptor 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 877

Table 185. Ethernet register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 921

Table 186. SWJ debug port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 930

Table 187. Flexible SWJ-DP pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 931

Table 188. JTAG debug port data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 935

Table 189. 32-bit debug port registers addressed through the shifted value A[3:2] . . . . . . . . . . . . . . 936

Table 190. Packet request (8-bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 937

Table 191. ACK response (3 bits). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 938

Table 192. DATA transfer (33 bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 938

Table 193. SW-DP registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 939

Table 194. Cortex-M3 AHB-AP registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 940

Table 195. Core debug registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 941

Table 196. Main ITM registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 943

Table 197. Asynchronous TRACE pin assignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 948

Table 198. Synchronous TRACE pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 948

Table 199. Flexible TRACE pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 949

Table 200. Important TPIU registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 952

Table 201. DBG register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 954

Table 202. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 955

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List of figures

Figure 1. System architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 2. System architecture in connectivity line devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Figure 3. CRC calculation unit block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Figure 4. Power supply overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Figure 5. Power on reset/power down reset waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Figure 6. PVD thresholds. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Figure 7. Reset circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Figure 8. Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Figure 9. HSE/ LSE clock sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Figure 10. Reset circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

Figure 11. Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

Figure 12. HSE/ LSE clock sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Figure 13. Basic structure of a standard I/O port bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

Figure 14. Basic structure of a five-volt tolerant I/O port bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

Figure 15. Input floating/pull up/pull down configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

Figure 16. Output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

Figure 17. Alternate function configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

Figure 18. High impedance-analog input configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

Figure 19. External interrupt/event controller block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

Figure 20. External interrupt/event GPIO mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

Figure 21. DMA block diagram in connectivity line devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

Figure 22. DMA1 request mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181

Figure 23. DMA2 request mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183

Figure 24. Single ADC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193

Figure 25. Timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196

Figure 26. Analog watchdog guarded area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196

Figure 27. Injected conversion latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198

Figure 28. Calibration timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199

Figure 29. Right alignment of data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200

Figure 30. Left alignment of data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200

Figure 31. Dual ADC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204

Figure 32. Injected simultaneous mode on 4 channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205

Figure 33. Regular simultaneous mode on 16 channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206

Figure 34. Fast interleaved mode on 1 channel in continuous conversion mode . . . . . . . . . . . . . . . 206

Figure 35. Slow interleaved mode on 1 channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207

Figure 36. Alternate trigger: injected channel group of each ADC. . . . . . . . . . . . . . . . . . . . . . . . . . . 207

Figure 37. Alternate trigger: 4 injected channels (each ADC) in discontinuous model . . . . . . . . . . . 208

Figure 38. Alternate + Regular simultaneous. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209

Figure 39. Case of trigger occurring during injected conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209

Figure 40. Interleaved single channel with injected sequence CH11, CH12 . . . . . . . . . . . . . . . . . . . 209

Figure 41. Temperature sensor and VREFINT channel block diagram . . . . . . . . . . . . . . . . . . . . . . 210

Figure 42. DAC channel block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227

Figure 43. Data registers in single DAC channel mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229

Figure 44. Data registers in dual DAC channel mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229

Figure 45. Timing diagram for conversion with trigger disabled TEN = 0 . . . . . . . . . . . . . . . . . . . . . 230

Figure 46. DAC LFSR register calculation algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231

Figure 47. DAC conversion (SW trigger enabled) with LFSR wave generation. . . . . . . . . . . . . . . . . 232

Figure 48. DAC triangle wave generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232

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Figure 49. DAC conversion (SW trigger enabled) with triangle wave generation . . . . . . . . . . . . . . . 233

Figure 50. Advanced-control timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248

Figure 51. Counter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . . 250

Figure 52. Counter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . . 250

Figure 53. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251

Figure 54. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251

Figure 55. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252

Figure 56. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252

Figure 57. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded) . . . . . 252

Figure 58. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded) . . . . . . . . 253

Figure 59. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254

Figure 60. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254

Figure 61. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254

Figure 62. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255

Figure 63. Counter timing diagram, update event when repetition counter is not used. . . . . . . . . . . 255

Figure 64. Counter timing diagram, internal clock divided by 1, TIMx_ARR = 0x6 . . . . . . . . . . . . . . 256

Figure 65. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256

Figure 66. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . . . . . . . . . . . 257

Figure 67. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257

Figure 68. Counter timing diagram, update event with ARPE=1 (counter underflow) . . . . . . . . . . . . 257

Figure 69. Counter timing diagram, Update event with ARPE=1 (counter overflow). . . . . . . . . . . . . 258

Figure 70. Update rate examples depending on mode and TIMx_RCR register settings . . . . . . . . . 259

Figure 71. Control circuit in normal mode, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . 260

Figure 72. TI2 external clock connection example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260

Figure 73. Control circuit in external clock mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261

Figure 74. External trigger input block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261

Figure 75. Control circuit in external clock mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262

Figure 76. Capture/compare channel (example: channel 1 input stage) . . . . . . . . . . . . . . . . . . . . . . 263

Figure 77. Capture/compare channel 1 main circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263

Figure 78. Output stage of capture/compare channel (channel 1 to 3) . . . . . . . . . . . . . . . . . . . . . . . 264

Figure 79. Output stage of capture/compare channel (channel 4). . . . . . . . . . . . . . . . . . . . . . . . . . . 264

Figure 80. PWM input mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266

Figure 81. Output compare mode, toggle on OC1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268

Figure 82. Edge-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269

Figure 83. Center-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270

Figure 84. Complementary output with dead-time insertion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271

Figure 85. Dead-time waveforms with delay greater than the negative pulse. . . . . . . . . . . . . . . . . . 271

Figure 86. Dead-time waveforms with delay greater than the positive pulse. . . . . . . . . . . . . . . . . . . 272

Figure 87. Output behavior in response to a break.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274

Figure 88. Clearing TIMx OCxREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275

Figure 89. 6-step generation, COM example (OSSR=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276

Figure 90. Example of one pulse mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277

Figure 91. Example of counter operation in encoder interface mode. . . . . . . . . . . . . . . . . . . . . . . . . 280

Figure 92. Example of encoder interface mode with TI1FP1 polarity inverted. . . . . . . . . . . . . . . . . . 280

Figure 93. Example of hall sensor interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282

Figure 94. Control circuit in reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283

Figure 95. Control circuit in gated mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284

Figure 96. Control circuit in trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285

Figure 97. Control circuit in external clock mode 2 + trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . 286

Figure 98. General-purpose timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314

Figure 99. Counter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . . 315

Figure 100. Counter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . . 316

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Figure 101. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317

Figure 102. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317

Figure 103. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317

Figure 104. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318

Figure 105. Counter timing diagram, Update event when ARPE=0 (TIMx_ARR not preloaded). . . . . 318

Figure 106. Counter timing diagram, Update event when ARPE=1 (TIMx_ARR preloaded). . . . . . . . 319

Figure 107. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320

Figure 108. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320

Figure 109. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320

Figure 110. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321

Figure 111. Counter timing diagram, Update event when repetition counter is not used . . . . . . . . . . 321

Figure 112. Counter timing diagram, internal clock divided by 1, TIMx_ARR=0x6 . . . . . . . . . . . . . . . 322

Figure 113. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322

Figure 114. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . . . . . . . . . . . 323

Figure 115. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323

Figure 116. Counter timing diagram, Update event with ARPE=1 (counter underflow). . . . . . . . . . . . 323

Figure 117. Counter timing diagram, Update event with ARPE=1 (counter overflow) . . . . . . . . . . . . . 324

Figure 118. Control circuit in normal mode, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . 325

Figure 119. TI2 external clock connection example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325

Figure 120. Control circuit in external clock mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326

Figure 121. External trigger input block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326

Figure 122. Control circuit in external clock mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327

Figure 123. Capture/compare channel (example: channel 1 input stage) . . . . . . . . . . . . . . . . . . . . . . 327

Figure 124. Capture/compare channel 1 main circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328

Figure 125. Output stage of capture/compare channel (channel 1). . . . . . . . . . . . . . . . . . . . . . . . . . . 328

Figure 126. PWM input mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330

Figure 127. Output compare mode, toggle on OC1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332

Figure 128. Edge-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333

Figure 129. Center-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334

Figure 130. Example of one pulse mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335

Figure 131. Clearing TIMx OCxREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337

Figure 132. Example of counter operation in encoder interface mode. . . . . . . . . . . . . . . . . . . . . . . . . 338

Figure 133. Example of encoder interface mode with IC1FP1 polarity inverted. . . . . . . . . . . . . . . . . . 339

Figure 134. Control circuit in reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340

Figure 135. Control circuit in gated mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341

Figure 136. Control circuit in trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341

Figure 137. Control circuit in external clock mode 2 + trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . 342

Figure 138. Master/Slave timer example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343

Figure 139. Gating timer 2 with OC1REF of timer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344

Figure 140. Gating timer 2 with Enable of timer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345

Figure 141. Triggering timer 2 with Update of timer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345

Figure 142. Triggering timer 2 with Enable of timer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346

Figure 143. Triggering timer 1 and 2 with timer 1 TI1 input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347

Figure 144. Basic timer block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369

Figure 145. Counter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . . 370

Figure 146. Counter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . . 370

Figure 147. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371

Figure 148. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372

Figure 149. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372

Figure 150. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372

Figure 151. Counter timing diagram, update event when ARPE = 0 (TIMx_ARR not

preloaded). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373

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Figure 152. Counter timing diagram, update event when ARPE=1 (TIMx_ARR

preloaded). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373

Figure 153. Control circuit in normal mode, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . 374

Figure 154. RTC simplified block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382

Figure 155. RTC second and alarm waveform example with PR=0003, ALARM=00004 . . . . . . . . . . 384

Figure 156. RTC Overflow waveform example with PR=0003. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384

Figure 157. Independent watchdog block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393

Figure 158. Watchdog block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398

Figure 159. Window watchdog timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399

Figure 160. FSMC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 403

Figure 161. FSMC memory banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405

Figure 162. Mode1 read accesses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411

Figure 163. Mode1 write accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412

Figure 164. ModeA read accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 413

Figure 165. ModeA write accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414

Figure 166. Mode2/B read accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416

Figure 167. Mode2 write accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416

Figure 168. ModeB write accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417

Figure 169. ModeC read accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 419

Figure 170. ModeC write accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 419

Figure 171. ModeD read accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421

Figure 172. ModeD write accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421

Figure 173. Muxed read accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423

Figure 174. Muxed write accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423

Figure 175. Synchronous multiplexed read mode - NOR, PSRAM (CRAM) . . . . . . . . . . . . . . . . . . . . 426

Figure 176. Synchronous multiplexed write mode - PSRAM (CRAM) . . . . . . . . . . . . . . . . . . . . . . . . . 428

Figure 177. NAND/PC Card controller timing for common memory access . . . . . . . . . . . . . . . . . . . . 439

Figure 178. Access to non ‘CE don’t care’ NAND-Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 440

Figure 179. SDIO “no response” and “no data” operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450

Figure 180. SDIO (multiple) block read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450

Figure 181. SDIO (multiple) block write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 451

Figure 182. SDIO sequential read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 451

Figure 183. SDIO sequential write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 451

Figure 184. SDIO block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 452

Figure 185. SDIO adapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453

Figure 186. Control unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 454

Figure 187. SDIO adapter command path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455

Figure 188. Command path state machine (CPSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456

Figure 189. SDIO command transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457

Figure 190. Data path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 459

Figure 191. Data path state machine (DPSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 460

Figure 192. USB peripheral block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 505

Figure 193. Packet buffer areas with examples of buffer description table locations . . . . . . . . . . . . . 510

Figure 194. CAN network topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 536

Figure 195. CAN general block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 538

Figure 196. Dual CAN block diagram (connectivity devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 539

Figure 197. bxCAN operating modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 541

Figure 198. bxCAN in silent mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 542

Figure 199. bxCAN in loop back mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 542

Figure 200. bxCAN in combined mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 543

Figure 201. Transmit mailbox states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 544

Figure 202. Receive FIFO states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 545

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RM0034 List of figures

Figure 203. Filter bank scale configuration - register organization . . . . . . . . . . . . . . . . . . . . . . . . . . . 548

Figure 204. Example of filter numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 549

Figure 205. Filtering mechanism - example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 550

Figure 206. CAN error state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 551

Figure 207. Bit timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 553

Figure 208. CAN frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 554

Figure 209. Event flags and interrupt generation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 555

Figure 210. SPI block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 581

Figure 211. Single master/ single slave application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 582

Figure 212. Hardware/software slave select management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 582

Figure 213. Data clock timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 584

Figure 214. I
Figure 215. I
Figure 216. I

2

S block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 591

2

S Phillips protocol waveforms (16/32-bit full accuracy, CPOL = 0) . . . . . . . . . . . . . . . . 593

2

S Phillips standard waveforms (24-bit frame with CPOL = 0) . . . . . . . . . . . . . . . . . . . . 593

Figure 217. Transmitting 0x8EAA33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 593

Figure 218. Receiving 0x8EAA33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 594

Figure 219. I

2

S Phillips standard (16-bit extended to 32-bit packet frame with CPOL = 0) . . . . . . . . . 594

Figure 220. Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 594

Figure 221. MSB Justified 16-bit or 32-bit full-accuracy length with CPOL = 0 . . . . . . . . . . . . . . . . . . 595

Figure 222. MSB Justified 24-bit frame length with CPOL = 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 595

Figure 223. MSB Justified 16-bit extended to 32-bit packet frame with CPOL = 0 . . . . . . . . . . . . . . . 595

Figure 224. LSB justified 16-bit or 32-bit full-accuracy with CPOL = 0 . . . . . . . . . . . . . . . . . . . . . . . . 596

Figure 225. LSB Justified 24-bit frame length with CPOL = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 596

Figure 226. Operations required to transmit 0x3478AE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 596

Figure 227. Operations required to receive 0x3478AE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 597

Figure 228. LSB Justified 16-bit extended to 32-bit packet frame with CPOL = 0 . . . . . . . . . . . . . . . . 597

Figure 229. Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 597

Figure 230. PCM standard waveforms (16-bit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 598

Figure 231. PCM standard waveforms (16-bit extended to 32-bit packet frame). . . . . . . . . . . . . . . . . 598

Figure 232. Audio sampling frequency definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 599

Figure 233. I

2

S clock generator architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 599

Figure 234. I2C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 619

Figure 235. I2C block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 620

Figure 236. Transfer sequence diagram for slave transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 621

Figure 237. Transfer sequence diagram for slave receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 622

Figure 238. Transfer sequence diagram for master transmitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 625

Figure 239. Transfer sequence diagram for master receiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 626

Figure 240. I2C interrupt mapping diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 633

Figure 241. USART block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 649

Figure 242. Word length programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 650

Figure 243. Configurable stop bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 652

Figure 244. Start bit detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 654

Figure 245. Data sampling for noise detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 656

Figure 246. Mute mode using Idle line detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 659

Figure 247. Mute mode using Address mark detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 660

Figure 248. Break detection in LIN mode (11-bit break length - LBDL bit is set) . . . . . . . . . . . . . . . . . 662

Figure 249. Break detection in LIN mode vs. Framing error detection. . . . . . . . . . . . . . . . . . . . . . . . . 663

Figure 250. USART example of synchronous transmission. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 664

Figure 251. USART data clock timing diagram (M=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 664

Figure 252. USART data clock timing diagram (M=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 665

Figure 253. RX data setup/hold time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 665

Figure 254. ISO 7816-3 asynchronous protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 666

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List of figures RM0034

Figure 255. Parity error detection using the 1.5 stop bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 667

Figure 256. IrDA SIR ENDEC- block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 669

Figure 257. IrDA data modulation (3/16) -Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 669

Figure 258. Hardware flow control between 2 USART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 671

Figure 259. RTS flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 671

Figure 260. CTS flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 672

Figure 261. USART interrupt mapping diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 673

Figure 262. USB OTG interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 686

Figure 263. OTG_FS controller block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 687

Figure 264. BIUS address map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 688

Figure 265. Host-mode FIFO address mapping and AHB FIFO access mapping . . . . . . . . . . . . . . . . 689

Figure 266. Device-mode FIFO address mapping and AHB FIFO access mapping . . . . . . . . . . . . . . 690

Figure 267. MAC components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 691

Figure 268. SOF trigger output to TIM2 ITR1 connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 693

Figure 269. Interrupt hierarchy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 694

Figure 270. CSR memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 696

Figure 271. Transmit FIFO write task . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 770

Figure 272. Receive FIFO read task . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 771

Figure 273. Normal bulk/control OUT/SETUP and bulk/control IN transactions . . . . . . . . . . . . . . . . . 773

Figure 274. Bulk/control IN transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 776

Figure 275. Normal interrupt OUT/IN transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 778

Figure 276. Normal isochronous OUT/IN transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 783

Figure 277. Receive FIFO packet read in slave mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 789

Figure 278. Processing a SETUP packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 791

Figure 279. Slave mode bulk OUT transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 798

Figure 280. TRDT max timing case . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 807

Figure 281. A-Device SRP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 808

Figure 282. B-device SRP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 809

Figure 283. A-device HNP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 810

Figure 284. B-device HNP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 812

Figure 285. ETH block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 818

Figure 286. SMI interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 819

Figure 287. MDIO timing and frame structure - Write cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 820

Figure 288. MDIO timing and frame structure - Read cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 821

Figure 289. Media independent interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 822

Figure 290. MII clock sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 823

Figure 291. Reduced media-independent interface signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 824

Figure 292. RMII clock sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 825

Figure 293. Clock scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 825

Figure 294. Address field format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 827

Figure 295. MAC frame format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 829

Figure 296. Tagged MAC frame format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 829

Figure 297. Transmission bit order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 836

Figure 298. Transmission with no collision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 836

Figure 299. Transmission with collision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 837

Figure 300. Frame transmission in MMI and RMII modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 837

Figure 301. Receive bit order. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 841

Figure 302. Reception with no error. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 842

Figure 303. Reception with errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 842

Figure 304. Reception with false carrier indication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 842

Figure 305. MAC core interrupt masking scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 843

Figure 306. Wakeup frame filter register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 847

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RM0034 List of figures

Figure 307. Networked time synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 850

Figure 308. System time update using the Fine correction method. . . . . . . . . . . . . . . . . . . . . . . . . . . 852

Figure 309. PTP trigger output to TIM2 ITR1 connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 854

Figure 310. PPS output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 855

Figure 311. Descriptor ring and chain structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 856

Figure 312. TxDMA operation in Default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 860

Figure 313. TxDMA operation in OSF mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 862

Figure 314. Transmit descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 863

Figure 315. Transmit descriptor field format with IEEE1588 time stamp enabled . . . . . . . . . . . . . . . . 868

Figure 316. Receive DMA operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 873

Figure 317. Rx DMA descriptor structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 875

Figure 318. Receive descriptor fields format with IEEE1588 time stamp enabled. . . . . . . . . . . . . . . . 879

Figure 319. Interrupt scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 881

Figure 320. Ethernet MAC remote wakeup frame filter register (ETH_MACRWUFFR). . . . . . . . . . . . 891

Figure 321. Block diagram of STM32F10xxx-level and Cortex-M3-level debug support. . . . . . . . . . . 928

Figure 322. SWJ debug port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 929

Figure 323. JTAG TAP connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 933

Figure 324. TPIU block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 948

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Documentation conventions RM0034

1 Documentation conventions

1.1 List of abbreviations for registers

The following abbreviations are used in register descriptions:

read/write (rw) Software can read and write to these bits.

read-only (r) Software can only read these bits.

write-only (w) Software can only write to this bit. Reading the bit returns the reset

value.

read/clear (rc_w1) Software can read as well as clear this bit by writing 1. Writing ‘0’ has

no effect on the bit value.

read/clear (rc_w0) Software can read as well as clear this bit by writing 0. Writing ‘1’ has

no effect on the bit value.

read/clear by read
(rc_r)

read/set (rs) Software can read as well as set this bit. Writing ‘0’ has no effect on the

read-only write
trigger (rt_w)

toggle (t) Software can only toggle this bit by writing ‘1’. Writing ‘0’ has no effect.

Reserved (Res.) Reserved bit, must be kept at reset value.

Software can read this bit. Reading this bit automatically clears it to ‘0’.
Writing ‘0’ has no effect on the bit value.

bit value.

Software can read this bit. Writing ‘0’ or ‘1’ triggers an event but has no
effect on the bit value.

1.2 Glossary

● Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx

microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.

● Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx

microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.

● High-density devices are STM32F101xx and STM32F103xx microcontrollers where

the Flash memory density ranges between 256 and 512 Kbytes.

● Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.

1.3 Peripheral availability

For peripheral availability and number across all STM32F10xxx sales types, please refer to
the low-, medium- and high-density STM32F101xx and STM32F103xx datasheets, to the
low- and medium-density STM32F102xx datasheets and to the connectivity line devices,
STM32F105xx/STM32F107xx.

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RM0034 Memory and bus architecture

FLITF

Ch.1

Ch.2

Ch.7

Cortex-M3

DMA1

ICode

DCode

System

AHB system bus

DMA Request

APB1

Flash

Bridge 2
Bridge 1

Ch.1

Ch.2

Ch.5

DMA2

SRAM

FSMC

SDIO

APB2

DMA request

ADC3

GPIOC

USART1

TIM8

SPI1
TIM1

ADC2

ADC1

GPIOG

GPIOF

GPIOE

GPIOD

GPIOB

GPIOA

EXTI

AFIO

DAC SPI3/I2S

TIM2

PWR
BKP
bxCAN
USB
I2C2
I2C1
UART5
UART4
USART3
USART2

SPI2/I2S

IWDG

WWDG

RTC
TIM7
TIM6
TIM5
TIM4
TIM3

ai14800c

Bus matrix

DMA

DMA

Reset & clock
control (RCC)

2 Memory and bus architecture

2.1 System architecture

In low-, medium- and high-density devices, the main system consists of:

● Four masters:

– Cortex™-M3 core DCode bus (D-bus) and System bus (S-bus)
– GP-DMA1 & 2 (general-purpose DMA)

● Four slaves:

– Internal SRAM
– Internal Flash memory
–FSMC
– AHB to APB bridges (AHB2APBx), which connect all the APB peripherals

These are interconnected using a multilayer AHB bus architecture as shown in Figure 1:

Figure 1. System architecture

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Memory and bus architecture RM0034

FLITF

Ch.1

Ch.2

Ch.7

Cortex-M3

DMA1

ICode

DCode

System

DMA request

APB1

Flash

Bridge 2
Bridge 1

Ch.1

Ch.2

Ch.5

DMA2

SRAM

APB2

GPIOC

USART1

SPI1
TIM1

ADC2

ADC1

GPIOE

GPIOD

GPIOB

GPIOA

EXTI

AFIO

DAC

SPI3/I2S

TIM2

PWR
BKP
CAN1
CAN2

I2C2
I2C1
UART5
UART4
USART3
USART2

SPI2/I2S

IWDG

WWDG

RTC
TIM7
TIM6
TIM5
TIM4
TIM3

ai15810

Bus matrix

DMA

DMA

Reset & clock
control (RCC)

USB OTG FS

AHB system bus

Ethernet MAC

DMA

DMA request

In connectivity line devices the main system consists of:

● Five masters:

– Cortex™-M3 core DCode bus (D-bus) and System bus (S-bus)
– GP-DMA1 & 2 (general-purpose DMA)
– Ethernet DMA

● Three slaves:

– Internal SRAM
– Internal Flash memory
– AHB to APB bridges (AHB2APBx), which connect all the APB peripherals

These are interconnected using a multilayer AHB bus architecture as shown in Figure 2:

Figure 2. System architecture in connectivity line devices

ICode bus

This bus connects the Instruction bus of the Cortex™-M3 core to the Flash memory
instruction interface. Prefetching is performed on this bus.

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RM0034 Memory and bus architecture

DCode bus

This bus connects the DCode bus (literal load and debug access) of the Cortex™-M3 core
to the Flash memory Data interface.

System bus

This bus connects the system bus of the Cortex™-M3 core (peripherals bus) to a BusMatrix
which manages the arbitration between the core and the DMA.

DMA bus

This bus connects the AHB master interface of the DMA to the BusMatrix which manages
the access of CPU DCode and DMA to SRAM, Flash memory and peripherals.

BusMatrix

The BusMatrix manages the access arbitration between the core system bus and the DMA
master bus. The arbitration uses a Round Robin algorithm. In connectivity line devices, the
BusMatrix is composed of five masters (CPU DCode, System bus, Ethernet DMA, DMA1
and DMA2 bus) and three slaves (FLITF, SRAM and AHB2APB bridges). In other devices,
the BusMatrix is composed of four masters (CPU DCode, System bus, DMA1 bus and
DMA2 bus) and four slaves (FLITF, SRAM, FSMC and AHB2APB bridges).

AHB peripherals are connected on system bus through a BusMatrix to allow DMA access.

AHB/APB bridges (APB)

The two AHB/APB bridges provide full synchronous connections between the AHB and the
2 APB buses. APB1 is limited to 36 MHz, APB2 operates at full speed (up to 72 MHz
depending on the device).

Refer to Table 1 on page 40 for the address mapping of the peripherals connected to each
bridge.

After each device reset, all peripheral clocks are disabled (except for the SRAM and FLITF).
Before using a peripheral you have to enable its clock in the RCC_AHBENR,
RCC_APB2ENR or RCC_APB1ENR register.

Note: When a 16- or 8-bit access is performed on an APB register, the access is transformed into

a 32-bit access: the bridge duplicates the 16- or 8-bit data to feed the 32-bit vector.

2.2 Memory organization

Program memory, data memory, registers and I/O ports are organized within the same linear
4-Gbyte address space.

The bytes are coded in memory in Little Endian format. The lowest numbered byte in a word
is considered the word’s least significant byte and the highest numbered byte the most
significant.

For the detailed mapping of peripheral registers, please refer to the related chapters.

The addressable memory space is divided into 8 main blocks, each of 512 MB.

All the memory areas that are not allocated to on-chip memories and peripherals are
considered “Reserved”). Refer to the Memory map figure in the corresponding product
datasheet.

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Memory and bus architecture RM0034

2.3 Memory map

See the datasheet corresponding to your device for a comprehensive diagram of the
memory map. Tab le 1 gives the boundary addresses of the peripherals available in all
STM32F10xxx devices.

Table 1. Register boundary addresses

Boundary address Peripheral Bus Register map

0x5000 0000 - 0x5000 03FF USB OTG FS

0x4003 0000 - 0x4FFF FFFF Reserved

0x4002 8000 - 0x4002 9FFF Ethernet Section 28.8.5 on page 921

0x4002 3400 - 0x4002 7FFF Reserved

0x4002 3000 - 0x4002 33FF CRC Section 3.4.4 on page 50

0x4002 2000 - 0x4002 23FF Flash memory interface

0x4002 1400 - 0x4002 1FFF Reserved

0x4002 1000 - 0x4002 13FF Reset and clock control RCC Section 6.3.11 on page 100

0x4002 0800 - 0x4002 0FFF Reserved

0x4002 0400 - 0x4002 07FF DMA2 Section 10.4.7 on page 189

0x4002 0000 - 0x4002 03FF DMA1 Section 10.4.7 on page 189

0x4001 8400 - 0x4001 7FFF Reserved

0x4001 8000 - 0x4001 83FF SDIO Section 20.9.16 on page 502

0x4001 4000 - 0x4001 7FFF Reserved

0x4001 3C00 - 0x4001 3FFF ADC3 Section 11.12.15 on page 224

0x4001 3800 - 0x4001 3BFF USART1 Section 25.6.8 on page 683

0x4001 3400 - 0x4001 37FF TIM8 timer Section 13.4.21 on page 310

0x4001 3000 - 0x4001 33FF SPI1 Section 23.5 on page 607

0x4001 2C00 - 0x4001 2FFF TIM1 timer Section 13.4.21 on page 310

0x4001 2800 - 0x4001 2BFF ADC2 Section 11.12.15 on page 224

AHB

AHB

Section 26.6.6 on page 751

0x4001 2400 - 0x4001 27FF ADC1 Section 11.12.15 on page 224

0x4001 2000 - 0x4001 23FF GPIO Port G Section 8.5 on page 160

0x4001 1C00 - 0x4001 1FFF GPIO Port F Section 8.5 on page 160

0x4001 1800 - 0x4001 1BFF GPIO Port E Section 8.5 on page 160

0x4001 1400 - 0x4001 17FF GPIO Port D Section 8.5 on page 160

0x4001 1000 - 0x4001 13FF GPIO Port C Section 8.5 on page 160

0x4001 0C00 - 0x4001 0FFF GPIO Port B Section 8.5 on page 160

0x4001 0800 - 0x4001 0BFF GPIO Port A Section 8.5 on page 160

0x4001 0400 - 0x4001 07FF EXTI Section 9.3.7 on page 174

0x4001 0000 - 0x4001 03FF AFIO Section 8.5 on page 160

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APB2

RM0034 Memory and bus architecture

Table 1. Register boundary addresses (continued)

Boundary address Peripheral Bus Register map

0x4000 7800 - 0x4000 FFFF Reserved

0x4000 7400 - 0x4000 77FF DAC Section 12.5.14 on page 245

0x4000 7000 - 0x4000 73FF Power control PWR Section 4.4.3 on page 63

0x4000 6C00 - 0x4000 6FFF Backup registers (BKP) Section 5.4.5 on page 69

0x4000 6800 - 0x4000 6BFF Reserved

0x4000 6400 - 0x4000 67FF bxCAN1 Section 22.9.5 on page 575

0x4000 6800 - 0x4000 6BFF bxCAN2 Section 22.9.5 on page 575

(1)

0x4000 6000

0x4000 5C00 - 0x4000 5FFF USB device FS registers Section 21.5.4 on page 533

0x4000 5800 - 0x4000 5BFF I2C2 Section 24.6.10 on page 645

0x4000 5400 - 0x4000 57FF I2C1 Section 24.6.10 on page 645

0x4000 5000 - 0x4000 53FF UART5 Section 25.6.8 on page 683

0x4000 4C00 - 0x4000 4FFF UART4 Section 25.6.8 on page 683

0x4000 4800 - 0x4000 4BFF USART3 Section 25.6.8 on page 683

0x4000 4400 - 0x4000 47FF USART2 Section 25.6.8 on page 683

- 0x4000 63FF Shared USB/CAN SRAM 512 bytes

APB1

0x4000 4000 - 0x4000 3FFF Reserved

0x4000 3C00 - 0x4000 3FFF SPI3/I2S Section 23.5 on page 607

0x4000 3800 - 0x4000 3BFF SPI2/I2S Section 23.5 on page 607

0x4000 3400 - 0x4000 37FF Reserved

0x4000 3000 - 0x4000 33FF Independent watchdog (IWDG) Section 17.4.5 on page 396

0x4000 2C00 - 0x4000 2FFF Window watchdog (WWDG) Section 18.6.4 on page 401

0x4000 2800 - 0x4000 2BFF RTC Section 16.4.7 on page 391

0x4000 1800 - 0x4000 27FF Reserved

0x4000 1400 - 0x4000 17FF TIM7 timer Section 15.4.9 on page 379

0x4000 1000 - 0x4000 13FF TIM6 timer Section 15.4.9 on page 379

0x4000 0C00 - 0x4000 0FFF TIM5 timer Section 14.4.19 on page 366

0x4000 0800 - 0x4000 0BFF TIM4 timer Section 14.4.19 on page 366

0x4000 0400 - 0x4000 07FF TIM3 timer Section 14.4.19 on page 366

0x4000 0000 - 0x4000 03FF TIM2 timer Section 14.4.19 on page 366

1. This shared SRAM can be fully accessed only in low-, medium- and high-density devices, not in connectivity line devices.

2.3.1 Embedded SRAM

The STM32F10xxx features 64 Kbytes of static SRAM. It can be accessed as bytes, half­words (16 bits) or full words (32 bits). The SRAM start address is 0x2000 0000.

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Memory and bus architecture RM0034

2.3.2 Bit banding

The Cortex™-M3 memory map includes two bit-band regions. These regions map each
word in an alias region of memory to a bit in a bit-band region of memory. Writing to a word
in the alias region has the same effect as a read-modify-write operation on the targeted bit in
the bit-band region.

In the STM32F10xxx both peripheral registers and SRAM are mapped in a bit-band region.
This allows single bit-band write and read operations to be performed.

A mapping formula shows how to reference each word in the alias region to a corresponding
bit in the bit-band region. The mapping formula is:

bit_word_addr = bit_band_base + (byte_offset x 32) + (bit_number × 4)

where:

bit_word_addr is the address of the word in the alias memory region that maps to the
targeted bit.

bit_band_base is the starting address of the alias region
byte_offset is the number of the byte in the bit-band region that contains the targeted bit
bit_number is the bit position (0-7) of the targeted bit.

Example:

The following example shows how to map bit 2 of the byte located at SRAM address
0x20000300 in the alias region:

0x22006008 = 0x22000000 + (0x300*32) + (2*4).

Writing to address 0x22006008 has the same effect as a read-modify-write operation on bit
2 of the byte at SRAM address 0x20000300.

Reading address 0x22006008 returns the value (0x01 or 0x00) of bit 2 of the byte at SRAM
address 0x20000300 (0x01: bit set; 0x00: bit reset).

For more information on Bit-Banding, please refer to the Cortex™-M3 Technical Reference
Manual.

2.3.3 Embedded Flash memory

The high-performance Flash memory module has the following key features:

● Density of up to 512 Kbytes

● Memory organization: the Flash memory is organized as a main block and an

information block:
– Main memory block of size:

up to 4 Kb × 64 bits divided into 32 pages of 1 Kbyte each for low-density devices
(see Ta bl e 2 )

up to 16 Kb × 64 bits divided into 128 pages of 1 Kbyte each for medium-density
devices (see Ta bl e 3 )

up to 64 Kb × 64 bits divided into 256 pages of 2 Kbytes each (see Tab l e 4) for
high-density devices

up to 32 Kbit × 64 bits divided into 128 pages of 2 Kbytes each (see Ta bl e 5 )

– Information block of size:

2360 × 64 bits for connectivity line devices
258 × 64 bits for other devices (see Tab le 3 )

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RM0034 Memory and bus architecture

The Flash memory interface (FLITF) features:

● Read interface with prefetch buffer (2x64-bit words)

● Option byte Loader

● Flash Program / Erase operation

● Read / Write protection

Table 2. Flash module organization (low-density devices)

Block Name Base addresses Size (bytes)

Page 0 0x0800 0000 - 0x0800 03FF 1 Kbyte

Page 1 0x0800 0400 - 0x0800 07FF 1 Kbyte

Page 2 0x0800 0800 - 0x0800 0BFF 1 Kbyte

Page 3 0x0800 0C00 - 0x0800 0FFF 1 Kbyte

Main memory

Page 4 0x0800 1000 - 0x0800 13FF 1 Kbyte

.
.
.

.
.
.

.
.
.

Page 31 0x0800 7C00 - 0x0800 7FFF 1 Kbyte

Information block

System memory 0x1FFF F000 - 0x1FFF F7FF 2 Kbytes

Option Bytes 0x1FFF F800 - 0x1FFF F80F 16

FLASH_ACR 0x4002 2000 - 0x4002 2003 4

FLASH_KEYR 0x4002 2004 - 0x4002 2007 4

FLASH_OPTKEYR 0x4002 2008 - 0x4002 200B 4

Flash memory

interface
registers

FLASH_SR 0x4002 200C - 0x4002 200F 4

FLASH_CR 0x4002 2010 - 0x4002 2013 4

FLASH_AR 0x4002 2014 - 0x4002 2017 4

Reserved 0x4002 2018 - 0x4002 201B 4

FLASH_OBR 0x4002 201C - 0x4002 201F 4

FLASH_WRPR 0x4002 2020 - 0x4002 2023 4

Table 3. Flash module organization (medium-density devices)

Block Name Base addresses Size (bytes)

Page 0 0x0800 0000 - 0x0800 03FF 1 Kbyte

Page 1 0x0800 0400 - 0x0800 07FF 1 Kbyte

Page 2 0x0800 0800 - 0x0800 0BFF 1 Kbyte

Page 3 0x0800 0C00 - 0x0800 0FFF 1 Kbyte

Main memory

Page 4 0x0800 1000 - 0x0800 13FF 1 Kbyte

.
.
.

.
.
.

Page 127 0x0801 FC00 - 0x0801 FFFF 1 Kbyte

.
.
.

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Memory and bus architecture RM0034

Table 3. Flash module organization (medium-density devices)

Block Name Base addresses Size (bytes)

Information block

System memory 0x1FFF F000 - 0x1FFF F7FF 2 Kbytes

Option Bytes 0x1FFF F800 - 0x1FFF F80F 16

FLASH_ACR 0x4002 2000 - 0x4002 2003 4

FLASH_KEYR 0x4002 2004 - 0x4002 2007 4

FLASH_OPTKEYR 0x4002 2008 - 0x4002 200B 4

Flash memory

interface
registers

FLASH_SR 0x4002 200C - 0x4002 200F 4

FLASH_CR 0x4002 2010 - 0x4002 2013 4

FLASH_AR 0x4002 2014 - 0x4002 2017 4

Reserved 0x4002 2018 - 0x4002 201B 4

FLASH_OBR 0x4002 201C - 0x4002 201F 4

FLASH_WRPR 0x4002 2020 - 0x4002 2023 4

Table 4. Flash module organization (high-density devices)

Block Name Base addresses Size (bytes)

Page 0 0x0800 0000 - 0x0800 07FF 2 Kbytes

Page 1 0x0800 0800 - 0x0800 0FFF 2 Kbytes

Page 2 0x0800 1000 - 0x0800 17FF 2 Kbytes

Main memory

Page 3 0x0800 1800 - 0x0800 1FFF 2 Kbytes

.
.
.

.
.
.

Page 255 0x0807 F800 - 0x0807 FFFF 2 Kbytes

System memory 0x1FFF F000 - 0x1FFF F7FF 2 Kbytes

Information block

Option Bytes 0x1FFF F800 - 0x1FFF F80F 16

FLASH_ACR 0x4002 2000 - 0x4002 2003 4

FLASH_KEYR 0x4002 2004 - 0x4002 2007 4

.
.
.

FLASH_OPTKEYR 0x4002 2008 - 0x4002 200B 4

Flash memory

interface
registers

FLASH_SR 0x4002 200C - 0x4002 200F 4

FLASH_CR 0x4002 2010 - 0x4002 2013 4

FLASH_AR 0x4002 2014 - 0x4002 2017 4

Reserved 0x4002 2018 - 0x4002 201B 4

FLASH_OBR 0x4002 201C - 0x4002 201F 4

FLASH_WRPR 0x4002 2020 - 0x4002 2023 4

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RM0034 Memory and bus architecture

Table 5. Flash module organization (connectivity line devices)

Block Name Base addresses Size (bytes)

Page 0 0x0800 0000 - 0x0800 07FF 2 Kbytes

Page 1 0x0800 0800 - 0x0800 0FFF 2 Kbytes

Page 2 0x0800 1000 - 0x0800 17FF 2 Kbytes

Main memory

Information block

Flash memory

interface
registers

Page 3 0x0800 1800 - 0x0800 1FFF 2 Kbytes

.
.
.

Page 127 0x0803 F800 - 0x0803 FFFF 2 Kbytes

System memory 0x1FFF B000 - 0x1FFF F7FF 18 Kbytes

Option Bytes 0x1FFF F800 - 0x1FFF F80F 16

FLASH_ACR 0x4002 2000 - 0x4002 2003 4

FLASH_KEYR 0x4002 2004 - 0x4002 2007 4

FLASH_OPTKEYR 0x4002 2008 - 0x4002 200B 4

FLASH_SR 0x4002 200C - 0x4002 200F 4

FLASH_CR 0x4002 2010 - 0x4002 2013 4

FLASH_AR 0x4002 2014 - 0x4002 2017 4

Reserved 0x4002 2018 - 0x4002 201B 4

FLASH_OBR 0x4002 201C - 0x4002 201F 4

FLASH_WRPR 0x4002 2020 - 0x4002 2023 4

.
.
.

Note: For further information on the Flash memory interface registers, please refer to the

STM32F10xxx Flash programming manual.

.
.
.

Reading Flash memory

Flash memory instructions and data access are performed through the AHB bus. The
prefetch block is used for instruction fetches through the ICode bus. Arbitration is performed
in the Flash memory interface, and priority is given to data access on the DCode bus.

Read accesses can be performed with the following configuration options:

● Latency: number of wait states for a read operation programmed on-the-fly

● Prefetch buffer (2 x 64-bit blocks): it is enabled after reset; a whole block can be

replaced with a single read from the Flash memory as the size of the block matches the
bandwidth of the Flash memory. Thanks to the prefetch buffer, faster CPU execution is
possible as the CPU fetches one word at a time with the next word readily available in
the prefetch buffer

● Half cycle: for power optimization

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Memory and bus architecture RM0034

Note: 1 These options should be used in accordance with the Flash memory access time. The wait

states represent the ratio of the SYSCLK (system clock) period to the Flash memory access
time:

zero wait state, if 0 < SYSCLK
one wait state, if 24 MHz < SYSCLK
two wait states, if 48 MHz < SYSCLK

≤

24 MHz

≤

48 MHz

≤

72 MHz

2 Half cycle configuration is not available in combination with a prescaler on the AHB. The

system clock (SYSCLK) should be equal to the HCLK clock. This feature can therefore be
used only with a low-frequency clock of 8 MHz or less. It can be generated from the HSI or
the HSE but not from the PLL.

3 The prefetch buffer must be kept on when using a prescaler different from 1 on the AHB

clock.

4 The prefetch buffer must be switched on/off only when SYSCLK is lower than 24 MHz. The

prefetch buffer is usually switched on/off during the initialization routine, while the
microcontroller is running on the internal 8 MHz RC (HSI) oscillator.

5 Using DMA: DMA accesses Flash memory on the DCode bus and has priority over ICode

instructions. The DMA provides one free cycle after each transfer. Some instructions can be
performed together with DMA transfer.

Programming and erasing Flash memory

The Flash memory can be programmed 16 bits (half words) at a time.

The Flash memory erase operation can be performed at page level or on the whole Flash
area (mass-erase). The mass-erase does not affect the information blocks.

To ensure that there is no over-programming, the Flash Programming and Erase Controller
blocks are clocked by a fixed clock.

The End of write operation (programming or erasing) can trigger an interrupt. This interrupt
can be used to exit from WFI mode, only if the FLITF clock is enabled. Otherwise, the
interrupt is served only after an exit from WFI.

Note: For further information on Flash memory operations and register configurations, please refer

to the STM32F10xxx Flash programming manual.

2.4 Boot configuration

In the STM32F10xxx, 3 different boot modes can be selected through BOOT[1:0] pins as
shown in Ta bl e 6 .

Table 6. Boot modes

Boot mode selection pins

Boot mode Aliasing

BOOT1 BOOT0

x 0 Main Flash memory Main Flash memory is selected as boot space

0 1 System memory System memory is selected as boot space

1 1 Embedded SRAM Embedded SRAM is selected as boot space

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RM0034 Memory and bus architecture

The values on the BOOT pins are latched on the 4th rising edge of SYSCLK after a Reset. It
is up to the user to set the BOOT1 and BOOT0 pins after Reset to select the required boot
mode.

The BOOT pins are also re-sampled when exiting from Standby mode. Consequently they
must be kept in the required Boot mode configuration in Standby mode. After this startup
delay has elapsed, the CPU fetches the top-of-stack value from address 0x0000 0000, then
starts code execution from the boot memory starting from 0x0000 0004.

Due to its fixed memory map, the code area starts from address 0x0000 0000 (accessed
through the ICode/DCode buses) while the data area (SRAM) starts from address
0x2000 0000 (accessed through the system bus). The Cortex-M3 CPU always fetches the
reset vector on the ICode bus, which implies to have the boot space available only in the
code area (typically, Flash memory). STM32F10xxx microcontrollers implement a special
mechanism to be able to boot also from SRAM and not only from main Flash memory and
System memory.

Depending on the selected boot mode main Flash memory, System memory or SRAM is
accessible as follows:

● Boot from main Flash memory: the main Flash memory is aliased in the boot memory

space (0x0000 0000), but still accessible from its original memory space (0x800 0000).
In other words, the Flash memory contents can be accessed starting from address
0x0000 0000 or 0x800 0000.

● Boot from System memory: the System memory is aliased in the boot memory space

(0x0000 0000), but still accessible from its original memory space (0x1FFF B000 in
connectivity line devices, 0x1FFF F000 in other devices).

● Boot from the embedded SRAM: SRAM is accessible only at address 0x2000 0000.

Note: When booting from SRAM, in the application initialization code, you have to relocate the

vector table in SRAM using the NVIC exception table and offset register.

Embedded boot loader

The embedded boot loader is used to reprogram the Flash memory using the USART1
serial interface. This program is located in the System memory and is programmed by ST
during production. For further details please refer to AN2606.
In connectivity line devices the bootloader can be activated through one of the following
interfaces: USART1, USART2 (remapped), CAN2 (remapped), USB OTG FS in Device
mode (DFU: device firmware upgrade) and Ethernet. For more information on the
interface(s) supported by your STM32F10xxx microcontroller, please refer to the datasheet
delivered with it.

47/959

CRC calculation unit RM0034

3 CRC calculation unit

Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx

microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.

Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx
microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.

High-density devices are STM32F101xx and STM32F103xx microcontrollers where the
Flash memory density ranges between 256 and 512 Kbytes.

Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.

This section applies to the whole STM32F10xxx family, unless otherwise specified.

3.1 CRC introduction

The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit
data word and a fixed generator polynomial.

Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of
verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of
the software during runtime, to be compared with a reference signature generated at link­time and stored at a given memory location.

3.2 CRC main features

● Uses CRC-32 (Ethernet) polynomial: 0x4C11DB7

32

–X

● Single input/output 32-bit data register

● CRC computation done in 4 AHB clock cycles (HCLK)

● General-purpose 8-bit register (can be used for temporary storage)

The block diagram is shown in Figure 3.

Figure 3. CRC calculation unit block diagram

+ X26 + X23 + X22 + X16 + X12 + X11 + X10 +X8 + X7 + X5 + X4 + X2+ X +1

32-bit (write access)

AHB bus

32-bit (read access)

Data register (output)

CRC computation (polynomial: 0x4C11DB7)

Data register (input)

ai14968

48/959

RM0034 CRC calculation unit

3.3 CRC functional description

The CRC calculation unit mainly consists of a single 32-bit data register, which:

● is used as an input register to enter new data in the CRC calculator (when writing into

the register)

● holds the result of the previous CRC calculation (when reading the register)

Each write operation into the data register creates a combination of the previous CRC value
and the new one (CRC computation is done on the whole 32-bit data word, and not byte per
byte).

The CPU is stalled during the computation, thus allowing back-to-back write accesses or
consecutive write and read accesses, without having to insert software wait cycles.

The CRC calculator can be reset to FFFF FFFFh with the RESET control bit in the CRC_CR
register. This operation does not affect the contents of the CRC_IDR register.

3.4 CRC registers

The CRC calculation unit contains two data registers and a control register.

3.4.1 Data register (CRC_DR)

Address offset: 0x00

Reset value: 0xFFFF FFFF

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

DR [31:16]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

1514131211109876543210

DR [15:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 Data register bits

Used as an input register when writing new data into the CRC calculator.
Holds the previous CRC calculation result when it is read.

49/959

CRC calculation unit RM0034

3.4.2 Independent data register (CRC_IDR)

Address offset: 0x04

Reset value: 0x0000 0000

1514131211109876543210

Reserved

Bits 31:8 Reserved

Bits 7:0 General-purpose 8-bit data register bits

Can be used as a temporary storage location for one byte.
This register is not affected by CRC resets generated by the RESET bit in the CRC_CR

register.

rw rw rw rw rw rw rw rw

IDR[7:0]

3.4.3 Control register (CRC_CR)

Address offset: 0x08

Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

1514131211109876543210

RESET

w

Bits 31:1 Reserved

RESET bit

Bit 0

Resets the CRC calculation unit and sets the data register to FFFF FFFFh.
This bit can only be set, it is automatically cleared by hardware.

Reserved

3.4.4 CRC register map

The following table provides the CRC register map and reset values.

Table 7. CRC calculation unit register map and reset values

Offset Register 31-24 23-16 15-8 7 6 5 4 3 2 1 0

CRC_DR

0x00

Reset value

CRC_IDR

0x04

Reset value

CRC_CR

0x08

Reset value

50/959

Reserved

Reserved

Data register

0xFFFF FFFF

Independent data register

0x00

Reserved0RESET

0

RM0034 Power control (PWR)

A/D converter

V

DDA

V

DD

V

SSA

V

REF+

V

BAT

V

SS

I/O Ring

(V

DD

)

(from 2.4 V up to V

DDA

)

BKP registers

Temp. sensor
Reset block

Standby circuitry

PLL

(Wakeup logic,
IWDG)

RTC

Voltage Regulator

Core

Memories

digital

peripherals

Low voltage detector

V

REF-

V

DDA

domain

V

DD

domain

1.8 V domain

Backup domain

LSE crystal 32K osc

RCC BDCR register

(V

SSA

)

(V

SS

)

4 Power control (PWR)

Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx

microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.

Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx
microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.

High-density devices are STM32F101xx and STM32F103xx microcontrollers where the
Flash memory density ranges between 256 and 512 Kbytes.

Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.

This section applies to the whole STM32F10xxx family, unless otherwise specified.

4.1 Power supplies

The device requires a 2.0-to-3.6 V operating voltage supply (VDD). An embedded regulator
is used to supply the internal 1.8 V digital power.

The real-time clock (RTC) and backup registers can be powered from the V
the main V

supply is powered off.

DD

Figure 4. Power supply overview

voltage when

BAT

Note: 1 V

DDA

and V

must be connected to VDD and VSS, respectively.

SSA

51/959

Power control (PWR) RM0034

4.1.1 Independent A/D converter supply and reference voltage

To improve conversion accuracy, the ADC has an independent power supply which can be
separately filtered and shielded from noise on the PCB.

● The ADC voltage supply input is available on a separate V

● An isolated supply ground connection is provided on pin V

When available (according to package), V

must be tied to V

REF-

On 100-pin and 144- pin packages

To ensure a better accuracy on low voltage inputs, the user can connect a separate external
reference voltage ADC input on V

2.4 V to V

DDA

.

REF+

and V

. The voltage on V

REF-

On 64-pin packages

DDA

SSA

SSA

pin.

.

.

can range from

REF+

The V
voltage supply (V

REF+

and V

pins are not available, they are internally connected to the ADC

REF-

) and ground (V

DDA

4.1.2 Battery backup domain

To retain the content of the Backup registers and supply the RTC function when V
turned off, V
by another source.

The V

BAT

the RTC to operate even when the main digital supply (V
V

supply is controlled by the Power Down Reset embedded in the Reset block.

BAT

Warning: During t

pin can be connected to an optional standby voltage supplied by a battery or

BAT

pin powers the RTC unit, the LSE oscillator and the PC13 to PC15 IOs, allowing

is detected, the power switch between V

RSTTEMPO

connected to V
During the startup phase, if V
t

RSTTEMPO

and V

DD

> V
through an internal diode connected between V
power switch (V
If the power supply/battery connected to the V
support this current injection, it is strongly recommended to
connect an external low-drop diode between this power
supply and the V

).

SSA

) is turned off. The switch to the

DD

(temporization at VDD startup) or after a PDR

and VDD remains

BAT

BAT

.

is established in less than

DD

(Refer to the datasheet for the value of t

+ 0.6 V, a current may be injected into V

BAT

DD

BAT

BAT

BAT

).

pin.

DD

RSTTEMPO

BAT

and the

pin cannot

is

)

If no external battery is used in the application, it is recommended to connect V
externally to VDD through a 100 nF external ceramic capacitor (for more details refer to
AN2586).

When the backup domain is supplied by V
following functions are available:

● PC14 and PC15 can be used as either GPIO or LSE pins

● PC13 can be used as GPIO, TAMPER pin, RTC Calibration Clock, RTC Alarm or

second output (refer to Section 5: Backup registers (BKP) on page 64)

52/959

(analog switch connected to VDD), the

DD

BAT

RM0034 Power control (PWR)

Note: Due to the fact that the switch only sinks a limited amount of current (3 mA), the use of

GPIOs PC13 to PC15 is restricted: only one I/O at a time can be used as an output, the
speed has to be limited to 2 MHz with a maximum load of 30 pF and these IOs must not be
used as a current source (e.g. to drive an LED).

When the backup domain is supplied by V
V

is not present), the following functions are available:

DD

● PC14 and PC15 can be used as LSE pins only

● PC13 can be used as TAMPER pin, RTC Alarm or Second output (refer to section

(analog switch connected to V

BAT

Section 5.4.2: RTC clock calibration register (BKP_RTCCR) on page 66).

4.1.3 Voltage regulator

The voltage regulator is always enabled after Reset. It works in three different modes
depending on the application modes.

● In Run mode, the regulator supplies full power to the 1.8 V domain (core, memories

and digital peripherals).

● In Stop mode the regulator supplies low-power to the 1.8 V domain, preserving

contents of registers and SRAM

● In Standby Mode, the regulator is powered off. The contents of the registers and SRAM

are lost except for the Standby circuitry and the Backup Domain.

4.2 Power supply supervisor

4.2.1 Power on reset (POR)/power down reset (PDR)

The device has an integrated POR/PDR circuitry that allows proper operation starting
from/down to 2 V.

because

BAT

The device remains in Reset mode when V
V

POR/PDR

, without the need for an external reset circuit. For more details concerning the

DD/VDDA

is below a specified threshold,

power on/power down reset threshold, refer to the electrical characteristics of the datasheet.

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Power control (PWR) RM0034

VDD/V

DDA

Reset

40 mV

hysteresis

POR

PDR

Temporization
t

RSTTEMPO

VDD/V

DDA

PVD output

100 mV
hysteresis

PVD threshold

Figure 5. Power on reset/power down reset waveform

4.2.2 Programmable voltage detector (PVD)

You can use the PVD to monitor the VDD/V

power supply by comparing it to a threshold

DDA

selected by the PLS[2:0] bits in the Power control register (PWR_CR).

The PVD is enabled by setting the PVDE bit.

A PVDO flag is available, in the Power control/status register (PWR_CSR), to indicate if
V

DD/VDDA

is higher or lower than the PVD threshold. This event is internally connected to
the EXTI line16 and can generate an interrupt if enabled through the EXTI registers. The
PVD output interrupt can be generated when V
and/or when V

DD/VDDA

rises above the PVD threshold depending on EXTI line16

DD/VDDA

drops below the PVD threshold

rising/falling edge configuration. As an example the service routine could perform
emergency shutdown tasks.

Figure 6. PVD thresholds

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RM0034 Power control (PWR)

4.3 Low-power modes

By default, the microcontroller is in Run mode after a system or a power Reset. Several low­power modes are available to save power when the CPU does not need to be kept running,
for example when waiting for an external event. It is up to the user to select the mode that
gives the best compromise between low-power consumption, short startup time and
available wakeup sources.

The STM32F10xxx devices feature three low-power modes:

● Sleep mode (CPU clock off, all peripherals including Cortex-M3 core peripherals like

NVIC, SysTick, etc. are kept running)

● Stop mode (all clocks are stopped)

● Standby mode (1.8V domain powered-off)

In addition, the power consumption in Run mode can be reduce by one of the following
means:

● Slowing down the system clocks

● Gating the clocks to the APB and AHB peripherals when they are unused.

Table 8. Low-power mode summary

Effect on

Mode name Entry wakeup

Effect on 1.8V

domain clocks

V

DD

domain

clocks

Voltag e

regulator

Sleep
(Sleep now or

Sleep-on ­exit)

Stop

Standby

WFI Any interrupt CPU clock OFF

WFE Wakeup event

PDDS and LPDS
bits +
SLEEPDEEP bit
+ WFI or WFE

PDDS bit +
SLEEPDEEP bit
+ WFI or WFE

Any EXTI line
(configured in the
EXTI registers)

WKUP pin rising
edge, RTC alarm,
external reset in
NRST pin,
IWDG reset

4.3.1 Slowing down system clocks

In Run mode the speed of the system clocks (SYSCLK, HCLK, PCLK1, PCLK2) can be
reduced by programming the prescaler registers. These prescalers can also be used to slow
down peripherals before entering Sleep mode.

For more details refer to Section 6.3.2: Clock configuration register (RCC_CFGR).

no effect on other
clocks or analog
clock sources

All 1.8V domain
clocks OFF

None ON

ON or in low­power mode

(depends on

HSI and
HSE
oscillators
OFF

Power control
register
(PWR_CR))

OFF

55/959

Power control (PWR) RM0034

4.3.2 Peripheral clock gating

In Run mode, the HCLK and PCLKx for individual peripherals and memories can be stopped
at any time to reduce power consumption.

To further reduce power consumption in Sleep mode the peripheral clocks can be disabled
prior to executing the WFI or WFE instructions.

Peripheral clock gating is controlled by the AHB peripheral clock enable register

(RCC_AHBENR), APB1 peripheral clock enable register (RCC_APB1ENR) and APB2
peripheral clock enable register (RCC_APB2ENR).

4.3.3 Sleep mode

Entering Sleep mode

The Sleep mode is entered by executing the WFI (Wait For Interrupt) or WFE (Wait for
Event) instructions. Two options are available to select the Sleep mode entry mechanism,
depending on the SLEEPONEXIT bit in the Cortex-M3 System Control register:

● Sleep-now: if the SLEEPONEXIT bit is cleared, the MCU enters Sleep mode as soon

as WFI or WFE instruction is executed.

● Sleep-on-exit: if the SLEEPONEXIT bit is set, the MCU enters Sleep mode as soon as

it exits the lowest priority ISR.

Refer to Ta bl e 9 and Ta bl e 1 0 for details on how to enter Sleep mode.

Exiting Sleep mode

If the WFI instruction is used to enter Sleep mode, any peripheral interrupt acknowledged by
the nested vectored interrupt controller (NVIC) can wake up the device from Sleep mode.

If the WFE instruction is used to enter Sleep mode, the MCU exits Sleep mode as soon as
an event occurs. The wakeup event can be generated either by:

● enabling an interrupt in the peripheral control register but not in the NVIC, and enabling

the SEVONPEND bit in the Cortex-M3 System Control register. When the MCU
resumes from WFE, the peripheral interrupt pending bit and the peripheral NVIC IRQ
channel pending bit (in the NVIC interrupt clear pending register) have to be cleared.

● or configuring an external or internal EXTI line in event mode. When the CPU resumes

from WFE, it is not necessary to clear the peripheral interrupt pending bit or the NVIC
IRQ channel pending bit as the pending bit corresponding to the event line is not set.

This mode offers the lowest wakeup time as no time is wasted in interrupt entry/exit.

Refer to Ta bl e 9 and Ta bl e 1 0 for more details on how to exit Sleep mode.

56/959

RM0034 Power control (PWR)

Table 9. Sleep-now

Sleep-now mode Description

WFI (Wait for Interrupt) or WFE (Wait for Event) while:

Mode entry

Mode exit

Wakeup latency None

Table 10. Sleep-on-exit

Sleep-on-exit Description

Mode entry

Mode exit Interrupt: refer to Table 42: Vector table for other STM32F10xxx devices.

– SLEEPDEEP = 0 and
– SLEEPONEXIT = 0
Refer to the Cortex™-M3 System Control register.

If WFI was used for entry:

Interrupt: Refer to Table 42: Vector table for other STM32F10xxx devices

If WFE was used for entry

Wakeup event: Refer to Section 9.2.3: Wakeup event management

WFI (wait for interrupt) while:
– SLEEPDEEP = 0 and
– SLEEPONEXIT = 1
Refer to the Cortex™-M3 System Control register.

Wakeup latency None

4.3.4 Stop mode

The Stop mode is based on the Cortex-M3 deepsleep mode combined with peripheral clock
gating. The voltage regulator can be configured either in normal or low-power mode. In Stop
mode, all clocks in the 1.8 V domain are stopped, the PLL, the HSI and the HSE RC
oscillators are disabled. SRAM and register contents are preserved.

Entering Stop mode

Refer to Ta bl e 1 1 for details on how to enter the Stop mode.

To further reduce power consumption in Stop mode, the internal voltage regulator can be
put in low-power mode. This is configured by the LPDS bit of the Power control register

(PWR_CR).

If Flash memory programming is ongoing, the Stop mode entry is delayed until the memory
access is finished.

If an access to the APB domain is ongoing, The Stop mode entry is delayed until the APB
access is finished.

57/959

Power control (PWR) RM0034

In Stop mode, the following features can be selected by programming individual control bits:

● Independent watchdog (IWDG): the IWDG is started by writing to its Key register or by

hardware option. Once started it cannot be stopped except by a Reset. See

Section 17.3 in Section 17: Independent watchdog (IWDG).

● real-time clock (RTC): this is configured by the RTCEN bit in the Backup domain control

register (RCC_BDCR)

● Internal RC oscillator (LSI RC): this is configured by the LSION bit in the Control/status

register (RCC_CSR).

● External 32.768 kHz oscillator (LSE OSC): this is configured by the LSEON bit in the

Backup domain control register (RCC_BDCR).

The ADC or DAC can also consume power during the Stop mode, unless they are disabled
before entering it. To disable them, the ADON bit in the ADC_CR2 register and the ENx bit
in the DAC_CR register must both be written to 0.

Exiting Stop mode

Refer to Ta bl e 1 1 for more details on how to exit Stop mode.

When exiting Stop mode by issuing an interrupt or a wakeup event, the HSI RC oscillator is
selected as system clock.

When the voltage regulator operates in low-power mode, an additional startup delay is
incurred when waking up from Stop mode. By keeping the internal regulator ON during Stop
mode, the consumption is higher although the startup time is reduced.

Table 11. Stop mode

Stop mode Description

Mode entry

Mode exit

Wakeup latency HSI RC wakeup time + regulator wakeup time from Low-power mode

4.3.5 Standby mode

The Standby mode allows to achieve the lowest power consumption. It is based on the
Cortex-M3 deepsleep mode, with the voltage regulator disabled. The 1.8 V domain is
consequently powered off. The PLL, the HSI oscillator and the HSE oscillator are also

WFI (Wait for Interrupt) or WFE (Wait for Event) while:
– Set SLEEPDEEP bit in Cortex™-M3 System Control register
– Clear PDDS bit in Power Control register (PWR_CR)
– Select the voltage regulator mode by configuring LPDS bit in PWR_CR

Note: To enter Stop mode, all EXTI Line pending bits (in Pending register

(EXTI_PR)) and RTC Alarm flag must be reset. Otherwise, the Stop mode

entry procedure is ignored and program execution continues.

If WFI was used for entry:

Any EXTI Line configured in Interrupt mode (the corresponding EXTI
Interrupt vector must be enabled in the NVIC). Refer to Table 42: Vector

table for other STM32F10xxx devices on page 165.

If WFE was used for entry:

Any EXTI Line configured in event mode. Refer to Section 9.2.3: Wakeup

event management on page 168

58/959

RM0034 Power control (PWR)

switched off. SRAM and register contents are lost except for registers in the Backup domain
and Standby circuitry (see Figure 4).

Entering Standby mode

Refer to Ta bl e 1 2 for more details on how to enter Standby mode.

In Standby mode, the following features can be selected by programming individual control
bits:

● Independent watchdog (IWDG): the IWDG is started by writing to its Key register or by

hardware option. Once started it cannot be stopped except by a reset. See

Section 17.3 in Section 17: Independent watchdog (IWDG).

● real-time clock (RTC): this is configured by the RTCEN bit in the Backup domain control

register (RCC_BDCR)

● Internal RC oscillator (LSI RC): this is configured by the LSION bit in the Control/status

register (RCC_CSR).

● External 32.768 kHz oscillator (LSE OSC): this is configured by the LSEON bit in the

Backup domain control register (RCC_BDCR)

Exiting Standby mode

The microcontroller exits Standby mode when an external Reset (NRST pin), IWDG Reset,
a rising edge on WKUP pin or an RTC alarm occurs. All registers are reset after wakeup
from Standby except for Power control/status register (PWR_CSR).

After waking up from Standby mode, program execution restarts in the same way as after a
Reset (boot pins sampling, vector reset is fetched, etc.). The SBF status flag in the Powe r

control/status register (PWR_CSR) indicates that the MCU was in Standby mode.

Refer to Ta bl e 1 2 for more details on how to exit Standby mode.

Table 12. Standby mode

Standby mode Description

WFI (Wait for Interrupt) or WFE (Wait for Event) while:

Mode entry

Mode exit

Wakeup latency Regulator start up. Reset phase

– Set SLEEPDEEP in Cortex™-M3 System Control register
– Set PDDS bit in Power Control register (PWR_CR)
– Clear WUF bit in Power Control/Status register (PWR_CSR)

WKUP pin rising edge, RTC alarm, external Reset in
Reset.

NRST pin, IWDG

I/O states in Standby mode

In Standby mode, all I/O pins are high impedance except:

● Reset pad (still available)

● TAMPER pin if configured for tamper or calibration out

● WKUP pin, if enabled

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Power control (PWR) RM0034

Debug mode

By default, the debug connection is lost if the application puts the MCU in Stop or Standby
mode while the debug features are used. This is due to the fact that the Cortex™-M3 core is
no longer clocked.

However, by setting some configuration bits in the DBGMCU_CR register, the software can
be debugged even when using the low-power modes extensively. For more details, refer to

Section 30.15.1: Debug support for low-power modes.

4.3.6 Auto-wakeup (AWU) from low-power mode

The RTC can be used to wakeup the MCU from low-power mode without depending on an
external interrupt (Auto-wakeup mode). The RTC provides a programmable time base for
waking up from Stop or Standby mode at regular intervals. For this purpose, two of the three
alternative RTC clock sources can be selected by programming the RTCSEL[1:0] bits in the

Backup domain control register (RCC_BDCR):

● Low-power 32.768 kHz external crystal oscillator (LSE OSC).

This clock source provides a precise time base with very low-power consumption (less
than 1µA added consumption in typical conditions)

● Low-power internal RC Oscillator (LSI RC)

This clock source has the advantage of saving the cost of the 32.768 kHz crystal. This
internal RC Oscillator is designed to add minimum power consumption.

To wakeup from Stop mode with an RTC alarm event, it is necessary to:

● Configure the EXTI Line 17 to be sensitive to rising edge

● Configure the RTC to generate the RTC alarm

To wakeup from Standby mode, there is no need to configure the EXTI Line 17.

4.4 Power control registers

4.4.1 Power control register (PWR_CR)

Address offset: 0x00

Reset value: 0x0000 0000 (reset by wakeup from Standby mode)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Res.

1514131211109876543210

Reserved DBP PLS[2:0] PVDE CSBF CWUF PDDS LPDS

Res rwrwrwrwrwrc_w1rc_w1rwrw

Bits 31:9 Reserved, always read as 0.

60/959

RM0034 Power control (PWR)

Bit 8 DBP: Disable backup domain write protection.

In reset state, the RTC and backup registers are protected against parasitic write access. This
bit must be set to enable write access to these registers.

0: Access to RTC and Backup registers disabled
1: Access to RTC and Backup registers enabled

Bits 7:5 PLS[2:0]: PVD level selection.

These bits are written by software to select the voltage threshold detected by the Power
Voltage Detector

000: 2.2V
001: 2.3V
010: 2.4V
011: 2.5V
100: 2.6V
101: 2.7V
110: 2.8V
111: 2.9V

Note: Refer to the electrical characteristics of the datasheet for more details.

Bit 4 PVDE: Power voltage detector enable.

This bit is set and cleared by software.

0: PVD disabled
1: PVD enabled

Bit 3 CSBF: Clear standby flag.

This bit is always read as 0.

0: No effect
1: Clear the SBF Standby Flag (write).

Bit 2 CWUF: Clear wakeup flag.

This bit is always read as 0.

0: No effect
1: Clear the WUF Wakeup Flag after 2 System clock cycles. (write)

Bit 1 PDDS: Power down deepsleep.

This bit is set and cleared by software. It works together with the LPDS bit.

0: Enter Stop mode when the CPU enters Deepsleep. The regulator status depends on the
LPDS bit.

1: Enter Standby mode when the CPU enters Deepsleep.

Bit 0 LPDS: Low-power deepsleep.

This bit is set and cleared by software. It works together with the PDDS bit.

0: Voltage regulator on during Stop mode
1: Voltage regulator in low-power mode during Stop mode

61/959

Power control (PWR) RM0034

4.4.2 Power control/status register (PWR_CSR)

Address offset: 0x04

Reset value: 0x0000 0000 (not reset by wakeup from Standby mode)

Additional APB cycles are needed to read this register versus a standard APB read.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Res.

1514131211109876543210

Reserved EWUP Reserved PVDO SBF WUF

Res. rw Res. r r r

Bits 31:9 Reserved, always read as 0.

Bit 8 EWUP: Enable WKUP pin

This bit is set and cleared by software.

0: WKUP pin is used for general purpose I/O. An event on the WKUP pin does not wakeup
the device from Standby mode.

1: WKUP pin is used for wakeup from Standby mode and forced in input pull down
configuration (rising edge on WKUP pin wakes-up the system from Standby mode).

Note: This bit is reset by a system Reset.

Bits 7:3 Reserved, always read as 0.

Bit 2 PVDO: PVD output

This bit is set and cleared by hardware. It is valid only if PVD is enabled by the PVDE bit.

0: V
1: V

DD/VDDA
DD/VDDA

is higher than the PVD threshold selected with the PLS[2:0] bits.
is lower than the PVD threshold selected with the PLS[2:0] bits.

Note: The PVD is stopped by Standby mode. For this reason, this bit is equal to 0 after

Standby or reset until the PVDE bit is set.

Bit 1 SBF: Standby flag

This bit is set by hardware and cleared only by a POR/PDR (power on reset/power down reset)
or by setting the CSBF bit in the Power control register (PWR_CR)

0: Device has not been in Standby mode
1: Device has been in Standby mode

Bit 0 WUF: Wakeup flag

This bit is set by hardware and cleared only by a POR/PDR (power on reset/power down
reset) or by setting the CWUF bit in the Power control register (PWR_CR)

0: No wakeup event occurred
1: A wakeup event was received from the WKUP pin or from the RTC alarm

Note: An additional wakeup event is detected if the WKUP pin is enabled (by setting the

EWUP bit) when the WKUP pin level is already high.

62/959

RM0034 Power control (PWR)

4.4.3 PWR register map

The following table summarizes the PWR registers.

Table 13. PWR - register map and reset values

Offset Register

0x000

0x004

313029282726252423222120191817161514131211

PWR_CR

Reset value 000000000

PWR_CSR

Reset value 0000

Reserved

Reserved

987654321

10

PLS[2:0]

DBP

EWUP

PVDE

Reserved

CSBF

PDDS

CWUF

SBF

PVDO

Refer to Table 1 on page 40 for the register boundary addresses.

0

LPDS

WUF

63/959

Backup registers (BKP) RM0034

5 Backup registers (BKP)

Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx

microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.

Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx
microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.

High-density devices are STM32F101xx and STM32F103xx microcontrollers where the
Flash memory density ranges between 256 and 512 Kbytes.

Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.

This Section applies to the whole STM32F10xxx family, unless otherwise specified.

5.1 BKP introduction

The backup registers are forty two 16-bit registers for storing 84 bytes of user application
data. They are implemented in the backup domain that remains powered on by V
the V

power is switched off. They are not reset when the device wakes up from Standby

DD

mode or by a system reset or power reset.

BAT

when

In addition, the BKP control registers are used to manage the Tamper detection feature and
RTC calibration.

After reset, access to the Backup registers and RTC is disabled and the Backup domain
(BKP) is protected against possible parasitic write access. To enable access to the Backup
registers and the RTC, proceed as follows:

● enable the power and backup interface clocks by setting the PWREN and BKPEN bits

in the RCC_APB1ENR register

● set the DBP bit the Power Control Register (PWR_CR) to enable access to the Backup

registers and RTC.

5.2 BKP main features

● 20-byte data registers (in medium-density and low-density devices) or 84-byte data

registers (in high-density and connectivity line devices)

● Status/control register for managing tamper detection with interrupt capability

● Calibration register for storing the RTC calibration value

● Possibility to output the RTC Calibration Clock, RTC Alarm pulse or Second pulse on

TAMPER pin PC13 (when this pin is not used for tamper detection)

64/959

RM0034 Backup registers (BKP)

5.3 BKP functional description

5.3.1 Tamper detection

The TAMPER pin generates a Tamper detection event when the pin changes from 0 to 1 or
from 1 to 0 depending on the TPAL bit in the Backup control register (BKP_CR). A tamper
detection event resets all data backup registers.

However to avoid losing Tamper events, the signal used for edge detection is logically
ANDed with the Tamper enable in order to detect a Tamper event in case it occurs before
the TAMPER pin is enabled.

● When TPAL=0: If the TAMPER pin is already high before it is enabled (by setting TPE

bit), an extra Tamper event is detected as soon as the TAMPER pin is enabled (while
there was no rising edge on the TAMPER pin after TPE was set)

● When TPAL=1: If the TAMPER pin is already low before it is enabled (by setting the

TPE bit), an extra Tamper event is detected as soon as the TAMPER pin is enabled
(while there was no falling edge on the TAMPER pin after TPE was set)

By setting the TPIE bit in the BKP_CSR register, an interrupt is generated when a Tamper
detection event occurs.

After a Tamper event has been detected and cleared, the TAMPER pin should be disabled
and then re-enabled with TPE before writing to the backup data registers (BKP_DRx) again.
This prevents software from writing to the backup data registers (BKP_DRx), while the
TAMPER pin value still indicates a Tamper detection. This is equivalent to a level detection
on the TAMPER pin.

Note: Tamper detection is still active when V

of the data backup registers, the TAMPER pin should be externally tied to the correct level.

5.3.2 RTC calibration

For measurement purposes, the RTC clock with a frequency divided by 64 can be output on
the TAMPER pin. This is enabled by setting the CCO bit in the RTC clock calibration register

(BKP_RTCCR).

The clock can be slowed down by up to 121 ppm by configuring CAL[6:0] bits.

For more details about RTC calibration and how to use it to improve timekeeping accuracy,
please refer to AN2604 "STM32F101xx and STM32F103xx RTC calibration”.

power is switched off. To avoid unwanted resetting

DD

65/959

Backup registers (BKP) RM0034

5.4 BKP registers

Refer to Section 1.1 on page 36 for a list of abbreviations used in register descriptions.

5.4.1 Backup data register x (BKP_DRx) (x = 1 ..42)

Address offset: 0x04 to 0x28, 0x40 to 0xBC

Reset value: 0x0000 0000

1514131211109876543210

D[15:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 15:0 D[15:0] Backup data

These bits can be written with user data.

Note: The BKP_DRx registers are not reset by a System reset or Power reset or when the

device wakes up from Standby mode.
They are reset by a Backup Domain reset or by a TAMPER pin event (if the TAMPER
pin function is activated).

5.4.2 RTC clock calibration register (BKP_RTCCR)

Address offset: 0x2C

Reset value: 0x0000 0000

1514131211109876543210

Reserved

Bits 15:10 Reserved, always read as 0.

Bit 9 ASOS: Alarm or second output selection

When the ASOE bit is set, the ASOS bit can be used to select whether the signal output on
the TAMPER pin is the RTC Second pulse signal or the Alarm pulse signal:
0: RTC Alarm pulse output selected
1: RTC Second pulse output selected

Note: This bit is reset only by a Backup domain reset.

ASOS ASOE CCO CAL[6:0]

rw rw rw rw rw rw rw rw rw rw

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RM0034 Backup registers (BKP)

Bit 8 ASOE: Alarm or second output enable

Setting this bit outputs either the RTC Alarm pulse signal or the Second pulse signal on the
TAMPER pin depending on the ASOS bit.
The output pulse duration is one RTC clock period. The TAMPER pin must not be enabled
while the ASOE bit is set.

Note: This bit is reset only by a Backup domain reset.

Bit 7 CCO: Calibration clock output

0: No effect
1: Setting this bit outputs the RTC clock with a frequency divided by 64 on the TAMPER pin.

The TAMPER pin must not be enabled while the CCO bit is set in order to avoid unwanted
Tamper detection.

Note: This bit is reset when the V

supply is powered off.

DD

Bit 6:0 CAL[6:0]: Calibration value

This value indicates the number of clock pulses that will be ignored every 2^20 clock pulses.
This allows the calibration of the RTC, slowing down the clock by steps of 1000000/2^20
PPM.
The clock of the RTC can be slowed down from 0 to 121PPM.

5.4.3 Backup control register (BKP_CR)

Address offset: 0x30

Reset value: 0x0000 0000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

TPAL TPE

rw rw

Bits 15:2 Reserved, always read as 0.

Bit 1 TPAL: TAMPER pin active level

0: A high level on the TAMPER pin resets all data backup registers (if TPE bit is set).
1: A low level on the TAMPER pin resets all data backup registers (if TPE bit is set).

Bit 0 TPE: TAMPER pin enable

0: The TAMPER pin is free for general purpose I/O
1: Tamper alternate I/O function is activated.

Note: Setting the TPAL and TPE bits at the same time is always safe, however resetting both at

the same time can generate a spurious Tamper event. For this reason it is recommended to
change the TPAL bit only when the TPE bit is reset.

67/959

Backup registers (BKP) RM0034

5.4.4 Backup control/status register (BKP_CSR)

Address offset: 0x34

Reset value: 0x0000 0000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

TIF TEF

rr rwww

Bits 15:10 Reserved, always read as 0.

Bit 9 TIF: Tamper interrupt flag

This bit is set by hardware when a Tamper event is detected and the TPIE bit is set. It is
cleared by writing 1 to the CTI bit (also clears the interrupt). It is also cleared if the TPIE bit
is reset.

0: No Tamper interrupt
1: A Tamper interrupt occurred

Note: This bit is reset only by a system reset and wakeup from Standby mode.

Bit 8 TEF: Tamper event flag

This bit is set by hardware when a Tamper event is detected. It is cleared by writing 1 to the
CTE bit.

0: No Tamper event
1: A Tamper event occurred

Note: A Tamper event resets all the BKP_DRx registers. They are held in reset as long as the

TEF bit is set. If a write to the BKP_DRx registers is performed while this bit is set, the
value will not be stored.

Reserved

TPIE CTI CTE

Bits 7:3 Reserved, always read as 0.

Bit 2 TPIE: TAMPER pin interrupt enable

0: Tamper interrupt disabled
1: Tamper interrupt enabled (the TPE bit must also be set in the BKP_CR register

Note 1: A Tamper interrupt does not wake up the core from low-power modes.
Note 2: This bit is reset only by a system reset and wakeup from Standby mode.

Bit 1 CTI: Clear tamper interrupt

This bit is write only, and is always read as 0.
0: No effect
1: Clear the Tamper interrupt and the TIF Tamper interrupt flag.

Bit 0 CTE: Clear tamper event

This bit is write only, and is always read as 0.
0: No effect
1: Reset the TEF Tamper event flag (and the Tamper detector)

68/959

RM0034 Backup registers (BKP)

5.4.5 BKP register map

BKP registers are mapped as 16-bit addressable registers as described in the table below:

Table 14. BKP register map and reset values

Offset Register

0x00 Reserved

313029282726252423222120191817161514131211

987654321

10

0

0x04

0x08

0x0C

0x10

0x14

0x18

0x1C

0x20

0x24

BKP_DR1

Reset value 0000000000000000

BKP_DR2

Reset value 0000000000000000

BKP_DR3

Reset value 0000000000000000

BKP_DR4

Reset value 0000000000000000

BKP_DR5

Reset value 0000000000000000

BKP_DR6

Reset value 0000000000000000

BKP_DR7

Reset value 0000000000000000

BKP_DR8

Reset value 0000000000000000

BKP_DR9

Reset value 0000000000000000

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

D[15:0]

D[15:0]

D[15:0]

D[15:0]

D[15:0]

D[15:0]

D[15:0]

D[15:0]

D[15:0]

0x28

0x2

0x30

0x34

0x38

0x3C

0x40

BKP_DR10

Reset value 0000000000000000

BKP_RTCCR

Reset value 0000000000

BKP_CR

Reset value 00

BKP_CSR

Reset value 00 000

BKP_DR11

Reset value 0000000000000000

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

D[15:0]

ASOS

TIF

D[15:0]

ASOE

TEF

CCO

Reserved

CAL[6:0]

TPAL

CTI

TPIE

69/959

TPE

CTE

Backup registers (BKP) RM0034

Table 14. BKP register map and reset values (continued)

Offset Register

0x44

BKP_DR12

Reset value 0000000000000000

313029282726252423222120191817161514131211

Reserved

987654321

10

D[15:0]

0

0x48

0x4C

0x50

0x54

0x58

0x5C

0x60 BKP_DR19

0x64

0x68

BKP_DR13

Reset value 0000000000000000

BKP_DR14

Reset value 0000000000000000

BKP_DR15

Reset value 0000000000000000

BKP_DR16

Reset value 0000000000000000

BKP_DR17

Reset value 0000000000000000

BKP_DR18

Reset value 0000000000000000

Reset value 0000000000000000

BKP_DR20

Reset value 0000000000000000

BKP_DR21

Reset value 0000000000000000

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

D[15:0]

D[15:0]

D[15:0]

D[15:0]

D[15:0]

D[15:0]

D[15:0]

D[15:0]

D[15:0]

0x6C

0x70

0x74

0x78

0x7C

0x80

0x84

BKP_DR22

Reset value 0000000000000000

BKP_DR23

Reset value 0000000000000000

BKP_DR24

Reset value 0000000000000000

BKP_DR25

Reset value 0000000000000000

BKP_DR26

Reset value 0000000000000000

BKP_DR27

Reset value 0000000000000000

BKP_DR28

Reset value 0000000000000000

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

70/959

D[15:0]

D[15:0]

D[15:0]

D[15:0]

D[15:0]

D[15:0]

D[15:0]

RM0034 Backup registers (BKP)

Table 14. BKP register map and reset values (continued)

Offset Register

0x88 BKP_DR29

Reset value 0000000000000000

313029282726252423222120191817161514131211

Reserved

987654321

10

D[15:0]

0

0x8C

0x90

0x94

0x98

0x9C

0xA0

0xA4

0xA8

0xAC

BKP_DR30

Reset value 0000000000000000

BKP_DR31

Reset value 0000000000000000

BKP_DR32

Reset value 0000000000000000

BKP_DR33

Reset value 0000000000000000

BKP_DR34

Reset value 0000000000000000

BKP_DR35

Reset value 0000000000000000

BKP_DR36

Reset value 0000000000000000

BKP_DR37

Reset value 0000000000000000

BKP_DR38

Reset value 0000000000000000

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

D[15:0]

D[15:0]

D[15:0]

D[15:0]

D[15:0]

D[15:0]

D[15:0]

D[15:0]

D[15:0]

0xB0 BKP_DR39

Reset value 0000000000000000

0xB4

0xB8 BKP_DR41

0xBC

BKP_DR40

Reset value 0000000000000000

Reset value 0000000000000000

BKP_DR42

Reset value 0000000000000000

Refer to Table 1 on page 40 for the register boundary addresses.

Reserved

Reserved

Reserved

Reserved

D[15:0]

D[15:0]

D[15:0]

D[15:0]

71/959

Low-, medium- and high-density reset and clock control (RCC) RM0034

6 Low-, medium- and high-density reset and clock

control (RCC)

Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx

microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.

Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx
microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.

High-density devices are STM32F101xx and STM32F103xx microcontrollers where the
Flash memory density ranges between 256 and 512 Kbytes.

Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.

This Section applies to low-, medium- and high-density STM32F10xxx devices.
Connectivity line devices are discussed in a separate section (refer to Connectivity line

devices: reset and clock control (RCC) on page 102).

6.1 Reset

There are three types of reset, defined as system Reset, power Reset and backup domain
Reset.

6.1.1 System reset

A system reset sets all registers to their reset values except the reset flags in the clock
controller CSR register and the registers in the Backup domain (see Figure 4).

A system reset is generated when one of the following events occurs:

1. A low level on the NRST pin (external reset)

2. Window watchdog end of count condition (WWDG reset)

3. Independent watchdog end of count condition (IWDG reset)

4. A software reset (SW reset) (see Section : Software reset)

5. Low-power management reset (see Section : Low-power management reset)

The reset source can be identified by checking the reset flags in the Control/Status register,
RCC_CSR (see Section 6.3.10: Control/status register (RCC_CSR)).

Software reset

The SYSRESETREQ bit in Cortex™-M3 Application Interrupt and Reset Control Register
must be set to force a software reset on the device. Refer to the Cortex™-M3 technical
reference manual for more details.

Low-power management reset

There are two ways to generate a low-power management reset:

72/959

RM0034 Low-, medium- and high-density reset and clock control (RCC)

NRST

R

PU

VDD/V

DDA

WWDG Reset
IWDG Reset

Pulse

generator

Power Reset

External

Reset

(min 20 µs)

System Reset

Filter

Software Reset

Low-power management Reset

1. Reset generated when entering Standby mode:

This type of reset is enabled by resetting nRST_STDBY bit in User Option Bytes. In this
case, whenever a Standby mode entry sequence is successfully executed, the device
is reset instead of entering Standby mode.

2. Reset when entering Stop mode:

This type of reset is enabled by resetting NRST_STOP bit in User Option Bytes. In this
case, whenever a Stop mode entry sequence is successfully executed, the device is
reset instead of entering Stop mode.

For further information on the User Option Bytes, refer to the STM32F10xxx Flash
programming manual.

6.1.2 Power reset

A power reset is generated when one of the following events occurs:

1. Power-on/power-down reset (POR/PDR reset)

2. When exiting Standby mode

A power reset sets all registers to their reset values except the Backup domain (see

Figure 4)

These sources act on the NRST pin and it is always kept low during the delay phase. The
RESET service routine vector is fixed at address
details, refer to Table 42: Vector table for other STM32F10xxx devices on page 165.

0x0000_0004 in the memory map. For more

Figure 7. Reset circuit

The Backup domain has two specific resets that affect only the Backup domain (see

Figure 4).

6.1.3 Backup domain reset

A backup domain reset is generated when one of the following events occurs:

1. Software reset, triggered by setting the BDRST bit in the Backup domain control

register (RCC_BDCR).

2. V

DD

or V

power on, if both supplies have previously been powered off.

BAT

73/959

Low-, medium- and high-density reset and clock control (RCC) RM0034

6.2 Clocks

Three different clock sources can be used to drive the system clock (SYSCLK):

● HSI oscillator clock

● HSE oscillator clock

● PLL clock

The devices have the following two secondary clock sources:

● 40 kHz low speed internal RC (LSI RC) which drives the independent watchdog and

optionally the RTC used for Auto-wakeup from Stop/Standby mode.

● 32.768 kHz low speed external crystal (LSE crystal) which optionally drives the real-

time clock (RTCCLK)

Each clock source can be switched on or off independently when it is not used, to optimize
power consumption.

74/959

RM0034 Low-, medium- and high-density reset and clock control (RCC)

HSE OSC

4-16 MHz

OSC_IN

OSC_OUT

OSC32_IN

OSC32_OUT

LSE OSC

32.768 kHz

HSI RC

8 MHz

LSI RC
40 kHz

to Independent Watchdog (IWDG)

PLL

x2, x3, x4

PLLMUL

HSE = High Speed External clock signal

LSE = Low Speed External clock signal

LSI = Low Speed Internal clock signal

HSI = High Speed Internal clock signal

Legend:

MCO

Clock Output

Main

PLLXTPRE

/2

..., x16

AHB
Prescaler
/1, 2..512

/2

PLLCLK

HSI

HSE

APB1

Prescaler

/1, 2, 4, 8, 16

ADC
Prescaler
/2, 4, 6, 8

ADCCLK

PCLK1

HCLK

PLLCLK

to AHB bus, core,
memory and DMA

USBCLK

to USB interface

USB

Prescaler

/1, 1.5

to ADC1, 2 or 3

LSE

LSI

HSI

/128

/2

HSI

HSE

peripherals

to APB1

Peripheral Clock

Enable (20 bits)

Enable (6 bits)

Peripheral Clock

APB2

Prescaler

/1, 2, 4, 8, 16

PCLK2

TIM1 & 8 timers

to TIM1 and TIM8

peripherals to APB2

Peripheral Clock

Enable (15 bits)

Enable (2 bit)

Peripheral Clock

48 MHz

72 MHz max

72 MHz

72 MHz max

36 MHz max

to RTC

PLLSRC

SW

MCO

CSS

to Cortex System timer

/8

Clock

Enable (4 bits)

SYSCLK

max

RTCCLK

RTCSEL[1:0]

TIMxCLK

TIMXCLK

IWDGCLK

SYSCLK

FCLK Cortex
free running clock

/2

TIM2,3,4,5,6,7

to TIM2,3,4,5,6 and 7

To SDIO AHB interface
Peripheral clock
enable

HCLK/2

to FSMC

FSMCCLK

to SDIO

Peripheral clock
enable

Peripheral clock
enable

to I2S3

to I2S2

Peripheral clock
enable

Peripheral clock
enable

I2S3CLK

I2S2CLK

SDIOCLK

ai14752b

If (APB1 prescaler =1) x1

else x2

If (APB2 prescaler =1) x1

else x2

Figure 8. Clock tree

1. When the HSI is used as a PLL clock input, the maximum system clock frequency that can be achieved is
64 MHz.

Several prescalers allow the configuration of the AHB frequency, the high speed APB
(APB2) and the low speed APB (APB1) domains. The maximum frequency of the AHB and
the APB2 domains is 72 MHz. The maximum allowed frequency of the APB1 domain is
36 MHz. The SDIO AHB interface is clocked with a fixed frequency equal to HCLK/2.

The RCC feeds the Cortex System Timer (SysTick) external clock with the AHB clock
(HCLK) divided by 8. The SysTick can work either with this clock or with the Cortex clock
(HCLK), configurable in the SysTick Control and Status Register. The ADCs are clocked by
the clock of the High Speed domain (APB2) divided by 2, 4, 6 or 8.

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Low-, medium- and high-density reset and clock control (RCC) RM0034

OSC_OUT

EXTERNAL

SOURCE

(HiZ)

OSC_IN OSC_OUT

LOAD

CAPACITORS

C

L2

C

L1

The timer clock frequencies are automatically fixed by hardware. There are two cases:

1. if the APB prescaler is 1, the timer clock frequencies are set to the same frequency as

that of the APB domain to which the timers are connected.

2. otherwise, they are set to twice (×2) the frequency of the APB domain to which the

timers are connected.

FCLK acts as Cortex™-M3 free running clock. For more details refer to the ARM Cortex™­M3 Technical Reference Manual.

6.2.1 HSE clock

The high speed external clock signal (HSE) can be generated from two possible clock
sources:

● HSE external crystal/ceramic resonator

● HSE user external clock

The resonator and the load capacitors have to be placed as close as possible to the
oscillator pins in order to minimize output distortion and startup stabilization time. The
loading capacitance values must be adjusted according to the selected oscillator.

Figure 9. HSE/ LSE clock sources

Hardware configuration

External ClockCrystal/Ceramic Resonators

External source (HSE bypass)

In this mode, an external clock source must be provided. It can have a frequency of up to 25
MHz. You select this mode by setting the HSEBYP and HSEON

register (RCC_CR). The external clock signal (square, sinus or triangle) with ~50% duty

cycle has to drive the OSC_IN pin while the OSC_OUT pin should be left hi-Z. See Figure 9.

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bits in the Clock control

RM0034 Low-, medium- and high-density reset and clock control (RCC)

External crystal/ceramic resonator (HSE crystal)

The 4 to 16 MHz external oscillator has the advantage of producing a very accurate rate on
the main clock.

The associated hardware configuration is shown in Figure 9. Refer to the electrical
characteristics section of the datasheet for more details.

The HSERDY flag in the Clock control register (RCC_CR) indicates if the high-speed
external oscillator is stable or not. At startup, the clock is not released until this bit is set by
hardware. An interrupt can be generated if enabled in the Clock interrupt register

(RCC_CIR).

The HSE Crystal can be switched on and off using the HSEON bit in the Clock control

register (RCC_CR).

6.2.2 HSI clock

The HSI clock signal is generated from an internal 8 MHz RC Oscillator and can be used
directly as a system clock or divided by 2 to be used as PLL input.

The HSI RC oscillator has the advantage of providing a clock source at low cost (no external
components). It also has a faster startup time than the HSE crystal oscillator however, even
with calibration the frequency is less accurate than an external crystal oscillator or ceramic
resonator.

Calibration

RC oscillator frequencies can vary from one chip to another due to manufacturing process
variations, this is why each device is factory calibrated by ST for 1% accuracy at T

After reset, the factory calibration value is loaded in the HSICAL[7:0] bits in the Clock control

register (RCC_CR).

If the application is subject to voltage or temperature variations this may affect the RC
oscillator speed. You can trim the HSI frequency in the application using the HSITRIM[4:0]
bits in the Clock control register (RCC_CR).

The HSIRDY flag in the Clock control register (RCC_CR) indicates if the HSI RC is stable or
not. At startup, the HSI RC output clock is not released until this bit is set by hardware.

The HSI RC can be switched on and off using the HSION bit in the Clock control register

(RCC_CR).

The HSI signal can also be used as a backup source (Auxiliary clock) if the HSE crystal
oscillator fails. Refer to Section 6.2.7: Clock security system (CSS) on page 79.

6.2.3 PLL

The internal PLL can be used to multiply the HSI RC output or HSE crystal output clock
frequency. Refer to Figure 8 and Clock control register (RCC_CR).

The PLL configuration (selection of HSI oscillator divided by 2 or HSE oscillator for PLL
input clock, and multiplication factor) must be done before enabling the PLL. Once the PLL
enabled, these parameters cannot be changed.

=25°C.

A

An interrupt can be generated when the PLL is ready if enabled in the Clock interrupt

register (RCC_CIR).

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Low-, medium- and high-density reset and clock control (RCC) RM0034

If the USB interface is used in the application, the PLL must be programmed to output 48 or
72 MHz. This is needed to provide a 48 MHz USBCLK.

6.2.4 LSE clock

The LSE crystal is a 32.768 kHz Low Speed External crystal or ceramic resonator. It has the
advantage providing a low-power but highly accurate clock source to the real-time clock
peripheral (RTC) for clock/calendar or other timing functions.

The LSE crystal is switched on and off using the LSEON bit in Backup domain control

register (RCC_BDCR).

The LSERDY flag in the Backup domain control register (RCC_BDCR) indicates if the LSE
crystal is stable or not. At startup, the LSE crystal output clock signal is not released until
this bit is set by hardware. An interrupt can be generated if enabled in the Clock interrupt

register (RCC_CIR).

External source (LSE bypass)

In this mode, an external clock source must be provided. It must have a frequency of

32.768 kHz. You select this mode by setting the LSEBYP and LSEON bits in the Backup

domain control register (RCC_BDCR). The external clock signal (square, sinus or triangle)

with ~50% duty cycle has to drive the OSC32_IN pin while the OSC32_OUT pin should be
left Hi-Z. See Figure 9.

6.2.5 LSI clock

The LSI RC acts as an low-power clock source that can be kept running in Stop and
Standby mode for the independent watchdog (IWDG) and Auto-wakeup unit (AWU). The
clock frequency is around 40 kHz (between 30 kHz and 60 kHz). For more details, refer to
the electrical characteristics section of the datasheets.

The LSI RC can be switched on and off using the LSION bit in the Control/status register

(RCC_CSR).

The LSIRDY flag in the Control/status register (RCC_CSR) indicates if the low-speed
internal oscillator is stable or not. At startup, the clock is not released until this bit is set by
hardware. An interrupt can be generated if enabled in the Clock interrupt register

(RCC_CIR).

Note: LSI calibration is only available on high-density and connectivity line devices.

LSI calibration

The frequency dispersion of the Low Speed Internal RC (LSI) oscillator can be calibrated to
have accurate RTC time base and/or IWDG timeout (when LSI is used as clock source for
these peripherals) with an acceptable accuracy.

This calibration is performed by measuring the LSI clock frequency with respect to TIM5
input clock (TIM5CLK). According to this measurement done at the precision of the HSE
oscillator, the software can adjust the programmable 20-bit prescaler of the RTC to get an
accurate time base or can compute accurate IWDG timeout.

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RM0034 Low-, medium- and high-density reset and clock control (RCC)

Use the following procedure to calibrate the LSI:

1. Enable TIM5 timer and configure channel4 in input capture mode

2. Set the TIM5CH4_IREMAP bit in the AFIO_MAPR register to connect the LSI clock

internally to TIM5 channel4 input capture for calibration purpose.

3. Measure the frequency of LSI clock using the TIM5 Capture/compare 4 event or

interrupt.

4. Use the measured LSI frequency to update the 20-bit prescaler of the RTC depending

on the desired time base and/or to compute the IWDG timeout.

6.2.6 System clock (SYSCLK) selection

After a system reset, the HSI oscillator is selected as system clock. When a clock source is
used directly or through the PLL as system clock, it is not possible to stop it.

A switch from one clock source to another occurs only if the target clock source is ready
(clock stable after startup delay or PLL locked). If a clock source which is not yet ready is
selected, the switch will occur when the clock source will be ready. Status bits in the Clock

control register (RCC_CR) indicate which clock(s) is (are) ready and which clock is currently

used as system clock.

6.2.7 Clock security system (CSS)

Clock Security System can be activated by software. In this case, the clock detector is
enabled after the HSE oscillator startup delay, and disabled when this oscillator is stopped.

If a failure is detected on the HSE oscillator clock, this oscillator is automatically disabled, a
clock failure event is sent to the break input of the TIM1 Advanced control timer and an
interrupt is generated to inform the software about the failure (Clock Security System
Interrupt CSSI), allowing the MCU to perform rescue operations. The CSSI is linked to the
Cortex™-M3 NMI (Non-Maskable Interrupt) exception vector.

Note: Once the CSS is enabled and if the HSE clock fails, the CSS interrupt occurs and an NMI is

automatically generated. The NMI will be executed indefinitely unless the CSS interrupt
pending bit is cleared. As a consequence, in the NMI ISR user must clear the CSS interrupt
by setting the CSSC bit in the Clock interrupt register (RCC_CIR).

If the HSE oscillator is used directly or indirectly as the system clock (indirectly means: it is
used as PLL input clock, and the PLL clock is used as system clock), a detected failure
causes a switch of the system clock to the HSI oscillator and the disabling of the external
HSE oscillator. If the HSE oscillator clock (divided or not) is the clock entry of the PLL used
as system clock when the failure occurs, the PLL is disabled too.

6.2.8 RTC clock

The RTCCLK clock source can be either the HSE/128, LSE or LSI clocks. This is selected
by programming the RTCSEL[1:0] bits in the Backup domain control register (RCC_BDCR).
This selection cannot be modified without resetting the Backup domain.

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Low-, medium- and high-density reset and clock control (RCC) RM0034

The LSE clock is in the Backup domain, whereas the HSE and LSI clocks are not.
Consequently:

● If LSE is selected as RTC clock:

– The RTC continues to work even if the V

V

supply is maintained.

BAT

● If LSI is selected as Auto-Wakeup unit (AWU) clock:

– The AWU state is not guaranteed if the V

supply is switched off, provided the

DD

supply is powered off. Refer to

DD

Section 6.2.5: LSI clock on page 78 for more details on LSI calibration.

● If the HSE clock divided by 128 is used as RTC clock:

– The RTC state is not guaranteed if the V

supply is powered off or if the internal

DD

voltage regulator is powered off (removing power from the 1.8 V domain).

6.2.9 Watchdog clock

If the Independent watchdog (IWDG) is started by either hardware option or software
access, the LSI oscillator is forced ON and cannot be disabled. After the LSI oscillator
temporization, the clock is provided to the IWDG.

6.2.10 Clock-out capability

The microcontroller clock output (MCO) capability allows the clock to be output onto the
external MCO pin. The configuration registers of the corresponding GPIO port must be
programmed in alternate function mode. One of 4 clock signals can be selected as the MCO
clock.

● SYSCLK

● HSI

● HSE

● PLL clock divided by 2

The selection is controlled by the MCO[2:0] bits of the Clock configuration register

(RCC_CFGR).

6.3 RCC registers

Refer to Section 1.1 on page 36 for a list of abbreviations used in register descriptions.

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RM0034 Low-, medium- and high-density reset and clock control (RCC)

6.3.1 Clock control register (RCC_CR)

Address offset: 0x00

Reset value: 0x0000 XX83 where X is undefined.

Access: no wait state, word, half-word and byte access

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

PLL

PLLON

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

HSICAL[7:0] HSITRIM[4:0]

rrrrrrr rrwrwrwrwrw rrw

RDY

rrw rwrwrrw

Reserved

CSS ONHSE

Res.

Bits 31:26 Reserved, always read as 0.

Bit 25 PLLRDY: PLL clock ready flag

Set by hardware to indicate that the PLL is locked.
0: PLL unlocked
1: PLL locked

Bit 24 PLLON: PLL enable

Set and cleared by software to enable PLL.
Cleared by hardware when entering Stop or Standby mode. This bit can not be reset if the

PLL clock is used as system clock or is selected to become the system clock.
0: PLL OFF
1: PLL ON

Bits 23:20 Reserved, always read as 0.

BYP

HSE
RDY

HSI

RDY

HSE

ON

HSION

Bit 19 CSSON: Clock security system enable

Set and cleared by software to enable clock detector.
0: Clock detector OFF
1: Clock detector ON if external 4-25 MHz oscillator is ready.

Bit 18 HSEBYP: External high-speed clock bypass

Set and cleared by software in debug for bypassing the oscillator with an external clock. This
bit can be written only if the external 4-25 MHz oscillator is disabled.
0: external 4-25 MHz oscillator not bypassed
1: external 4-25 MHz oscillator bypassed with external clock

Bit 17 HSERDY: External high-speed clock ready flag

Set by hardware to indicate that the external 4-25 MHz oscillator is stable. This bit needs 6
cycles of external 4-25 MHz oscillator clock to fall down after HSEON reset.

0: external 4-25 MHz oscillator not ready
1: external 4-25 MHz oscillator ready

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Low-, medium- and high-density reset and clock control (RCC) RM0034

Bit 16 HSEON: External high-speed clock enable

Set and cleared by software.
Cleared by hardware to stop the external 1-25MHz oscillator when entering in Stop or
Standby mode. This bit cannot be reset if the external 4-25 MHz oscillator is used directly or

indirectly as the system clock or is selected to become the system clock.
0: HSE oscillator OFF
1: HSE oscillator ON

Bits 15:8 HSICAL[7:0]: Internal high-speed clock calibration

These bits are initialized automatically at startup.

Bits 7:3 HSITRIM[4:0]: Internal high-speed clock trimming

These bits provide an additional user-programmable trimming value that is added to the
HSICAL[7:0] bits. It can be programmed to adjust to variations in voltage and temperature
that influence the frequency of the internal HSI RC.

The default value is 16, which, when added to the HSICAL value, should trim the HSI to 8
MHz ± 1%. The trimming step (F
steps.

Bit 2 Reserved, always read as 0.

Bit 1 HSIRDY: Internal high-speed clock ready flag

Set by hardware to indicate that internal 8 MHz RC oscillator is stable. After the HSION bit is
cleared, HSIRDY goes low after 6 internal 8 MHz RC oscillator clock cycles.

0: internal 8 MHz RC oscillator not ready
1: internal 8 MHz RC oscillator ready

) is around 40 kHz between two consecutive HSICAL

hsitrim

Bit 0 HSION: Internal high-speed clock enable

Set and cleared by software.
Set by hardware to force the internal 8 MHz RC oscillator ON when leaving Stop or Standby
mode or in case of failure of the external 4-25 MHz oscillator used directly or indirectly as

system clock. This bit cannot be reset if the internal 8 MHz RC is used directly or indirectly
as system clock or is selected to become the system clock.

0: internal 8 MHz RC oscillator OFF
1: internal 8 MHz RC oscillator ON

6.3.2 Clock configuration register (RCC_CFGR)

Address offset: 0x04

Reset value: 0x0000 0000

Access: 0 ≤ wait state ≤ 2, word, half-word and byte access

1 or 2 wait states inserted only if the access occurs during clock source switch.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

PLL

XTPRE

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ADC PRE[1:0] PPRE2[2:0] PPRE1[2:0] HPRE[3:0] SWS[1:0] SW[1:0]

rw rw rw rw rw rw rw rw rw rw rw rw r r rw rw

MCO[2:0]

rw rw rw rw rw rw rw rw rw rw

Res.

USB
PRE

PLLMUL[3:0]

Bits 31:27 Reserved, always read as 0.

PLL

SRC

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RM0034 Low-, medium- and high-density reset and clock control (RCC)

Bits 26:24 MCO: Microcontroller clock output

Set and cleared by software.
0xx: No clock
100: System clock (SYSCLK) selected
101: HSI clock selected
110: HSE clock selected
111: PLL clock divided by 2 selected

Note: This clock output may have some truncated cycles at startup or during MCO clock

source switching.
When the System Clock is selected to output to the MCO pin, make sure that this clock

does not exceed 50 MHz (the maximum I/O speed).

Bit 22 USBPRE: USB prescaler

Set and cleared by software to generate 48 MHz USB clock. This bit must be valid before
enabling the USB clock in the RCC_APB1ENR register. This bit can’t be reset if the USB
clock is enabled.
0: PLL clock is divided by 1.5
1: PLL clock is not divided

Bits 21:18 PLLMUL: PLL multiplication factor

These bits are written by software to define the PLL multiplication factor. These bits can be
written only when PLL is disabled.
Caution: The PLL output frequency must not exceed 72 MHz.
0000: PLL input clock x 2
0001: PLL input clock x 3
0010: PLL input clock x 4
0011: PLL input clock x 5
0100: PLL input clock x 6
0101: PLL input clock x 7
0110: PLL input clock x 8
0111: PLL input clock x 9
1000: PLL input clock x 10
1001: PLL input clock x 11
1010: PLL input clock x 12
1011: PLL input clock x 13
1100: PLL input clock x 14
1101: PLL input clock x 15
1110: PLL input clock x 16
1111: PLL input clock x 16

Bit 17 PLLXTPRE: HSE divider for PLL entry

Set and cleared by software to divide HSE before PLL entry. This bit can be written only
when PLL is disabled.

0: HSE clock not divided
1: HSE clock divided by 2

Bit 16 PLLSRC: PLL entry clock source

Set and cleared by software to select PLL clock source. This bit can be written only when
PLL is disabled.

0: HSI oscillator clock / 2 selected as PLL input clock
1: HSE oscillator clock selected as PLL input clock

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Low-, medium- and high-density reset and clock control (RCC) RM0034

Bits 14:14 ADCPRE: ADC prescaler

Set and cleared by software to select the frequency of the clock to the ADCs.
00: PLCK2 divided by 2
01: PLCK2 divided by 4
10: PLCK2 divided by 6
11: PLCK2 divided by 8

Bits 13:11 PPRE2: APB high-speed prescaler (APB2)

Set and cleared by software to control the division factor of the APB high-speed clock
(PCLK2).
0xx: HCLK not divided
100: HCLK divided by 2
101: HCLK divided by 4
110: HCLK divided by 8
111: HCLK divided by 16

Bits 10:8 PPRE1: APB low-speed prescaler (APB1)

Set and cleared by software to control the division factor of the APB low-speed clock
(PCLK1).

Warning: the software has to set correctly these bits to not exceed 36 MHz on this domain.
0xx: HCLK not divided
100: HCLK divided by 2
101: HCLK divided by 4
110: HCLK divided by 8
111: HCLK divided by 16

Bits 7:4 HPRE: AHB prescaler

Set and cleared by software to control the division factor of the AHB clock.
0xxx: SYSCLK not divided
1000: SYSCLK divided by 2
1001: SYSCLK divided by 4
1010: SYSCLK divided by 8
1011: SYSCLK divided by 16
1100: SYSCLK divided by 64
1101: SYSCLK divided by 128
1110: SYSCLK divided by 256
1111: SYSCLK divided by 512

Note: The prefetch buffer must be kept on when using a prescaler different from 1 on the

AHB clock. Refer to Reading Flash memory on page 45 section for more details.

Bits 3:2 SWS: System clock switch status

Set and cleared by hardware to indicate which clock source is used as system clock.
00: HSI oscillator used as system clock
01: HSE oscillator used as system clock
10: PLL used as system clock
11: not applicable

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RM0034 Low-, medium- and high-density reset and clock control (RCC)

Bits 1:0 SW: System clock switch

Set and cleared by software to select SYSCLK source.
Set by hardware to force HSI selection when leaving Stop and Standby mode or in case of
failure of the HSE oscillator used directly or indirectly as system clock (if the Clock Security

System is enabled).
00: HSI selected as system clock
01: HSE selected as system clock
10: PLL selected as system clock
11: not allowed

6.3.3 Clock interrupt register (RCC_CIR)

Address offset: 0x08

Reset value: 0x0000 0000

Access: no wait state, word, half-word and byte access

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

PLL

LSI

RDYIE

CSSC

CSSF

Reserved

wwwwww

Reserved

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PLL

HSE

HSI

LSE

RDYIE

Reserved

RDYIE

RDYIE

RDYIE

rw rw rw rw rw r r r r r r

RDYC

RDYF

PLL

HSE

RDYC

HSE

RDYF

Bits 31:24 Reserved, always read as 0.

Bit 23 CSSC: Clock security system interrupt clear

This bit is set by software to clear the CSSF flag.
0: No effect
1: Clear CSSF flag

Bits 22:21 Reserved, always read as 0.

Bit 20 PLLRDYC: PLL ready interrupt clear

This bit is set by software to clear the PLLRDYF flag.
0: No effect
1: PLLRDYF cleared

Bit 19 HSERDYC: HSE ready interrupt clear

This bit is set by software to clear the HSERDYF flag.
0: No effect
1: HSERDYF cleared

Bit 18 HSIRDYC: HSI ready interrupt clear

This bit is set software to clear the HSIRDYF flag.
0: No effect
1: HSIRDYF cleared

Bit 17 LSERDYC: LSE ready interrupt clear

This bit is set by software to clear the LSERDYF flag.
0: No effect
1: LSERDYF cleared

HSI

RDYC

HSI

RDYF

LSE

RDYC

LSE

RDYF

LSI

RDYC

LSI

RDYF

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Low-, medium- and high-density reset and clock control (RCC) RM0034

Bit 16 LSIRDYC: LSI ready interrupt clear

This bit is set by software to clear the LSIRDYF flag.
0: No effect
1: LSIRDYF cleared

Bits 15:13 Reserved, always read as 0.

Bit 12 PLLRDYIE: PLL ready interrupt enable

Set and cleared by software to enable/disable interrupt caused by PLL lock.
0: PLL lock interrupt disabled
1: PLL lock interrupt enabled

Bit 11 HSERDYIE: HSE ready interrupt enable

Set and cleared by software to enable/disable interrupt caused by the external 4-25 MHz
oscillator stabilization.

0: HSE ready interrupt disabled
1: HSE ready interrupt enabled

Bit 10 HSIRDYIE: HSI ready interrupt enable

Set and cleared by software to enable/disable interrupt caused by the internal 8 MHz RC
oscillator stabilization.
0: HSI ready interrupt disabled
1: HSI ready interrupt enabled

Bit 9 LSERDYIE: LSE ready interrupt enable

Set and cleared by software to enable/disable interrupt caused by the external 32 kHz
oscillator stabilization.

0: LSE ready interrupt disabled
1: LSE ready interrupt enabled

Bit 8 LSIRDYIE: LSI ready interrupt enable

Set and cleared by software to enable/disable interrupt caused by internal RC 40 kHz
oscillator stabilization.

0: LSI ready interrupt disabled
1: LSI ready interrupt enabled

Bit 7 CSSF: Clock security system interrupt flag

Set by hardware when a failure is detected in the external 4-25 MHz oscillator.
Cleared by software setting the CSSC bit.
0: No clock security interrupt caused by HSE clock failure
1: Clock security interrupt caused by HSE clock failure

Bits 6:5 Reserved, always read as 0.

Bit 4 PLLRDYF: PLL ready interrupt flag

Set by hardware when the PLL locks and PLLRDYDIE is set.
Cleared by software setting the PLLRDYC bit.
0: No clock ready interrupt caused by PLL lock
1: Clock ready interrupt caused by PLL lock

Bit3 HSERDYF: HSE ready interrupt flag

Set by hardware when External Low Speed clock becomes stable and HSERDYDIE is set.
Cleared by software setting the HSERDYC bit.
0: No clock ready interrupt caused by the external 4-25 MHz oscillator
1: Clock ready interrupt caused by the external 4-25 MHz oscillator

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RM0034 Low-, medium- and high-density reset and clock control (RCC)

Bit 2 HSIRDYF: HSI ready interrupt flag

Set by hardware when the Internal High Speed clock becomes stable and HSIRDYDIE is
set.
Cleared by software setting the HSIRDYC bit.
0: No clock ready interrupt caused by the internal 8 MHz RC oscillator
1: Clock ready interrupt caused by the internal 8 MHz RC oscillator

Bit 1 LSERDYF: LSE ready interrupt flag

Set by hardware when the External Low Speed clock becomes stable and LSERDYDIE is
set.

Cleared by software setting the LSERDYC bit.
0: No clock ready interrupt caused by the external 32 kHz oscillator
1: Clock ready interrupt caused by the external 32 kHz oscillator

Bit 0 LSIRDYF: LSI ready interrupt flag

Set by hardware when the internal low speed clock becomes stable and LSIRDYDIE is set.
Cleared by software setting the LSIRDYC bit.
0: No clock ready interrupt caused by the internal RC 40 kHz oscillator
1: Clock ready interrupt caused by the internal RC 40 kHz oscillator

6.3.4 APB2 peripheral reset register (RCC_APB2RSTR)

Address offset: 0x0C

Reset value: 0x00000 0000

Access: no wait state, word, half-word and byte access

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

1514131211109 8 76543210

ADC3

USART1

RST

rw rw rw rw rw rw rw rw rw rw rw rw rw rw Res. rw

TIM8

SPI1

TIM1

ADC2

RST

RST

RST

RST

RST

ADC1

RST

Bits 31:16 Reserved, always read as 0.

Bit 15 ADC3RST: ADC3 interface reset

Set and cleared by software.
0: No effect
1: Reset ADC3 interface

Bit 14 USART1RST: USART1 reset

Set and cleared by software.
0: No effect
1: Reset USART1

Bit 13 TIM8RST: TIM8 timer reset

Set and cleared by software.
0: No effect
1: Reset TIM8 timer

IOPG

RST

IOPF

RST

IOPE

RST

IOPD

RST

IOPC

RST

IOPB

RST

IOPA

RST

Res.

AFIO

RST

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Low-, medium- and high-density reset and clock control (RCC) RM0034

Bit 12 SPI1RST: SPI 1 reset

Set and cleared by software.
0: No effect
1: Reset SPI 1

Bit 11 TIM1RST: TIM1 timer reset

Set and cleared by software.
0: No effect
1: Reset TIM1 timer

Bit 10 ADC2RST: ADC 2 interface reset

Set and cleared by software.
0: No effect
1: Reset ADC 2 interface

Bit 9 ADC1RST: ADC 1 interface reset

Set and cleared by software.
0: No effect
1: Reset ADC 1 interface

Bit 8 IOPGRST: IO port G reset

Set and cleared by software.
0: No effect
1: Reset IO port G

Bit 7 IOPFRST: IO port F reset

Set and cleared by software.
0: No effect
1: Reset IO port F

Bit 6 IOPERST: IO port E reset

Set and cleared by software.
0: No effect
1: Reset IO port E

Bit 5 IOPDRST: IO port D reset

Set and cleared by software.
0: No effect
1: Reset I/O port D

Bit 4 IOPCRST: IO port C reset

Set and cleared by software.
0: No effect
1: Reset I/O port C

Bit 3 IOPBRST: IO port B reset

Set and cleared by software.
0: No effect
1: Reset I/O port B

Bit 2 IOPARST: I/O port A reset

Set and cleared by software.
0: No effect
1: Reset I/O port A

Bit 1 Reserved, always read as 0.

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RM0034 Low-, medium- and high-density reset and clock control (RCC)

Bit 0 AFIORST: Alternate function I/O reset

Set and cleared by software.
0: No effect
1: Reset Alternate Function

6.3.5 APB1 peripheral reset register (RCC_APB1RSTR)

Address offset: 0x10

Reset value: 0x0000 0000

Access: no wait state, word, half-word and byte access

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

UART

UART

USART

DAC

PWR

RST

BKP
RST

WWD
GRST

SPI2
RST

RST

rw rw rw rw rw rw rw rw rw rw rw

Reserved

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

SPI3
RST

rw rw rw rw rw rw rw rw rw

Res.

CAN
RST

Res.

Reserved

USB
RST

I2C2
RST

I2C1

RST

TIM7

RST

5

RST

TIM6

RST

4

RST

TIM5
RST

Bits 31:30 Reserved, always read as 0.

Bit 29 DACRST: DAC interface reset

Set and cleared by software.
0: No effect
1: Reset DAC interface

Bit 28 PWRRST: Power interface reset

Set and cleared by software.
0: No effect
1: Reset power interface

Bit 27 BKPRST: Backup interface reset

Set and cleared by software.
0: No effect
1: Reset backup interface

Bit 26 Reserved, always read as 0.

Bit 25 CANRST: CAN reset

Set and cleared by software.
0: No effect
1: Reset CAN

Bit 24 Reserved, always read as 0.

3

RST

TIM4

RST

USART

2

RST

TIM3

RST

Res.

TIM2
RST

Bit 23 USBRST: USB reset

Set and cleared by software.
0: No effect
1: Reset USB

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Low-, medium- and high-density reset and clock control (RCC) RM0034

Bit 22 I2C2RST: I2C 2 reset

Set and cleared by software.
0: No effect
1: Reset I2C 2

Bit 21 I2C1RST: I2C 1 reset

Set and cleared by software.
0: No effect
1: Reset I2C 1

Bit 20 UART5RST: USART 5 reset

Set and cleared by software.
0: No effect
1: Reset USART 5

Bit 19 UART4RST: USART 4 reset

Set and cleared by software.
0: No effect
1: Reset USART 4

Bit 18 USART3RST: USART 3 reset

Set and cleared by software.
0: No effect
1: Reset USART 3

Bit 17 USART2RST: USART 2 reset

Set and cleared by software.
0: No effect
1: Reset USART 2

Bits 16 Reserved, always read as 0.

Bit 15 SPI3RST: SPI 3 reset

Set and cleared by software.
0: No effect
1: Reset SPI 3

Bit 14 SPI2RST: SPI 2 reset

Set and cleared by software.
0: No effect
1: Reset SPI 2

Bits 13:12 Reserved, always read as 0.

Bit 11 WWDGRST: Window watchdog reset

Set and cleared by software.
0: No effect
1: Reset window watchdog

Bits 10:6 Reserved, always read as 0.

Bit 5 TIM7RST: Timer 7 reset

Set and cleared by software.
0: No effect
1: Reset timer 7

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RM0034 Low-, medium- and high-density reset and clock control (RCC)

Bit 4 TIM6RST: Timer 6 reset

Set and cleared by software.
0: No effect
1: Reset timer 6

Bit 3 TIM5RST: Timer 5 reset

Set and cleared by software.
0: No effect
1: Reset timer 5

Bit 2 TIM4RST: Timer 4 reset

Set and cleared by software.
0: No effect
1: Reset timer 4

Bit 1 TIM3RST: Timer 3 reset

Set and cleared by software.
0: No effect
1: Reset timer 3

Bit 0 TIM2RST: Timer 2 reset

Set and cleared by software.
0: No effect
1: Reset timer 2

6.3.6 AHB peripheral clock enable register (RCC_AHBENR)

Address offset: 0x14

Reset value: 0x0000 0014

Access: no wait state, word, half-word and byte access

Note: When the peripheral clock is not active, the peripheral register values may not be readable

by software and the returned value is always 0x0.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

SDIO

Reserved

EN

Res.

rw rw rw rw rw rw rw

Bits 31:11 Reserved, always read as 0.

Bit 10 SDIOEN: SDIO clock enable

Set and cleared by software.
0: SDIO clock disabled
1: SDIO clock enabled

FSMC

EN

Res.

CRCE

N

Res.

FLITF

EN

SRAMENDMA2ENDMA1

Res.

EN

Bits 9 Reserved, always read as 0.

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Bit 8 FSMCEN: FSMC clock enable

Set and cleared by software.
0: FSMC clock disabled
1: FSMC clock enabled

Bit 7 Reserved, always read as 0.

Bit 6 CRCEN: CRC clock enable

Set and cleared by software.
0: CRC clock disabled
1: CRC clock enabled

Bit 5 Reserved, always read as 0.

Bit 4 FLITFEN: FLITF clock enable

Set and cleared by software to disable/enable FLITF clock during sleep mode.
0: FLITF clock disabled during Sleep mode
1: FLITF clock enabled during Sleep mode

Bit 3 Reserved, always read as 0.

Bit 2 SRAMEN: SRAM interface clock enable

Set and cleared by software to disable/enable SRAM interface clock during Sleep mode.
0: SRAM interface clock disabled during Sleep mode.
1: SRAM interface clock enabled during Sleep mode

Bit 1 DMA2EN: DMA2 clock enable

Set and cleared by software.
0: DMA2 clock disabled
1: DMA2 clock enabled

Bit 0 DMA1EN: DMA1 clock enable

Set and cleared by software.
0: DMA1 clock disabled
1: DMA1 clock enabled

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RM0034 Low-, medium- and high-density reset and clock control (RCC)

6.3.7 APB2 peripheral clock enable register (RCC_APB2ENR)

Address: 0x18

Reset value: 0x0000 0000

Access: word, half-word and byte access

No wait states, except if the access occurs while an access to a peripheral in the APB2
domain is on going. In this case, wait states are inserted until the access to APB2 peripheral
is finished.

Note: When the peripheral clock is not active, the peripheral register values may not be readable

by software and the returned value is always 0x0.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ADC3

EN

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

TIM8ENSPI1ENTIM1ENADC2ENADC1ENIOPGENIOPFENIOPEENIOPDENIOPCENIOPBENIOPA

USAR

T1EN

Bits 31:16 Reserved, always read as 0.

Bit 15 ADC3EN: ADC 3 interface clock enable

Set and cleared by software.
0: ADC 3 interface clock disabled
1: ADC 3 interface clock enabled

Bit 14 USART1EN: USART1 clock enable

Set and cleared by software.
0: USART1 clock disabled
1: USART1 clock enabled

Bit 13 TIM8EN: TIM8 Timer clock enable

Set and cleared by software.
0: TIM8 timer clock disabled
1: TIM8 timer clock enabled

EN

Res.

AFIO

EN

Bit 12 SPI1EN: SPI 1 clock enable

Set and cleared by software.
0: SPI 1 clock disabled
1: SPI 1 clock enabled

Bit 11 TIM1EN: TIM1 Timer clock enable

Set and cleared by software.
0: TIM1 timer clock disabled
1: TIM1 timer clock enabled

Bit 10 ADC2EN: ADC 2 interface clock enable

Set and cleared by software.
0: ADC 2 interface clock disabled
1: ADC 2 interface clock enabled

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Low-, medium- and high-density reset and clock control (RCC) RM0034

Bit 9 ADC1EN: ADC 1 interface clock enable

Set and cleared by software.
0: ADC 1 interface disabled
1: ADC 1 interface clock enabled

Bit 8 IOPGEN: I/O port G clock enable

Set and cleared by software.
0: I/O port G clock disabled
1: I/O port G clock enabled

Bit 7 IOPFEN: I/O port F clock enable

Set and cleared by software.
0: I/O port F clock disabled
1: I/O port F clock enabled

Bit 6 IOPEEN: I/O port E clock enable

Set and cleared by software.
0: I/O port E clock disabled
1: I/O port E clock enabled

Bit 5 IOPDEN: I/O port D clock enable

Set and cleared by software.
0: I/O port D clock disabled
1: I/O port D clock enabled

Bit 4 IOPCEN: I/O port C clock enable

Set and cleared by software.
0: I/O port C clock disabled
1:I/O port C clock enabled

Bit 3 IOPBEN: I/O port B clock enable

Set and cleared by software.
0: I/O port B clock disabled
1:I/O port B clock enabled

Bit 2 IOPAEN: I/O port A clock enable

Set and cleared by software.
0: I/O port A clock disabled
1:I/O port A clock enabled

Bit 1 Reserved, always read as 0.

Bit 0 AFIOEN: Alternate function I/O clock enable

Set and cleared by software.
0: Alternate Function I/O clock disabled
1:Alternate Function I/O clock enabled

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RM0034 Low-, medium- and high-density reset and clock control (RCC)

6.3.8 APB1 peripheral clock enable register (RCC_APB1ENR)

Address: 0x1C

Reset value: 0x0000 0000

Access: word, half-word and byte access

No wait state, except if the access occurs while an access to a peripheral on APB1 domain
is on going. In this case, wait states are inserted until this access to APB1 peripheral is
finished.

Note: When the peripheral clock is not active, the peripheral register values may not be readable

by software and the returned value is always 0x0.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Res. rw rw rw Res. rw Res. rw rw rw rw rw rw rw Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

SPI3ENSPI2

rw rw Res. rw Res. rw rw rw rw rw rw

DACENPWRENBKP

Reserved

EN

EN

WWD

GEN

Res.

CAN

EN

Reserved

USBENI2C2ENI2C1ENUART5ENUART4ENUSART

Res.

TIM7ENTIM6ENTIM5ENTIM4ENTIM3ENTIM2

Bits 31:30 Reserved, always read as 0.

Bit 29 DACEN: DAC interface clock enable

Set and cleared by software.
0: DAC interface clock disabled
1: DAC interface clock enable

Bit 28 PWREN: Power interface clock enable

Set and cleared by software.
0: Power interface clock disabled
1: Power interface clock enable

Bit 27 BKPEN: Backup interface clock enable

Set and cleared by software.
0: Backup interface clock disabled
1: Backup interface clock enabled

Bit 26 Reserved, always read as 0.

Bit 25 CANEN: CAN clock enable

Set and cleared by software.
0: CAN clock disabled
1: CAN clock enabled

Bit 24 Reserved, always read as 0.

3EN

USART

2EN

Res.

EN

Bit 23 USBEN: USB clock enable

Set and cleared by software.
0: USB clock disabled
1: USB clock enabled

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Low-, medium- and high-density reset and clock control (RCC) RM0034

Bit 22 I2C2EN: I2C 2 clock enable

Set and cleared by software.
0: I2C 2 clock disabled
1: I2C 2 clock enabled

Bit 21 I2C1EN: I2C 1 clock enable

Set and cleared by software.
0: I2C 1 clock disabled
1: I2C 1 clock enabled

Bit 20 UART 5EN: USART 5 clock enable

Set and cleared by software.
0: USART 5 clock disabled
1: USART 5 clock enabled

Bit 19 UART 4EN: USART 4 clock enable

Set and cleared by software.
0: USART 4 clock disabled
1: USART 4 clock enabled

Bit 18 USART3EN: USART 3 clock enable

Set and cleared by software.
0: USART 3 clock disabled
1: USART 3 clock enabled

Bit 17 USART2EN: USART 2 clock enable

Set and cleared by software.
0: USART 2 clock disabled
1: USART 2 clock enabled

Bits 16 Reserved, always read as 0.

Bit 15 SPI3EN: SPI 3 clock enable

Set and cleared by software.
0: SPI 3 clock disabled
1: SPI 3 clock enabled

Bit 14 SPI2EN: SPI 2 clock enable

Set and cleared by software.
0: SPI 2 clock disabled
1: SPI 2 clock enabled

Bits 13:12 Reserved, always read as 0.

Bit 11 WWDGEN: Window watchdog clock enable

Set and cleared by software.
0: Window watchdog clock disabled
1: Window watchdog clock enabled

Bits 10:6 Reserved, always read as 0.

Bit 5 TIM7EN: Timer 7 clock enable

Set and cleared by software.
0: Timer 7 clock disabled
1: Timer 7 clock enabled

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RM0034 Low-, medium- and high-density reset and clock control (RCC)

Bit 4 TIM6EN: Timer 6 clock enable

Set and cleared by software.
0: Timer 6 clock disabled
1: Timer 6 clock enabled

Bit 3 TIM5EN: Timer 5 clock enable

Set and cleared by software.
0: Timer 5 clock disabled
1: Timer 5 clock enabled

Bit 2 TIM4EN: Timer 4 clock enable

Set and cleared by software.
0: Timer 4 clock disabled
1: Timer 4 clock enabled

Bit 1 TIM3EN: Timer 3 clock enable

Set and cleared by software.
0: Timer 3 clock disabled
1: Timer 3 clock enabled

Bit 0 TIM2EN: Timer 2 clock enable

Set and cleared by software.
0: Timer 2 clock disabled
1: Timer 2 clock enabled

6.3.9 Backup domain control register (RCC_BDCR)

Address offset: 0x20
Reset value: 0x0000 0000, reset by Backup domain Reset.
Access: 0 ≤ wait state ≤ 3, word, half-word and byte access
Wait states are inserted in case of successive accesses to this register.

Note: LSEON, LSEBYP, RTCSEL and RTCEN bits of the Backup domain control register

(RCC_BDCR) are in the Backup domain. As a result, after Reset, these bits are write-

protected and the DBP bit in the Power control register (PWR_CR) has to be set before
these can be modified. Refer to Section 5 on page 64 for further information. These bits are
only reset after a Backup domain Reset (see Section 6.1.3: Backup domain reset). Any
internal or external Reset will not have any effect on these bits.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RTC

EN

rw rw rw rw r rw

Reserved

RTCSEL[1:0]

Reserved

Bits 31:17 Reserved, always read as 0.

Bit 16 BDRST: Backup domain software reset

Set and cleared by software.
0: Reset not activated
1: Resets the entire Backup domain

LSE
BYP

LSE
RDY

BDRST

rw

LSEON

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Low-, medium- and high-density reset and clock control (RCC) RM0034

Bit 15 RTCEN: RTC clock enable

Set and cleared by software.
0: RTC clock disabled
1: RTC clock enabled

Bits 14:10 Reserved, always read as 0.

Bits 9:8 RTCSEL[1:0]: RTC clock source selection

Set by software to select the clock source for the RTC. Once the RTC clock source has been
selected, it cannot be changed anymore unless the Backup domain is reset. The BDRST bit
can be used to reset them.

00: No clock
01: LSE oscillator clock used as RTC clock
10: LSI oscillator clock used as RTC clock
11: HSE oscillator clock divided by 128 used as RTC clock

Bits 7:3 Reserved, always read as 0.

Bit 2 LSEBYP: External low-speed oscillator bypass

Set and cleared by software to bypass oscillator in debug mode. This bit can be written only
when the external 32 kHz oscillator is disabled.

0: LSE oscillator not bypassed
1: LSE oscillator bypassed

Bit 1 LSERDY: External low-speed oscillator ready

Set and cleared by hardware to indicate when the external 32 kHz oscillator is stable. After
the LSEON bit is cleared, LSERDY goes low after 6 external low-speed oscillator clock
cycles.
0: External 32 kHz oscillator not ready
1: External 32 kHz oscillator ready

Bit 0 LSEON: External low-speed oscillator enable

Set and cleared by software.
0: External 32 kHz oscillator OFF
1: External 32 kHz oscillator ON

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RM0034 Low-, medium- and high-density reset and clock control (RCC)

6.3.10 Control/status register (RCC_CSR)

Address: 0x24

Reset value: 0x0C00 0000, reset by system Reset, except reset flags by power Reset only.

Access: 0 ≤ wait state ≤ 3, word, half-word and byte access

Wait states are inserted in case of successive accesses to this register.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

LPWR

WWDG

RSTF

rw rw rw rw rw rw rw

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RSTF

IWDG

RSTF

SFT

RSTF

POR

RSTF

PIN

RSTF

Bit 31 LPWRRSTF: Low-power reset flag

Set by hardware when a Low-power management reset occurs.
Cleared by writing to the RMVF bit.

0: No Low-power management reset occurred
1: Low-power management reset occurred
For further information on Low-power management reset, refer to Section : Low-power

management reset.

Res.

Reserved

RMVF

Reserved

LSI

LSION

RDY

rrw

Bit 30 WWDGRSTF: Window watchdog reset flag

Set by hardware when a window watchdog reset occurs.
Cleared by writing to the RMVF bit.
0: No window watchdog reset occurred
1: Window watchdog reset occurred

Bit 29 IWDGRSTF: Independent watchdog reset flag

Set by hardware when an independent watchdog reset from V
Cleared by writing to the RMVF bit.

0: No watchdog reset occurred
1: Watchdog reset occurred

Bit 28 SFTRSTF: Software reset flag

Set by hardware when a software reset occurs.
Cleared by writing to the RMVF bit.

0: No software reset occurred
1: Software reset occurred

Bit 27 PORRSTF: POR/PDR reset flag

Set by hardware when a POR/PDR reset occurs.
Cleared by writing to the RMVF bit.
0: No POR/PDR reset occurred
1: POR/PDR reset occurred

Bit 26 PINRSTF: PIN reset flag

Set by hardware when a reset from the NRST pin occurs.
Cleared by writing to the RMVF bit.
0: No reset from NRST pin occurred
1: Reset from NRST pin occurred

domain occurs.

DD

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Low-, medium- and high-density reset and clock control (RCC) RM0034

Bit 25 Reserved, always read as 0.

Bit 24 RMVF: Remove reset flag

Set by software to clear the reset flags.
0: No effect
1: Clear the reset flags

Bits 23:2 Reserved, always read as 0.

Bit 1 LSIRDY: Internal low-speed oscillator ready

Set and cleared by hardware to indicate when the internal RC 40 kHz oscillator is stable.
After the LSION bit is cleared, LSIRDY goes low after 3 internal RC 40 kHz oscillator clock
cycles.

0: Internal RC 40 kHz oscillator not ready
1: Internal RC 40 kHz oscillator ready

Bit 0 LSION: Internal low-speed oscillator enable

Set and cleared by software.
0: Internal RC 40 kHz oscillator OFF
1: Internal RC 40 kHz oscillator ON

6.3.11 RCC register map

The following table gives the RCC register map and the reset values.

Table 15. RCC - register map and reset values

Offset Register

313029282726252423222120191817161514131211

987654321

10

0

0x000

0x004

0x008

0x00C

0x010

0x014

RCC_CR

Reset value 00 00000000000010000 11

RCC_CFGR

Reset value 000 00000000000000000000000

RCC_CIR

Reset value 0 00000 000000 00000

RCC_APB2RSTR

Reset value 00000000000000 0

RCC_APB1RSTR

Reset value 000 0 0000000 00 0 000000

RCC_AHBENR

Reset value 000 1 100

Reser

ved

Reserved

Reserved

Reserved

DACRST

MCO [2:0]

BKPRST

PWRRST

Reserved

PLL ON

PLL RDY

Reserved

CANRST

Reserved

Reserved

PLLMUL[3:0]

USBPRE

Reserved

CSSC

Reserved

USBRST

I2C2RST

Reserved

PLLRDYC

I2C1RST

UART5RST

CSSON

HSERDYC

UART4RST

HSEBYP

HSERDY

PLLXTPRE

HSIRDYC

LSERDYC

USART3RST

USART2RST

HSEON

PLLSRC

LSIRDYC

Reserved

HSICAL[7:0] HSITRIM[4:0]

ADC
PRE

[1:0]

Reserved

ADC3RST

USART1RST

SPI3RST

SPI2RST

PPRE2

TIM8RST

[2:0]

Reserved

PLLRDYIE

SPI1RST

PPRE1

[2:0]

HSIRDYIE

HSERDYIE

TIM1RST

ADC2RST

Reserved

WWDGRST

SDIOEN

LSIRDYIE

LSERDYIE

IOPGRST

ADC1RST

FSMCEN

Reserved

HPRE[3:0]

CSSF

Reserved

IOPFRST

IOPERST

IOPDRST

TM7RST

CRCEN

Reserved

Reserved

SWS

[1:0]

PLLRDYF

HSERDYF

IOPBRST

IOPCRST

TM6RST

TM5RST

FLITFEN

Reserved

Reserved

HSIRDYF

IOPARST

TIM4RST

SRAMEN

HSIRDY

SW

[1:0]

LSERDYF

Reserved

TIM3RST

DM2AEN

HSION

LSIRDYF

AFIORST

TIM2RST

DM1AEN

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