ST STM32F103x6, STM32F103x8, STM32F103xB User Manual

STM32F103x6

STM32F103x8 STM32F103xB

Performance line, ARM-based 32-bit MCU with Flash, USB, CAN,

seven 16-bit timers, two ADCs and nine communication interfaces

Preliminary Data

Features

■ Core: ARM 32-bit Cortex™-M3 CPU

– 72 MHz, 90 DMIPS with 1.25 DMIPS/MHz
– Single-cycle multiplication and hardware

division

– Nested interrupt controller with 43

maskable interrupt channels

– Interrupt processing (down to 6 CPU

cycles) with tail chaining

■ Memories

– 32-to -1 2 8 Kbytes of Flash me m ory
– 6-to- 20 Kbytes of SRAM

■ Clock, reset and supply management

– 2.0 to 3.6 V application supply and I/Os
– POR, PDR, and programmable voltage

detector (PVD)
– 4-to-16 MHz quartz oscillator
– Internal 8 MHz factory-trimmed RC
– Internal 32 kHz RC
– PLL for CPU clock
– Dedicated 32 kHz oscillator for RTC with

calibration

■ Low power

– Sleep, Stop and Standby modes
–V

■ 2 x 12-bit, 1 µs A/D converters (16-channel)

supply for RTC and backup registers

BAT

– Conversion range: 0 to 3.6 V
– Dual-sample and hold capability
– Synchronizable with advanced control timer
– Temperature sensor

■ DMA

– 7-channel DMA controller
– Peripherals supported: timers, ADC, SPIs,

2

I

Cs and USARTs

LQFP48

7 x 7 mm

■ Debug mode

LQFP100

14 x 14 mm

– Serial wire debug (SWD) & JTAG int erfaces

■ Up to 80 fast I/O ports

– 32/49/80 5 V-tolerant I/Os
– All mappable on 16 external interrupt

vectors

– Atomi c re ad /m o dif y/write operations

■ Up to 7 timers

– Up to three 16-bit timers, each with up to 4

IC/OC/PWM or pulse counter

– 16-bit, 6-channel advanced control timer:

up to 6 channels for PWM output
Dead time generation and emergency

stop

– 2 x 16-bit watchdog timers (Independent

and Window)

– SysTick timer: a 24-bit downcounter

■ Up to 9 communication interfaces

– Up to 2 x I

2

C interfaces (SMBus/PMBus)

– Up to 3 USARTs (ISO 7816 interface, LIN,

IrDA capability, modem control)
– Up to 2 SPIs (18 Mbit/s)
– CAN interface (2.0B Active)
– USB 2.0 full speed interface

Table 1. Device summary

Reference Root part number

STM32F103x6 STM32F103C6, STM32F103R6
STM32F103x8
STM32F103xB STM32F103RB STM32F103VB

STM32F103C8, STM32F103R8
STM32F103V8

LQFP64

10 x 10 mm

BGA100

10 x 10 mm

July 2007 Rev 2 1/67

This is preliminary information on a new product now in development or undergoing ev aluation. Details are subject to
change without notice.

www.st.com

1

STM32F103xx Description

2.1 Device overview

Table 2. Device features and peripheral counts (STM32F103xx performance line)

Peripheral

Flash - Kbytes 32 64 32 64 128 64 128
SRAM - Kbytes 10 20 10 20 20

General purpose 232 3 3
Advanced Control 111

Timers

SPI 121 2 2

2

I

C 121 2 2
USART 232 3 3
USB 111 1 1

Communication

CAN 1 1 1 1 1

GPIOs 32 49 80

STM32F103Cx STM32F103Rx STM32F103Vx

12-bit synchronized ADC
Number of channels

2

10 channels

2

16 channels

CPU frequency 72 MHz
Operating voltage 2.0 to 3.6 V
Operating temperature -40 to +85 °C / -40 to +105 °C

Packages LQFP48 LQFP64

LQFP100,

BGA100

7/67

Description STM32F103xx

Figure 1. STM32F103xx performance line block diagram

JNTRST

JTDI

JTCK/SWCLK

JTMS/SWDIO

JTDO
as AF

NRST

VDDA

VSSA

80AF

PA[15:0]

PB[15:0]

PC[15:0]

PD[15:0]

PE[15:0]

4 Channels
3 compl. Channels

Brk input

MOSI,MISO,

SCK,NSS as AF

RX,TX, CTS, RTS,
SmartCard as AF

16AF

V

REF+

V

REF-

JTAG & SWD

CORTEX M3 CPU

F

: 72 MHz

max

NVIC

GP DMA

7 channels

@VDDA

SUPPLY

SUPERVISION

POR / PDR

PVD

EXTI

WAKEUP

GPIOA

GPIOB

GPIOC

GPIOD

GPIOE

TIM1

SPI1

USART1

@VDDA

12bit ADC1

12bit ADC2

Temp sensor

Ibus

=48 / 72 MHz

APB2 : F

max

BusMatrix

Controller

AHB2
APB2

Trace

=48/72 MHz

max

AHB:F

obl

FLASH 128 KB

Interface

flash

SRAM
20 KB

PCLK1
PCLK2

HCLK
FCLK

RC 8 MHz

RC 32 kHz

@VDDA

AHB2
APB1

64 bit

PLL &

CLOCK
MANAGT

@VBAT

=24 / 36 MHz

max

APB1 : F

POWER

VOLT. REG.

3.3V TO 1.8V

@VDD

@VDD

XTAL OSC

4-16 MHz

IWDG

Standby

interface

XTAL 32 kHz

Backup

RTC

AWU

Backup interface

TIM2

TIM3

TIM 4

USART2

USART3

SPI2

2x(8x16bit)

I2C1

I2C2

bxCAN

USB 2.0 FS

SRAM 512B

WWDG

reg

V

= 2 to 3.6V

DD

V

SS

OSC_IN
OSC_OUT

V

BAT

OSC32_IN
OSC32_OUT

ANTI_TAMP

4 Channels

4 Channels

8 Channels

RX,TX, CTS, RTS,
SmartCard as AF

RX,TX, CTS, RTS,
SmartCard as AF

MOSI,MISO,SCK,NSS
as AF

SCL,SDA,SMBAL
as AF

SCL,SDA
as AF

USBDP/CANTX
USBDM/CANRX

pbus

Dbus

System

Rst

Int

IF

IFIF

1. TA = –40 °C to +105 °C (junction temperature up to 125 °C).

2. AF = alternate function on I/O port pin.

14/67

ai14390

STM32F103xx Pin descriptions

3 Pin descriptions

Figure 2. STM32F103xx performance line LQFP100 pinout

VDD_3

VSS_3

PE1

PE0

PB9

PB8

BOOT0

PB7

PB6

PB5

PB4

PB3

PD7

PD6

PD5

PD4

PD3

PD2

PD1

PD0

PC12

PC11

PC10

PA15

PA14

PE2
PE3
PE4
PE5
PE6

VBAT

PC13-ANTI_T AMP

PC14-OSC32_IN

PC15-OSC32_OUT

VSS_5

VDD_5

OSC_IN

OSC_OUT

NRST

PC0
PC1
PC2
PC3

VSSA

VREF-

VREF+

VDDA

PA0-WKUP

PA1
PA2

100999897969594939291908988878685848382818079787776
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

26272829303132333435363738394041424344454647484950

PA3

PA4

PA5

PA6

VSS_4

VDD_4

LQFP100

PA7

PB0

PB1

PB2

PE7

PE8

PC4

PC5

PE9

PE10

PE11

PE12

PE13

PE14

PE15

PB10

PB11

VSS_1

75

VDD_2

74

VSS_2

73

NC

72

PA 13

71

PA 12

70

PA 11

69

PA 10

68

PA 9

67

PA 8

66

PC9

65

PC8

64

PC7

63

PC6

62

PD15

61

PD14

60

PD13

59

PD12

58

PD11

57

PD10

56

PD9

55

PD8

54

PB15

53

PB14

52

PB13

51

PB12

VDD_1

ai14391

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Pin descriptions STM32F103xx

Figure 3. STM32F103xx performance line LQFP64 pinout

VDD_3

VSS_3

PB9

PB8

BOOT0

PB7

PB6

PB5

PB4

PB3

PD2

PC12

PC11

PC10

PA15

PA14

PC13-ANTI_T AMP

VBAT

PC14-OSC32_IN

PC15-OSC32_OUT

PD0 OSC_IN

PD1 OSC_OUT

NRST

PC0
PC1
PC2

PC3
VSSA
VDDA

PA0-WKUP

PA1
PA2

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

17 18 19 20 21 22 23 24 29 30 31 3225 26 27 28

PA3

VSS_4

VDD_4

LQFP64

PA4

PA5

PA6

PA7

PB0

PB1

PC5

PB2

PB10

PB11

PC4

VDD_2

48

VSS_2

47

PA13

46

PA12

45

PA11

44

PA10

43

PA9

42

PA8

41

PC9

40

PC8

39

PC7

38

PC6

37

PB15

36

PB14

35

PB13

34
33

PB12

VSS_1

VDD_1

ai14392

Figure 4. STM32F103xx performance line LQFP48 pinout

VDD_3

VSS_3

PB9

PB8

BOOT0

PB7

PB6

PB5

PB4

PB3

PA15

PA14

PC13-ANTI_TAMP

VBAT

PC14-OSC32_IN

PC15-OSC32_OUT

PD0 OSC_IN

PD1 OSC_OUT

NRST
VSSA
VDDA

PA0-WKUP

PA1
PA2

48 47 46 45

1
2
3
4
5
6
7
8
9
10
11

12

13 14 15 16 17 18 19 20 21 22

PA3

44 43 42 41 40 39 38 37

LQFP48

PA4

PA5

PA6

PA7

PB0

PB1

PB2

36

35

34

33
32
31
30
29
28
27
26
25

24

23

PB10

PB11

VSS_1

VDD_1

VDD_2
VSS_2
PA13
PA12
PA11
PA10
PA9
PA8
PB15
PB14
PB13
PB12

ai14393

16/67

STM32F103xx Pin descriptions

Figure 5. STM32F103xx performance line BGA100 ballout

A

B PC11PD2

C

D PD4

E

F

PC14-

OSC32_IN

PC15-

OSC32_OUT

OSC_IN

OSC_OUT V

PC0

PC13-

ANTI_TAMP

V

BAT

V

SS_5

DD_5

PCD

PC1

PE2

PE4

PE5

PC3

PB9

PB8PE3

PE1

PE0

V

SS_4

V

DD_4

PB7

PB6

PB5

BOOT0

V

SS_3

DD_3

PB4

PD5

PD6

PD7

V

V

DD_2

SS_2

PB3

PD3

V

SS_1

V

DD_1

87654321

PA15

PC12

PD0

PD1PE6NRST

NCV

PA14

PC10

PA9

PA8

PC9

PC8

109

APA13

PA12

PA11

PA10

PC7

PC6

G

H

K

V

V

J

V

SSA

REF–

REF+

DDA

PA0-WKUP

PA1

PA2

PA3

PC4PA4

PC5PA5

PB0PA6

PB1PA7

PB2

PE8

PE10

PE11PE7

PE12

PE13PE9V

PE14

PE15

PB10

PB11

PB15

PB14

PB13

PB12

PD11

PD10

PD9

PD8

PD15

PD14

PD13

PD12

AI16001

17/67

Pin descriptions STM32F103xx

Pins

LQFP48

(2)

Pin name

(1)

Type

LQFP64

LQFP100

BAT

(4)

(4)

(4)

SS_5
DD_5

SV
I/O PC13 ANTI_TAMP
I/O PC14-OSC32_IN
I/O PC15-OSC32_OUT

SV

SV

I / O Level

FT
FT
FT
FT
FT

Main function

(after reset)

PE2 TRACECK
PE3 TRACED0
PE4 TRACED1
PE5 TRACED2
PE6 TRACED3

SS_5

DD_5

BAT

(3)

Default alternate functions

Table 3. Pin definitions

BGA100

A3 - - 1 PE2/TRACECK I/O
B3 - - 2 PE3/TRACED0 I/O
C3 - - 3 PE4/TRACED1 I/O
D3 - - 4 PE5/TRACED2 I/O
E3 - - 5 PE6/TRACED3 I/O
B2 1 1 6 V
A2 2 2 7 PC13-ANTI_TAMP
A1 3 3 8 PC14-OSC32_IN
B1 4 4 9 PC15-OSC32_OUT
C2 - - 10 V
D2 - - 11 V
C1 5 5 12 OSC_IN I OSC_IN
D1 6 6 13 OSC_OUT O OSC_OUT
E1 7 7 14 NRST I/O NRST
F1 - 8 15 PC0/ADC_IN10 I/O PC0 ADC_IN10
F2 - 9 16 PC1/ADC_IN11 I/O PC1 ADC_IN11
E2 - 10 17 PC2/ADC_IN12 I/O PC2 ADC_IN12
F3 - 11 18 PC3/ADC_IN13 I/O PC3 ADC_IN13
G1 8 12 19 V
H1 - - 20 V

J1 - - 21 V

K1 9 13 22 V

PA0-WKUP/

G2 10 14 23

USART2_CTS/

ADC_IN0/TIM2_CH1_ETR

H2 11 15 24

J2 12 16 25

K2 13 17 26

PA1/USAR T2_RTS/

ADC_IN1/TIM2_CH2

PA2/USART2_TX/

ADC_IN2/ TIM2_CH3

PA3/USART2_RX/

ADC_IN3/TIM2_CH4
E4 - 18 27 V
F4 - 19 28 V

SSA

REF-

REF+

DDA

SS_4
DD_4

SV
SV
SV
SV

SSA

REF-

REF+

DDA

WKUP/USART2_CTS

I/O PA0

I/O PA1

I/O PA2

I/O PA3

SV
SV

SS_4

DD_4

ADC_IN2/ TIM2_CH3

ADC_IN3/TIM2_CH4

C_IN0/

TIM2_CH1_ETR

USART2_RTS

ADC_IN1/

TIM2_CH2

USART2_TX

USART2_RX

(6)

(6)

(6)

(6)

(6)

(6)

/

/

/

/AD

(6)

(6)

18/67

STM32F103xx Pin descriptions

Table 3. Pin definitions (continued)

Pins

Pin name

LQFP48

BGA100

G3 14 20 29

LQFP64

LQFP100

PA4/SPI1_NSS/

USART2_CK/ADC_IN4

I/O PA4

H3 15 21 30 PA5/SPI1_SCK/ ADC_IN5 I/O PA5 SPI1_SCK

J3 16 22 31

K3 17 23 32

PA6/SPI1_MISO/

ADC_IN6/TIM3_CH1

PA7/SPI1_MOSI/

ADC_IN7/TIM3_CH2

I/O PA6

I/O PA7

(2)

(1)

Type

Main function

(after reset)

(3)

Default alternate functions

I / O Level

(6)

(6)

/ ADC_IN4

(6)

/ ADC_IN5

(6)

(6)

/

/

(6)

/

(6)

SPI1_NSS

USART2_CK

SPI1_MISO

ADC_IN6/TIM3_CH1

SPI1_MOSI

ADC_IN7/TIM3_CH2
G4 - 24 33 PC4/ADC_IN14 I/O PC4 ADC_IN14
H4 - 25 34 PC5/ADC_IN15 I/O PC5 ADC_IN15

J4 18 26 35 PB0/ADC_IN8/ TIM3_CH3 I/O PB0 ADC_IN8/TIM3_CH3

K4 19 27 36 PB1/ADC_IN9/ TIM3_CH4 I/O PB1 ADC_IN9/TIM3_CH4

(6)
(6)

G5 20 28 37 PB2 / BOOT1 I/O FT PB2/BOOT1
H5 - - 38 PE7 I/O FT PE7

J5 - - 39 PE8 I/O FT PE8
K5 - - 40 PE9 I/O FT PE9
G6 - - 41 PE10 I/O FT PE10
H6 - - 42 PE11 I/O FT PE11

J6 - - 43 PE12 I/O FT PE12
K6 - - 44 PE13 I/O FT PE13
G7 - - 45 PE14 I/O FT PE14
H7 - - 46 PE15 I/O FT PE15

J7 21 29 47

K7 22 30 48

PB10/I2C2_SCL/

USART3_TX

PB11/I2C2_SDA /

USART3_RX
E7 23 31 49 V
F7 24 32 50 V

PB12/SPI2_NSS /

K8 25 33 51

I2C2_SMBAl/ USART3_CK /

TIM1_BKIN

PB13/SPI2_SCK /

J8 26 34 52

USART3_CTS /

TIM1_CH1N

PB14/SPI2_MISO /

H8 27 35 53

USART3_RTS /

TIM1_CH2N

SS_1
DD_1

I/O FT PB10 I2C2_SCL/USART3_TX

I/O FT PB11

SV
SV

SS_1

DD_1

I2C2_SDA/

USART3_RX

SPI2_NSS

I/O FT PB12

/I2C2_SMBAl

USART3_CK

TIM1_BKIN
SPI2_SCK

I/O FT PB13

USART3_CTS

TIM1_CH1N

SPI2_MISO

I/O FT PB14

/USART3_RTS

TIM1_CH2N

(5)(6)

(5)

(5)

(5)(6)

(6)

(5)

/

(5)(6)

(6)

(5)

(5)(6)
(6)

(5)(6)

/

/

/

19/67

Pin descriptions STM32F103xx

Table 3. Pin definitions (continued)

Pins

LQFP48

BGA100

LQFP64

G8 28 36 54

Pin name

LQFP100

PB15/SPI2_MOSI

TIM1_CH3N

I/O FT PB15

(2)

(1)

Type

Main function

(after reset)

(3)

Default alternate functions

I / O Level

SPI2_MOSI
TIM1_CH3N

K9 - - 55 PD8 I/O FT PD8

J9 - - 56 PD9 I/O FT PD9
H9 - - 57 PD10 I/O FT PD10
G9 - - 58 PD11 I/O FT PD11

K10 - - 59 PD12 I/O FT PD12

J10 - - 60 PD13 I/O FT PD13
H10 - - 61 PD14 I/O FT PD14
G10 - - 62 PD15 I/O FT PD15
F10 - 37 63 PC6 I/O FT PC6
E10 38 64 PC7 I/O FT PC7

F9 39 65 PC8 I/O FT PC8
E9 - 40 66 PC9 I/O FT PC9

D9 29 41 67

C9 30 42 68

D10314369

C10324470

B10334571

PA8/USART1_CK/

TIM1_CH1/MCO

PA9/USART1_TX/

TIM1_CH2

PA10/USART1_RX/

TIM1_CH3

PA11 / USART1_CTS/

CANRX / USBDM/

TIM1_CH4

PA12 / USART1_RTS/

CANTX / USBDP/

TIM1_ETR

I/O FT PA8

I/O FT PA9

I/O FT PA10

I/O FT PA11

I/O FT PA12

USART1_CK/

TIM1_CH1

USART1_TX

TIM1_CH2

USART1_RX

TIM1_CH3

USART1_CTS/

CANRX

TIM1_CH4

USART1_RTS/

CANTX

TIM1_ETR

(6)

(6)

A10344672 PA13/JTMS/SWDIO I/O FT JTMS/SWDIO PA13

F8 - - 73 Not connected
E6 35 47 74 V
F6 36 48 75 V

SS_2
DD_2

SV
SV

SS_2

DD_2

A9 37 49 76 PA14/JTCK/SWCLK I/O FT JTCK/SWCLK PA14
A8 38 50 77 PA15/JTDI I/O FT JTDI PA15
B9 - 51 78 PC10 I/O FT PC10
B8 - 52 79 PC11 I/O FT PC11
C8 - 53 80 PC12 I/O FT PC12

(5)

/

(6)

(6)

/MCO

(6)

/

(6)

(6)

/

(6)

(6)

/

/ USBDM

(6)

/

/ USBDP

20/67

STM32F103xx Pin descriptions

Table 3. Pin definitions (continued)

Pins

Pin name

LQFP48

BGA100

LQFP64

LQFP100

D8 5 5 81 PD0 I/O FT OSC_IN
E8 6 6 82 PD1 I/O FT OSC_OUT

(2)

(1)

Type

Main function

(after reset)

(3)

Default alternate functions

I / O Level

(7)

(7)

B7 54 83 PD2/TIM3_ETR I/O FT PD2 TIM3_ETR
C7 - - 84 PD3 I/O FT PD3
D7 - - 85 PD4 I/O FT PD4
B6 - - 86 PD5 I/O FT PD5
C6 - - 87 PD6 I/O FT PD6
D6 - - 88 PD7 I/O FT PD7
A7 39 55 89 PB3/JTDO/TRACESWO I/O FT JTDO PB3/TRACESWO
A6 40 56 90 PB4/JNTRST I/O FT JNTRST PB4
C5 41 57 91 PB5/I2C1_SMBAl I/O PB5 I2C1_SMBAl

B5 42 58 92 PB6/I2C1_SCL/ TIM4_CH1 I/O FT PB6

A5 43 59 93 PB7/I2C1_SDA/ TIM4_CH2 I/O FT PB7

I2C1_SCL

TIM4_CH1

I2C1_SDA

TIM4_CH2

(6)

(5)(6)

(6)

(5) (6)

/

/

D5 44 60 94 BOOT0 I BOOT0
B4 45 61 95 PB8/TIM4_CH3 I/O FT PB8 TIM4_CH3
A4 46 62 96 PB9/TIM4_CH4 I/O FT PB9 TIM4_CH4
D4 - - 97 PE0/TIM4_ETR I/O FT PE0 TIM4_ETR

(5) (6)
(5) (6)

(5)

C4 - - 98 PE1 I/O FT PE1
E5 47 63 99 V
F5 48 64 100 V

1. I = input, O = output, S = supply, HiZ = high impedance.

2. FT= 5 V tolerant.

3. Function availability depends on the chosen device. Refer to Table 2 on page 7.

4. PC13, PC14 and PC15 are supplied through the power switch, and so their use in ouptut mode is limited: they can be used
only in output 2 MHz mode with a maximum load of 30 pF and only one pin can be put in output mode at a time.

5. Available only on devices with a Flash memory density equal or higher than 64 Kbytes.

6. This alternate function can be remapped by software to some other port pins (if available on the used package). For more
details, refer to the Alternate function I/O and debug configuration section in the STM32F10xxx reference manual,
UM0306, available from the STMicroelectronics website: www.st.com.

7. For the LQFP48 and LQFP64 packages, the pins number 5 and 6 are configured as OSC_IN/OSC_OUT after reset,
however the functionality of PD0 and PD1 can be remapped by software on these pins.

SS_3
DD_3

SV
SV

SS_3

DD_3

21/67

Memory mapping STM32F103xx

4 Memory mapping

The memory map is shown in Figure 6.

Figure 6. Memory map

APB memory space

0xFFFF FFFF

0xFFFF F000

7

0xE010 0000

0xE000 0000

6

0xC000 0000

5

0xA000 0000

4

0x8000 0000

3

0x6000 0000

2

0x4000 0000

1

0x2000 0000

0

0x0000 0000

Cortex-M3 Internal

Peripherals

PERIPHERALS

SRAM

CODE

Reserved

0x1FFF FFFF

0x1FFF F9FF

0x1FFF F800

0x1FFF F000

0x0801 FFFF

0x0800 0000

reserved

OPTION BYTES

SYSTEM MEMORY

reserved

FLASH

0xFFFF FFFF

0xE010 0000

0x6000 0000

0x4002 3400

0x4002 3000

0x4002 2400

0x4002 2000

0x4002 1400

0x4002 1000

0x4002 0400

0x4002 0000

0x4001 3C00

0x4001 3800

0x4001 3400

0x4001 3000

0x4001 2C00

0x4001 2800

0x4001 2400

0x4001 1C00

0x4001 1800

0x4001 1400

0x4001 1000

0x4001 0C00

0x4001 0800

0x4001 0400

0x4001 0000

0x4000 7400

0x4000 7000

0x4000 6C00

0x4000 6800

0x4000 6400

0x4000 6000

0x4000 5C00

0x4000 5800

0x4000 5400

0x4000 4C00

0x4000 4800

0x4000 4400

0x4000 3C00

0x4000 3800

0x4000 3400

0x4000 3000

0x4000 2C00

0x4000 2800

0x4000 0C00

0x4000 0800

0x4000 0400

0x4000 0000

reserved
reserved

reserved
reserved
reserved

Flash Interface

reserved

RCC

reserved

DMA

reserved

USART1
reserved

SPI1
TIM1

ADC2
ADC1

reserved

Port E
Port D
Port C

Port B
Port A

EXTI
AFIO

reserved

PWR
BKP

reserved

bxCAN

shared 512 byte

USB/CAN SRAM

USB Registers

I2C2
I2C1

reserved

USART3
USART2

reserved

SPI2

reserved

IWDG

WWDG

RTC

reserved

TIM4

TIM3
TIM2

ai14394

4 Kbits

1 Kbit
3 Kbits
1 Kbit

3 Kbits
1 Kbit

3 Kbits

1 Kbit

1 Kbit

1 Kbit

1 Kbit

1 Kbit
1 Kbit
1 Kbit
1 Kbit

2 Kbits

1 Kbit
1 Kbit
1 Kbit
1 Kbit

1 Kbit

1 Kbit

1 Kbit

35 Kbits

1 Kbit
1 Kbit
1 Kbit
1 Kbit
1 Kbit
1 Kbit
1 Kbit

1 Kbit

2 Kbits

1 Kbit

1 Kbit

2 Kbits

1 Kbit

1 Kbit

1 Kbit

1 Kbit

1 Kbit

7 Kbits

1 Kbit

1 Kbit

1 Kbit

22/67

Electrical characteristics STM32F103xx

Figure 7. Pin loading conditions Figure 8. Pin input voltage

STM32F103xx pin

C = 50 pF

5.1.6 Power supply scheme

Figure 9. Power supply scheme

1.8-3.6 V

V

DD

5 × 100 nF
+ 1 × 10 µF

V

DD

V

REF

10 nF

+ 1 µF

10 nF

+ 1 µF

ai14141

V

BAT

GP I/Os

V

DD

1/2/3/4/5

V

SS

1/2/3/4/5

V

DDA

V

REF+

V

REF-

V

SSA

3.3 V

3.3V

Power switch

OUT

IN

Regulator

ADC

Backup circuitry

(OSC32K,RTC,

Wake-up logic

Backup registers)

IO

Logic

Level shifter

Analog:

RCs, PLL,

...

V

IN

STM32F103xx pin

ai14142

Kernel logic

(CPU,
Digital

& Memories)

ai14125

24/67

STM32F103xx Electrical characteristics

5.1.7 Current consumption measurement

Figure 10. Current consumption measurement scheme

IDD_V

BAT

V

BAT

I

DD

V

DD

V

DDA

ai14126

25/67

Electrical characteristics STM32F103xx

5.2 Absolute maximum ratings

Stresses above the absolute maximum ratings listed in Table 4: Voltage characteristics,

Table 5: Current characteristics, and T ab le 6: Thermal characteristics may cause permanent

damage to the device. These are stress ratings only and functional operation of the device
at these conditions is not implied. Exposure to maximum rating conditions for extended
periods may affect device reliability.

Table 4. Voltage characteri stics

Symbol Ratings Min Max Unit

VDD–V

External 3.3 V supply voltage (including V

SS

and VDD)

(1)

Input voltage on five volt tolerant pin

V

IN

|∆V

DDx

− VSS| Variations between all the different ground pins 50 50

|V

SSX

V

ESD(HBM)

1. All 3.3 V power (VDD, V
supply.

2. I

INJ(PIN)

maximum is respected. If VIN maximum cannot be respected, the injection current must be limited
externally to the I
induced by V

Table 5. Current characteristics

Input voltage on any other pin

| Variations between different power pins 50 50

Electrostatic discharge voltage (human body
model)

) and ground (VSS, V

DDA

must never be exceeded (see Table 5: Current characteristics). This is implicitly insured if VIN

value. A positive injection is induced by VIN>VDD while a negative injection is

INJ(PIN)

< VSS.

IN

(2)

) pins must always be connected to the external 3.3 V

SSA

(2)

DDA

–0.3 4.0

V

− 0.3 +5.5

SS

VSS − 0.3 VDD+0.3

see Section 5.3.11:

Absolute maximum ratings

(electrical sensitivity)

Symbol Ratings Max. Unit

I

VDD

I

VSS

Total current into V

DD

Total current ou t of V

power lines (source)

ground lines (sink)

SS

(1)
(1)

150
150

Output current sunk by any I/O and control pin 25

I

IO

Output current source by any I/Os and control pin − 25

mA

Injected current on NRST pin ± 5

(2)(3)

I

INJ(PIN)

ΣI

INJ(PIN)

1. All 3.3 V power (VDD, V
supply.

2. I

3. Negative injection disturbs the analog performance of the device. See note in Section 5.3.17: 12-bit ADC

4. When several inputs are submitted to a current injection, the maximum ΣI

must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum

INJ(PIN)

cannot be respected, the injection current must be limited externally to the I
injection is induced by V

characteristics.

positive and negative injected currents (instantaneous values). These results are based on
characterization with ΣI

Injected current on HSE OSC_IN and LSE OSC_IN pins ± 5
Injected current on any other pin

(2)

Total injected current (sum of all I/O and control pins)

) and ground (VSS, V

DDA

> VDD while a negative injection is induced by V

IN

maximum current injection on four I/O port pins of the device.

INJ(PIN)

(4)

(4)

) pins must always be connected to the external 3.3 V

SSA

INJ(PIN)

< VSS.

IN

INJ(PIN)

± 5

± 25

value. A positive

is the absolute sum of the

V

mV

26/67

STM32F103xx Electrical characteristics

Table 6. Thermal characteristics

Symbol Ratings Value Unit

T

STG

T

J

Storage temperature range –65 to +150 °C

Maximum junction temperature (see Thermal characteristics)

5.3 Operating conditions

5.3.1 General operating conditions

Table 7. General operating conditions

Symbol Parameter Conditions Min Max Unit

f

HCLK

PCLK1

f

PCLK2

V

DD

V

BAT

T

A

5.3.2 Operating conditions at power-up / power-down

The parameters given in Table 8 are derived from tests performed under the ambient
temperature condition summarized in Table 7.

Internal AHB clock frequency 0 72
Internal APB1 clock frequency 0 36
Internal APB2 clock frequency 0 72

Standard operating voltage 2 3.6 V

Backup operating voltage 1.8 3.6 V

Ambient temperature range −40 105 °C

MHzf

Table 8. Operating conditions at power-up / power-down

Symbol Parameter Conditions Min Typ Max Unit

t

VDD

VDD rise/fall time rate

20 µs/V

20 ms/V

27/67

Electrical characteristics STM32F103xx

5.3.3 Embedded reset and power control block characteristics

The parameters given in Table 9 are derived from tests performed under ambient
temperature and V

Table 9. Embedded reset and power control block characteristics

Symbol Parameter Conditions Min Typ Max Unit

supply voltage conditions summarized in Table 7.

DD

PLS[2:0]=000 (rising edge) 2.1 2.18 2.26 V
PLS[2:0]=000 (falling edge) 2 2.08 2.16 V
PLS[2:0]=001 (rising edge) 2.19 2.28 2.37 V
PLS[2:0]=001 (falling edge) 2.09 2.18 2.27 V
PLS[2:0]=010 (rising edge) 2.28 2.38 2.48 V
PLS[2:0]=010 (falling edge) 2.18 2.28 2.38 V
PLS[2:0]=011 (rising edge) 2.38 2.48 2.58 V

V

PVD

V

PVDhyst

V

POR/PDR

V

PDRhyst

T

RSTTEMPO

Programmable voltage
detector level selection

PVD hysteresis 100 mV
Power on/power down reset

threshold
PDR hysteresis 40 mV

Reset temporization 1 2.5 4.5 mS

5.3.4 Embedded reference voltage

The parameters given in Table 10 are derived from tests performed under ambient
temperature and V

Table 10. Embedded internal reference voltage

Symbol Parameter Conditions Min

supply voltage conditions summarized in Table 7.

DD

PLS[2:0]=011 (falling edge) 2.28 2.38 2.48 V
PLS[2:0]=100 (rising edge) 2.47 2.58 2.69 V
PLS[2:0]=100 (falling edge) 2.37 2.48 2.59 V
PLS[2:0]=101 (rising edge) 2.57 2.68 2.79 V
PLS[2:0]=101 (falling edge) 2.47 2.58 2.69 V
PLS[2:0]=110 (rising edge) 2.66 2.78 2.9 V
PLS[2:0]=110 (falling edge) 2.56 2.68 2.8 V
PLS[2:0]=111 (rising edge) 2.76 2.88 3 V
PLS[2:0]=111 (falling edge) 2.66 2.78 2.9 V

Falling edge 1.8 1.88 1.96 V
Rising edge 1.84 1.92 2.0 V

Max Unit

Typ

V

REFINT

Internal reference voltage

28/67

−45°C < TA < +105°C 1.16 1.20 1.26 V

−45°C < T

< +85°C 1.16 1.20 1.24 V

A

STM32F103xx Electrical characteristics

5.3.5 Supply current characteristics

The current consumption is measured as described in Figure 10: Current consumption

measurement scheme.

Maximum current consumption

The MCU is placed under the following conditions:

● All I/O pins are in input mode with a static value at V

● All peripherals are disabled except if it is explicitly mentioned

● The Flash access time is adjusted to f

frequency (0 wait state from 0 to 24 MHz, 1

HCLK

wait state from 24 to 48 MHz and 2 wait states above)

The parameters given in Table 11 are derived from tests performed under ambient
temperature and V

Table 11. Maximum current con sumption in Run and Sleep modes

Symbol Parameter Conditions F

supply voltage conditions summarized in Table 7.

DD

or VSS (no load)

DD

(1)

(2)

HCLK

Typ

=

T

A

85 °C

Max

(3)

TA=

105 °C

Unit

External clock with PLL, code running from
Flash, all peripherals enabled (see RCC
register description):

= f

f

PCLK1

HCLK

/2, f

PCLK2

= f

HCLK

External clock, PLL stopped, code running
from Flash, all peripherals enabled (see RCC
register description):

Supply

current in

Run mode

f

= f

PCLK1

HCLK

/2, f

PCLK2

= f

HCLK

External clock with PLL, code running from
RAM, all peripherals enabled (see RCC
register description):

I

DD

PCLK1

HCLK

/2, f

PCLK2

= f

HCLK

f

= f

External clock, PLL stopped, code running
from RAM, all peripherals enabled (see RCC
register description):

= f

f

PCLK1

HCLK

/2, f

PCLK2

= f

HCLK

External clock with PLL, code running from
RAM or Flash, all peripherals enabled (see
RCC register description):

Supply

current in

Sleep mode

f

= f

PCLK1

HCLK

/2, f

PCLK2

= f

HCLK

External clock, PLL stopped, code running
from RAM or Flash, all peripherals enabled
(see RCC register description):

= f

f

PCLK1

1. TBD stands for to be determined.

2. Typical values are measured at T

3. Data based on characterization results, tested in production at V

/2, f

HCLK

= 25 °C, and V

A

PCLK2

= f

DD

HCLK

= 3.3 V

Dmax

, f

72 MHz 36 TBD TBD
48 MHz 30 TBD TBD
36 MHz 22 TBD TBD
24 MHz 21 TBD TBD

8 MHz 10 TBD TBD

72 MHz 32 45 47
48 MHz 22 31 33
36 MHz 13 18 20
24 MHz 11 15 17

8 MHz 4.5 TBD TBD

72 MHz 22 35 37
48 MHz 14 23 25
36 MHz 13 22 24
24 MHz 10 17 19

8 MHz 3.5 TBD TBD

HCLK

max. T

and code executed from RAM.

Amax,

mA

mA

29/67

Electrical characteristics STM32F103xx

Table 12. Maximum current consumption in Stop and Standby modes

Symbol Parameter Conditions

(2)

Typ

V

/ V

BAT

VDD/V

= 3.3 V

DD

= 2.4 V

Regulator in Run mode,
Low-speed and high-speed internal
RC oscillators and high-speed

TBD 24 TBD TBD

oscillator OFF (no independent

Supply current

in Stop mode

I

DD

watchdog)
Regulator in Low Power mode,

Low-speed and high-speed internal
RC oscillators and high-speed

TBD

(4)

oscillator OFF (no independent
watchdog)

Supply current

in Standby

(5)

mode

I

DD_VBAT

1. TBD stands for to be determined.

2. Typical values are measured at T

3. Data based on characterization results, tested in production at V

4. Values expected for next silicon revision.

5. To have the Standby consumption with RTC ON, add I
VDD is present the Backup Domain is powered by VDD supply).

Backup domain

supply current

Low-speed internal RC oscillator and
independent watchdog OFF, low-

TBD

speed oscillator and RTC OFF

Low-speed oscillator and RTC ON 1

= 25 °C, V

A

= 3.3 V, unless otherwise specified.

DD

, f

DD max

DD_VBAT

(Low-speed oscillator and RTC ON) to IDD Standby (when

HCLK

(4)

(4)

max. and TA max (for other temperature.

14

2

1.4

(1)

(4)

(4)

(4)

BAT

TA =

85 °C

TBD

TBD

TBD

Max

(4)

(4)

(4)

(3)

TA =

105 °C

(4)

TBD

(4)

TBD

(4)

TBD

Unit

µA

30/67

STM32F103xx Electrical characteristics

Typical current consumption

The MCU is placed under the following conditions:

● All I/O pins are in input mode with a static value at V

● All peripherals are disabled except if it is explicitly mentioned.

● The Flash access time is adjusted to f

frequency (0 wait state from 0 to 24 MHz, 1

HCLK

wait state from 24 to 48 MHZ and 2 wait states above).

● Ambient temperature and V

Table 13. Typical current consumption in Run and Sleep modes

Symbol Parameter Conditions f

Oscillator running at 8 MHz with PLL, code

running from Flash, all peripheral disabled

(see RCC register description): f

Running on HSI clock, code running from

Flash, all peripheral disabled (see RCC

Supply

current in

Run mode

register description): f
f

PCLK2=fHCLK.

Running on HSI clock, code running from

I

DD

RAM, all peripheral disabled (see RCC

register description): f
f

PCLK2=fHCLK.

Oscillator running at 8MHz with PLL, code
running from Flash, all peripheral disabled

(see RCC register description): f

Supply

current in

Sleep mode

Running on HSI clock, code running from

Flash, all peripheral disabled (see RCC

register description): f
f

PCLK2=fHCLK.

supply voltage conditions summarized in Table 7.

DD

/2, f

f

HCLK

PCLK2=fHCLK

PCLK1

= f

AHB pre-scaler used to

reduce the frequency

= f

PCLK1

AHB pre-scaler used to

reduce the frequency

f

/2, f

HCLK

PCLK2=fHCLK

PCLK1

= f

AHB pre-scaler used to

reduce the frequency

or VSS (no load).

DD

=

PCLK1

/2,

HCLK

/2,

HCLK

=

PCLK1

/2,

HCLK

(1)

HCLK

Typ

72 MHz 21
48 MHz 18
36 MHz TBD
24 MHz 13
16 MHz TBD

8 MHz 7.8
4 MHz 7
2 MHz 6.3

1 MHz 6.2
500 kHz 6.1
125 kHz 5.95

8 MHz 2.3

4 MHz 1.6

2 MHz 1.2

1 MHz 1
500 kHz 0.88
125 kHz 0.82

72 MHz 6
48 MHz TBD
36 MHz TBD
24 MHz TBD
16 MHz 1

8 MHz TBD

4 MHz TBD

2 MHz TBD

1 MHz TBD
500 kHz TBD

(2)

Unit

mA

mA

mA

mA

mA

1. TBD stands for to be determined.

2. Typical values are measures at TA = 25 °C, VDD = 3.3 V.

31/67

Electrical characteristics STM32F103xx

Table 14. Typical current consumption in Stop and Standby modes

Symbol Parameter Conditions

Regulator in Run mode,
Low-speed and high-speed internal RC
oscillators OFF
High-speed oscillator OFF (no

Supply current in

Stop mode

independent watchdog)
Regulator in Low Power mode,

Low-speed and high-speed internal RC
oscillators OFF,
High-speed oscillator OFF (no

I

DD

independent watchdog)
Low-speed internal RC oscillator and

independent watchdog OFF

Supply current in
Standby mode

Low-speed internal RC oscillator and

(4)

independent watchdog ON

Low-speed internal RC oscillator ON,
independent watchdog OFF

Low-speed oscillator and RTC ON

I

DD_VBAT

Backup domain

supply current

Low-speed oscillator OFF, RTC ON

1. TBD stands for to be determined.

2. Typical values are measures at T

3. Values expected for next silicon revision.

4. To obtain Standby consumption with RTC ON, add I
Standby.

= 25 °C, V

A

DD

= 3.3 V.

DD_VBAT

(Low-speed oscillator and RTC ON) to IDD

V

DD

3.3 V 24

2.4 V TBD

3.3 V 14

2.4 V TBD

3.3 V 2

2.4 V TBD

3.3 V 3.1

2.4 V TBD

3.3 V 2.9

2.4 V TBD

3.3 V 1.4

2.4 V 1

3.3 V 0.5

2.4 V TBD

(1)

Typ

(3)

(3)

(3)

(3)

(3)

(3)

(3)

(2)

(3)

(3)

(3)

(3)

(3)

Unit

µA

µA

µA

32/67

STM32F103xx Electrical characteristics

5.3.6 External clock source characteristics

High-speed external user clock

The characteristics given in Table 15 result from tests performed using an high-speed
external clock source, and under ambient temperature and supply voltage conditions
summarized in Table 7.

Table 15. High-speed external (HSE) user clock characteristics

Symbol Parameter Conditions Min Typ Max Unit

f

HSE_ext

V

HSEH

V

HSEL

t

w(HSE)

t

w(HSE)

t

r(HSE)

t

f(HSE)

1. Value based on design simulation and/or technology characteristics. It is not tested in production.

User external clock source
frequency

(1)

OSC_IN input pin high level
voltage

OSC_IN input pin low level
voltage

OSC_IN high or low time

OSC_IN rise or fall time

OSC_IN Input leakage

I

L

current

(1)

(1)

V

SS≤VIN≤VDD

0.7V

V

16

SS

DD

825MHz

V

DD

0.3V

DD

5

±1 µA

Low-speed external user clock

The characteristics given in Table 16 result from tests performed using an low-speed
external clock source, and under ambient temperature and supply voltage conditions
summarized in Table 7.

Table 16. Low-spee d external user clock characteristics

Symbol Parameter Conditions Min Typ Max Unit

f

LSE_ext

V

LSEH

V

LSEL

t

w(LSE)

t

w(LSE)

t

r(LSE)

t

f(LSE)

1. Value based on design simulation and/or technology characteristics. It is not tested in production.

User External clock source
frequency

(1)

OSC32_IN input pin high level
voltage

OSC32_IN input pin low level
voltage

OSC32_IN high or low time

OSC32_IN rise or fall time

OSC32_IN Input leakage

I

L

current

(1)

(1)

V

SS≤VIN≤VDD

0.7V

V

450

32.768 1000 kHz

DD

SS

V

DD

0.3V

DD

5

±1 µA

V

ns

V

ns

33/67

Electrical characteristics STM32F103xx

Figure 11. High-speed external clock source AC timing diagram

V

HSEH

V

HSEL

90%
10%

t

r(HSE)

EXTERNAL
CLOCK SOURC E

T

f

HSE_ext

HSE

t

f(HSE)

OSC _I N

t

W(HSE)

I

L
STM32F103xx

t

W(HSE)

ai14143

t

Figure 12. Low-speed external clock source AC timing diagram

V

LSEH

V

LSEL

90%
10%

t

r(LSE)

EXTERNAL
CLOCK SOURC E

f

LSE_ext

T

LSE

t

f(LSE)

OSC32_IN

t

W(LSE)

I

L

STM32F103xx

t

W(LSE)

ai14144b

t

34/67

STM32F103xx Electrical characteristics

High-speed external clock

The high-speed external (HSE) clock can be supplied with a 4 to 16 MHz crystal/ceramic
resonator oscillator. All the inf ormation given in this paragraph are based on characterization
results obtained with typical external components specified in Table 17. In the application,
the resonator and the load capacitors have to be placed as close as possible to the oscillator
pins in order to minimize output distortion and startup stabilization time. Refer to the crystal
resonator manufacturer for more details on the resonator characte ristics (frequency,
package, accuracy).

Table 17. HSE 4-16 MHz oscillator chara cteristics

Symbol Parameter Conditions Min Typ Max Unit

(1)

f

OSC_IN

R

C

C

L2

Oscillator frequency 4 8 16 MHz
Feedback resistor 200 kΩ

F

Recommended load capacitance

L1

versus equivalent serial

(2)

resistance of the crystal (R

(3)

)

S

RS = 30 Ω 30 pF

VDD= 3.3 V

i

HSE driving current

2

VIN=V

with 30 pF

SS

1mA

load

g

t

SU(HSE)

1. Resonator characteristics given by the crystal/ceramic resonator manufacturer.

2. For CL1 and C
designed for high-frequency applications, and selected to match the requirements of the crystal or
resonator. C
capacitance which is the series combination of CL1 and CL2. PCB and MCU pin capacitance must be
included when sizing CL1 and C
capacitance).

3. The relatively low value of the RF resistor offers a good protection against issues resulting from use in a
humid environment, due to the induced leakage and the bias condition change. However, it is
recommended to take this point into account if the MCU is used in tough humidity conditions.

4. t

SU(HSE)

oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly
with the crystal manufacturer

Oscillator Transconductance Startup 25 mA/V

m

(4)

startup time VSS is stabilized 2 ms

it is recommended to use high-quality ceramic capacitors in the 5 pF to 25pF range (typ.),

L2

and C

L1

is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz

are usually the same size. The crystal manufacturer typically specifies a load

L2,

(10 pF can be used as a rough estimate of the combined pin and board

L2

Figure 13. Typical application with a 8-MHz c rysta l

1. R

Resonator with
integrated capacitors

C

L1

OSC_IN

8 MHz
resonator

OSC_OUT

(1)

R

C

L2

value depends on the crystal characteristics. Typical value is in the range of 5 to 6RS.

EXT

EXT

R

F

Bias

controlled

gain

f

STM32F103xx

35/67

HSE

ai14145

Electrical characteristics STM32F103xx

Low-speed external clock

The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic
resonator oscillator. All the inf ormation given in this paragraph are based on characterization
results obtained with typical external components specified in Table 18. In the application,
the resonator and the load capacitors have to be placed as close as possible to the oscillator
pins in order to minimize output distortion and startup stabilization time. Refer to the crystal
resonator manufacturer for more details on the resonator characte ristics (frequency,
package, accuracy).

Table 18. LSE oscillator characteristics (f

Symbol Parameter Conditions Min Typ Max Unit

= 32.768 kHz)

LSE

R

C

L1

C

L2

I

2

g

m

t

SU(LSE)

1. The oscillator selection can be optimized in terms of supply current using an high quality resonator with
small RS value for example MSIV-TIN32.768kHz. Refer to crystal manufacturer for more details

2. t

SU(LSE)

kHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary
significantly with the crystal manufacturer

Feedback resistor 5 MΩ

F

Recommended load capacitance
versus equivalent serial
resistance of the crystal (R

LSE driving current

(1)

)

S

RS = 30 kΩ 15 pF

= 3.3 V

V

DD

= V

V

IN

SS

Oscillator Transconductance 5 µA/V

(2)

startup time VSS is stabilized 3 s

is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768

1.4 µA

Figure 14. Typical application with a 32.768 kHz crystal

Resonator with
integrated capacitors

C

L1

32.768 kHz
resonator

C

L2

OSC32_IN

OSC32_OUT

R

F

Bias

controlled

gain

f

LSE

STM32F103xx

ai14146

36/67

STM32F103xx Electrical characteristics

5.3.7 Internal clock source characteristics

The parameters given in Table 19 are derived from tests performed under ambient
temperature and V

High-speed internal (HSI) RC oscillator

Table 19. HSI oscillator characteristics

Symbol Parameter Conditions Min Typ Max

supply voltage conditions summarized in Table 7.

DD

(1)(2)

(3)

Unit

f

ACC

t

su(HSI)

I

DD(HSI)

1. V

2. TBD stands for to be determined.

3. Values based on device characterization, not tested in production.

Frequency 8 MHz

HSI

T

= –40 to 105 °C TBD ±3TBD%

Accuracy of HSI oscillator

HSI

A

= 25°C TBD ±1TBD%

at T

A

HSI oscillator start up time 1 2 µs
HSI oscillator power

consumption

= 3.3 V, TA = −40 to 105 °C unless otherwise specified.

DD

LSI Low Speed Internal RC Oscillator

Table 20. LSI oscillator characteristics

Symbol Parameter Conditions Min Typ

f

t

su(LSI)

I

DD(LSI)

1. V

2. Value based on device characterization, not tested in production.

Frequency 30 60 kHz

LSI

LSI oscillator start up time 85 µs
LSI oscillator power

consumption

= 3 V, TA = −40 to 105 °C unless otherwise specified.

DD

(1)

0.65 1.2 µA

80 100 µA

(2)

Max

Unit

37/67

Electrical characteristics STM32F103xx

Wakeup time from low power mode

The wakeup times giv en in Table 21 is measured on a wakeup phase with a 8-MHz HSI RC
oscillator. The clock source used to wake up the device depends from the current operating
mode:

● Stop or Standby mode: the clock source is the RC oscillator

● Sleep mode: the clock source is the clock that was set before entering Sleep mode.

All timings are derived from tests performed under ambient temperature and V
voltage conditions summarized in Table 7.

Table 21. Low-power mode wakeup timings

Symbol Parameter Conditions Typ Max Unit

(2)

t

WUSLEEP

Wakeup from Sleep mode Wakeup on HSI RC clock 0.75 TBD µs
Wakeup from Stop mode

(regulator in run mode)

t

WUSTOP

(2)

Wakeup from Stop mode
(regulator in low power mode)

(3)

t

WUSTDBY

1. TBD stands for to be determined.

2. The wakeup time from Sleep and Stop mode are measured from the wakeup event to the point in which the
user application code reads the first instruction.

3. The wakeup time from Standby mode is measured from the wakeup event to the point in which the device
exits from reset.

Wakeup from Standby mode

5.3.8 PLL characteristics

The parameters given in Table 22 are derived from tests performed under ambient
temperature and V

Table 22. PLL characteristics

supply voltage conditions summarized in Table 7.

DD

(1)

supply

DD

(1)

HSI RC wakeup tim e = 2 µs 4 TBD

HSI RC wakeup tim e = 2 µs,
Regulator wakeup from LP

7TBD

mode time = 5 µs
HSI RC wakeup tim e = 2 µs,

Regulator wakeup from power

40 TBD µs

down time = 38 µs

µs

Symbol Parameter Test Conditions

PLL input clock 8.0 MHz

f

PLL_IN

f

PLL_OUT

f

VCO

t

LOCK

t

JITTER

1. TBD stands for to be determined.

2. Data based on device characterization, not tested in production.

PLL input clock duty cycle 40 60 %
PLL multiplier output clock 16 72 MHz

VCO frequency range

When PLL operates

(locked)
PLL lock time 200 µs
Cycle to cycle jitter (+/-3Σ

peak to peak)

V

38/67

Value

Min Typ Max

(2)

32 144 MHz

is stable TBD TBD %

DD

Unit

STM32F103xx Electrical characteristics

5.3.9 Memory characteristics

Flash memory

The characteristics are given at TA = −40 to 105 °C unless otherwise specified.

Table 23. Flash memory characteristics

Symbol Parameter Conditions Min Typ Max

(1)

Unit

t

prog

t

ERASE

t

ME

Word programming time TA = −40 to +105 °C 20 40 µs

Page (1kB) erase time TA = −40 to +105 °C 20 40 ms

Mass erase time TA = −40 to +105 °C 20 40 ms

Read mode

f

= 72 MHz with

HCLK

2 wait states,

= 3.3 V

V

DD

I

DD

Supply current

Write / Erase modes

= 72 MHz,

f

HCLK

VDD = 3.3 V

Pow er-down mode /

HALT,

= 3.0 to 3.6 V

V

DD

1. Values based on characterization and not tested in production.

Table 24. Flash memory endurance and dat a retention

Symbol Parameter Conditions

N

t

1. Values based on characterization not tested in production.

Endurance

END

Data retention TA = 85 °C 30 Years

RET

Min

(1)

1

20 mA

5mA

50 µA

Value

Unit

Typ Max

10 kcycles

39/67

Electrical characteristics STM32F103xx

5.3.10 EMC characteristics

Susceptibility tests are performed on a sample basis during device characterization.

Functional EMS (electromagnetic susceptibility)

While a simple application is e xec uted on the de vice (toggling 2 LEDs through I /O ports). the
device is stressed by two electromagnetic events until a failure occurs. The failure is
indicated by the LEDs:

● Electrostatic discharge (ESD) (positive and negative ) is applied to all de vice pins until

a functional disturbance occurs. This test is complian t with the IEC 1000-4-2 standard.

● FTB: A Burst of Fast Transient voltage (positive and negative) is applied to V

V

through a 100 pF capacitor, until a functional disturbance occurs. This test is

SS

compliant with the IEC 1000-4-4 standard.
A device reset allows normal operations to be resumed.
The test results are given in Table 25. They are based on the EMS levels and classes

defined in application note AN1709.

Table 25. EMS characteristics

(1)

DD

and

Symbol Parameter Conditions

= 3.3 V, TA = +25 °C,

V

V

FESD

V

EFTB

1. TBD stands for to be determined.

V oltage limits to be applied on any I/O pin to
induce a functional disturbance

Fast transient voltage burst limits to be
applied through 100pF on VDD and V
to induce a functional disturbance

SS

pins

DD

f

=48 MHz

HCLK

conforms to IEC 1000-4-2
VDD = 3.3 V, TA = +25 °C,

f

= 48 MHz

HCLK

conforms to IEC 1000-4-4

Level/

Class

TBD

4A

Designing hardened software to avoid noise problems

EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU sof tware. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular .

Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.

Software recommendations

The software flowchart must include the management of runaway conditions such as:

● Corrupted program counte r

● Unexpected reset

● Critical Data corruption (control registers...)

40/67

STM32F103xx Electrical characteristics

Prequalification trials

Most of the common failures (u nexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1
second.

To complete these trials , ESD stress can be applie d directly on the de vice , o v er the r ange of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverab le errors occurring (see application note AN1015).

Electromagnetic Interference (EMI)

The electromagnetic field emitted by the device are monitored while a simple application is
executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with SAE J
1752/3 standard which specifies the test board and the pin loading.

Table 26. EMI characteristics

Symbol Parameter Conditions

= 3.3 V, TA = 2 5 °C,

V

DD

S

EMI

Peak level

LQFP100 package
compliant with SAE J
1752/3

Monitored

Frequency Band

0.1 to 30 MHz 12 12

130 MHz to 1GHz 23 29

SAE EMI Level 4 4 -

Max vs. [f

8/48 MHz 8/72 MHz

HSE/fHCLK

]

Unit

dBµV30 to 130 MHz 22 19

41/67

Electrical characteristics STM32F103xx

5.3.11 Absolute maximum ratings (electrical sensitivity)

Based on three different tests (ESD, LU) using specific measurement methods, the device is
stressed in order to determine its performance in terms of electrical sensitivity.

Electrostatic discharge (ESD)

Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size is
either 3 parts (cumulative mode) or 3 parts × (n + 1) supply pins (non-cumulative mode).
The human body model (HBM) can be simulated. The tests are compliant with JESD22­A114A standard.
For more details, refer to the application note AN1181.

Table 27. ESD absolute maximum ratings

Symbol Ratings Conditions Maximum value

(1)

(2)

Unit

V

ESD(HBM)

V

ESD(CDM)

1. TBD stands for to be determined.

2. Values based on characterization results, not tested in production.

Electrostatic discharge voltage
(human body model)

Electrostatic discharge voltage
(charge device model)

= +25 °C

T

A

2000

TBD

Static latch-up

Two complementary static tests are required on six parts to assess the latch-up
performance:

● A supply overvoltage is applied to each power supply pin

● A current injection is applied to each input, output and configurable I/O pin

These tests are compliant with EIA/JESD 78A IC latch-up standard.

Table 28. Electrical sensitivities

Symbol Parameter Conditions Class

LU Static latch-up class T

= +105 °C II level A

A

V

42/67

STM32F103xx Electrical characteristics

5.3.12 I/O port pin characteristics

General input/output characteristics

Unless otherwise specified, the parameters given in Table 29 are derived from tests
performed under ambient temperature and V

Table 7.

All unused pins must be held at a fixed voltage, by using the I/O output mode, an external
pull-up or pull-down resistor (see Figure 15).

Table 29. I/O static characteristics

Symbol Parameter Conditions Min Typ

V

Input low level voltage

IL

IO TC input high level

(2)

voltage

V

IH

IO FT high level voltage
Input low level voltage

V

IL

Input high level voltage

V

IH

IO TC Schmitt trigger voltage
hysteresis

V

hys

IO TC Schmitt trigger voltage
hysteresis

Input leakage current

I

lkg

(3)

(3)

(2)

(2)

(2)

(2)

(5)

(1)

V

Standard I/Os

5 V tolerant I/Os

supply voltage conditions summarized in

DD

–0.5 0.8

TTL ports

2V

25.5V

–0.5 0.35 V

CMOS ports

0.65 V

DD

200 mV

DD

(4)

SS≤VIN≤VDD

= 5 V

V

IN

5% V

Max Unit

+0.5

DD

DD

VDD+0.5

±1

3

V

V

mV

µA

R

R

1. V

2. Values based on characterization results, and not tested in production.

3. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested.

4. With a minimum of 100 mV.

5. Leakage could be higher than max. if negative current is injected on adjacent pins.

6. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable

Weak pull-up equivalent

PU

PD

C

IO

= 3.3 V, TA = −40 to 105 °C unless otherwise specified.

DD

PMOS/NMOS. This MOS/NMOS contribution to the series resistance is minimum (~10% order).

(6)

resistor
Weak pull-down equivalent

(6)

resistor
I/O pin capacitance 5 pF

V

= V

IN

SS

V

= V

IN

DD

30 40 50 kΩ

30 40 50 kΩ

43/67

Electrical characteristics STM32F103xx

Figure 15. Unused I/O pin connection

V

DD

10 kΩ

10 kΩ

STM32F103xx

UNUSED I/O PORT

STM32F103xx

UNUSED I/O PORT

ai14147b

Output driving current

The GPIOs (general purpose input/outputs) can sink or source up to +/-8 mA, and sink
+20 mA (with a relaxed V

In the user application, the number of I/O pins which can drive current must be limited to
respect the absolute maximum rating specified in Section 5.2:

● The sum of the currents sourced by all the I/Os on V

consumption of the MCU sourced on V

I

(see Table 5).

VDD

● The sum of the currents sunk by all the I/Os on V

consumption of the MCU sunk on V

I

(see Table 5).

VSS

OL

).

plus the maximum Run

cannot exceed the absolute ma ximum r ating

DD,

cannot exceed the absolute maximum rating

SS

DD,

plus the maximum Run

SS

44/67

STM32F103xx Electrical characteristics

Output voltage levels

Unless otherwise specified, the parameters given in Table 30 are derived from tests
performed under ambient temperature and V

Table 7.

Table 30. Output voltage characteristics

Symbol Parameter Conditions Min Max Unit

Output low level voltage for an I/O pin

(1)

V

OL

when 8 pins are sunk at same time
Output high level voltage for an I/O pin

(2)

V

OH

when 4 pins are sourced at same time
Output low level voltage for an I/O pin

(1)

V

OL

when 8 pins are sunk at same time
Output high level voltage for an I/O pin

(2)

V

OH

V

V

V

V

OH

when 4 pins are sourced at same time
Output low level voltage for an I/O pin

(1)

OL

when 8 pins are sunk at same time
Output high level voltage for an I/O pin

(2)

OH

when 4 pins are sourced at same time
Output low level voltage for an I/O pin

(1)

OL

when 8 pins are sunk at same time
Output high level voltage for an I/O pin

(2)

when 4 pins are sourced at same time

supply voltage conditions summarized in

DD

TTL port

= +8 mA

I

IO

2.7 V < V

< 3.6 V

DD

CMOS port

=+ 8mA

I

IO

2.7 V < V

I

IO

< 3.6 V

DD

= +20 mA

2.7 V < VDD < 3.6 V

= +6 mA

I

IO

2 V < V

< 2.7 V

DD

–0.4

V

DD

2.4

–1.3

V

DD

V

–0.4

DD

0.4

0.4

1.3

0.4

V

V

V

V

1. The IIO current sunk by the device must always respect the absolute maximum rating specified in Table 5

and the sum of IIO (I/O ports and control pins) must not exceed I

2. The IIO current sourced by the device must always respect the absolute maximum rating specified in

Table 5 and the sum of IIO (I/O ports and control pins) must not exceed I

VSS

.

.

VDD

45/67

Electrical characteristics STM32F103xx

Input/output AC characteristics

The definition and values of input /output AC characteristics are given in Figure 16 and

Table 31, respectively.

Unless otherwise specified, the parameters given in Table 31 are derived from tests
performed under ambient temperature and V

Table 7.

Table 31. I/O AC characteristics

(1)

supply voltage conditions summarized in

DD

I/O

(1)

mode

10

01

F

11

-t

Symbol Parameter Conditions Min Max Unit

f

max(IO)out

t

f(IO)out

t

r(IO)out

f

max(IO)out

t

f(IO)out

t

r(IO)out

max(IO)out

t

f(IO)out

t

r(IO)out

Maximum frequency
Output high to low level f all

(3)

time
Output low to high level

rise time

(3)

Maximum frequency
Output high to low level f all

(3)

time
Output low to high level

rise time

(3)

Maximum frequency

Output high to low level f all

(3)

time

Output low to high level
rise time

(3)

(2)

(2)

(2)

CL = 50 pF, V

= 2 V to 3.6 V 2 MHz

DD

125

CL = 50 pF, V

= 2 V to 3.6 V

DD

125

CL = 50 pF, V

= 2 V to 3.6 V 10 MHz

DD

25

CL = 50 pF, V

= 2 V to 3.6 V

DD

25

CL = 30 pF, V

= 50 pF, VDD = 2.7 V to 3.6 V 30 MHz

C

L

= 50 pF, V

C

L

CL = 30 pF, V

= 50 pF, V

C

L

= 50 pF, V

C

L

CL = 30 pF, V

= 50 pF, V

C

L

= 50 pF, V

C

L

= 2.7 V to 3.6 V 50 MHz

DD

= 2 V to 2.7 V 20 MHz

DD

= 2.7 V to 3.6 V 5

DD

= 2.7 V to 3.6 V 8

DD

= 2 V to 2.7 V 12

DD

= 2.7 V to 3.6 V 5

DD

= 2.7 V to 3.6 V 8

DD

= 2 V to 2.7 V 12

DD

Pulse width of external

EXTIpw

signals detected by the

10 ns

EXTI controller

ns

ns

ns

1. Refer to the Reference user manual UM0306 for a description of GPIO Port configuration register.

2. The maximum frequency is defined in Figure 16.

3. Values based on design simulation and validated on silicon, not tested in production.

46/67

STM32F103xx Electrical characteristics

Figure 16. I/O AC characteristics definition

EXTERNAL

OUTPUT
ON 50pF

Maximum frequency is achieved if (tr + tf) £ 2/3)T and if the duty cycle is (45-55%)

t

r(IO)out

5.3.13 NRST pin characteristics

The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up
resistor, R

Unless otherwise specified, the parameters given in Table 32 are derived from tests
performed under ambient temperature and V

Table 7.

Table 32. NRST pin characteristics

Symbol Parameter Conditions Min Typ Max Unit

V

IL(NRST)

V

IH(NRST)

V

hys(NRST)

R

PU

V

F(NRST)

V

NF(NRST)

1. TBD stands for to be determined.

2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution

to the series resistance must be minimum (~10% order).

3. Values guaranteed by design, not tested in production.

(see Table 29).

PU

NRST Input low level voltage –0.5 0.8
NRST Input high level voltage 2 VDD+0.5
NRST Schmitt trigger voltage

hysteresis
Weak pull-up equivalent resistor
NRST Input filtered pulse
NRST Input not filtered pulse

90%

50%

10%

when loaded by 50pF

(1)

(2)

(3)

(3)

10%

50%

90%

t

r(IO)out

T

supply voltage conditions summarized in

DD

ai14131

200

V

IN

= V

SS

30 40 50 kΩ

100 ns

300 µs

V

47/67

Electrical characteristics STM32F103xx

Figure 17. Recommended NRST pin protection

V

External
reset circuit

NRST

0.1 µF

2. The reset network protects the device against parasitic resets.

3. The user must ensure that the level on the NRST pin can go below the V

Table 32. Otherwise the reset will not be taken into account by the device.

DD

R

PU

FILTER

Internal Reset

STM32F101xx

max level specified in

IL(NRST)

ai14132b

5.3.14 TIM timer characteristics

Unless otherwise specified, the parameters given in Table 33 are derived from tests
performed under ambient temper at ure, f
summarized in Table 7.

Refer to Section 5.3.12: I/O port pin characteristics for details on the input/output alternate
function characteristics (output compare, input capture, external clock, PWM output).

Table 33. TIMx

(1)

characteristics

frequency and VDD supply voltage conditions

PCLKx

Symbol Parameter Conditions Min Max Unit

1

t

res(TIM)

f

EXT

Res

t

COUNTER

Timer resolution time

f

TIMxCLK

Timer external clock
frequency on CH1 to CH4

Timer resolution 16 bit

TIM

0
f

TIMxCLK

16-bit counter clock period

= 72 MHz

= 72 MHz

13.9 ns
f

TIMxCLK

036MHz

1 65536
when internal clock is
selected

f

TIMxCLK

= 72 MHz

0.0139 910 µs

/2

65536 × 65536

t

MAX_COUNT

1. TIMx is used as a general term to refer to the TIM1, TIM2, TIM3 and TIM4 timers.

Maximum possible count

f

TIMxCLK

= 72 MHz

59.6 s

t

TIMxCLK

MHz

t

TIMxCLK

t

TIMxCLK

48/67

STM32F103xx Electrical characteristics

5.3.15 Communications interfaces

I2C interface characteristics

Unless otherwise specified, the parameters given in Table 34 are derived from tests
performed under ambient temperature, f
summarized in Table 7.

2

The STM32F103xx performance line

2

I

C communication protocol with the following restrictions: the I/O pins SDA and SCL are

I

C interface meets the requirements of the standard

mapped to are not “true” open-drain. Wh en configur ed as open-dr ain, t he PMOS connect ed
between the I/O pin and V
diode between the I/O pin and V
connected to the

2

C

I

bus, it is not possible to po wer o ff the STM3 2F103xx while anot her

is disabled, but is still present. In addition, there is a protection

DD

. As a consequence, when multiple master devices are

DD

master node remains powered on. Otherwise, the STM32F103xx would be powered by the
protection diode.

2

The I

C characteristics are described in Table 34. Refer also to Section 5.3.12: I/O port pin

characteristics

and SCL)

Table 34. I2C characteristics

Symbol Parameter

for more details on the input/output alternate function characteristics (SDA

.

frequency and VDD supply voltage conditions

PCLK1

Standard mode I

2C(1)

Fast mode I2C

(1)(2)

Min Max Min Max

Unit

2

I

C

t

w(SCLL)

t

w(SCLH)

t

su(SDA)

t

h(SDA)

t

r(SDA)

t

r(SCL)

t

f(SDA)

t

f(SCL)

t

h(STA)

t

su(STA)

t

su(STO)

t

w(STO:STA)

C

Values based on standard I

1.

2. f

PCLK1

higher than 4 MHz to achieve the maximum fast mode I
The maximum hold time of the Start condition has only to be met if the interface does not stretch the low

3.
period of SCL signal.

The device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the

4.
undefined region of the falling edge of SCL.

SCL clock low time 4.7 1.3
SCL clock high time 4.0 0.6
SDA setup time 250 100
SDA data hold time 0

(3)

SDA and SCL rise time 1000 20 + 0.1C

SDA and SCL fall time 300 20 + 0.1C

(4)

0

900

300

b

300

b

Start condition hold time 4.0 0.6
Repeated Start condition

setup time

4.7 0.6

Stop condition setup time 4.0 0.6 µs
Stop to Start condition time

(bus free)
Capacitive load for each bus

b

line

2

C protocol requirement, not tested in production.

must be higher than 2 MHz to achieve the maximum standard mode I2C frequency. It must be

4.7 1.3 µs

400 400 pF

2

C frequency.

(3)

µs

ns

µs

49/67

Electrical characteristics STM32F103xx

Figure 18. I2C bus AC waveforms and measurement circuit

V

DD

t

w(SCKL)

r(SCK)

4.7kΩ

t

= 36 MHz.,VDD = 3.3 V)

PCLK1

4.7kΩ

2

C bus

I

START

SDA

t

f(SDA)

SCL

t

w(SCKH)

Measurement points are done at CMOS levels: 0.3V

1.

Table 35. SCL frequency (f

t

h(STA)

f

SCL

t

r(SDA)

(kHz)

t

400 TBD
300 TBD

V

DD

su(SDA)

100Ω

100Ω

t

h(SDA)

t

f(SCK)

and 0.7VDD.

DD

STM32F103xx

SDA
SCL

t

su(STA)

(1)(2)(3)

I2C_CCR value

START REPEATED

STOP

t

su(STO)

R

= 4.7 kΩ

P

START

t

su(STA:STO)

ai14149b

200 TBD
100 TBD

50 TBD
20 TBD

1. TBD = to be determined.

= External pull-up resistance, f

2. R

P

3. For speeds around 200 kHz, the tolerance on the achieved speed is of ±5%. For other speed ranges, the
tolerance on the achieved speed ±2%. These variations depend on the accuracy of the external
components used to design the application.

= I2C speed,

SCL

50/67

STM32F103xx Electrical characteristics

SPI interface characteristics

Unless otherwise specified, the parameters given in Table 36 are derived from tests
performed under ambient temper at ure, f
summarized in Table 7.

Refer to Section 5.3.12: I/O port pin characteristics for more details on the input/output
alternate function characteristics (NSS, SCK, MOSI, MISO).

Table 36. SPI characteristics

Symbol Parameter Conditions Min Max Unit

(1)

frequency and VDD supply voltage conditions

PCLKx

f

SCK

1/t

c(SCK)

t

r(SCK)

t

f(SCK)

t

su(NSS)

t

h(NSS)

t

w(SCKH)

t

w(SCKL)

t

su(MI)

t

su(SI)

t

h(MI)

t

h(SI)

t

a(SO)

t

dis(SO)

t

v(SO)

t

v(MO)

t

h(SO)

t

h(MO)

SPI clock frequency

Master mode TBD TBD

Slave mode 0 TBD

SPI clock rise and fall
time

(2)

NSS setup time Slave mode 0

(2)

NSS hold time Slave mode 0

(2)

SCK high and low

(2)

time

(2)

Data input setup time

(2)

Capacitive load: C=50 pF TBD

Master mode, f

PCLK

= TBD,

presc = TBD

Master mode TBD

Slave mode TBD

Master mode TBD

(2)

Data input hold time

(2)

Data output access

(2)(4)

time
Data output disable

(2)(5)

time

(2)(1)

Data output valid time

Slave mode (after enable edge) TBD

Slave mode TBD

Master mode, f

Slave mode, f

= TBD TBD

PCLK

= TBD TBD

PCLK

Slave mode TBD TBD

Slave mode, f

= TBD TBD TBD

PCLK

Slave mode TBD TBD

f

= TBD TBD

PCLK

Master mode (after enable

(2)(1)

Data output valid time

(2)

Data output hold time

(2)

Slave mode (after enable edge) TBD

Master mode (after enable

edge)

= TBD TBD TBD

f

PCLK

edge)

MHz

TBD

(3)

(3)

ns

TBD

TBD

1. TBD = to be determined.

2. Values based on design simulation and/or characterization results, and not tested in production.

3. Depends on f

4. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate
the data.

5. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put
the data in Hi-Z

. For example, if f

PCLK

= 8MHz, then t

PCLK

PCLK

= 1/f

=125 ns and t

PLCLK

v(MO)

= 255 ns.

51/67

Electrical characteristics STM32F103xx

Figure 19. SPI timing diagram - slave mode and CPHA = 0

NSS input

t

CPHA=0
CPOL=0

CPHA=0
CPOL=1

SCK Input

SU(NSS)

t

w(SCKH)

t

w(SCKL)

t

c(SCK)

t

h(NSS)

t

v(SO)

MSB O UT

MSB IN

t

h(SI)

MISO

OUT PU T

MOSI

INPUT

t

a(SO)

t

su(SI)

1. Measurement points are done at CMOS levels: 0.3VDD and 0.7V

t

h(SO)

BIT6 OUT

BIT1 IN

.

DD

Figure 20. SPI timing diagram - slave mode and CPHA = 1

NSS input

CPHA=1
CPOL=0

CPHA=1
CPOL=1

SCK Input

MISO

OUT PU T

MOSI

INPUT

t

SU(NSS)

t

w(SCKH)

t

w(SCKL)

t

a(SO)

t

su(SI)

MSB O UT

MSB IN

t

v(SO)

t

h(SI)

t

c(SCK)

BIT6 OUT

BIT1 IN

1)

t

h(SO)

t

r(SCK)

t

f(SCK)
LSB OUT

LSB IN

t

h(NSS)

t

r(SCK)

t

f(SCK)

LSB IN

t

dis(SO)

t

dis(SO)

LSB OUT

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52/67

ai14135

STM32F103xx Electrical characteristics

Figure 21. SPI timing diagram - master mode

High

NSS input

t

c(SCK)

CPHA=0
CPOL=0

CPHA=0
CPOL=1

SCK Input

CPHA=1
CPOL=0

CPHA=1
CPOL=1

SCK Input

MISO

INPUT

MOSI

OUTUT

t

su(MI)

t

w(SCKH)

t

w(SCKL)

MSBIN

MSB OUT

t

v(MO)

t

h(MI)

BIT6 IN

BIT1 OUT

t

h(MO)

t

r(SCK)

t

f(SCK)

LSB IN

LSB OUT

ai14136

1. Measurement points are done at CMOS levels: 0.3VDD and 0.7V

DD

.

USB characteristics

The USB interface is USB-IF certified (Full Speed).

Table 37. USB DC electrical characteristics

Symbol Parameter Conditions Min.

Input levels

V

V

CM

V

Output levels

V

V

OH

1. All the voltages are measured from the local ground potential.
R

2.

L

Differential input sensitivity I(USBDP, USBDM) 0.2

DI

Differential common mode
range

Single ended receiver

SE

threshold

Static output level low RL of 1.5 kΩ to 3.6 V

OL

Includes V

range 0.8 2.5

DI

Static output level high RL of 15 kΩ to V

is the load connected on the USB drivers

SS

(2)

(2)

(1)

Max.

1.3 2.0

0.3

2.8 3.6

(1)

Unit

V

V

53/67

Electrical characteristics STM32F103xx

Figure 22. USB timings: definition of data signal rise and fall time

Crossover

(1)

(1)

points

t

r

CL = 50 pF

420ns

ai14137

CL = 50 pF 4 20 ns

f

90 110 %

Differential

Data Lines

V

CRS

V

SS

Table 38. USB: Full speed electrical characteristics

t

f

Symbol Parameter Conditions Min Max Unit

Driver characteristics

t

r

t

f

t

rfm

V

CRS

Measured from 10% to 90% of the data signal. For more detailed informations, please refer to USB

1.
Specification - Chapter 7 (version 2.0).

Output signal crossover voltage 1.3 2.0 V

Rise time
Fall Time

Rise/ fall time matching tr/t

5.3.16 CAN (controller area network) interface

Refer to I/O port characteristics for more details on the input/output alternate function char­acteristics (CANTX and CANRX).

5.3.17 12-bit ADC characteristics

Unless otherwise specified, the parameters given in Table 39 are derived from tests
performed under ambient temperature, f
conditions summarized in Table 7.

Note: It is recommended to perform a calibration after each power-up.

Table 39. ADC characteristics

Symbol Parameter Conditions Min Typ Max Unit

V

V

f

f

V

ADC power supply 2.4V 3.6V V

DDA

Positive reference voltage 2.0

REF+

ADC clock frequency 0.6 14 MHz

ADC

f

Sampling rate TBD 0.05 1 MHz

S

External trigger frequency f

TRIG

Conversion voltage range

AIN

(2)

(1)

frequency and V

PCLK2

= 14 MHz

ADC

supply voltage

DDA

V

SSA

V

DDA

823 kHz

17 1/f

V

DDA

V

ADC

V

54/67

STM32F103xx Electrical characteristics

Table 39. ADC characteristics

(1)

(continued)

Symbol Parameter Conditions Min Typ Max Unit

R

C

R

C

t

t

STAB

External input impedance

AIN

External capacitor on analog

AIN

input
Negative input leakage current

I

lkg

on analog pins
Sampling switch resistance 1 kΩ

ADC

Internal sample and hold

ADC

capacitor

V

< V

| I

SS,

| < 400 µA

IN

IN

on adjacent analog pin

(2)(3)

TBD

56µA

5.9 µs

Calibration time f

CAL

t

Injection conversion latency f

lat

t

Sampling time f

S

= 14MHz

ADC

= 14 MHz

ADC

= 14 MHz 0.107 17.1 µs

ADC

83 1/f

Power-up time 0 0 1 µs

kΩ

pF

5pF

0.214 µs
31/f

118µs

t

CONV

T otal conversion time (including
sampling time)

f

ADC

= 14 MHz

14 (1.5 for sampling
+12.5 for successive

1/f

approximation)

1. TBD = to be determined.

), C

2. Depending on the input signal variation (f
allow the use of a larger serial resistor (R

3. During the sample time the input capacitance C
source. The internal resistance of the analog source must allow the capacitance to reach its final voltage
level within t
the conversion result. Values for the sample clock tS depend on programming.

Table 40. ADC accuracy (f

After the end of the sample time tS, changes of the analog input voltage have no effect on

S.

(1)

3.3 V)

PCLK2

AIN
AIN

= 14 MHz, f

can be increased for stabilization time and reduced to

AIN

). It is valid for all f

(5 max) can be charged/discharged by the external

AIN

ADC

frequencies ≤ 14 MHz.

ADC

= 14 MHz, R

AIN

<10 kΩ, V

DDA

=

ADC

ADC

ADC

Symbol Parameter Conditions Typ Max Unit

(2)

(2)

(2)

INJ(PIN)

and ΣI

3TBD
1TBD
2TBD
3TBD
2TBD

in Section 5.3.12 does not

INJ(PIN)

LSB

| Total unadjusted error

|E

T

|E

| Offset error

O

|Gain Error

|E

G

| Differential linearity error

|E

D

|E

| Integral linearity error

L

1. TBD = to be determined.

2. ADC Accuracy vs. Negative Injection Current: Injecting negative current on any of the standard (non­robust) analog input pins should be avoided as this significantly reduces the accuracy of the conversion
being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to
standard analog pins which may potentially inject negative current.
Any positive injection current within the limits specified for I
affect the ADC accuracy.

(2)

(2)

55/67

Electrical characteristics STM32F103xx

Figure 23. ADC accuracy characteristics

E

G

1023
1022
1021

V

1LSB

IDEAL

7
6
5

E

4
3
2
1

O

0

1234567

V

SSA

DDAVSSA

--------------------------- ------------- -=

–

1024

E

1LSB

T

IDEAL

(2)

(3)

(1)

E

L

E

D

1021 102210231024

(1) Example of an actual transfer curve
(2) The ideal transfer curve
(3) End point correlation line

E

=Total Unadjusted Error: maximum deviation

T

between the actual and the ideal transfer curves.

=Offset Error: deviation between th e fir st actual

E

O

transition and the first ideal one.

=Gain Error: deviation between the last ideal

E

G

transition and the last actual one.

=Differential Linearity Error: maximum deviation

E

D

between actual steps and the ideal one.

=Integral Linearity Error: maximum deviation

E

L

between any actual transition and the end point
correlation line.

V

DDA

ai14395

Figure 24. Typical connection diagram using the ADC

V

DD

V

T

R

AIN

V

AIN

AINx

(1)

C

AIN

0.6V

V

0.6V

R

ADC

T

IL±1mA

12-bit A/D
conversion

STM32F103xx

C

ADC

1. Refer to Table 39 for the values of R

2. C

PARASITIC

PCB layout quality) plus the pad capacitance (3 pF). A high C
accuracy. To remedy this, f

must be added to C

ADC

AIN

should be reduced.

ADC

and C

ADC

.

. It represents the capacitance of the PCB (dependent on soldering and

PARASITIC

ai14150

value will downgrade conversion

56/67

STM32F103xx Electrical characteristics

General PCB design guidelines

Po wer supply decoupling should be performed as shown in Figure 25 or Figure 26,
depending on whether V
ceramic (good quality). They should be placed them as close as possible to the chip.

is connected to V

REF+

or not. The 10 nF capacitors should be

DDA

Figure 25. Power supply and reference decoupling (V

STM32F103xx

V

REF+

(see note 1)

1. V

REF+

and V

1 µF // 10 nF

1 µF // 10 nF

inputs are available only on 100-pin packages.

REF–

V

DDA

V

SSA/VREF+

Figure 26. Power supply and reference decoupling (V

STM32F103xx

not connected to V

REF+

(see note 1)

connected to V

REF+

ai14388

DDA

DDA

)

)

1. V

REF+

and V

1 µF // 10 nF

inputs are available only on 100-pin packages.

REF–

57/67

V

REF+/VDDA

(See note 1)

V

REF–/VSSA

(See note 1)

ai14389

Electrical characteristics STM32F103xx

5.3.18 Temperature sensor characteristics

Table 41. TS characteristics

Symbol Parameter Conditions Min Typ Max Unit

T

L

V

linearity with temperature

SENSE

±1.5

°C

Avg_Slope Average slope 4.478 mV/°C

V

25

t

START

V o ltage at 25 °C 1.4 V
Startup time 4 10 µs

58/67

STM32F103xx Package characteristics

6 Package characteristics

Figure 27. LFBGA100 - low profile fine pitch ball grid array package outline

Seating plane

C

A2 A4 A3 A1 A

e

Bottom view

D
D1

F

F

e

b

∅

(100 balls)

eee

CA

∅

M

∅

fff

CM

B

K

J
H
G

F

E
D
C

B

A

12345678910

A1 corner index area

(see note 5)

Table 42. LFBGA100 - low profile fine pitch ball grid ar ray package mechan ic al data

mm inches

Dim.

Min Typ Max Min Typ Max

ddd

C

A

E

E1

B

ai14396

A 1.700 0.067
A1 0.270 0.011
A2 1.085 0.043
A3 0.30 0.012
A4 0.80 0.031
b 0.45 0.50 0.55 0.018 0.020 0.022
D 9.85 10.00 10.15 0.388 0.394 0.40
D1 7.20 0.283
E 9.85 10.00 10.15 0.388 0.394 0.40
E1 7.20 0.283
e 0.80 0.031
F 1.40 0.055
ddd 0.12 0.005
eee 0.15 0.006
fff 0.08 0.003
N (number of balls) 100

59/67

Package characteristics STM32F103xx

Figure 28. Recommended PCB design rules (0.80/0.75 mm pitch BGA)

Dpad 0.37 mm
Dsm
Solder paste 0.37 mm aperture diameter

– Non solder mask defined pads are recommended
– 4 to 6 mils screen print

Dpad

Dsm

0.52 mm typ. (depends on solder
mask registration tolerance

60/67

STM32F103xx Package characteristics

Figure 29. LQFP100 – 100-pin low-profile quad flat package outline

A

A

2

A1

b

e

D1

D

E

E

1

L

1

L

Table 43. LQFP100 – 100-pin low-profile quad flat package mechanical data

c

h

ai14397

mm inches

Dim.

Min Typ Max Min Typ Max

A 1.60 0.063
A1 0.05 0.15 0.002 0.006
A2 1.35 1.40 1.45 0.053 0.055 0.057

b 0.17 0.22 0.27 0.007 0.009 0.011

C 0.09 0.20 0.004 0.008

D 16.00 0.630
D1 14.00 0.551

E 16.00 0.630
E1 14.00 0.551

e 0.50 0.020

θ 0° 3.5° 7° 0° 3.5° 7°

L 0.45 0.60 0.75 0.018 0.024 0.030
L1 1.00 0.039

Number of pins

N 100

61/67

Package characteristics STM32F103xx

Figure 30. LQFP64 – 64 pin low-profile quad flat package outline

D1

D

E1

E

A

A2

A1

b

e

L1

L

ai14398

Table 44. LQFP64 – 64 pin low-profile quad flat package mechanical data

mm inches

Dim.

Min Typ Max Min Typ Max

A 1.60 0.063
A1 0.05 0.15 0.002 0.006
A2 1.35 1.40 1.45 0.053 0.055 0.057

b 0.17 0.22 0.27 0.007 0.009 0.011

c 0.09 0.20 0.004 0.008

D 12.00 0.472
D1 10.00 0.394

E 12.00 0.472
E1 10.00 0.394

e 0.50 0.020

c

θ 0° 3.5° 7° 0° 3.5° 7°

L 0.45 0.60 0.75 0.018 0.024 0.030
L1 1.00 0.039

N64

62/67

Number of pins

STM32F103xx Package characteristics

Figure 31. LQFP48 – 48 pin low-profile quad flat package outline

D

D1

b

EE1

Table 45. LQFP48 – 48 pin low-profile quad flat package mechanical data

e

L1

mm inches

A

A2

A1

c

L

ai14399

(1)

Dim.

Min Typ Max Min Typ Max

A 1.60 0.063
A1 0.05 0.15 0.002 0.006
A2 1.35 1.40 1.45 0.053 0.055 0.057

b 0.17 0.22 0.27 0.007 0.009 0.011

C 0.09 0.20 0.004 0.008

D 9.00 0.354
D1 7.00 0.276

E 9.00 0.354
E1 7.00 0.276

e 0.50 0.020

θ 0° 3.5° 7° 0° 3.5° 7°

L 0.45 0.60 0.75 0.018 0.024 0.030
L1 1.00 0.039

Number of pins

N48

1. Values in inches are converted from mm and rounded to 3 decimal digits.

63/67

Package characteristics STM32F103xx

6.1 Thermal characteristics

The avera ge chip-ju nction temp era ture , TJ, in degrees Celsius, ma y be calculat ed using the
following equation:

T

= TA + (PD x ΘJA) (1)

J

Where:

● T

● Θ

● P

● P

P
Most of the time for the application P

may be significant if the device is configured to drive continuously external modules and/or
memories.

is the Ambient Temperature in ° C,

A

is the Package Junction-to-Ambient Thermal Resistance, in °C/W,

JA

is the sum of P

D

is the product of I

INT

represents the Power Dissipation on Input and Output Pins;

I/O

INT

and P

and VDD, expressed in Watts. This is the Chip Internal Power.

DD

I/O (PD

I/O< PINT

= P

INT

+ P

I/O

),

and can be neglected. On the other han d, P

I/O

An approximate relationship between P

P

= K / (TJ + 273 °C) (2)

D

and TJ (if P

D

is neglected) is given by:

I/O

Therefore (solving equations 1 and 2):

K = P

x (TA + 273°C) + ΘJA x P

D

2

D

(3)
where:
K is a constant for the particular part, which may be determined from equation (3) by

measuring P
may be obtained by solving equations (1) and (2) iteratively for any value of T

Table 46. Thermal characteristics

Symbol Parameter Value Unit

Θ

JA

(at equilibrium) for a known TA. Using this value of K, the values of PD and TJ

D

Thermal resistance junction-ambient

LFBGA100 - 10 x 10 mm / 0.5 mm pitch

Thermal resistance junction-ambient

LQFP100 - 14 x 14 mm / 0.5 mm pitch

Thermal Resistance Junction-Ambient

LQFP64 - 10 x 10 mm / 0.5 mm pitch

Thermal resistance junction-ambient

LQFP48 - 7 x 7 mm / 0.5 mm pitch

41

46

45

55

.

A

°C/W

64/67

STM32F103xx Order codes

7 Order codes

Table 47. Order codes

Flash program

Part number

STM32F103C6T6 32 10
STM32F103C8T6 64 20
STM32F103R6T6 32 10

STM32F103RBT6 128 20

STM32F103V8T6 64 20
STM32F103VBT6 128 20
STM32F103V8H6 64 20

STM32F103VBH6 128 20

memory

Kbytes

7.1 Future family enhancements

Further developments of the STM32F103xx performance line will see an expansion of the
current options. Larger packages will soon be available with up to 512KB Flash, 64KB
SRAM and with extended features such as EMI support, SDIO, I2S, DA C and additional
timers and USARTS.

SRAM

memory

Kbytes

Package

LQFP48

LQFP64STM32F103R8T6 64 20

LQFP100

LFBGA100

65/67