STM32F103xC STM32F103xD
FBGA
LQFP64 10 × 10 mm,
LQFP100 14 × 14 mm,
LQFP144 20 × 20 mm
LFBGA100 10 × 10 mm
LFBGA144 10 × 10 mm
WLCSP64
STM32F103xE
High-density performance line ARM-based 32-bit MCU with 256 to
512KB Flash, USB, CAN, 11 timers, 3 ADCs, 13 communication interfaces
Features
■ Core: ARM 32-bit Cortex™-M3 CPU
– 72 MHz maximum frequency,
1.25 DMIPS/MHz (Dhrystone 2.1)
performance at 0 wait state memory
access
– Single-cycle multiplication and hardware
division
■ Memories
– 256 to 512 Kbytes of Flash memory
– up to 64 Kbytes of SRAM
– Flexible static memory controller with 4
Chip Select. Supports Compact Flash,
SRAM, PSRAM, NOR and NAND
– LCD parallel interface, 8080/6800 modes
■ Clock, reset and supply management
– 2.0 to 3.6 V application supply and I/Os
– POR, PDR, and programmable voltage
detector (PVD)
– 4-to-16 MHz crystal oscillator
– Internal 8 MHz factory-trimmed RC
– Internal 40 kHz RC with calibration
– 32 kHz oscillator for RTC with calibration
■ Low power
– Sleep, Stop and Standby modes
–V
■ 3 × 12-bit, 1 µs A/D converters (up to 21
supply for RTC and backup registers
BAT
channels)
– Conversion range: 0 to 3.6 V
– Triple-sample and hold capability
– Temperature sensor
■ 2 × 12-bit D/A converters
■ DMA: 12-channel DMA controller
– Supported peripherals: timers, ADCs, DAC,
SDIO, I
■ Debug mode
2
Ss, SPIs, I2Cs and USARTs
– Serial wire debug (SWD) & JTAG interfaces
– Cortex-M3 Embedded Trace Macrocell™
memories
■ Up to 112 fast I/O ports
– 51/80/112 I/Os, all mappable on 16
external interrupt vectors and almost all
5 V-tolerant
■ Up to 11 timers
– Up to four 16-bit timers, each with up to 4
IC/OC/PWM or pulse counter and
quadrature (incremental) encoder input
– 2 × 16-bit motor control PWM timers with
dead-time generation and emergency stop
– 2 × watchdog timers (Independent and
Window)
– SysTick timer: a 24-bit downcounter
– 2 × 16-bit basic timers to drive the DAC
■ Up to 13 communication interfaces
– Up to 2 × I
2
C interfaces (SMBus/PMBus)
– Up to 5 USARTs (ISO 7816 interface, LIN,
IrDA capability, modem control)
– Up to 3 SPIs (18 Mbit/s), 2 with I
interface multiplexed
– CAN interface (2.0B Active)
– USB 2.0 full speed interface
– SDIO interface
■ CRC calculation unit, 96-bit unique ID
■ ECOPACK
Table 1. Device summary
Reference Part number
STM32F103xC
STM32F103xD
STM32F103xE
®
packages
STM32F103RC STM32F103VC
STM32F103ZC
STM32F103RD STM32F103VD
STM32F103ZD
STM32F103RE STM32F103ZE
STM32F103VE
2
S
April 2011 Doc ID 14611 Rev 8 1/130
www.st.com
1
Contents STM32F103xC, STM32F103xD, STM32F103xE
Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.1 Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.2 Full compatibility throughout the family . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.3 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.3.1 ARM® Cortex™-M3 core with embedded Flash and SRAM . . . . . . . . . 15
2.3.2 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.3.3 CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . 15
2.3.4 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.3.5 FSMC (flexible static memory controller) . . . . . . . . . . . . . . . . . . . . . . . . 15
2.3.6 LCD parallel interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.3.7 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 16
2.3.8 External interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . 16
2.3.9 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.3.10 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.3.11 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.3.12 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.3.13 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.3.14 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.3.15 DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.3.16 RTC (real-time clock) and backup registers . . . . . . . . . . . . . . . . . . . . . . 18
2.3.17 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.3.18 I²C bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.3.19 Universal synchronous/asynchronous receiver transmitters (USARTs) 21
2.3.20 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.3.21 Inter-integrated sound (I
2
S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.3.22 SDIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.3.23 Controller area network (CAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.3.24 Universal serial bus (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.3.25 GPIOs (general-purpose inputs/outputs) . . . . . . . . . . . . . . . . . . . . . . . . 22
2.3.26 ADC (analog to digital converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.3.27 DAC (digital-to-analog converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.3.28 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
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2.3.29 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.3.30 Embedded Trace Macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3 Pinouts and pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
5.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
5.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
5.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
5.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
5.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
5.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
5.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
5.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
5.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
5.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
5.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
5.3.2 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 43
5.3.3 Embedded reset and power control block characteristics . . . . . . . . . . . 43
5.3.4 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
5.3.5 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
5.3.6 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
5.3.7 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
5.3.8 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
5.3.9 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
5.3.10 FSMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
5.3.11 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
5.3.12 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . . 84
5.3.13 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
5.3.14 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
5.3.15 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
5.3.16 TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
5.3.17 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
5.3.18 CAN (controller area network) interface . . . . . . . . . . . . . . . . . . . . . . . . 102
5.3.19 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
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5.3.20 DAC electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
5.3.21 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
6 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
6.1 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
6.2 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
6.2.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
6.2.2 Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . . 121
7 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
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STM32F103xC, STM32F103xD, STM32F103xE List of tables
List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. STM32F103xC, STM32F103xD and STM32F103xE features and peripheral counts . . . . 11
Table 3. STM32F103xx family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 4. High-density timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 5. High-density STM32F103xx pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 6. FSMC pin definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 7. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 8. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 9. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 10. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 11. Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 12. Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 13. Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 14. Maximum current consumption in Run mode, code with data processing
running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 15. Maximum current consumption in Run mode, code with data processing
running from RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 16. Maximum current consumption in Sleep mode, code running from Flash or RAM. . . . . . . 47
Table 17. Typical and maximum current consumptions in Stop and Standby modes . . . . . . . . . . . . 48
Table 18. Typical current consumption in Run mode, code with data processing
running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 19. Typical current consumption in Sleep mode, code running from Flash or
RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 20. Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 21. High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 22. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 23. HSE 4-16 MHz oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 24. LSE oscillator characteristics (f
Table 25. HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 26. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 27. Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 28. PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 29. Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 30. Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 31. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings . . . . . . . . . . . . . . . . . . 64
Table 32. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . 65
Table 33. Asynchronous multiplexed PSRAM/NOR read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Table 34. Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 35. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Table 36. Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Table 37. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . 73
Table 38. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Table 39. Switching characteristics for PC Card/CF read and write cycles . . . . . . . . . . . . . . . . . . . . 79
Table 40. Switching characteristics for NAND Flash read and write cycles . . . . . . . . . . . . . . . . . . . . 82
Table 41. EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Table 42. EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Table 43. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Table 44. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
= 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
LSE
Doc ID 14611 Rev 8 5/130
List of tables STM32F103xC, STM32F103xD, STM32F103xE
Table 45. I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Table 46. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Table 47. Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Table 48. I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Table 49. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Table 50. TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Table 51. I
Table 52. SCL frequency (f
Table 53. SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Table 54. I
2
C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
= 36 MHz.,VDD = 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
PCLK1
2
S characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Table 55. SD / MMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Table 56. USB startup time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Table 57. USB DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Table 58. USB: full-speed electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Table 59. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Table 60. R
max for f
AIN
= 14 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
ADC
Table 61. ADC accuracy - limited test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Table 62. ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Table 63. DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Table 64. TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Table 65. Recommended PCB design rules (0.80/0.75 mm pitch BGA) . . . . . . . . . . . . . . . . . . . . . 112
Table 66. LFBGA144 – 144-ball low profile fine pitch ball grid array, 10 x 10 mm,
0.8 mm pitch, package data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Table 67. LFBGA100 - 10 x 10 mm low profile fine pitch ball grid array package
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Table 68. WLCSP, 64-ball 4.466 × 4.395 mm, 0.500 mm pitch, wafer-level chip-scale
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Table 69. Recommended PCB design rules (0.5mm pitch BGA) . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Table 70. LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package mechanical data . . . . . . . 117
Table 71. LQPF100 – 14 x 14 mm 100-pin low-profile quad flat package mechanical data. . . . . . . 118
Table 72. LQFP64 – 10 x 10 mm 64 pin low-profile quad flat package mechanical data. . . . . . . . . 119
Table 73. Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Table 74. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
6/130 Doc ID 14611 Rev 8
STM32F103xC, STM32F103xD, STM32F103xE List of figures
List of figures
Figure 1. STM32F103xC, STM32F103xD and STM32F103xE performance line block diagram . . . 12
Figure 2. Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 3. STM32F103xC and STM32F103xE performance line BGA144 ballout . . . . . . . . . . . . . . . 24
Figure 4. STM32F103xC and STM32F103xE performance line BGA100 ballout . . . . . . . . . . . . . . . 25
Figure 5. STM32F103xC and STM32F103xE performance line LQFP144 pinout. . . . . . . . . . . . . . . 26
Figure 6. STM32F103xC and STM32F103xE performance line LQFP100 pinout. . . . . . . . . . . . . . . 27
Figure 7. STM32F103xC and STM32F103xE performance line
LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 8. STM32F103xC and STM32F103xE performance line
WLCSP64 ballout, ball side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 9. Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 10. Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 11. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 12. Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 13. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 14. Typical current consumption in Run mode versus frequency (at 3.6 V) -
code with data processing running from RAM, peripherals enabled . . . . . . . . . . . . . . . . . 46
Figure 15. Typical current consumption in Run mode versus frequency (at 3.6 V)-
code with data processing running from RAM, peripherals disabled . . . . . . . . . . . . . . . . 46
Figure 16. Typical current consumption on V
values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 17. Typical current consumption in Stop mode with regulator in run mode
versus temperature at different V
Figure 18. Typical current consumption in Stop mode with regulator in low-power
mode versus temperature at different V
Figure 19. Typical current consumption in Standby mode versus temperature at
different V
values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
DD
Figure 20. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 21. Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Figure 22. Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 23. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Figure 24. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . . 64
Figure 25. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . . 65
Figure 26. Asynchronous multiplexed PSRAM/NOR read waveforms. . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 27. Asynchronous multiplexed PSRAM/NOR write waveforms . . . . . . . . . . . . . . . . . . . . . . . . 68
Figure 28. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Figure 29. Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Figure 30. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . 73
Figure 31. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Figure 32. PC Card/CompactFlash controller waveforms for common memory read access . . . . . . . 75
Figure 33. PC Card/CompactFlash controller waveforms for common memory write access . . . . . . . 76
Figure 34. PC Card/CompactFlash controller waveforms for attribute memory read
access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Figure 35. PC Card/CompactFlash controller waveforms for attribute memory write
access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Figure 36. PC Card/CompactFlash controller waveforms for I/O space read access . . . . . . . . . . . . . 78
Figure 37. PC Card/CompactFlash controller waveforms for I/O space write access . . . . . . . . . . . . . 79
Figure 38. NAND controller waveforms for read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
with RTC on vs. temperature at different V
BAT
values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
DD
values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
DD
BAT
Doc ID 14611 Rev 8 7/130
List of figures STM32F103xC, STM32F103xD, STM32F103xE
Figure 39. NAND controller waveforms for write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Figure 40. NAND controller waveforms for common memory read access . . . . . . . . . . . . . . . . . . . . . 81
Figure 41. NAND controller waveforms for common memory write access . . . . . . . . . . . . . . . . . . . . . 82
Figure 42. Standard I/O input characteristics - CMOS port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Figure 43. Standard I/O input characteristics - TTL port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Figure 44. 5 V tolerant I/O input characteristics - CMOS port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Figure 45. 5 V tolerant I/O input characteristics - TTL port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Figure 46. I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Figure 47. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Figure 48. I
Figure 49. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Figure 50. SPI timing diagram - slave mode and CPHA = 1
Figure 51. SPI timing diagram - master mode
Figure 52. I
Figure 53. I
2
C bus AC waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
(1)
(1)
2
S slave timing diagram (Philips protocol)
2
S master timing diagram (Philips protocol)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
(1)
(1)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Figure 54. SDIO high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Figure 55. SD default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Figure 56. USB timings: definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Figure 57. ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Figure 58. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Figure 59. Power supply and reference decoupling (V
Figure 60. Power supply and reference decoupling (V
not connected to V
REF+
connected to V
REF+
). . . . . . . . . . . . . 106
DDA
). . . . . . . . . . . . . . . . 107
DDA
Figure 61. 12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Figure 62. BGA pad footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Figure 63. LFBGA144 – 144-ball low profile fine pitch ball grid array, 10 x 10 mm,
0.8 mm pitch, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Figure 64. LFBGA100 - 10 x 10 mm low profile fine pitch ball grid array package
outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Figure 65. WLCSP, 64-ball 4.466 × 4.395 mm, 0.500 mm pitch, wafer-level chip-scale
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Figure 66. BGA pad footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Figure 67. LQFP144, 20 x 20 mm, 144-pin low-profile quad
flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Figure 68. Recommended footprint
Figure 69. LQFP100, 14 x 14 mm 100-pin low-profile quad flat package outline . . . . . . . . . . . . . . . 118
Figure 70. Recommended footprint
Figure 71. LQFP64 – 10 x 10 mm 64 pin low-profile quad flat package outline . . . . . . . . . . . . . . . . 119
Figure 72. Recommended footprint
Figure 73. LQFP100 P
max vs. TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
D
(1)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
(1)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
(1)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
8/130 Doc ID 14611 Rev 8
STM32F103xC, STM32F103xD, STM32F103xE Introduction
1 Introduction
This datasheet provides the ordering information and mechanical device characteristics of
the STM32F103xC, STM32F103xD and STM32F103xE high-density performance line
microcontrollers. For more details on the whole STMicroelectronics STM32F103xx family,
please refer to Section 2.2: Full compatibility throughout the family.
The high-density STM32F103xx datasheet should be read in conjunction with the
STM32F10xxx reference manual.
For information on programming, erasing and protection of the internal Flash memory
please refer to the STM32F10xxx Flash programming manual.
The reference and Flash programming manuals are both available from the
STMicroelectronics website www.st.com.
For information on the Cortex™-M3 core please refer to the Cortex™-M3 Technical
Reference Manual, available from the www.arm.com website at the following address:
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0337e/.
Doc ID 14611 Rev 8 9/130
Description STM32F103xC, STM32F103xD, STM32F103xE
2 Description
The STM32F103xC, STM32F103xD and STM32F103xE performance line family
incorporates the high-performance ARM
®
Cortex™-M3 32-bit RISC core operating at a
72 MHz frequency, high-speed embedded memories (Flash memory up to 512 Kbytes and
SRAM up to 64 Kbytes), and an extensive range of enhanced I/Os and peripherals
connected to two APB buses. All devices offer three 12-bit ADCs, four general-purpose 16bit timers plus two PWM timers, as well as standard and advanced communication
interfaces: up to two I
2
Cs, three SPIs, two I2Ss, one SDIO, five USARTs, an USB and a
CAN.
The STM32F103xx high-density performance line family operates in the –40 to +105 °C
temperature range, from a 2.0 to 3.6 V power supply. A comprehensive set of power-saving
mode allows the design of low-power applications.
These features make the STM32F103xx high-density performance line microcontroller
family suitable for a wide range of applications such as motor drives, application control,
medical and handheld equipment, PC and gaming peripherals, GPS platforms, industrial
applications, PLCs, inverters, printers, scanners, alarm systems video intercom, and HVAC.
10/130 Doc ID 14611 Rev 8
STM32F103xC, STM32F103xD, STM32F103xE Description
2.1 Device overview
The STM32F103xx high-density performance line family offers devices in six different
package types: from 64 pins to 144 pins. Depending on the device chosen, different sets of
peripherals are included, the description below gives an overview of the complete range of
peripherals proposed in this family.
Figure 1 shows the general block diagram of the device family.
Table 2. STM32F103xC, STM32F103xD and STM32F103xE features and peripheral
counts
Peripherals STM32F103Rx STM32F103Vx STM32F103Zx
Flash memory in Kbytes 256 384 512 256 384 512 256 384 512
SRAM in Kbytes 48 64
FSMC No Yes
General-purpose 4
Timers
Advanced-control 2
Basic 2
SPI(I2S)
2
I
(3)
C2
(1)
48 64 48 64
(2)
Ye s
3(2)
Comm
USART 5
USB 1
CAN 1
SDIO 1
GPIOs 51 80 112
12-bit ADC
Number of channels
12-bit DAC
Number of channels
16
3
16
3
3
21
2
2
CPU frequency 72 MHz
Operating voltage 2.0 to 3.6 V
Operating temperatures
Ambient temperatures: –40 to +85 °C /–40 to +105 °C (see Ta b le 1 0 )
Junction temperature: –40 to + 125 °C (see Ta b le 1 0)
Package LQFP64, WLCSP64 LQFP100, BGA100 LQFP144, BGA144
1. 64 KB RAM for 256 KB Flash are available on devices delivered in CSP packages only.
2. For the LQFP100 and BGA100 packages, only FSMC Bank1 and Bank2 are available. Bank1 can only
support a multiplexed NOR/PSRAM memory using the NE1 Chip Select. Bank2 can only support a 16- or
8-bit NAND Flash memory using the NCE2 Chip Select. The interrupt line cannot be used since Port G is
not available in this package.
3. The SPI2 and SPI3 interfaces give the flexibility to work in an exclusive way in either the SPI mode or the
I2S audio mode.
Doc ID 14611 Rev 8 11/130
Description STM32F103xC, STM32F103xD, STM32F103xE
Figure 1. STM32F103xC, STM32F103xD and STM32F103xE performance line block diagram
TRACECLK
TRACED[0:3]
as AS
NJTRST
JTDI
JTCK/SWCLK
JTMS/SWDIO
JTDO
as AF
A[25:0]
D[15:0]
CLK
NOE
NWE
NE[4:1]
NBL[1:0]
NWAIT
NL (or NADV)
as AF
D[7:0]
CMD
CK as AF
112AF
PA[15:0]
PB[15:0]
PC[15:0]
PD[15:0]
PE[15:0]
PF[15:0]
PG[15:0]
4 channels
3 compl. channels
BKIN, ETR as AF
4 channels
3 compl. channels
BKIN, ETR as AF
MOSI, MISO,
SCK, NSS as AF
RX, TX, CTS,
RTS, CK as AF
8 ADC123_INs
common to the 3 ADCs
8 ADC12_INs common
to ADC1 & ADC2
5 ADC3_INs on ADC3
V
REF–
V
REF+
TPIU
Trace/trig
SW/JTAG
Cortex-M3 CPU
F
: 48/72 MHz
max
NVIC
GP DMA1
7 channels
GP DMA2
5 channels
EXT.IT
WKUP
GPIO port A
GPIO port B
GPIO port C
GPIO port D
GPIO port E
GPIO port F
GPIO port G
TIM1
TIM8
SPI1
USART1
Temp. sensor
12-bit ADC1
12-bit ADC2
12-bit ADC3
@ V
DDA
FSMC
SDIO
IF
IF
IF
Pbus
Dbus
System
Ibus
Bus Matrix
APB2: Fmax = 48/72 MHz
Trace
controller
AHB2
APB2
obl
Flash 512 Kbytes
Flash
interface
SRAM
64 KB
Reset &
Clock
control
AHB: Fmax = 48/72 MHz
AHB2
APB1
64 bit
SRAM 512 B
WWDG
TIM6
TIM7
RC 8 MHz
RC 40 kHz
PCLK1
PCLK2
HCLK
FCLK
@V
PLL
DDA
POR
Reset
= 24/36 MHz
max
APB1: F
V
DD
Supply
supervision
POR / PDR
Int
Standby
interface
RTC
AWU
Backup interface
SPI2 / I2 S2
2x(8x16bit)
SPI3 / I2S3
2x(8x16bit)
bxCAN device
USB 2.0 FS
device
IFIF
IF
@V
@V
DD
Power
Volt. reg.
3.3 V to 1.8 V
@V
DDA
PVD
@V
DD
XTAL OSC
4-16 MHz
IWDG
V
@
BAT
XTAL 32kHz
Backup
reg
TIM2
TIM3
TIM4
TIM5
USART 2
USART 3
UART4
UART5
I2C1
I2C2
12bit DAC1
12bit DAC 2
DDA
V
SS
NRST
V
DDA
V
SSA
OSC_IN
OSC_OUT
V
=1.8 V to 3.6 V
BAT
OSC32_IN
OSC32_OUT
TAMPER-RTC/
ALARM/SECOND OUT
4 channels, ETR as AF
4 channels, ETR as AF
4 channels, ETR as AF
4 channels as AF
RX, TX, CTS, RTS,
CK as AF
RX, TX, CTS, RT S,
CK as AF
RX,TX as AF
RX,TX as AF
MOSI/SD, MISO
SCK/CK, MCK, NSS/WS as AF
MOSI/SD, MISO
SCK/CK, MCK, NSS/WS as AF
SCL, SDA, SMBA as AF
SCL, SDA, SMBA as AF
USBDP/CAN_TX
USBDM/CAN_RX
DAC_OUT1 as AF
DAC_OUT2 as AF
ai14666f
1. TA = –40 °C to +85 °C (suffix 6, see Table 74) or –40 °C to +105 °C (suffix 7, see Table 74), junction temperature up to
105 °C or 125 °C, respectively.
2. AF = alternate function on I/O port pin.
12/130 Doc ID 14611 Rev 8
STM32F103xC, STM32F103xD, STM32F103xE Description
HSE OSC
4-16 MHz
OSC_IN
OSC_OUT
OSC32_IN
OSC32_OUT
LSE OSC
32.768 kHz
HSI RC
8 MHz
LSI RC
40 kHz
to Independent Watchdog (IWDG)
PLL
x2, x3, x4
PLLMUL
HSE = High Speed External clock signal
LSE = Low Speed External clock signal
LSI = Low Speed Internal clock signal
HSI = High Speed Internal clock signal
Legend:
MCO
Clock Output
Main
PLLXTPRE
/2
..., x16
AHB
Prescaler
/1, 2..512
/2
PLLCLK
HSI
HSE
APB1
Prescaler
/1, 2, 4, 8, 16
ADC
Prescaler
/2, 4, 6, 8
ADCCLK
PCLK1
HCLK
PLLCLK
to AHB bus, core,
memory and DMA
USBCLK
to USB interface
USB
Prescaler
/1, 1.5
to ADC1, 2 or 3
LSE
LSI
HSI
/128
/2
HSI
HSE
peripherals
to APB1
Peripheral Clock
Enable (20 bits)
Enable (6 bits)
Peripheral Clock
APB2
Prescaler
/1, 2, 4, 8, 16
PCLK2
TIM1 & 8 timers
to TIM1 and TIM8
peripherals to APB2
Peripheral Clock
Enable (15 bits)
Enable (2 bit)
Peripheral Clock
48 MHz
72 MHz max
72 MHz
72 MHz max
36 MHz max
to RTC
PLLSRC
SW
MCO
CSS
to Cortex System timer
/8
Clock
Enable (4 bits)
SYSCLK
max
RTCCLK
RTCSEL[1:0]
TIMxCLK
TIMXCLK
IWDGCLK
SYSCLK
FCLK Cortex
free running clock
/2
TIM2,3,4,5,6,7
to TIM2,3,4,5,6 and 7
To SDIO AHB interface
Peripheral clock
enable
HCLK/2
to FSMC
FSMCCLK
to SDIO
Peripheral clock
enable
Peripheral clock
enable
to I2S3
to I2S2
Peripheral clock
enable
Peripheral clock
enable
I2S3CLK
I2S2CLK
SDIOCLK
ai14752b
If (APB1 prescaler =1) x1
else x2
If (APB2 prescaler =1) x1
else x2
FLITFCLK
to Flash programming interface
Figure 2. Clock tree
1. When the HSI is used as a PLL clock input, the maximum system clock frequency that can be achieved is
64 MHz.
2. For the USB function to be available, both HSE and PLL must be enabled, with the USBCLK at 48 MHz.
3. To have an ADC conversion time of 1 µs, APB2 must be at 14 MHz, 28 MHz or 56 MHz.
Doc ID 14611 Rev 8 13/130
Description STM32F103xC, STM32F103xD, STM32F103xE
2.2 Full compatibility throughout the family
The STM32F103xx is a complete family whose members are fully pin-to-pin, software and
feature compatible. In the reference manual, the STM32F103x4 and STM32F103x6 are
identified as low-density devices, the STM32F103x8 and STM32F103xB are referred to as
medium-density devices and the STM32F103xC, STM32F103xD and STM32F103xE are
referred to as high-density devices.
Low-density and high-density devices are an extension of the STM32F103x8/B mediumdensity devices, they are specified in the STM32F103x4/6 and STM32F103xC/D/E
datasheets, respectively. Low-density devices feature lower Flash memory and RAM
capacities, less timers and peripherals. High-density devices have higher Flash memory
and RAM capacities, and additional peripherals like SDIO, FSMC, I
remaining fully compatible with the other members of the family.
The STM32F103x4, STM32F103x6, STM32F103xC, STM32F103xD and STM32F103xE
are a drop-in replacement for the STM32F103x8/B devices, allowing the user to try different
memory densities and providing a greater degree of freedom during the development cycle.
Moreover, the STM32F103xx performance line family is fully compatible with all existing
STM32F101xx access line and STM32F102xx USB access line devices.
Table 3. STM32F103xx family
2
S and DAC while
Low-density devices Medium-density devices High-density devices
Pinout
16 KB
Flash
32 KB
Flash
(1)
64 KB
Flash
128 KB
Flash
256 KB
Flash
384 KB
Flash
512 KB
Flash
6 KB RAM 10 KB RAM 20 KB RAM 20 KB RAM 48 RAM 64 KB RAM 64 KB RAM
144 5 × USARTs
100
2 × USARTs
64
2 × 16-bit timers
1 × SPI, 1 × I
48
CAN, 1 × PWM timer
2 × ADCs
36
1. For orderable part numbers that do not show the A internal code after the temperature range code (6 or 7),
the reference datasheet for electrical characteristics is that of the STM32F103x8/B medium-density
devices.
2. Ports F and G are not available in devices delivered in 100-pin packages.
2
C, USB,
3 × USARTs
3 × 16-bit timers
2 × SPIs, 2 × I
2
Cs, USB,
CAN, 1 × PWM timer
2 × ADCs
4 × 16-bit timers, 2 × basic timers
3 × SPIs, 2 × I
2
Ss, 2 × I2Cs
USB, CAN, 2 × PWM timers
3 × ADCs, 2 × DACs, 1 × SDIO
FSMC (100- and 144-pin packages
(2)
)
14/130 Doc ID 14611 Rev 8
STM32F103xC, STM32F103xD, STM32F103xE Description
2.3 Overview
2.3.1 ARM® Cortex™-M3 core with embedded Flash and SRAM
The ARM Cortex™-M3 processor is the latest generation of ARM processors for embedded
systems. It has been developed to provide a low-cost platform that meets the needs of MCU
implementation, with a reduced pin count and low-power consumption, while delivering
outstanding computational performance and an advanced system response to interrupts.
The ARM Cortex™-M3 32-bit RISC processor features exceptional code-efficiency,
delivering the high-performance expected from an ARM core in the memory size usually
associated with 8- and 16-bit devices.
With its embedded ARM core, STM32F103xC, STM32F103xD and STM32F103xE
performance line family is compatible with all ARM tools and software.
Figure 1 shows the general block diagram of the device family.
2.3.2 Embedded Flash memory
Up to 512 Kbytes of embedded Flash is available for storing programs and data.
2.3.3 CRC (cyclic redundancy check) calculation unit
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit
data word and a fixed generator polynomial.
Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of
verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of
the software during runtime, to be compared with a reference signature generated at linktime and stored at a given memory location.
2.3.4 Embedded SRAM
Up to 64 Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0 wait
states.
2.3.5 FSMC (flexible static memory controller)
The FSMC is embedded in the STM32F103xC, STM32F103xD and STM32F103xE
performance line family. It has four Chip Select outputs supporting the following modes: PC
Card/Compact Flash, SRAM, PSRAM, NOR and NAND.
Functionality overview:
● The three FSMC interrupt lines are ORed in order to be connected to the NVIC
● Write FIFO
● Code execution from external memory except for NAND Flash and PC Card
● The targeted frequency, f
is at 72 MHz and external access is at 24 MHz when HCLK is at 48 MHz
, is HCLK/2, so external access is at 36 MHz when HCLK
CLK
Doc ID 14611 Rev 8 15/130
Description STM32F103xC, STM32F103xD, STM32F103xE
2.3.6 LCD parallel interface
The FSMC can be configured to interface seamlessly with most graphic LCD controllers. It
supports the Intel 8080 and Motorola 6800 modes, and is flexible enough to adapt to
specific LCD interfaces. This LCD parallel interface capability makes it easy to build costeffective graphic applications using LCD modules with embedded controllers or highperformance solutions using external controllers with dedicated acceleration.
2.3.7 Nested vectored interrupt controller (NVIC)
The STM32F103xC, STM32F103xD and STM32F103xE performance line embeds a nested
vectored interrupt controller able to handle up to 60 maskable interrupt channels (not
including the 16 interrupt lines of Cortex™-M3) and 16 priority levels.
● Closely coupled NVIC gives low latency interrupt processing
● Interrupt entry vector table address passed directly to the core
● Closely coupled NVIC core interface
● Allows early processing of interrupts
● Processing of late arriving higher priority interrupts
● Support for tail-chaining
● Processor state automatically saved
● Interrupt entry restored on interrupt exit with no instruction overhead
This hardware block provides flexible interrupt management features with minimal interrupt
latency.
2.3.8 External interrupt/event controller (EXTI)
The external interrupt/event controller consists of 19 edge detector lines used to generate
interrupt/event requests. Each line can be independently configured to select the trigger
event (rising edge, falling edge, both) and can be masked independently. A pending register
maintains the status of the interrupt requests. The EXTI can detect an external line with a
pulse width shorter than the Internal APB2 clock period. Up to 112 GPIOs can be connected
to the 16 external interrupt lines.
2.3.9 Clocks and startup
System clock selection is performed on startup, however the internal RC 8 MHz oscillator is
selected as default CPU clock on reset. An external 4-16 MHz clock can be selected, in
which case it is monitored for failure. If failure is detected, the system automatically switches
back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full
interrupt management of the PLL clock entry is available when necessary (for example with
failure of an indirectly used external oscillator).
Several prescalers allow the configuration of the AHB frequency, the high speed APB
(APB2) and the low speed APB (APB1) domains. The maximum frequency of the AHB and
the high speed APB domains is 72 MHz. The maximum allowed frequency of the low speed
APB domain is 36 MHz. See Figure 2 for details on the clock tree.
16/130 Doc ID 14611 Rev 8
STM32F103xC, STM32F103xD, STM32F103xE Description
2.3.10 Boot modes
At startup, boot pins are used to select one of three boot options:
● Boot from user Flash: you have an option to boot from any of two memory banks. By
default, boot from Flash memory bank 1 is selected. You can choose to boot from Flash
memory bank 2 by setting a bit in the option bytes.
● Boot from system memory
● Boot from embedded SRAM
The boot loader is located in system memory. It is used to reprogram the Flash memory by
using USART1.
2.3.11 Power supply schemes
● V
= 2.0 to 3.6 V: external power supply for I/Os and the internal regulator.
DD
Provided externally through V
● V
SSA
, V
= 2.0 to 3.6 V: external analog power supplies for ADC, DAC, Reset blocks,
DDA
RCs and PLL (minimum voltage to be applied to VDDA is 2.4 V when the ADC or DAC
● V
is used). V
= 1.8 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and backup
BAT
DDA
and V
must be connected to VDD and VSS, respectively.
SSA
registers (through power switch) when V
For more details on how to connect power pins, refer to Figure 12: Power supply scheme.
2.3.12 Power supply supervisor
The device has an integrated power-on reset (POR)/power-down reset (PDR) circuitry. It is
always active, and ensures proper operation starting from/down to 2 V. The device remains
in reset mode when V
external reset circuit.
The device features an embedded programmable voltage detector (PVD) that monitors the
V
DD/VDDA
generated when V
than the V
power supply and compares it to the V
DD/VDDA
threshold. The interrupt service routine can then generate a warning
PVD
message and/or put the MCU into a safe state. The PVD is enabled by software. Refer to
Table 12: Embedded reset and power control block characteristics for the values of
V
POR/PDR
and V
PVD
is below a specified threshold, V
DD
drops below the V
.
DD
pins.
is not present.
DD
POR/PDR
threshold. An interrupt can be
PVD
threshold and/or when VDD/V
PVD
, without the need for an
is higher
DDA
2.3.13 Voltage regulator
The regulator has three operation modes: main (MR), low power (LPR) and power down.
● MR is used in the nominal regulation mode (Run)
● LPR is used in the Stop modes.
● Power down is used in Standby mode: the regulator output is in high impedance: the
kernel circuitry is powered down, inducing zero consumption (but the contents of the
registers and SRAM are lost)
This regulator is always enabled after reset. It is disabled in Standby mode.
Doc ID 14611 Rev 8 17/130
Description STM32F103xC, STM32F103xD, STM32F103xE
2.3.14 Low-power modes
The STM32F103xC, STM32F103xD and STM32F103xE performance line supports three
low-power modes to achieve the best compromise between low power consumption, short
startup time and available wakeup sources:
● Sleep mode
In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can
wake up the CPU when an interrupt/event occurs.
● Stop mode
Stop mode achieves the lowest power consumption while retaining the content of
SRAM and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC
and the HSE crystal oscillators are disabled. The voltage regulator can also be put
either in normal or in low-power mode.
The device can be woken up from Stop mode by any of the EXTI line. The EXTI line
source can be one of the 16 external lines, the PVD output, the RTC alarm or the USB
wakeup.
● Standby mode
The Standby mode is used to achieve the lowest power consumption. The internal
voltage regulator is switched off so that the entire 1.8 V domain is powered off. The
PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering
Standby mode, SRAM and register contents are lost except for registers in the Backup
domain and Standby circuitry.
The device exits Standby mode when an external reset (NRST pin), an IWDG reset, a
rising edge on the WKUP pin, or an RTC alarm occurs.
Note: The RTC, the IWDG, and the corresponding clock sources are not stopped by entering Stop
or Standby mode.
2.3.15 DMA
The flexible 12-channel general-purpose DMAs (7 channels for DMA1 and 5 channels for
DMA2) are able to manage memory-to-memory, peripheral-to-memory and memory-toperipheral transfers. The two DMA controllers support circular buffer management,
removing the need for user code intervention when the controller reaches the end of the
buffer.
Each channel is connected to dedicated hardware DMA requests, with support for software
trigger on each channel. Configuration is made by software and transfer sizes between
source and destination are independent.
The DMA can be used with the main peripherals: SPI, I
and advanced-control timers TIMx, DAC, I
2
S, SDIO and ADC.
2
C, USART, general-purpose, basic
2.3.16 RTC (real-time clock) and backup registers
The RTC and the backup registers are supplied through a switch that takes power either on
V
supply when present or through the V
DD
registers used to store 84 bytes of user application data when V
They are not reset by a system or power reset, and they are not reset when the device
wakes up from the Standby mode.
pin. The backup registers are forty-two 16-bit
BAT
power is not present.
DD
The real-time clock provides a set of continuously running counters which can be used with
suitable software to provide a clock calendar function, and provides an alarm interrupt and a
18/130 Doc ID 14611 Rev 8
STM32F103xC, STM32F103xD, STM32F103xE Description
periodic interrupt. It is clocked by a 32.768 kHz external crystal, resonator or oscillator, the
internal low power RC oscillator or the high-speed external clock divided by 128. The
internal low-speed RC has a typical frequency of 40 kHz. The RTC can be calibrated using
an external 512 Hz output to compensate for any natural quartz deviation. The RTC features
a 32-bit programmable counter for long term measurement using the Compare register to
generate an alarm. A 20-bit prescaler is used for the time base clock and is by default
configured to generate a time base of 1 second from a clock at 32.768 kHz.
2.3.17 Timers and watchdogs
The high-density STM32F103xx performance line devices include up to two advancedcontrol timers, up to four general-purpose timers, two basic timers, two watchdog timers and
a SysTick timer.
Ta bl e 4 compares the features of the advanced-control, general-purpose and basic timers.
Table 4. High-density timer feature comparison
Timer
TIM1,
TIM8
TIM2,
TIM3,
TIM4,
TIM5
TIM6,
TIM7
Counter
resolution
16-bit
16-bit
16-bit Up
Counter
type
Up,
down,
up/down
Up,
down,
up/down
Prescaler
factor
Any integer
between 1
and 65536
Any integer
between 1
and 65536
Any integer
between 1
and 65536
DMA request
generation
Capture/compare
channels
Ye s 4 Ye s
Ye s 4 N o
Ye s 0 N o
Complementary
outputs
Advanced-control timers (TIM1 and TIM8)
The two advanced-control timers (TIM1 and TIM8) can each be seen as a three-phase
PWM multiplexed on 6 channels. They have complementary PWM outputs with
programmable inserted dead-times. They can also be seen as a complete general-purpose
timer. The 4 independent channels can be used for:
● Input capture
● Output compare
● PWM generation (edge or center-aligned modes)
● One-pulse mode output
If configured as a standard 16-bit timer, it has the same features as the TIMx timer. If
configured as the 16-bit PWM generator, it has full modulation capability (0-100%).
In debug mode, the advanced-control timer counter can be frozen and the PWM outputs
disabled to turn off any power switch driven by these outputs.
Many features are shared with those of the general-purpose TIM timers which have the
same architecture. The advanced-control timer can therefore work together with the TIM
timers via the Timer Link feature for synchronization or event chaining.
Doc ID 14611 Rev 8 19/130
Description STM32F103xC, STM32F103xD, STM32F103xE
General-purpose timers (TIMx)
There are up to 4 synchronizable general-purpose timers (TIM2, TIM3, TIM4 and TIM5)
embedded in the STM32F103xC, STM32F103xD and STM32F103xE performance line
devices. These timers are based on a 16-bit auto-reload up/down counter, a 16-bit prescaler
and feature 4 independent channels each for input capture/output compare, PWM or onepulse mode output. This gives up to 16 input captures / output compares / PWMs on the
largest packages.
The general-purpose timers can work together with the advanced-control timer via the Timer
Link feature for synchronization or event chaining. Their counter can be frozen in debug
mode. Any of the general-purpose timers can be used to generate PWM outputs. They all
have independent DMA request generation.
These timers are capable of handling quadrature (incremental) encoder signals and the
digital outputs from 1 to 3 hall-effect sensors.
Basic timers TIM6 and TIM7
These timers are mainly used for DAC trigger generation. They can also be used as a
generic 16-bit time base.
Independent watchdog
The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is
clocked from an independent 40 kHz internal RC and as it operates independently from the
main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog
to reset the device when a problem occurs, or as a free running timer for application timeout
management. It is hardware or software configurable through the option bytes. The counter
can be frozen in debug mode.
2.3.18 I²C bus
Window watchdog
The window watchdog is based on a 7-bit downcounter that can be set as free running. It
can be used as a watchdog to reset the device when a problem occurs. It is clocked from the
main clock. It has an early warning interrupt capability and the counter can be frozen in
debug mode.
SysTick timer
This timer is dedicated to real-time operating systems, but could also be used as a standard
down counter. It features:
● A 24-bit down counter
● Autoreload capability
● Maskable system interrupt generation when the counter reaches 0.
● Programmable clock source
Up to two I²C bus interfaces can operate in multimaster and slave modes. They can support
standard and fast modes.
They support 7/10-bit addressing mode and 7-bit dual addressing mode (as slave). A
hardware CRC generation/verification is embedded.
They can be served by DMA and they support SMBus 2.0/PMBus.
20/130 Doc ID 14611 Rev 8
STM32F103xC, STM32F103xD, STM32F103xE Description
2.3.19 Universal synchronous/asynchronous receiver transmitters (USARTs)
The STM32F103xC, STM32F103xD and STM32F103xE performance line embeds three
universal synchronous/asynchronous receiver transmitters (USART1, USART2 and
USART3) and two universal asynchronous receiver transmitters (UART4 and UART5).
These five interfaces provide asynchronous communication, IrDA SIR ENDEC support,
multiprocessor communication mode, single-wire half-duplex communication mode and
have LIN Master/Slave capability.
The USART1 interface is able to communicate at speeds of up to 4.5 Mbit/s. The other
available interfaces communicate at up to 2.25 Mbit/s.
USART1, USART2 and USART3 also provide hardware management of the CTS and RTS
signals, Smart Card mode (ISO 7816 compliant) and SPI-like communication capability. All
interfaces can be served by the DMA controller except for UART5.
2.3.20 Serial peripheral interface (SPI)
Up to three SPIs are able to communicate up to 18 Mbits/s in slave and master modes in
full-duplex and simplex communication modes. The 3-bit prescaler gives 8 master mode
frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC
generation/verification supports basic SD Card/MMC modes.
All SPIs can be served by the DMA controller.
2.3.21 Inter-integrated sound (I2S)
Two standard I2S interfaces (multiplexed with SPI2 and SPI3) are available, that can be
operated in master or slave mode. These interfaces can be configured to operate with 16/32
bit resolution, as input or output channels. Audio sampling frequencies from 8 kHz up to
48 kHz are supported. When either or both of the I
mode, the master clock can be output to the external DAC/CODEC at 256 times the
sampling frequency.
2.3.22 SDIO
An SD/SDIO/MMC host interface is available, that supports MultiMediaCard System
Specification Version 4.2 in three different databus modes: 1-bit (default), 4-bit and 8-bit.
The interface allows data transfer at up to 48 MHz in 8-bit mode, and is compliant with SD
Memory Card Specifications Version 2.0.
The SDIO Card Specification Version 2.0 is also supported with two different databus
modes: 1-bit (default) and 4-bit.
The current version supports only one SD/SDIO/MMC4.2 card at any one time and a stack
of MMC4.1 or previous.
In addition to SD/SDIO/MMC, this interface is also fully compliant with the CE-ATA digital
protocol Rev1.1.
2
S interfaces is/are configured in master
2.3.23 Controller area network (CAN)
The CAN is compliant with specifications 2.0A and B (active) with a bit rate up to 1 Mbit/s. It
can receive and transmit standard frames with 11-bit identifiers as well as extended frames
with 29-bit identifiers. It has three transmit mailboxes, two receive FIFOs with 3 stages and
14 scalable filter banks.
Doc ID 14611 Rev 8 21/130
Description STM32F103xC, STM32F103xD, STM32F103xE
2.3.24 Universal serial bus (USB)
The STM32F103xC, STM32F103xD and STM32F103xE performance line embed a USB
device peripheral compatible with the USB full-speed 12 Mbs. The USB interface
implements a full-speed (12 Mbit/s) function interface. It has software-configurable endpoint
setting and suspend/resume support. The dedicated 48 MHz clock is generated from the
internal main PLL (the clock source must use a HSE crystal oscillator).
2.3.25 GPIOs (general-purpose inputs/outputs)
Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as
input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the
GPIO pins are shared with digital or analog alternate functions. All GPIOs are high currentcapable except for analog inputs.
The I/Os alternate function configuration can be locked if needed following a specific
sequence in order to avoid spurious writing to the I/Os registers.
2.3.26 ADC (analog to digital converter)
Three 12-bit analog-to-digital converters are embedded into STM32F103xC, STM32F103xD
and STM32F103xE performance line devices and each ADC shares up to 21 external
channels, performing conversions in single-shot or scan modes. In scan mode, automatic
conversion is performed on a selected group of analog inputs.
Additional logic functions embedded in the ADC interface allow:
● Simultaneous sample and hold
● Interleaved sample and hold
● Single shunt
The ADC can be served by the DMA controller.
An analog watchdog feature allows very precise monitoring of the converted voltage of one,
some or all selected channels. An interrupt is generated when the converted voltage is
outside the programmed thresholds.
The events generated by the general-purpose timers (TIMx) and the advanced-control
timers (TIM1 and TIM8) can be internally connected to the ADC start trigger and injection
trigger, respectively, to allow the application to synchronize A/D conversion and timers.
2.3.27 DAC (digital-to-analog converter)
The two 12-bit buffered DAC channels can be used to convert two digital signals into two
analog voltage signal outputs. The chosen design structure is composed of integrated
resistor strings and an amplifier in inverting configuration.
22/130 Doc ID 14611 Rev 8
STM32F103xC, STM32F103xD, STM32F103xE Description
This dual digital Interface supports the following features:
● two DAC converters: one for each output channel
● 8-bit or 12-bit monotonic output
● left or right data alignment in 12-bit mode
● synchronized update capability
● noise-wave generation
● triangular-wave generation
● dual DAC channel independent or simultaneous conversions
● DMA capability for each channel
● external triggers for conversion
● input voltage reference V
REF+
Eight DAC trigger inputs are used in the STM32F103xC, STM32F103xD and
STM32F103xE performance line family. The DAC channels are triggered through the timer
update outputs that are also connected to different DMA channels.
2.3.28 Temperature sensor
The temperature sensor has to generate a voltage that varies linearly with temperature. The
conversion range is between 2 V < V
connected to the ADC1_IN16 input channel which is used to convert the sensor output
voltage into a digital value.
< 3.6 V. The temperature sensor is internally
DDA
2.3.29 Serial wire JTAG debug port (SWJ-DP)
The ARM SWJ-DP Interface is embedded, and is a combined JTAG and serial wire debug
port that enables either a serial wire debug or a JTAG probe to be connected to the target.
The JTAG TMS and TCK pins are shared respectively with SWDIO and SWCLK and a
specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP.
2.3.30 Embedded Trace Macrocell™
The ARM® Embedded Trace Macrocell provides a greater visibility of the instruction and
data flow inside the CPU core by streaming compressed data at a very high rate from the
STM32F10xxx through a small number of ETM pins to an external hardware trace port
analyzer (TPA) device. The TPA is connected to a host computer using USB, Ethernet, or
any other high-speed channel. Real-time instruction and data flow activity can be recorded
and then formatted for display on the host computer running debugger software. TPA
hardware is commercially available from common development tool vendors. It operates
with third party debugger software tools.
Doc ID 14611 Rev 8 23/130
Pinouts and pin descriptions STM32F103xC, STM32F103xD, STM32F103xE
AI14798b
V
DD_7
PC3PC2
PF6
V
DD_6
V
SS_4
PF8
H
V
DD_1
D PG13
PG14
PE6PE5
C
PG10
PG11
V
DD_5
PB8
NRST
B PG12PG15
PC15-
OSC32_OUT
PB9
A
87654321
V
BAT
OSC_IN
OSC_OUT
V
SS_5
G
F
E
PF7
PC0
PF0 PF1
PF2
V
SS_10
PG9PF4
PF3
V
SS_3
PF5
V
DD_8
V
DD_3
V
DD_4
V
SS_8
PE4
PB5
PB6
BOOT0 PB7
V
SS_11
PF10
PC1
V
DD_11VDD_10
PF9
109
K
J
V
SS_2
PD3
PD4
PD1
PC12
PC11
PD5
PD2 PD0
V
DD_9
V
SS_9
V
DD_2
PG1
PC5PA5 PE9
PB2/
BOOT1
PC4PA4
PE10
PG0PF13V
REF–
PE12V
SSA
PA1 PE13
PA0-WKUP
PD9
PD10
PG4
PD13
1211
PG8
PA10
NC
PA9
PA11
PA12
PC10
PC9 PA8
PC7
PC6
PC8
PD14
PG3
PG2
PD15
M
L
PF15
PB1PA7 PE7
PF12
PB0PA6
PE8
PF14PF11V
DDA
PE14V
REF+
PA3 PE15
PA2
PB10
PD8
PD12
PB11
PB12
PB14
PB15
PB13
PC13-
TAMPER-RTC
PE3 PE2 PE1 PE0
PB4
JTRST
PB3
JTDO
PD6 PD7
PA15
JTDI
PA14
JTCK
PA13
JTMS
PE11V
SS_6
V
SS_7VSS_1
PG7
PD11
PG5
PG6
PC14-
OSC32_IN
3 Pinouts and pin descriptions
Figure 3. STM32F103xC and STM32F103xE performance line BGA144 ballout
24/130 Doc ID 14611 Rev 8
STM32F103xC, STM32F103xD, STM32F103xE Pinouts and pin descriptions
AI14601c
PE10
PC14-
OSC32_IN
PC5PA5
PC3
PB4
PE15
PB2
PC4PA4
H
PE14
PE11PE7
D PD4
PD3
PB8PE3
C
PD0
PC12
PE5
PB5
PC0
PE2
B PC11PD2
PC15-
OSC32_OUT
PB7
PB6
A
87654321
V
SS_5
OSC_IN
OSC_OUT V
DD_5
G
F
E
PC1
V
REF–
PC13-
TAMPER-RTC
PB9
PA15
PB3
PE4
PE1
PE0
V
SS_1
PD1PE6NRST
PC2
V
SS_3
V
SS_4
NCV
DD_3
V
DD_4
PB15
V
BAT
PD5
PD6
BOOT0 PD7
V
SS_2
V
SSA
PA1
V
DD_2
V
DD_1
PB14
PA0-WKUP
109
K
J
PD10
PD11
PA8
PA9
PA10
PA11
PA12
PC10
PA13
PA14
PC9
PC7
PC6
PD15
PC8
PD14
PE12
PB1PA7
PB11
PE8
PB0PA6
PB10
PE13PE9V
DDA
PB13
V
REF+
PA3
PB12
PA2
PD8
PD9
PD13
PD12
Figure 4. STM32F103xC and STM32F103xE performance line BGA100 ballout
Doc ID 14611 Rev 8 25/130
Pinouts and pin descriptions STM32F103xC, STM32F103xD, STM32F103xE
V
DD_3VSS_3
PE1
PE0
PB9
PB8
BOOT0
PB7
PB6
PB5
PB4
PB3
PG15
V
DD_11VSS_11
PG14
PG13
PG12
PG11
PG10
PG9
PD7
PD6
V
DD_10VSS_10
PD5
PD4
PD3
PD2
PD1
PD0
PC12
PC11
PC10
PA15
PA14
PE2
V
DD_2
PE3
V
SS_2
PE4
NC
PE5
PA13
PE6
PA12
VBAT
PA11
PC13-TAMPER-RTC
PA10
PC14-OSC32_IN
PA9
PC15-OSC32_OUT
PA8
PF0
PC9
PF1
PC8
PF2
PC7
PF3
PC6
PF4
V
DD_9
PF5
V
SS_9
V
SS_5
PG8
V
DD_5
PG7
PF6
PG6
PF7
PG5
PF8
PG4
PF9
PG3
PF10
PG2
OSC_IN
PD15
OSC_OUT
PD14
NRST
V
DD_8
PC0
V
SS_8
PC1
PD13
PC2
PD12
PC3
PD11
V
SSA
PD10
V
REF-
PD9
V
REF+
PD8
V
DDA
PB15
PA0-WKUP
PB14
PA1
PB13
PA2
PB12
PA3
V
SS_4
V
DD_4
PA4
PA5
PA6
PA7
PC4
PC5
PB0
PB1
PB2
PF11
PF12
VSS_6
V
DD_6
PF13
PF14
PF15
PG0
PG1
PE7
PE8
PE9
V
SS_7
V
DD_7
PE10
PE11
PE12
PE13
PE14
PE15
PB10
PB11
V
SS_1
V
DD_1
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
109
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
3738394041424344454647484950515253545556575859
60
72
LQFP144
120
119
118
117
116
115
114
113
112
111
110
6162636465666768697071
26
27
28
29
30
31
32
33
34
35
36
83
82
81
80
79
78
77
76
75
74
73
ai14667
Figure 5. STM32F103xC and STM32F103xE performance line LQFP144 pinout
26/130 Doc ID 14611 Rev 8
STM32F103xC, STM32F103xD, STM32F103xE Pinouts and pin descriptions
100999897969594939291908988878685848382818079787776
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
VDD_2
VSS_2
NC
PA 1 3
PA 1 2
PA 1 1
PA 1 0
PA 9
PA 8
PC9
PC8
PC7
PC6
PD15
PD14
PD13
PD12
PD11
PD10
PD9
PD8
PB15
PB14
PB13
PB12
PA 3
VSS_4
VDD_4
PA 4
PA 5
PA 6
PA 7
PC4
PC5
PB0
PB1
PB2
PE7
PE8
PE9
PE10
PE11
PE12
PE13
PE14
PE15
PB10
PB11
VSS_1
VDD_1
VDD_3
VSS_3
PE1
PE0
PB9
PB8
BOOT0
PB7
PB6
PB5
PB4
PB3
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
PC12
PC11
PC10
PA15
PA14
26272829303132333435363738394041424344454647484950
PE2
PE3
PE4
PE5
PE6
VBAT
PC13-TAMPER-RTC
PC14-OSC32_IN
PC15-OSC32_OUT
VSS_5
VDD_5
OSC_IN
OSC_OUT
NRST
PC0
PC1
PC2
PC3
VSSA
VREF-
VREF+
VDDA
PA 0- W K UP
PA 1
PA 2
ai14391
LQFP100
Figure 6. STM32F103xC and STM32F103xE performance line LQFP100 pinout
Doc ID 14611 Rev 8 27/130
Pinouts and pin descriptions STM32F103xC, STM32F103xD, STM32F103xE
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
17 18 19 20 21 22 23 24 29 30 31 3225 26 27 28
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
VBAT
PC13-TAMPER-RTC
PC14-OSC32_IN
PC15-OSC32_OUT
PD0 OSC_IN
PD1 OSC_OUT
NRST
PC0
PC1
PC2
PC3
VSSA
VDDA
PA 0- W K UP
PA 1
PA 2
VDD_3
VSS_3
PB9
PB8
BOOT0
PB7
PB6
PB5
PB4
PB3
PD2
PC12
PC11
PC10
PA1 5
PA 14
VDD_2
VSS_2
PA 1 3
PA 1 2
PA 1 1
PA 1 0
PA 9
PA 8
PC9
PC8
PC7
PC6
PB15
PB14
PB13
PB12
PA 3
VSS_4
VDD_4
PA 4
PA 5
PA 6
PA 7
PC4
PC5
PB0
PB1
PB2
PB10
PB11
VSS_1
VDD_1
LQFP64
ai14392
Figure 7. STM32F103xC and STM32F103xE performance line
LQFP64 pinout
28/130 Doc ID 14611 Rev 8
STM32F103xC, STM32F103xD, STM32F103xE Pinouts and pin descriptions
Figure 8. STM32F103xC and STM32F103xE performance line
WLCSP64 ballout, ball side
87654321
A
V
DD_3
V
SS_3
B
C
D
E
F
G
H
PC13 NRST V
BAT
OSC_IN OSC_OUT PC2 PB8 PA13 PA10 PA9 PC9
PC0 V
PC1
V
DDA
V
PA3
SSA
REF+
PA1 PA5 PA8 PC8 PC7 PC6
PA0WKUP
V
DD_4
PA2 PA4 PC4 PC5 PB0 PB2
PB7 PC12 PA15 PA12 PA11
V
SS_4
PB1 PB11 PB14 PB15
PA6 PA7 PB10 PB12 PB13
PC10PD2PB5 PB3BOOT0
BYPASS/
PA14PC11PB4PB6PB9PC15PC14
V
V
SS_1VDD_1
V
DD_2
SS_2
ai15460b
Doc ID 14611 Rev 8 29/130
Pinouts and pin descriptions STM32F103xC, STM32F103xD, STM32F103xE
LFBGA100
Pins
WLCSP64
LQFP64
(2)
Pin name
(1)
Typ e
LQFP100
LQFP144
Main
function
(after reset)
I / O Level
(3)
Default Remap
Table 5. High-density STM32F103xx pin definitions
LFBGA144
A3 A3 - - 1 1 PE2 I/O FT PE2 TRACECK/ FSMC_A23
A2 B3 - - 2 2 PE3 I/O FT PE3 TRACED0/FSMC_A19
B2 C3 - - 3 3 PE4 I/O FT PE4 TRACED1/FSMC_A20
B3 D3 - - 4 4 PE5 I/O FT PE5 TRACED2/FSMC_A21
B4 E3 - - 5 5 PE6 I/O FT PE6 TRACED3/FSMC_A22
C2 B2 C6 1 6 6 V
A1 A2 C8 2 7 7
B1 A1 B8 3 8 8
C1 B1 B7 4 9 9
PC13-TAMPER-
RTC
PC14-
OSC32_IN
PC15-
OSC32_OUT
BAT
(5)
SV
I/O PC13
I/O PC14
(5)
I/O PC15
(5)
BAT
(6)
(6)
(6)
TAMPER-RTC
OSC32_IN
OSC32_OUT
C3 - - - - 10 PF0 I/O FT PF0 FSMC_A0
C4 - - - - 11 PF1 I/O FT PF1 FSMC_A1
D4 - - - - 12 PF2 I/O FT PF2 FSMC_A2
E2 - - - - 13 PF3 I/O FT PF3 FSMC_A3
E3 - - - - 14 PF4 I/O FT PF4 FSMC_A4
E4 - - - - 15 PF5 I/O FT PF5 FSMC_A5
D2 C2 - - 10 16 V
D3 D2 - - 11 17 V
SS_5
DD_5
SV
SV
SS_5
DD_5
F3 - - - - 18 PF6 I/O PF6 ADC3_IN4/FSMC_NIORD
F2 - - - - 19 PF7 I/O PF7 ADC3_IN5/FSMC_NREG
G3 - - - - 20 PF8 I/O PF8 ADC3_IN6/FSMC_NIOWR
G2 - - - - 21 PF9 I/O PF9 ADC3_IN7/FSMC_CD
G1 - - - - 22 PF10 I/O PF10 ADC3_IN8/FSMC_INTR
D1 C1 D8 5 12 23 OSC_IN I OSC_IN
E1 D1 D7 6 13 24 OSC_OUT O OSC_OUT
F1 E1 C7 7 14 25 NRST I/O NRST
H1 F1 E8 8 15 26 PC0 I/O PC0 ADC123_IN10
H2 F2 F8 9 16 27 PC1 I/O PC1 ADC123_IN11
H3 E2 D6 10 17 28 PC2 I/O PC2 ADC123_IN12
H4 F3 - 11 18 29 PC3 I/O PC3 ADC123_IN13
J1 G1 E7 12 19 30 V
SSA
SV
SSA
Alternate functions
(4)
30/130 Doc ID 14611 Rev 8
STM32F103xC, STM32F103xD, STM32F103xE Pinouts and pin descriptions
Table 5. High-density STM32F103xx pin definitions (continued)
Pins
Pin name
LQFP64
LQFP100
LFBGA144
LFBGA100
WLCSP64
LQFP144
K1 H1 - - 20 31 V
L1 J1
F7
-2132 V
(7)
REF-
REF+
(2)
(1)
Type
Main
function
(3)
(after reset)
I / O Level
SV
SV
REF-
REF+
Alternate functions
Default Remap
(4)
M1 K1 G8 13 22 33 V
DDA
SV
DDA
WKUP/USART2_CTS
J2 G2 F6 14 23 34 PA0-WKUP I/O PA0
TIM2_CH1_ETR
TIM5_CH1/TIM8_ETR
USART2_RTS
K2 H2 E6 15 24 35 PA1 I/O PA1
TIM5_CH2/TIM2_CH2
USART2_TX
L2 J2 H8 16 25 36 PA2 I/O PA2
M2 K2 G7 17 26 37 PA3 I/O PA3
G4 E4 F5 18 27 38 V
F4 F4 G6 19 28 39 V
SS_4
DD_4
SV
SV
SS_4
DD_4
USART2_RX
ADC123_IN3/TIM2_CH4
J3 G3 H7 20 29 40 PA4 I/O PA4
DAC_OUT1/ADC12_IN4
K3 H3 E5 21 30 41 PA5 I/O PA5
L3 J3 G5 22 31 42 PA6 I/O PA6
M3 K3 G4 23 32 43 PA7 I/O PA7
DAC_OUT2 ADC12_IN5
TIM8_BKIN/ADC12_IN6
TIM8_CH1N/ADC12_IN7
J4 G4 H6 24 33 44 PC4 I/O PC4 ADC12_IN14
K4 H4 H5 25 34 45 PC5 I/O PC5 ADC12_IN15
L4 J4 H4 26 35 46 PB0 I/O PB0
M4 K4 F4 27 36 47 PB1 I/O PB1
J5 G5 H3 28 37 48 PB2 I/O FT PB2/BOOT1
ADC12_IN8/TIM3_CH3
ADC12_IN9/TIM3_CH4
M5 - - - - 49 PF11 I/O FT PF11 FSMC_NIOS16
L5 - - - - 50 PF12 I/O FT PF12 FSMC_A6
ADC123_IN0
ADC123_IN1/
(8)
/TIM5_CH3
ADC123_IN2/
TIM2_CH3
(8)
/TIM5_CH4
SPI1_NSS
(8)
USART2_CK
SPI1_SCK
(8)
SPI1_MISO
TIM3_CH1
SPI1_MOSI
TIM3_CH2
TIM8_CH2N
TIM8_CH3N
(8)
(8)
(8)
(8)
(8)
(8)
(8)
/
(8)
(8)
(8)
TIM1_BKIN
/
TIM1_CH1N
TIM1_CH2N
(8)
TIM1_CH3N
Doc ID 14611 Rev 8 31/130
Pinouts and pin descriptions STM32F103xC, STM32F103xD, STM32F103xE
Table 5. High-density STM32F103xx pin definitions (continued)
Pins
Pin name
LQFP64
LQFP100
LFBGA144
LFBGA100
WLCSP64
LQFP144
H5 - - - - 51 V
G5 - - - - 52 V
SS_6
DD_6
(2)
(1)
Type
Main
function
(3)
(after reset)
I / O Level
SV
SV
SS_6
DD_6
Alternate functions
Default Remap
K5 - - - - 53 PF13 I/O FT PF13 FSMC_A7
M6 - - - - 54 PF14 I/O FT PF14 FSMC_A8
L6 - - - - 55 PF15 I/O FT PF15 FSMC_A9
K6 - - - - 56 PG0 I/O FT PG0 FSMC_A10
J6 - - - - 57 PG1 I/O FT PG1 FSMC_A11
M7 H5 - - 38 58 PE7 I/O FT PE7 FSMC_D4 TIM1_ETR
L7 J5 - - 39 59 PE8 I/O FT PE8 FSMC_D5 TIM1_CH1N
K7 K5 - - 40 60 PE9 I/O FT PE9 FSMC_D6 TIM1_CH1
H6 - - - - 61 V
G6 - - - - 62 V
SS_7
DD_7
SV
SV
SS_7
DD_7
J7 G6 - - 41 63 PE10 I/O FT PE10 FSMC_D7 TIM1_CH2N
H8 H6 - - 42 64 PE11 I/O FT PE11 FSMC_D8 TIM1_CH2
J8 J6 - - 43 65 PE12 I/O FT PE12 FSMC_D9 TIM1_CH3N
K8 K6 - - 44 66 PE13 I/O FT PE13 FSMC_D10 TIM1_CH3
L8 G7 - - 45 67 PE14 I/O FT PE14 FSMC_D11 TIM1_CH4
M8 H7 - - 46 68 PE15 I/O FT PE15 FSMC_D12 TIM1_BKIN
M9 J7 G3 29 47 69 PB10 I/O FT PB10 I2C2_SCL/USART3_TX
M10 K7 F3 30 48 70 PB11 I/O FT PB11 I2C2_SDA/USART3_RX
H7 E7 H2 31 49 71 V
G7 F7 H1 32 50 72 V
SS_1
DD_1
SV
SV
SS_1
DD_1
(8)
(8)
SPI2_NSS/I2S2_WS/
M11 K8 G2 33 51 73 PB12 I/O FT PB12
M12 J8 G1 34 52 74 PB13 I/O FT PB13
I2C2_SMBA/
USART3_CK
TIM1_BKIN
SPI2_SCK/I2S2_CK
USART3_CTS
(8)
(8)
(8)
/
/
TIM1_CH1N
L11 H8 F2 35 53 75 PB14 I/O FT PB14
L12 G8 F1 36 54 76 PB15 I/O FT PB15
SPI2_MISO/TIM1_CH2N
USART3_RTS
SPI2_MOSI/I2S2_SD
TIM1_CH3N
(8)
(8)
/
/
L9 K9 - - 55 77 PD8 I/O FT PD8 FSMC_D13 USART3_TX
K9 J9 - - 56 78 PD9 I/O FT PD9 FSMC_D14 USART3_RX
(4)
TIM2_CH3
TIM2_CH4
32/130 Doc ID 14611 Rev 8
STM32F103xC, STM32F103xD, STM32F103xE Pinouts and pin descriptions
Table 5. High-density STM32F103xx pin definitions (continued)
Alternate functions
Default Remap
LFBGA144
Pins
LFBGA100
LQFP64
WLCSP64
(2)
Pin name
(1)
Type
LQFP100
LQFP144
Main
function
(after reset)
I / O Level
(3)
J9 H9 - - 57 79 PD10 I/O FT PD10 FSMC_D15 USART3_CK
H9 G9 - - 58 80 PD11 I/O FT PD11 FSMC_A16 USART3_CTS
L10 K10 - - 59 81 PD12 I/O FT PD12 FSMC_A17
K10 J10 - - 60 82 PD13 I/O FT PD13 FSMC_A18 TIM4_CH2
G8 - - - - 83 V
F8 - - - - 84 V
SS_8
DD_8
SV
SV
SS_8
DD_8
K11 H10 - - 61 85 PD14 I/O FT PD14 FSMC_D0 TIM4_CH3
K12 G10 - - 62 86 PD15 I/O FT PD15 FSMC_D1 TIM4_CH4
J12 - - - - 87 PG2 I/O FT PG2 FSMC_A12
J11 - - - - 88 PG3 I/O FT PG3 FSMC_A13
J10 - - - - 89 PG4 I/O FT PG4 FSMC_A14
H12 - - - - 90 PG5 I/O FT PG5 FSMC_A15
H11 - - - - 91 PG6 I/O FT PG6 FSMC_INT2
H10 - - - - 92 PG7 I/O FT PG7 FSMC_INT3
G11 - - - - 93 PG8 I/O FT PG8
G10 - - - - 94 V
F10 - - - - 95 V
SS_9
DD_9
G12 F10 E1 37 63 96 PC6 I/O FT PC6
F12 E10 E2 38 64 97 PC7 I/O FT PC7
SV
SV
SS_9
DD_9
I2S2_MCK/
TIM8_CH1/SDIO_D6
I2S3_MCK/
TIM8_CH2/SDIO_D7
F11 F9 E3 39 65 98 PC8 I/O FT PC8 TIM8_CH3/SDIO_D0 TIM3_CH3
E11 E9 D1 40 66 99 PC9 I/O FT PC9 TIM8_CH4/SDIO_D1 TIM3_CH4
E 1 2 D 9 E 4 4 1 6 7 1 0 0 PA 8 I / O F T PA 8
D 1 2 C 9 D 2 4 2 6 8 1 0 1 PA 9 I / O F T PA 9
D11 D10 D3 43 69 102 PA10 I/O FT PA10
C12 C10 C1 44 70 103 PA11 I/O FT PA11
B12 B10 C2 45 71 104 PA12 I/O FT PA12
USART1_CK/
TIM1_CH1
USART1_TX
TIM1_CH2
USART1_RX
TIM1_CH3
USART1_CTS/USBDM
CAN_RX
USART1_RTS/USBDP/
CAN_TX
(8)
/MCO
(8)
/TIM1_CH4
(8)
/TIM1_ETR
(8)
(8)
(8)
(8)
/
/
(8)
(8)
(4)
TIM4_CH1 /
USART3_RTS
TIM3_CH1
TIM3_CH2
Doc ID 14611 Rev 8 33/130
Pinouts and pin descriptions STM32F103xC, STM32F103xD, STM32F103xE
Table 5. High-density STM32F103xx pin definitions (continued)
Pins
Pin name
(1)
Type
LQFP64
LQFP100
LFBGA144
LFBGA100
WLCSP64
LQFP144
A12 A10 D4 46 72 105 PA13 I/O FT
(2)
Main
function
(after reset)
I / O Level
JTMS-
SWDIO
(3)
Alternate functions
Default Remap
C11 F8 - - 73 106 Not connected
G9 E6 B1 47 74 107
F9 F6 A1 48 75 108
A11 A9 B2 49 76 109 PA14 I/O FT
A10 A8 C3 50 77 110 PA15 I/O FT JTDI
B11 B9 A2 51 78 111 PC10 I/O FT
B10 B8 B3 52 79 112 PC11 I/O FT
V
V
SS_2
DD_2
SV
SV
SS_2
DD_2
JTCK-
SWCLK
PC10 UART4_TX/SDIO_D2
PC11 UART4_RX/SDIO_D3
SPI3_NSS/
I2S3_WS
C10 C8 C4 53 80 113 PC12 I/O FT PC12 UART5_TX/SDIO_CK USART3_CK
E10 D8 D8 5 81 114 PD0 I/O FT OSC_IN
D10 E8 D7 6 82 115 PD1 I/O FT OSC_OUT
E9 B7 A3 54 83 116 PD2 I/O FT PD2
(9)
(9)
FSMC_D2
FSMC_D3
TIM3_ETR/UART5_RX
SDIO_CMD
(10)
(10)
D9 C7 - - 84 117 PD3 I/O FT PD3 FSMC_CLK USART2_CTS
C9 D7 - - 85 118 PD4 I/O FT PD4 FSMC_NOE USART2_RTS
B9 B6 - - 86 119 PD5 I/O FT PD5 FSMC_NWE USART2_TX
E7 - - - - 120
F7 - - - - 121
V
SS_10
V
DD_10
S
S
V
SS_10
V
DD_10
A8 C6 - - 87 122 PD6 I/O FT PD6 FSMC_NWAIT USART2_RX
A9 D6 - - 88 123 PD7 I/O FT PD7 FSMC_NE1/FSMC_NCE2 USART2_CK
E8 - - - - 124 PG9 I/O FT PG9 FSMC_NE2/FSMC_NCE3
D8 - - - - 125 PG10 I/O FT PG10
FSMC_NCE4_1/
FSMC_NE3
C8 - - - - 126 PG11 I/O FT PG11 FSMC_NCE4_2
B8 - - - - 127 PG12 I/O FT PG12 FSMC_NE4
D7 - - - - 128 PG13 I/O FT PG13 FSMC_A24
C7 - - - - 129 PG14 I/O FT PG14 FSMC_A25
E6 - - - - 130 V
F6 - - - - 131 V
SS_11
DD_11
SV
SV
SS_11
DD_11
B7 - - - - 132 PG15 I/O FT PG15
(4)
TIM2_CH1_ETR
15 /
PA
USART3_TX
USART3_RX
CAN_RX
CAN_TX
PA 1 3
PA 1 4
SPI1_NSS
34/130 Doc ID 14611 Rev 8
STM32F103xC, STM32F103xD, STM32F103xE Pinouts and pin descriptions
Table 5. High-density STM32F103xx pin definitions (continued)
Pins
Pin name
LQFP64
LQFP100
LFBGA100
WLCSP64
LFBGA144
A7 A7 A4 55 89 133
A6 A6 B4 56 90 134
LQFP144
PB3 I/O FT JTDO SPI3_SCK / I2S3_CK/
PB4 I/O FT
B6 C5 A5 57 91 135 PB5 I/O PB5
(1)
Type
(2)
Main
function
(3)
(after reset)
I / O Level
NJTRST SPI3_MISO
I2C1_SMBA/ SPI3_MOSI
C6 B5 B5 58 92 136 PB6 I/O FT PB6 I2C1_SCL
D6 A5 C5 59 93 137 PB7 I/O FT PB7
Alternate functions
Default Remap
I2S3_SD
(8)
/ TIM4_CH1
I2C1_SDA
FSMC_NADV /
TIM4_CH2
(8)
/
(8)
D5 D5 A6 60 94 138 BOOT0 I BOOT0
(8)
C5 B4 D5 61 95 139 PB8 I/O FT PB8 TIM4_CH3
B5 A4 B6 62 96 140 PB9 I/O FT PB9 TIM4_CH4
/SDIO_D4
(8)
/SDIO_D5
A5 D4 - - 97 141 PE0 I/O FT PE0 TIM4_ETR / FSMC_NBL0
A4 C4 - - 98 142 PE1 I/O FT PE1 FSMC_NBL1
E5 E5 A7 63 99 143 V
F5 F5 A8 64 100 144 V
SS_3
DD_3
1. I = input, O = output, S = supply.
2. FT = 5 V tolerant.
3. Function availability depends on the chosen device.
4. If several peripherals share the same I/O pin, to avoid conflict between these alternate functions only one peripheral should
be enabled at a time through the peripheral clock enable bit (in the corresponding RCC peripheral clock enable register).
5. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current (3
mA), the use of GPIOs PC13 to PC15 in output mode is limited: the speed should not exceed 2 MHz with a maximum load
of 30 pF and these IOs must not be used as a current source (e.g. to drive an LED).
6. Main function after the first backup domain power-up. Later on, it depends on the contents of the Backup registers even
after reset (because these registers are not reset by the main reset). For details on how to manage these IOs, refer to the
Battery backup domain and BKP register description sections in the STM32F10xxx reference manual, available from the
STMicroelectronics website: www.st.com.
7. Unlike in the LQFP64 package, there is no PC3 in the WLCSP package. The V
8. This alternate function can be remapped by software to some other port pins (if available on the used package). For more
details, refer to the Alternate function I/O and debug configuration section in the STM32F10xxx reference manual,
available from the STMicroelectronics website: www.st.com.
9. For the LQFP64 package, the pins number 5 and 6 are configured as OSC_IN/OSC_OUT after reset, however the
functionality of PD0 and PD1 can be remapped by software on these pins. For the LQFP100/BGA100 and
LQFP144/BGA144 packages, PD0 and PD1 are available by default, so there is no need for remapping. For more details,
refer to Alternate function I/O and debug configuration section in the STM32F10xxx reference manual.
10. For devices delivered in LQFP64 packages, the FSMC function is not available.
SV
SV
SS_3
DD_3
functionality is provided instead.
REF+
(4)
PB3/TRACESWO
TIM2_CH2 /
SPI1_SCK
/
PB4
SPI1_MISO
TIM3_CH2 /
SPI1_MOSI
(8)
USART1_TX
USART1_RX
I2C1_SCL/
CAN_RX
I2C1_SDA /
CAN_TX
TIM3_CH1
Doc ID 14611 Rev 8 35/130
Pinouts and pin descriptions STM32F103xC, STM32F103xD, STM32F103xE
Table 6. FSMC pin definition
FSMC
Pins
CF CF/IDE
NOR/PSRAM/
SRAM
NOR/PSRAM Mux NAND 16 bit
PE2 A23 A23 Yes
PE3 A19 A19 Yes
PE4 A20 A20 Yes
PE5 A21 A21 Yes
PE6 A22 A22 Yes
PF0 A0 A0 A0 -
PF1 A1 A1 A1 -
PF2 A2 A2 A2 -
PF3 A3 A3 -
PF4 A4 A4 -
PF5 A5 A5 -
PF6 NIORD NIORD -
PF7 NREG NREG -
LQFP100
BGA100
(1)
PF8 NIOWR NIOWR -
PF9 CD CD -
PF10 INTR INTR -
PF11 NIOS16 NIOS16 -
PF12 A6 A6 -
PF13 A7 A7 -
PF14 A8 A8 -
PF15 A9 A9 -
PG0 A10 A10 -
PG1 A11 -
PE7 D4 D4 D4 DA4 D4 Yes
PE8 D5 D5 D5 DA5 D5 Yes
PE9 D6 D6 D6 DA6 D6 Yes
PE10 D7 D7 D7 DA7 D7 Yes
PE11 D8 D8 D8 DA8 D8 Yes
PE12 D9 D9 D9 DA9 D9 Yes
PE13 D10 D10 D10 DA10 D10 Yes
PE14 D11 D11 D11 DA11 D11 Yes
PE15 D12 D12 D12 DA12 D12 Yes
PD8 D13 D13 D13 DA13 D13 Yes
36/130 Doc ID 14611 Rev 8
STM32F103xC, STM32F103xD, STM32F103xE Pinouts and pin descriptions
Table 6. FSMC pin definition (continued)
FSMC
Pins
CF CF/IDE
NOR/PSRAM/
SRAM
NOR/PSRAM Mux NAND 16 bit
PD9 D14 D14 D14 DA14 D14 Yes
PD10 D15 D15 D15 DA15 D15 Yes
PD11 A16 A16 CLE Yes
PD12 A17 A17 ALE Yes
PD13 A18 A18 Yes
PD14 D0 D0 D0 DA0 D0 Yes
PD15 D1 D1 D1 DA1 D1 Yes
PG2 A12 -
PG3 A13 -
PG4 A14 -
PG5 A15 -
PG6 INT2 -
PG7 INT3 -
PD0 D2 D2 D2 DA2 D2 Yes
LQFP100
BGA100
(1)
PD1 D3 D3 D3 DA3 D3 Yes
PD3 CLK CLK Yes
PD4 NOE NOE NOE NOE NOE Yes
PD5 NWE NWE NWE NWE NWE Yes
PD6 NWAIT NWAIT NWAIT NWAIT NWAIT Yes
PD7 NE1 NE1 NCE2 Yes
PG9 NE2 NE2 NCE3 -
PG10 NCE4_1 NCE4_1 NE3 NE3 -
PG11 NCE4_2 NCE4_2 -
PG12 NE4 NE4 -
PG13 A24 A24 -
PG14 A25 A25 -
PB7 NADV NADV Yes
PE0 NBL0 NBL0 Yes
PE1 NBL1 NBL1 Yes
1. Ports F and G are not available in devices delivered in 100-pin packages.
Doc ID 14611 Rev 8 37/130
512-Mbyte
block 7
Cortex-M3's
internal
peripherals
512-Mbyte
block 6
Not used
512-Mbyte
block 5
FSMC register
512-Mbyte
block 4
FSMC bank 3
& bank4
512-Mbyte
block 3
FSMC bank1
& bank2
512-Mbyte
block 2
Peripherals
512-Mbyte
block 1
SRAM
0x0000 0000
0x1FFF FFFF
0x2000 0000
0x3FFF FFFF
0x4000 0000
0x5FFF FFFF
0x6000 0000
0x7FFF FFFF
0x8000 0000
0x9FFF FFFF
0xA000 0000
0xBFFF FFFF
0xC000 0000
0xDFFF FFFF
0xE000 0000
0xFFFF FFFF
512-Mbyte
block 0
Code
Flash
0x0808 0000
0x1FFF EFFF
0x1FFF F000- 0x1FFF F7FF
0x1FFF F800 - 0x1FFF F80F
0x0800 0000
0x0807 FFFF
0x0008 0000
0x07FF FFFF
0x0000 0000
0x0007 FFFF
System memory
Reserved
Reserved
Aliased to Flash or system
memory depending on
BOOT pins
SRAM (64 KB aliased
by bit-banding)
Reserved
0x2000 0000
0x2000 FFFF
0x2001 0000
0x3FFF FFFF
TIM2
TIM3
0x4000 0000 - 0x4000 03FF
TIM4
TIM5
TIM6
TIM7
Reserved
0x4000 0400 - 0x4000 07FF
0x4000 0800 - 0x4000 0BFF
0x4000 0C00 - 0x4000 0FFF
0x4000 1000 - 0x4000 13FF
0x4000 1400 - 0x4000 17FF
0x4000 1800 - 0x4000 27FF
RTC
0x4000 2800 - 0x4000 2BFF
WWDG
0x4000 2C00 - 0x4000 2FFF
IWDG
0x4000 3000 - 0x4000 33FF
Reserved
0x4000 3400 - 0x4000 37FF
SPI2/I
2
S2
0x4000 3800 - 0x4000 3BFF
SPI3/I
2
S3
0x4000 3C00 - 0x4000 3FFF
Reserved
0x4000 4000 - 0x4000 43FF
USART2
0x4000 4400 - 0x4000 47FF
0x4000 4800 - 0x4000 4BFF
USART3
UART4
0x4000 4C00 - 0x4000 4FFF
UART5
0x4000 5000 - 0x4000 53FF
I2C1
0x4000 5400 - 0x4000 57FF
I2C2
0x4000 5800 - 0x4000 5BFF
Reserved 0x4000 6800 - 0x4000 6BFF
BKP 0x4000 6C00 - 0x4000 6FFF
PWR
0x4000 7000 - 0x4000 73FF
DAC 0x4000 7400 - 0x4000 77FF
Reserved
0x4000 7800 - 0x4000 FFFF
AFIO
0x4001 0000 - 0x4001 03FF
Port A
EXTI
0x4001 0400 - 0x4001 07FF
0x4001 0800 - 0x4001 0BFF
Port B
0x4001 0C00 - 0x4001 0FFF
Port C
0x4001 1000 - 0x4001 13FF
Port D
0x4001 1400 - 0x4001 17FF
Port E
0x4001 1800 - 0x4001 1BFF
Port F
0x4001 1C00 - 0x4001 1FFF
Port G 0x4001 2000 - 0x4001 23FF
ADC1 0x4001 2400 - 0x4001 27FF
0x4001 2800 - 0x4001 2BFF
SPI1
0x4001 3000 - 0x4001 33FF
0x4001 3400 - 0x4001 37FF
USART1
0x4001 3800 - 0x4001 3BFF
Reserved 0x4001 400 - 0x4001 7FFF
DMA1
0x4002 0000 - 0x4002 03FF
DMA2
0x4002 0400 - 0x4002 07FF
Reserved
0x4002 0400 - 0x4002 0FFF
RCC
0x4002 1000 - 0x4002 13FF
Reserved
0x4002 1400 - 0x4002 1FFF
Flash interface
0x4002 2000 - 0x4002 23FF
Reserved
0x4002 2400 - 0x4002 2FFF
CRC
0x4002 3000 - 0x4002 33FF
Reserved
0x4002 4400 - 0x5FFF FFFF
FSMC bank1 NOR/PSRAM 1
0x6000 0000 - 0x63FF FFFF
FSMC bank1 NOR/PSRAM 2
0x6400 0000 - 0x67FF FFFF
FSMC bank1 NOR/PSRAM 3
0x6800 0000 - 0x6BFF FFFF
FSMC bank1 NOR/PSRAM 4
0x6C00 0000 - 0x6FFF FFFF
FSMC bank2 NAND (NAND1)
0x7000 0000 - 0x7FFF FFFF
FSMC bank3 NAND (NAND2)
0x8000 0000 - 0x8FFF FFFF
FSMC bank4 PCCARD
0x9000 0000 - 0x9FFF FFFF
FSMC register
0xA000 0000 - 0xA000 0FFF
Reserved 0xA000 1000 - 0xBFFF FFFF
ai14753d
Option Bytes
TIM8
ADC2
0x4001 8000 - 0x4001 83FF
0x4001 8400 - 0x4001 FFFF
SDIO
Reserved
ADC3
0x4001 3C00 - 0x4001 3FFF
TIM1
0x4001 2C00 - 0x4001 2FFF
USB registers
Shared USB/CAN SRAM 512
bytes
BxCAN
0x4000 5C00 - 0x4000 5FFF
0x4000 6000 - 0x4000 63FF
0x4000 6400 - 0x4000 67FF
Memory mapping STM32F103xC, STM32F103xD, STM32F103xE
4 Memory mapping
The memory map is shown in Figure 9.
Figure 9. Memory map
38/130 Doc ID 14611 Rev 8
STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics
ai14141
C = 50 pF
STM32F103xx pin
ai14142
STM32F103xx pin
V
IN
5 Electrical characteristics
5.1 Parameter conditions
Unless otherwise specified, all voltages are referenced to VSS.
5.1.1 Minimum and maximum values
Unless otherwise specified the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at T
the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean±3Σ).
5.1.2 Typical values
Unless otherwise specified, typical data are based on TA = 25 °C, VDD = 3.3 V (for the
2V≤ V
tested.
≤ 3.6 V voltage range). They are given only as design guidelines and are not
DD
= 25 °C and TA = TAmax (given by
A
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated
5.1.3 Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
5.1.4 Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 10.
5.1.5 Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 11.
Figure 10. Pin loading conditions Figure 11. Pin input voltage
(mean±2Σ).
Doc ID 14611 Rev 8 39/130
Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE
ai14126
V
BAT
V
DD
V
DDA
IDD_V
BAT
I
DD
5.1.6 Power supply scheme
Figure 12. Power supply scheme
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&
6
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§&
6
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&
6
$$
6
6
2%&
6
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$$
6
33
6
6
2%&
6
2%&
6
"!4
$$!
33!
0OWERSWITCH
/54
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)/
,OGIC
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2#S0,,
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#05
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AI
Caution: In Figure 12, the 4.7 µF capacitor must be connected to V
5.1.7 Current consumption measurement
Figure 13. Current consumption measurement scheme
DD3
.
40/130 Doc ID 14611 Rev 8
STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics
5.2 Absolute maximum ratings
Stresses above the absolute maximum ratings listed in Table 7: Voltage characteristics,
Table 8: Current characteristics, and Table 9: Thermal characteristics may cause permanent
damage to the device. These are stress ratings only and functional operation of the device
at these conditions is not implied. Exposure to maximum rating conditions for extended
periods may affect device reliability.
Table 7. Voltage characteristics
Symbol Ratings Min Max Unit
VDD–V
(2)
V
IN
|ΔV
DDx
− VSS| Variations between all the different ground pins 50
|V
SSX
V
ESD(HBM)
1. All main power (VDD, V
supply, in the permitted range.
2. VIN maximum must always be respected. Refer to Table 8: Current characteristics for the maximum
allowed injected current values.
Table 8. Current characteristics
External main supply voltage (including V
SS
and VDD)
(1)
Input voltage on five volt tolerant pin V
Input voltage on any other pin V
| Variations between different V
power pins 50
DD
Electrostatic discharge voltage (human body
model)
) and ground (VSS, V
DDA
) pins must always be connected to the external power
SSA
DDA
–0.3 4.0
− 0.3 V
SS
− 0.3 4.0
SS
DD
+ 4.0
see Section 5.3.12:
Absolute maximum ratings
(electrical sensitivity)
V
mV
Symbol Ratings Max. Unit
(1)
(1)
150
150
I
VDD
I
VSS
Total current into VDD/V
Total current out of V
SS
power lines (source)
DDA
ground lines (sink)
Output current sunk by any I/O and control pin 25
I
IO
I
INJ(PIN)
ΣI
INJ(PIN)
1. All main power (VDD, V
supply, in the permitted range.
2. Negative injection disturbs the analog performance of the device. See note 3 below Table 62 on page 105.
3. Positive injection is not possible on these I/Os. A negative injection is induced by VIN<VSS. I
never be exceeded. Refer to Table 7: Voltage characteristics for the maximum allowed input voltage
values.
4. A positive injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS. I
never be exceeded. Refer to Table 7: Voltage characteristics for the maximum allowed input voltage
values.
5. When several inputs are submitted to a current injection, the maximum ΣI
positive and negative injected currents (instantaneous values).
Output current source by any I/Os and control pin − 25
Injected current on five volt tolerant pins
(2)
Injected current on any other pin
(4)
Total injected current (sum of all I/O and control pins)
) and ground (VSS, V
DDA
) pins must always be connected to the external power
SSA
(3)
(5)
INJ(PIN)
mA
-5/+0
± 5
± 25
must
INJ(PIN)
must
INJ(PIN)
is the absolute sum of the
Doc ID 14611 Rev 8 41/130
Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE
Table 9. Thermal characteristics
Symbol Ratings Value Unit
T
STG
T
J
Storage temperature range –65 to +150 °C
Maximum junction temperature 150 °C
5.3 Operating conditions
5.3.1 General operating conditions
Table 10. General operating conditions
Symbol Parameter Conditions Min Max Unit
f
HCLK
PCLK1
f
PCLK2
V
V
DDA
V
DD
BAT
P
Internal AHB clock frequency 0 72
Internal APB1 clock frequency 0 36
Internal APB2 clock frequency 0 72
Standard operating voltage 2 3.6 V
Analog operating voltage
(ADC not used)
(1)
Analog operating voltage
(ADC used)
Backup operating voltage 1.8 3.6 V
Power dissipation at T
85 °C for suffix 6 or TA =
D
105 °C for suffix 7
(3)
=
A
Must be the same potential
(2)
as V
DD
2.4 3.6
LQFP144 666
LQFP100 434
LQFP64 444
LFBGA100 500
LFBGA144 500
WLCSP64 400
23.6
MHzf
V
mW
Ambient temperature for 6
suffix version
A
T
Ambient temperature for 7
suffix version
T
J Junction temperature range
1. When the ADC is used, refer to Table 59: ADC characteristics.
2. It is recommended to power VDD and V
between VDD and V
3. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJmax (see Table 6.2: Thermal
characteristics on page 120).
4. In low power dissipation state, TA can be extended to this range as long as TJ does not exceed TJmax (see
Table 6.2: Thermal characteristics on page 120).
can be tolerated during power-up and operation.
DDA
DDA
42/130 Doc ID 14611 Rev 8
Maximum power dissipation –40 85
Low power dissipation
(4)
–40 105
Maximum power dissipation –40 105
Low power dissipation
(4)
–40 125
6 suffix version –40 105
7 suffix version –40 125
from the same source. A maximum difference of 300 mV
°C
°C
°C
STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics
5.3.2 Operating conditions at power-up / power-down
The parameters given in Tab l e 1 1 are derived from tests performed under the ambient
temperature condition summarized in Ta bl e 1 0 .
Table 11. Operating conditions at power-up / power-down
Symbol Parameter Conditions Min Max Unit
t
VDD
V
fall time rate 20
DD
5.3.3 Embedded reset and power control block characteristics
The parameters given in Tab l e 1 2 are derived from tests performed under ambient
VDD rise time rate 0
temperature and V
Table 12. Embedded reset and power control block characteristics
Symbol Parameter Conditions Min Typ Max Unit
V
PVD
supply voltage conditions summarized in Tab l e 1 0 .
DD
PLS[2:0]=000 (rising edge) 2.1 2.18 2.26 V
PLS[2:0]=000 (falling edge) 2 2.08 2.16 V
PLS[2:0]=001 (rising edge) 2.19 2.28 2.37 V
PLS[2:0]=001 (falling edge) 2.09 2.18 2.27 V
PLS[2:0]=010 (rising edge) 2.28 2.38 2.48 V
PLS[2:0]=010 (falling edge) 2.18 2.28 2.38 V
PLS[2:0]=011 (rising edge) 2.38 2.48 2.58 V
Programmable voltage
detector level selection
PLS[2:0]=011 (falling edge) 2.28 2.38 2.48 V
PLS[2:0]=100 (rising edge) 2.47 2.58 2.69 V
PLS[2:0]=100 (falling edge) 2.37 2.48 2.59 V
∞
µs/V
∞
PLS[2:0]=101 (rising edge) 2.57 2.68 2.79 V
PLS[2:0]=101 (falling edge) 2.47 2.58 2.69 V
PLS[2:0]=110 (rising edge) 2.66 2.78 2.9 V
PLS[2:0]=110 (falling edge) 2.56 2.68 2.8 V
PLS[2:0]=111 (rising edge) 2.76 2.88 3 V
PLS[2:0]=111 (falling edge) 2.66 2.78 2.9 V
(2)
V
PVDhyst
V
POR/PDR
V
PDRhyst
T
RSTTEMPO
1. The product behavior is guaranteed by design down to the minimum V
2. Guaranteed by design, not tested in production.
PVD hysteresis 100 mV
(1)
Power on/power down
reset threshold
(2)
PDR hysteresis 40 mV
(2)
Reset temporization 1 2.5 4.5 mS
Falling edge
Rising edge 1.84 1.92 2.0 V
POR/PDR
1.88 1.96 V
1.8
value.
Doc ID 14611 Rev 8 43/130
Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE
5.3.4 Embedded reference voltage
The parameters given in Tab l e 1 3 are derived from tests performed under ambient
temperature and V
Table 13. Embedded internal reference voltage
Symbol Parameter Conditions Min
supply voltage conditions summarized in Tab l e 1 0 .
DD
Typ
Max Unit
V
REFINT
T
S_vrefint
Internal reference voltage
ADC sampling time when
(1)
reading the internal reference
voltage
Internal reference voltage
RERINT
(2)
spread over the temperature
V
range
(2)
T
Coeff
1. Shortest sampling time can be determined in the application by multiple iterations.
2. Guaranteed by design, not tested in production.
Temperature coefficient 100 ppm/°C
5.3.5 Supply current characteristics
The current consumption is a function of several parameters and factors such as the
operating voltage, ambient temperature, I/O pin loading, device software configuration,
operating frequencies, I/O pin switching rate, program location in memory and executed
binary code.
The current consumption is measured as described in Figure 13: Current consumption
measurement scheme.
All Run-mode current consumption measurements given in this section are performed with a
reduced code that gives a consumption equivalent to Dhrystone 2.1 code.
–40 °C < T
–40 °C < T
< +105 °C 1.16 1.20 1.26 V
A
< +85 °C 1.16 1.20 1.24 V
A
5.1 17.1
(2)
VDD = 3 V ±10 mV 10 mV
µs
Maximum current consumption
The MCU is placed under the following conditions:
● All I/O pins are in input mode with a static value at V
● All peripherals are disabled except when explicitly mentioned
● The Flash memory access time is adjusted to the f
to 24 MHz, 1 wait state from 24 to 48 MHz and 2 wait states above)
● Prefetch in ON (reminder: this bit must be set before clock setting and bus prescaling)
● When the peripherals are enabled f
The parameters given in Tab l e 1 4 , Tab le 1 5 and Ta bl e 1 6 are derived from tests performed
under ambient temperature and V
44/130 Doc ID 14611 Rev 8
DD
or VSS (no load)
DD
frequency (0 wait state from 0
HCLK
PCLK1
= f
HCLK
/2, f
PCLK2
= f
HCLK
supply voltage conditions summarized in Ta bl e 1 0 .
STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics
Table 14. Maximum current consumption in Run mode, code with data processing
running from Flash
(1)
Max
Symbol Parameter Conditions f
(2)
External clock
, all
peripherals enabled
I
DD
Supply current in
Run mode
External clock
(2)
, all
peripherals disabled
HCLK
T
= 85 °C TA = 105 °C
A
72 MHz 69 70
48 MHz 50 50.5
36 MHz 39 39.5
24 MHz 27 28
16 MHz 20 20.5
8 MHz 11 11.5
72 MHz 37 37.5
48 MHz 28 28.5
36 MHz 22 22.5
24 MHz 16.5 17
16 MHz 12.5 13
8 MHz 8 8
Unit
mA
1. Based on characterization, not tested in production.
2. External clock is 8 MHz and PLL is on when f
Table 15. Maximum current consumption in Run mode, code with data processing
HCLK
> 8 MHz.
running from RAM
(1)
Max
Symbol Parameter Conditions f
HCLK
= 85 °C TA = 105 °C
T
A
72 MHz 66 67
48 MHz 43.5 45.5
External clock
(2)
peripherals enabled
36 MHz 33 35
, all
24 MHz 23 24.5
16 MHz 16 18
I
DD
Supply current
in Run mode
8 MHz 9 10.5
72 MHz 33 33.5
48 MHz 23 23.5
External clock
(2)
peripherals disabled
36 MHz 18 18.5
, all
24 MHz 13 13.5
16 MHz 10 10.5
8 MHz 6 6.5
1. Data based on characterization results, tested in production at V
2. External clock is 8 MHz and PLL is on when f
HCLK
> 8 MHz.
DD
max, f
HCLK
max.
Unit
mA
Doc ID 14611 Rev 8 45/130
Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE
0
10
20
30
40
50
60
70
-45 25 70 85 105
8 MHz
16 MHz
24 MHz
36 MHz
48 MHz
72 MHz
0
5
10
15
20
25
30
35
-45 25 70 85 105
Consumption
16 MHz
24 MHz
36 MHz
48 MHz
72 MHz
Figure 14. Typical current consumption in Run mode versus frequency (at 3.6 V) -
code with data processing running from RAM, peripherals enabled
Consumption (mA)
Temperature (°C)
Figure 15. Typical current consumption in Run mode versus frequency (at 3.6 V)-
code with data processing running from RAM, peripherals disabled
8 MHz
(mA)
Temperature (°C)
46/130 Doc ID 14611 Rev 8
STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics
Table 16. Maximum current consumption in Sleep mode, code running from Flash
or RAM
(1)
Max
Symbol Parameter Conditions f
(2)
External clock
, all
peripherals enabled
I
DD
Supply current
in Sleep mode
External clock
(2)
, all
peripherals disabled
1. Based on characterization, tested in production at V
2. External clock is 8 MHz and PLL is on when f
HCLK
DD
> 8 MHz.
HCLK
= 85 °C TA = 105 °C
T
A
72 MHz 45 46
48 MHz 31 32
36 MHz 24 25
24 MHz 17 17.5
16 MHz 12.5 13
8 MHz 8 8
72 MHz 8.5 9
48 MHz 7 7.5
36 MHz 6 6.5
24 MHz 5 5.5
16 MHz 4.5 5
8 MHz 4 4
max, f
max with peripherals enabled.
HCLK
Unit
mA
Doc ID 14611 Rev 8 47/130
Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE
1.8 V
2 V
2.4 V
3.3 V
3.6 V
Table 17. Typical and maximum current consumptions in Stop and Standby modes
Symbol Parameter Conditions
(1)
Typ
V
DD/VBAT
= 2.0 V
VDD/V
= 2.4 V
BAT
VDD/V
= 3.3 V
BAT
TA =
85 °C
Regulator in run mode, low-speed
Supply current in
Stop mode
I
DD
Supply current in
Standby mode
and high-speed internal RC
oscillators and high-speed oscillator
OFF (no independent watchdog)
Regulator in low-power mode, lowspeed and high-speed internal RC
oscillators and high-speed oscillator
OFF (no independent watchdog)
Low-speed internal RC oscillator
and independent watchdog ON
Low-speed internal RC oscillator
ON, independent watchdog OFF
Low-speed internal RC oscillator
and independent watchdog OFF,
34.5 35 379 1130
24.5 25 365 1110
33.8--
2.8 3.6 - -
1.9 2.1 5
(2)
low-speed oscillator and RTC OFF
I
DD_VBAT
Backup domain
supply current
Low-speed oscillator and RTC ON 1.05 1.1 1.4 2
(2)
Max
TA =
105 °C
(2)
6.5
(2)
2.3
Unit
µA
1. Typical values are measured at TA = 25 °C.
2. Based on characterization, not tested in production.
Figure 16. Typical current consumption on V
values
2.5
2
1.5
1
Consumption (µA)
0.5
0
–45 25 85105
with RTC on vs. temperature at different V
BAT
Temperature (°C)
BAT
ai17337
48/130 Doc ID 14611 Rev 8
STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics
0
100
200
300
400
500
600
700
-45257085105
2.4V
2.7V
3.0V
3.3V
3.6V
4EMPERATURE#
AI
Figure 17. Typical current consumption in Stop mode with regulator in run mode
versus temperature at different V
Consumption (µA)
values
DD
Temperat ure (°C)
6
6
6
#ONSUMPTIONμ!
6
6
# # # #
Doc ID 14611 Rev 8 49/130
Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE
0
100
200
300
400
500
600
700
-45257085105
2.4V
2.7V
3.0V
3.3V
3.6V
4EMPERATURE#
AI
Figure 18. Typical current consumption in Stop mode with regulator in low-power
mode versus temperature at different V
Consumption (µA)
values
DD
#ONSUMPTION μ!
Temperat ure (°C)
6
6
6
6
6
# # # #
50/130 Doc ID 14611 Rev 8
STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
-45 25 70 85 105
2.4V
2.7V
3.0V
3.3V
3.6V
#ONSUMPTION
!
AI
Figure 19. Typical current consumption in Standby mode versus temperature at
different V
Consumption (µA)
values
DD
Temperature (°C)
μ
6
6
6
6
6
# # # #
4EMPERATURE#
Doc ID 14611 Rev 8 51/130
Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE
Typical current consumption
The MCU is placed under the following conditions:
● All I/O pins are in input mode with a static value at V
● All peripherals are disabled except if it is explicitly mentioned.
● The Flash access time is adjusted to f
frequency (0 wait state from 0 to 24 MHz, 1
HCLK
wait state from 24 to 48 MHZ and 2 wait states above).
● Ambient temperature and V
● Prefetch is ON (Reminder: this bit must be set before clock setting and bus prescaling)
When the peripherals are enabled f
Table 18. Typical current consumption in Run mode, code with data processing
supply voltage conditions summarized in Tab le 1 0 .
DD
PCLK1
= f
HCLK
/4, f
running from Flash
Symbol Parameter Conditions f
External clock
(3)
Supply
I
DD
current in
Run mode
Running on high
speed internal RC
(HSI), AHB
prescaler used to
reduce the
frequency
1. Typical values are measures at TA = 25 °C, VDD = 3.3 V.
2. Add an additional power consumption of 0.8 mA per ADC for the analog part. In applications, this
consumption occurs only while the ADC is on (ADON bit is set in the ADC_CR2 register).
3. External clock is 8 MHz and PLL is on when f
HCLK
72 MHz 51 30.5
48 MHz 34.6 20.7
36 MHz 26.6 16.2
24 MHz 18.5 11.4
16 MHz 12.8 8.2
8 MHz 7.2 5
4 MHz 4.2 3.1
2 MHz 2.7 2.1
1 MHz 2 1.7
500 kHz 1.6 1.4
125 kHz 1.3 1.2
64 MHz 45 27
48 MHz 34 20.1
36 MHz 26 15.6
24 MHz 17.9 10.8
16 MHz 12.2 7.6
8 MHz 6.6 4.4
4 MHz 3.6 2.5
2 MHz 2.1 1.5
1 MHz 1.4 1.1
500 kHz 1 0.8
125 kHz 0.7 0.6
> 8 MHz.
HCLK
or VSS (no load).
DD
2 = f
PCLK
HCLK
Typ
All peripherals
enabled
(2)
/2, f
ADCCLK
(1)
All peripherals
disabled
= f
PCLK2
/4
Unit
mA
mA
52/130 Doc ID 14611 Rev 8
STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics
Table 19. Typical current consumption in Sleep mode, code running from Flash or
RAM
(1)
Typ
Symbol Parameter Conditions f
72 MHz 29.5 6.4
48 MHz 20 4.6
36 MHz 15.1 3.6
24 MHz 10.4 2.6
16 MHz 7.2 2
External clock
(3)
8 MHz 3.9 1.3
4 MHz 2.6 1.2
2 MHz 1.85 1.15
1 MHz 1.5 1.1
500 kHz 1.3 1.05
Supply
I
DD
current in
Sleep mode
125 kHz 1.2 1.05
64 MHz 25.6 5.1
48 MHz 19.4 4
HCLK
All peripherals
enabled
(2)
All peripherals
disabled
Unit
mA
36 MHz 14.5 3
24 MHz 9.8 2
Running on high
speed internal RC
(HSI), AHB prescaler
used to reduce the
frequency
16 MHz 6.6 1.4
8 MHz 3.3 0.7
4 MHz 2 0.6
2 MHz 1.25 0.55
1 MHz 0.9 0.5
500 kHz 0.7 0.45
125 kHz 0.6 0.45
1. Typical values are measures at TA = 25 °C, VDD = 3.3 V.
2. Add an additional power consumption of 0.8 mA per ADC for the analog part. In applications, this
consumption occurs only while the ADC is on (ADON bit is set in the ADC_CR2 register).
3. External clock is 8 MHz and PLL is on when f
HCLK
> 8 MHz.
Doc ID 14611 Rev 8 53/130
Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE
On-chip peripheral current consumption
The current consumption of the on-chip peripherals is given in Ta bl e 2 0 . The MCU is placed
under the following conditions:
● all I/O pins are in input mode with a static value at V
● all peripherals are disabled unless otherwise mentioned
● the given value is calculated by measuring the current consumption
– with all peripherals clocked off
– with only one peripheral clocked on
● ambient operating temperature and V
supply voltage conditions summarized in
DD
Ta bl e 7
Table 20. Peripheral current consumption
(1)
or VSS (no load)
DD
APB1
Peripheral Typical consumption at 25 °C
TIM2 1.2
TIM3 1.2
TIM4 1.2
TIM5 1.2
TIM6 0.4
TIM7 0.4
SPI2 0.2
SPI3 0.2
USART2 0.4
USART3 0.4
UART4 0.5
UART5 0.6
I2C1 0.4
I2C2 0.4
USB 0.65
CAN 0.72
DAC 0.72
Unit
mA
54/130 Doc ID 14611 Rev 8
STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics
Table 20. Peripheral current consumption
Peripheral Typical consumption at 25 °C
GPIOA 0.55
GPIOB 0.72
GPIOC 0.72
GPIOD 0.55
GPIOE 1
GPIOF 0.72
APB2
1. f
2. Specific conditions for ADC: f
= 72 MHz, f
HCLK
in the ADC_CR2 register is set to 1.
GPIOG 1
(2)
ADC1
ADC2 1.7
TIM1 1.8
SPI1 0.4
TIM8 1.7
USART1 0.9
ADC3 1.7
= f
/2, f
= f
APB1
HCLK
APB2
= 56 MHz, f
HCLK
, default prescaler value for each peripheral.
HCLK
= f
APB1
(1)
(continued)
/2, f
HCLK
APB2
= f
1.9
HCLK
, f
ADCCLK
= f
APB2/4
Unit
mA
, ADON bit
5.3.6 External clock source characteristics
High-speed external user clock generated from an external source
The characteristics given in Tab l e 2 1 result from tests performed using an high-speed
external clock source, and under ambient temperature and supply voltage conditions
summarized in Ta bl e 1 0 .
Table 21. High-speed external user clock characteristics
Symbol Parameter Conditions Min Typ Max Unit
f
HSE_ext
V
HSEH
V
HSEL
t
w(HSE)
t
w(HSE)
t
r(HSE)
t
f(HSE)
C
in(HSE)
DuCy
I
1. Guaranteed by design, not tested in production.
User external clock source
frequency
(1)
OSC_IN input pin high level voltage 0.7V
OSC_IN input pin low level voltage V
OSC_IN high or low time
OSC_IN rise or fall time
(1)
(1)
OSC_IN input capacitance
Duty cycle 45 55 %
(HSE)
OSC_IN Input leakage current VSS≤ VIN≤ V
L
(1)
1825MHz
DD
SS
V
0.3V
DD
5
20
5pF
DD
±1 µA
V
DD
ns
Doc ID 14611 Rev 8 55/130
Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE
ai14143
OS C _I N
EXTERNAL
STM32F103xx
CLOCK SO URCE
V
HSEH
t
f(HSE)
t
W(HSE)
I
L
90%
10%
T
HSE
t
t
r(HSE)
t
W(HSE)
f
HSE_ext
V
HSEL
Low-speed external user clock generated from an external source
The characteristics given in Tab l e 2 2 result from tests performed using an low-speed
external clock source, and under ambient temperature and supply voltage conditions
summarized in Ta bl e 1 0 .
Table 22. Low-speed external user clock characteristics
Symbol Parameter Conditions Min Typ Max Unit
f
LSE_ext
V
LSEH
V
t
w(LSE)
t
w(LSE)
t
r(LSE)
t
f(LSE)
C
in(LSE)
DuCy
LSEL
User External clock source
frequency
OSC32_IN input pin high level
voltage
OSC32_IN input pin low level
voltage
OSC32_IN high or low time
OSC32_IN rise or fall time
OSC32_IN input capacitance
Duty cycle 30 70 %
(LSE)
I
OSC32_IN Input leakage current
L
(1)
(1)
(1)
(1)
V
SS
≤ VIN≤ V
D
0.7V
DD
V
SS
450
D
1. Guaranteed by design, not tested in production.
Figure 20. High-speed external clock source AC timing diagram
32.768 1000 kHz
V
DD
V
0.3V
DD
ns
50
5pF
±1 µA
56/130 Doc ID 14611 Rev 8
STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics
ai14144b
OSC32_IN
EXTERNAL
STM32F103xx
CLOCK SO URCE
V
LSEH
t
f(LSE)
t
W(LSE)
I
L
90%
10%
T
LSE
t
t
r(LSE)
t
W(LSE)
f
LSE_ext
V
LSEL
Figure 21. Low-speed external clock source AC timing diagram
Doc ID 14611 Rev 8 57/130
Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE
ai14145
OSC_OU T
OSC_IN
f
HSE
C
L1
R
F
STM32F103xx
8 MHz
resonator
R
EXT
(1)
C
L2
Resonator with
integrated capacitors
Bias
controlled
gain
High-speed external clock generated from a crystal/ceramic resonator
The high-speed external (HSE) clock can be supplied with a 4 to 16 MHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on characterization
results obtained with typical external components specified in Ta bl e 2 3. In the application,
the resonator and the load capacitors have to be placed as close as possible to the oscillator
pins in order to minimize output distortion and startup stabilization time. Refer to the crystal
resonator manufacturer for more details on the resonator characteristics (frequency,
package, accuracy).
Table 23. HSE 4-16 MHz oscillator characteristics
Symbol Parameter Conditions Min Typ Max Unit
(1)(2)
f
OSC_IN
R
Oscillator frequency 4 8 16 MHz
Feedback resistor 200 kΩ
F
Recommended load capacitance
C
i
g
t
SU(HSE)
versus equivalent serial
resistance of the crystal (R
HSE driving current
2
Oscillator transconductance Startup 25 mA/V
m
(4)
Startup time VDD is stabilized 2 ms
(3)
)
S
RS = 30 Ω 30 pF
V
= 3.3 V, VIN=V
DD
SS
with 30 pF load
1mA
1. Resonator characteristics given by the crystal/ceramic resonator manufacturer.
2. Based on characterization results, not tested in production.
3. The relatively low value of the RF resistor offers a good protection against issues resulting from use in a
humid environment, due to the induced leakage and the bias condition change. However, it is
recommended to take this point into account if the MCU is used in tough humidity conditions.
4. t
is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz
SU(HSE)
oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly
with the crystal manufacturer
For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors in the
5 pF to 25 pF range (typ.), designed for high-frequency applications, and selected to match
the requirements of the crystal or resonator (see Figure 22). C
and C
L1
are usually the
L2
same size. The crystal manufacturer typically specifies a load capacitance which is the
series combination of C
and CL2. PCB and MCU pin capacitance must be included (10 pF
L1
can be used as a rough estimate of the combined pin and board capacitance) when sizing
C
and CL2. Refer to the application note AN2867 “Oscillator design guide for ST
L1
microcontrollers” available from the ST website www.st.com.
Figure 22. Typical application with an 8 MHz crystal
1. R
58/130 Doc ID 14611 Rev 8
value depends on the crystal characteristics.
EXT
STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics
Low-speed external clock generated from a crystal/ceramic resonator
The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on characterization
results obtained with typical external components specified in Ta bl e 2 4. In the application,
the resonator and the load capacitors have to be placed as close as possible to the oscillator
pins in order to minimize output distortion and startup stabilization time. Refer to the crystal
resonator manufacturer for more details on the resonator characteristics (frequency,
package, accuracy).
Table 24. LSE oscillator characteristics (f
= 32.768 kHz)
LSE
Symbol Parameter Conditions Min Typ Max Unit
(1) (2)
R
Feedback resistor 5 MΩ
F
Recommended load capacitance
, C
C
L1
I
g
versus equivalent serial
L2
resistance of the crystal (R
LSE driving current V
2
Oscillator transconductance 5 µA/V
m
)
S
R
= 30 kΩ 15 pF
S
= 3.3 V, V
DD
IN
= V
SS
1.4 µA
TA = 50 °C 1.5
T
= 25 °C 2.5
A
T
= 10 °C 4
A
= 0 °C 6
T
is
t
1. Based on characterization, not tested in production.
2. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator design guide for
3. t
(3)
SU(LSE)
ST microcontrollers”.
SU(LSE)
reached. This value is measured for a standard crystal and it can vary significantly with the crystal manufacturer
Startup time
is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation is
V
DD
stabilized
A
= -10 °C 10
T
A
T
= -20 °C 17
A
= -30 °C 32
T
A
= -40 °C 60
T
A
s
Note: For CL1 and CL2, it is recommended to use high-quality ceramic capacitors in the 5 pF to
15 pF range selected to match the requirements of the crystal or resonator (see Figure 23).
C
and C
L1
capacitance which is the series combination of C
Load capacitance C
C
is the pin capacitance and board or trace PCB-related capacitance. Typically, it is
stray
are usually the same size. The crystal manufacturer typically specifies a load
L2,
has the following formula: CL = CL1 x CL2 / (CL1 + CL2) + C
L
and CL2.
L1
between 2 pF and 7 pF.
Caution: To avoid exceeding the maximum value of C
to use a resonator with a load capacitance C
capacitance of 12.5 pF.
Example: if you choose a resonator with a load capacitance of C
then C
= CL2 = 8 pF.
L1
Doc ID 14611 Rev 8 59/130
and CL2 (15 pF) it is strongly recommended
L1
≤
7 pF. Never use a resonator with a load
L
= 6 pF, and C
L
stray
stray
where
= 2 pF,
Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE
ai14146
OSC32_OUT
OSC32_IN
f
LSE
C
L1
R
F
STM32F103xx
32.768 kHz
resonator
C
L2
Resonator with
integrated capacitors
Bias
controlled
gain
Figure 23. Typical application with a 32.768 kHz crystal
5.3.7 Internal clock source characteristics
The parameters given in Tab l e 2 5 are derived from tests performed under ambient
temperature and V
High-speed internal (HSI) RC oscillator
Table 25. HSI oscillator characteristics
Symbol Parameter Conditions Min Typ Max Unit
supply voltage conditions summarized in Tab l e 1 0 .
DD
(1)
f
HSI
DuCy
ACC
t
su(HSI)
I
DD(HSI)
1. V
DD
2. Refer to application note AN2868 “STM32F10xxx internal RC oscillator (HSI) calibration” available from
the ST website www.st.com.
Frequency 8 MHz
Duty cycle 45 55 %
(HSI)
User-trimmed with the RCC_CR
(2)
register
Accuracy of the HSI
HSI
oscillator
Factorycalibrated
HSI oscillator
(4)
startup time
HSI oscillator power
(4)
consumption
= 3.3 V, TA = –40 to 105 °C unless otherwise specified.
TA = –40 to 105 °C –2 2.5 %
= –10 to 85 °C –1.5 2.2 %
T
A
(4)
T
= 0 to 70 °C –1.3 2 %
A
= 25 °C –1.1 1.8 %
T
A
12µs
80 100 µA
(3)
1
%
3. Guaranteed by design, not tested in production.
4. Based on characterization, not tested in production.
Low-speed internal (LSI) RC oscillator
Table 26. LSI oscillator characteristics
Symbol Parameter Min Typ Max Unit
(2)
f
LSI
Frequency 30 40 60 kHz
(1)
60/130 Doc ID 14611 Rev 8
STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics
Table 26. LSI oscillator characteristics
(1)
Symbol Parameter Min Typ Max Unit
(3)
t
su(LSI)
I
DD(LSI)
LSI oscillator startup time 85 µs
(3)
LSI oscillator power consumption 0.65 1.2 µA
1. VDD = 3 V, TA = –40 to 105 °C unless otherwise specified.
2. Based on characterization, not tested in production.
3. Guaranteed by design, not tested in production.
Wakeup time from low-power mode
The wakeup times given in Ta bl e 2 7 is measured on a wakeup phase with a 8-MHz HSI RC
oscillator. The clock source used to wake up the device depends from the current operating
mode:
● Stop or Standby mode: the clock source is the RC oscillator
● Sleep mode: the clock source is the clock that was set before entering Sleep mode.
All timings are derived from tests performed under ambient temperature and V
voltage conditions summarized in Tabl e 1 0.
Table 27. Low-power mode wakeup timings
Symbol Parameter Typ Unit
supply
DD
(1)
t
WUSLEEP
t
WUSTOP
t
WUSTDBY
1. The wakeup times are measured from the wakeup event to the point in which the user application code
reads the first instruction.
Wakeup from Sleep mode 1.8 µs
Wakeup from Stop mode (regulator in run mode) 3.6
(1)
Wakeup from Stop mode (regulator in low power mode) 5.4
(1)
Wakeup from Standby mode 50 µs
µs
Doc ID 14611 Rev 8 61/130
Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE
5.3.8 PLL characteristics
The parameters given in Tab l e 2 8 are derived from tests performed under ambient
temperature and V
Table 28. PLL characteristics
Symbol Parameter
f
PLL_IN
f
PLL_OUT
t
LOCK
Jitter Cycle-to-cycle jitter 300 ps
1. Based on characterization, not tested in production.
2. Take care of using the appropriate multiplier factors so as to have PLL input clock values compatible with
the range defined by f
supply voltage conditions summarized in Tab l e 1 0 .
DD
Val ue
Unit
PLL input clock
(2)
Min Typ Max
(1)
18.0 25 MHz
PLL input clock duty cycle 40 60 %
PLL multiplier output clock 16 72 MHz
PLL lock time 200 µs
.
PLL_OUT
5.3.9 Memory characteristics
Flash memory
The characteristics are given at TA = –40 to 105 °C unless otherwise specified.
Table 29. Flash memory characteristics
Symbol Parameter Conditions Min Typ Max
t
t
ERASE
V
1. Guaranteed by design, not tested in production.
16-bit programming time TA = –40 to +105 °C 40 52.5 70 µs
prog
Page (2 KB) erase time TA = –40 to +105 °C 20 40 ms
Mass erase time TA = –40 to +105 °C 20 40 ms
t
ME
Read mode
= 72 MHz with 2 wait
f
HCLK
states, V
= 3.3 V
DD
Write mode
= 72 MHz, VDD = 3.3 V
f
I
DD
Supply current
HCLK
Erase mode
= 72 MHz, VDD = 3.3 V
f
HCLK
Power-down mode / Halt,
V
= 3.0 to 3.6 V
DD
Programming voltage 2 3.6 V
prog
(1)
Unit
28 mA
7mA
5mA
50 µA
62/130 Doc ID 14611 Rev 8
STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics
Table 30. Flash memory endurance and data retention
Val ue
Symbol Parameter Conditions
Min
(1)
Unit
N
t
RET
END
Endurance
Data retention
1. Based on characterization not tested in production.
2. Cycling performed over the whole temperature range.
5.3.10 FSMC characteristics
Asynchronous waveforms and timings
Figure 24 through Figure 27 represent asynchronous waveforms and Ta bl e 3 1 through
Ta bl e 3 4 provide the corresponding timings. The results shown in these tables are obtained
with the following FSMC configuration:
● AddressSetupTime = 0
● AddressHoldTime = 1
● DataSetupTime = 1
TA = –40 to +85 °C (6 suffix versions)
TA = –40 to +105 °C (7 suffix versions)
1 kcycle
10 kcycles
(2)
at TA = 85 °C
(2)
at TA = 105 °C 10
(2)
at TA = 55 °C 20
10
30
kcycles
Years1 kcycle
Doc ID 14611 Rev 8 63/130
Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE
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T
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Figure 24. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms
1. Mode 2/B, C and D only. In Mode 1, FSMC_NADV is not used.
Table 31. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings
Symbol Parameter Min Max Unit
t
w(NE)
t
v(NOE_NE)
t
w(NOE)
t
h(NE_NOE)
t
v(A_NE)
t
h(A_NOE)
t
v(BL_NE)
t
h(BL_NOE)
t
su(Data_NE)
t
su(Data_NOE)
t
h(Data_NOE)
t
h(Data_NE)
64/130 Doc ID 14611 Rev 8
FSMC_NE low time 5t
FSMC_NEx low to FSMC_NOE low 0.5 1.5 ns
FSMC_NOE low time 5t
FSMC_NOE high to FSMC_NE high hold time –1.5 ns
FSMC_NEx low to FSMC_A valid 0 ns
Address hold time after FSMC_NOE high 0.1 ns
FSMC_NEx low to FSMC_BL valid 0 ns
FSMC_BL hold time after FSMC_NOE high 0 ns
Data to FSMC_NEx high setup time 2t
Data to FSMC_NOEx high setup time 2t
Data hold time after FSMC_NOE high 0 ns
Data hold time after FSMC_NEx high 0 ns
– 1.5 5t
HCLK
– 1.5 5t
HCLK
+ 25 ns
HCLK
+ 25 ns
HCLK
HCLK
HCLK
(1) (2)
+ 2 ns
+ 1.5 ns
STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics
Table 31. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings
(1) (2)
Symbol Parameter Min Max Unit
t
v(NADV_NE)
t
w(NADV)
1. CL = 15 pF.
2. Based on characterisation, not tested in production.
FSMC_NEx low to FSMC_NADV low 5 ns
FSMC_NADV low time t
+ 1.5 ns
HCLK
Figure 25. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms
t
w(NE)
FSMC_NEx
FSMC_NOE
Address
NBL
t
w(NWE)
t
h(BL_NWE)
t
h(Data_NWE)
t
h(A_NWE)
Data
t
h(NE_NWE)
FSMC_NWE
FSMC_A[25:0]
FSMC_NBL[1:0]
FSMC_D[15:0]
FSMC_NADV
t
v(NWE_NE)
t
v(A_NE)
t
v(BL_NE)
t
v(Data_NE)
t
v(NADV_NE)
t
(1)
w(NADV)
ai14990
1. Mode 2/B, C and D only. In Mode 1, FSMC_NADV is not used.
Table 32. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings
(1)(2)
Symbol Parameter Min Max Unit
t
w(NE)
t
v(NWE_NE)
t
w(NWE)
t
h(NE_NWE)
t
v(A_NE)
t
h(A_NWE)
t
v(BL_NE)
t
h(BL_NWE)
t
v(Data_NE)
t
h(Data_NWE)
FSMC_NE low time 3t
FSMC_NEx low to FSMC_NWE low t
FSMC_NWE low time t
FSMC_NWE high to FSMC_NE high hold time t
FSMC_NEx low to FSMC_A valid 7.5 ns
Address hold time after FSMC_NWE high t
FSMC_NEx low to FSMC_BL valid 1.5 ns
FSMC_BL hold time after FSMC_NWE high t
FSMC_NEx low to Data valid t
Data hold time after FSMC_NWE high t
– 1 3t
HCLK
– 0.5 t
HCLK
– 0.5 t
HCLK
HCLK
HCLK
– 0.5 ns
HCLK
HCLK
HCLK
+ 1.5 ns
HCLK
+ 1.5 ns
HCLK
+ 7 ns
HCLK
+ 2 ns
ns
ns
ns
Doc ID 14611 Rev 8 65/130
Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE
NBL
Data
FSMC_NBL[1:0]
FSMC_
AD[15:0]
t
v(BL_NE)
t
h(Data_NE)
Address
FSMC_A[25:16]
t
v(A_NE)
FSMC_NWE
t
v(A_NE)
ai14892b
Address
FSMC_NADV
t
v(NADV_NE)
t
w(NADV)
t
su(Data_NE)
t
h(AD_NADV)
FSMC_NE
FSMC_NOE
t
w(NE)
t
w(NOE)
t
v(NOE_NE)
t
h(NE_NOE)
t
h(A_NOE)
t
h(BL_NOE)
t
su(Data_NOE)
t
h(Data_NOE)
Table 32. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings
Symbol Parameter Min Max Unit
t
v(NADV_NE)
t
w(NADV)
1. CL = 15 pF.
2. Based on characterisation, not tested in production.
FSMC_NEx low to FSMC_NADV low 5.5 ns
FSMC_NADV low time t
+ 1.5 ns
HCLK
Figure 26. Asynchronous multiplexed PSRAM/NOR read waveforms
(1)(2)
Table 33. Asynchronous multiplexed PSRAM/NOR read timings
Symbol Parameter Min Max Unit
t
66/130 Doc ID 14611 Rev 8
w(NE)
t
v(NOE_NE)
t
w(NOE)
t
h(NE_NOE)
t
v(A_NE)
t
v(NADV_NE)
t
w(NADV)
t
h(AD_NADV)
t
h(A_NOE)
FSMC_NE low time 7t
FSMC_NEx low to FSMC_NOE low 3t
FSMC_NOE low time 4t
FSMC_NOE high to FSMC_NE high hold time –1 ns
FSMC_NEx low to FSMC_A valid 0 ns
FSMC_NEx low to FSMC_NADV low 3 5 ns
FSMC_NADV low time t
FSMC_AD (address) valid hold time after
FSMC_NADV high
Address hold time after FSMC_NOE high t
HCLK
HCLK
HCLK
HCLK
t
HCLK
HCLK
– 2 7t
– 0.5 3t
– 1 4t
–1.5 t
(1)(2)
HCLK
HCLK
HCLK
HCLK
+ 2 ns
+ 1.5 ns
+ 2 ns
+ 1.5 ns
ns
ns
STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics
Table 33. Asynchronous multiplexed PSRAM/NOR read timings
(1)(2)
(continued)
Symbol Parameter Min Max Unit
t
h(BL_NOE)
t
v(BL_NE)
t
su(Data_NE)
t
su(Data_NOE)
t
h(Data_NE)
t
h(Data_NOE)
1. CL = 15 pF.
2. Based on characterization, not tested in production.
FSMC_BL hold time after FSMC_NOE high 0 ns
FSMC_NEx low to FSMC_BL valid 0 ns
Data to FSMC_NEx high setup time 2t
Data to FSMC_NOE high setup time 2t
+ 24 ns
HCLK
+ 25 ns
HCLK
Data hold time after FSMC_NEx high 0 ns
Data hold time after FSMC_NOE high 0 ns
Doc ID 14611 Rev 8 67/130
Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE
NBL
Data
FSMC_NEx
FSMC_NBL[1:0]
FSMC_
AD[15:0]
t
v(BL_NE)
t
h(Data_NWE)
FSMC_NOE
Address
FSMC_A[25:16]
t
v(A_NE)
t
w(NWE)
FSMC_NWE
t
v(NWE_NE)
t
h(NE_NWE)
t
h(A_NWE)
t
h(BL_NWE)
t
v(A_NE)
t
w(NE)
ai14891B
Address
FSMC_NADV
t
v(NADV_NE)
t
w(NADV)
t
v(Data_NADV)
t
h(AD_NADV)
Figure 27. Asynchronous multiplexed PSRAM/NOR write waveforms
68/130 Doc ID 14611 Rev 8
Table 34. Asynchronous multiplexed PSRAM/NOR write timings
(1)(2)
Symbol Parameter Min Max Unit
t
w(NE)
t
v(NWE_NE)
t
w(NWE)
t
h(NE_NWE)
t
v(A_NE)
t
v(NADV_NE)
t
w(NADV)
t
h(AD_NADV)
t
h(A_NWE)
t
v(BL_NE)
t
h(BL_NWE)
t
v(Data_NADV)
t
h(Data_NWE)
1. C
= 15 pF.
L
2. Based on characterization, not tested in production.
FSMC_NE low time 5t
FSMC_NEx low to FSMC_NWE low 2t
FSMC_NWE low time 2t
FSMC_NWE high to FSMC_NE high hold time t
FSMC_NEx low to FSMC_A valid 7 ns
FSMC_NEx low to FSMC_NADV low 3 5 ns
FSMC_NADV low time t
FSMC_AD (address) valid hold time after
FSMC_NADV high
Address hold time after FSMC_NWE high 4t
FSMC_NEx low to FSMC_BL valid 1.6 ns
FSMC_BL hold time after FSMC_NWE high t
FSMC_NADV high to Data valid t
Data hold time after FSMC_NWE high t
– 1 5t
HCLK
HCLK
– 1 2t
HCLK
– 1 ns
HCLK
– 1 t
HCLK
t
– 3 ns
HCLK
HCLK
– 1.5 ns
HCLK
– 5 ns
HCLK
HCLK
2t
HCLK
HCLK
HCLK
HCLK
+ 2 ns
+ 1 ns
+ 2 ns
+ 1 ns
+ 1.5 ns
ns
STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics
Synchronous waveforms and timings
Figure 28 through Figure 31 represent synchronous waveforms and Ta bl e 3 6 through
Ta bl e 3 8 provide the corresponding timings. The results shown in these tables are obtained
with the following FSMC configuration:
● BurstAccessMode = FSMC_BurstAccessMode_Enable;
● MemoryType = FSMC_MemoryType_CRAM;
● WriteBurst = FSMC_WriteBurst_Enable;
● CLKDivision = 1; (0 is not supported, see the STM32F10xxx reference manual)
● DataLatency = 1 for NOR Flash; DataLatency = 0 for PSRAM
Figure 28. Synchronous multiplexed NOR/PSRAM read timings
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Doc ID 14611 Rev 8 69/130
Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE
Table 35. Synchronous multiplexed NOR/PSRAM read timings
(1)(2)
Symbol Parameter Min Max Unit
t
w(CLK)
t
d(CLKL-NExL)
t
d(CLKL-NExH)
t
d(CLKL-NADVL)
t
d(CLKL-NADVH)
t
d(CLKL-AV)
t
d(CLKL-AIV)
t
d(CLKL-NOEL)
t
d(CLKL-NOEH)
t
d(CLKL-ADV)
t
d(CLKL-ADIV)
t
su(ADV-CLKH)
t
h(CLKH-ADV)
t
su(NWAITV-CLKH)
t
h(CLKH-NWAITV)
= 15 pF.
1. C
L
2. Based on characterization, not tested in production.
FSMC_CLK period 27.7 ns
FSMC_CLK low to FSMC_NEx low (x = 0...2) 1.5 ns
FSMC_CLK low to FSMC_NEx high (x = 0...2) 2 ns
FSMC_CLK low to FSMC_NADV low 4 ns
FSMC_CLK low to FSMC_NADV high 5 ns
FSMC_CLK low to FSMC_Ax valid (x = 16...25) 0 ns
FSMC_CLK low to FSMC_Ax invalid (x = 16...25) 2 ns
FSMC_CLK low to FSMC_NOE low 1 ns
FSMC_CLK low to FSMC_NOE high 0.5 ns
FSMC_CLK low to FSMC_AD[15:0] valid 12 ns
FSMC_CLK low to FSMC_AD[15:0] invalid 0 ns
FSMC_A/D[15:0] valid data before FSMC_CLK
high
6 ns
FSMC_A/D[15:0] valid data after FSMC_CLK high 0 ns
FSMC_NWAIT valid before FSMC_CLK high 8 ns
FSMC_NWAIT valid after FSMC_CLK high 2 ns
70/130 Doc ID 14611 Rev 8
STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics
Figure 29. Synchronous multiplexed PSRAM write timings
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Doc ID 14611 Rev 8 71/130
Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE
Table 36. Synchronous multiplexed PSRAM write timings
(1)(2)
Symbol Parameter Min Max Unit
t
w(CLK)
t
d(CLKL-NExL)
t
d(CLKL-NExH)
t
d(CLKL-NADVL)
t
d(CLKL-NADVH)
t
d(CLKL-AV)
t
d(CLKL-AIV)
t
d(CLKL-NWEL)
t
d(CLKL-NWEH)
t
d(CLKL-ADV)
t
d(CLKL-ADIV)
t
d(CLKL-Data)
t
su(NWAITV-CLKH)
t
h(CLKH-NWAITV)
t
d(CLKL-NBLH)
1. C
= 15 pF.
L
2. Based on characterization, not tested in production.
FSMC_CLK period 27.7 ns
FSMC_CLK low to FSMC_Nex low (x = 0...2) 2 ns
FSMC_CLK low to FSMC_NEx high (x = 0...2) 2 ns
FSMC_CLK low to FSMC_NADV low 4 ns
FSMC_CLK low to FSMC_NADV high 5 ns
FSMC_CLK low to FSMC_Ax valid (x = 16...25) 0 ns
FSMC_CLK low to FSMC_Ax invalid (x = 16...25) 2 ns
FSMC_CLK low to FSMC_NWE low 1 ns
FSMC_CLK low to FSMC_NWE high 1 ns
FSMC_CLK low to FSMC_AD[15:0] valid 12 ns
FSMC_CLK low to FSMC_AD[15:0] invalid 3 ns
FSMC_A/D[15:0] valid after FSMC_CLK low 6 ns
FSMC_NWAIT valid before FSMC_CLK high 7 ns
FSMC_NWAIT valid after FSMC_CLK high 2 ns
FSMC_CLK low to FSMC_NBL high 1 ns
72/130 Doc ID 14611 Rev 8
STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics
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Figure 30. Synchronous non-multiplexed NOR/PSRAM read timings
Table 37. Synchronous non-multiplexed NOR/PSRAM read timings
Symbol Parameter Min Max Unit
t
w(CLK)
t
d(CLKL-NExL)
t
t
t
t
t
t
t
t
t
t
t
1. C
d(CLKL-NExH)
d(CLKL-NADVL)
d(CLKL-NADVH)
d(CLKL-AV)
d(CLKL-AIV)
d(CLKL-NOEL)
d(CLKL-NOEH)
su(DV-CLKH)
h(CLKH-DV)
su(NWAITV-CLKH)
h(CLKH-NWAITV)
= 15 pF.
L
2. Based on characterization, not tested in production.
FSMC_CLK period 27.7 ns
FSMC_CLK low to FSMC_NEx low (x = 0...2) 1.5 ns
FSMC_CLK low to FSMC_NEx high (x = 0...2) 2 ns
FSMC_CLK low to FSMC_NADV low 4 ns
FSMC_CLK low to FSMC_NADV high 5 ns
FSMC_CLK low to FSMC_Ax valid (x = 0...25) 0 ns
FSMC_CLK low to FSMC_Ax invalid (x = 0...25) 4 ns
FSMC_CLK low to FSMC_NOE low 1.5 ns
FSMC_CLK low to FSMC_NOE high 1.5 ns
FSMC_D[15:0] valid data before FSMC_CLK high 6.5 ns
FSMC_D[15:0] valid data after FSMC_CLK high 7 ns
FSMC_NWAIT valid before FSMC_SMCLK high 7 ns
FSMC_NWAIT valid after FSMC_CLK high 2 ns
Doc ID 14611 Rev 8 73/130
(1)(2)
Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE
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Figure 31. Synchronous non-multiplexed PSRAM write timings
Table 38. Synchronous non-multiplexed PSRAM write timings
Symbol Parameter Min Max Unit
FSMC_CLK period 27.7 ns
FSMC_CLK low to FSMC_NEx low (x = 0...2) 2 ns
FSMC_CLK low to FSMC_NEx high (x = 0...2) 2 ns
FSMC_CLK low to FSMC_NADV low 4 ns
FSMC_CLK low to FSMC_NADV high 5 ns
FSMC_CLK low to FSMC_Ax valid (x = 16...25) 0 ns
FSMC_CLK low to FSMC_Ax invalid (x = 16...25) 2 ns
FSMC_CLK low to FSMC_NWE low 1 ns
FSMC_CLK low to FSMC_NWE high 1 ns
FSMC_D[15:0] valid data after FSMC_CLK low 6 ns
FSMC_NWAIT valid before FSMC_CLK high 7 ns
FSMC_NWAIT valid after FSMC_CLK high 2 ns
FSMC_CLK low to FSMC_NBL high 1 ns
t
w(CLK)
t
d(CLKL-NExL)
t
d(CLKL-NExH)
t
d(CLKL-NADVL)
t
d(CLKL-NADVH)
t
t
t
t
t
t
t
t
1. C
d(CLKL-AV)
d(CLKL-AIV)
d(CLKL-NWEL)
d(CLKL-NWEH)
d(CLKL-Data)
su(NWAITV-CLKH)
h(CLKH-NWAITV)
d(CLKL-NBLH)
= 15 pF.
L
2. Based on characterization, not tested in production.
74/130 Doc ID 14611 Rev 8
(1)(2)
STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics
PC Card/CompactFlash controller waveforms and timings
Figure 32 through Figure 37 represent synchronous waveforms and Ta bl e 3 9 provides the
corresponding timings. The results shown in this table are obtained with the following FSMC
configuration:
● COM.FSMC_SetupTime = 0x04;
● COM.FSMC_WaitSetupTime = 0x07;
● COM.FSMC_HoldSetupTime = 0x04;
● COM.FSMC_HiZSetupTime = 0x00;
● ATT.FSMC_SetupTime = 0x04;
● ATT.FSMC_WaitSetupTime = 0x07;
● ATT.FSMC_HoldSetupTime = 0x04;
● ATT.FSMC_HiZSetupTime = 0x00;
● IO.FSMC_SetupTime = 0x04;
● IO.FSMC_WaitSetupTime = 0x07;
● IO.FSMC_HoldSetupTime = 0x04;
● IO.FSMC_HiZSetupTime = 0x00;
● TCLRSetupTime = 0;
● TARSetupTime = 0;
Figure 32. PC Card/CompactFlash controller waveforms for common memory read
access
FSMC_NCE4_2
FSMC_NCE4_1
FSMC_A[10:0]
FSMC_NREG
FSMC_NIOWR
FSMC_NIORD
FSMC_NWE
FSMC_N
FSMC_D[15:0]
1. FSMC_NCE4_2 remains high (inactive during 8-bit access.
(1)
t
d(NCE4_1-NOE)
OE
t
v(NCEx-A)
t
d(NREG-NCEx)
t
d(NIORD-NCEx)
t
w(NOE)
t
su(D-NOE)
t
h(NCEx-AI)
t
h(NCEx-NREG)
t
h(NCEx-NIORD)
t
h(NCEx-
NIOWR
t
h(NOE-D)
)
ai14895b
Doc ID 14611 Rev 8 75/130
Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE
t
d(NCE4_1-NWE)
t
w(NWE)
t
h(NWE-D)
t
v(NCE4_1-A)
t
d(NREG-NCE4_1)
t
d(NIORD-NCE4_1)
t
h(NCE4_1-AI)
MEMxHIZ =1
t
v(NWE-D)
t
h(NCE4_1-NREG)
t
h(NCE4_1-NIORD)
t
h(NCE4_1-NIOWR)
ai14896b
FSMC_NWE
FSMC_N
OE
FSMC_D[15:0]
FSMC_A[10:0]
FSMC_NCE4_1
FSMC_NREG
FSMC_NIOWR
FSMC_NIORD
t
d(NWE-NCE4_1)
t
d(D-NWE)
FSMC_NCE4_2
High
Figure 33. PC Card/CompactFlash controller waveforms for common memory write
access
76/130 Doc ID 14611 Rev 8
STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics
t
d(NCE4_1-NOE)
t
w(NOE)
t
su(D-NOE)
t
h(NOE-D)
t
v(NCE4_1-A)
t
h(NCE4_1-AI)
t
d(NREG-NCE4_1)
t
h(NCE4_1-NREG)
ai14897b
FSMC_NWE
FSMC_NOE
FSMC_D[15:0]
(1)
FSMC_A[10:0]
FSMC_NCE4_2
FSMC_NCE4_1
FSMC_NREG
FSMC_NIOWR
FSMC_NIORD
t
d(NOE-NCE4_1)
High
Figure 34. PC Card/CompactFlash controller waveforms for attribute memory read
access
1. Only data bits 0...7 are read (bits 8...15 are disregarded).
Doc ID 14611 Rev 8 77/130
Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE
Figure 35. PC Card/CompactFlash controller waveforms for attribute memory write
access
FSMC_NCE4_1
FSMC_NCE4_2
High
t
v(NCE4_1-A)
t
h(NCE4_1-AI)
FSMC_A[10:0]
FSMC_NIOWR
FSMC_NIORD
t
d(NREG-NCE4_1)
t
h(NCE4_1-NREG)
FSMC_NREG
t
d(NCE4_1-NWE)
t
w(NWE)
FSMC_NWE
t
d(NWE-NCE4_1)
FSMC_NOE
t
v(NWE-D)
FSMC_D[7:0](1)
ai14898b
1. Only data bits 0...7 are driven (bits 8...15 remains HiZ).
Figure 36. PC Card/CompactFlash controller waveforms for I/O space read access
FSMC_NCE4_1
FSMC_NCE4_2
t
v(NCEx-A)
FSMC_A[10:0]
FSMC_NREG
FSMC_NWE
FSMC_NOE
FSMC_NIOWR
t
d(NIORD-NCE4_1)
FSMC_NIORD
FSMC_D[15:0]
78/130 Doc ID 14611 Rev 8
t
su(D-NIORD)
t
h(NCE4_1-AI)
t
w(NIORD)
t
d(NIORD-D)
ai14899B
STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics
t
d(NCE4_1-NIOWR)
t
w(NIOWR)
t
v(NCEx-A)
t
h(NCE4_1-AI)
t
h(NIOWR-D)
ATTxHIZ =1
t
v(NIOWR-D)
ai14900b
FSMC_NWE
FSMC_NOE
FSMC_D[15:0]
FSMC_A[10:0]
FSMC_NIOWR
FSMC_NREG
FSMC_NIOWR
FSMC_NIORD
Figure 37. PC Card/CompactFlash controller waveforms for I/O space write access
Table 39. Switching characteristics for PC Card/CF read and write cycles
(1)(2)
Symbol Parameter Min Max Unit
t
v(NCEx-A)
t
v(NCE4_1-A)
t
h(NCEx-AI)
t
h(NCE4_1-AI)
t
d(NREG-NCEx)
t
d(NREG-NCE4_1)
t
h(NCEx-NREG)
t
h(NCE4_1-NREG)
t
d(NCE4_1-NOE)
t
w(NOE)
t
d(NOE-NCE4_1
t
su(D-NOE)
t
h(NOE-D)
t
w(NWE)
t
d(NWE-NCE4_1)
t
d(NCE4_1-NWE)
t
v(NWE-D)
t
h(NWE-D)
t
d(D-NWE)
FSMC_NCEx low (x = 4_1/4_2) to FSMC_Ay valid (y =
0...10) FSMC_NCE4_1 low (x = 4_1/4_2) to FSMC_Ay valid
0 ns
(y = 0...10)
FSMC_NCEx high (x = 4_1/4_2) to FSMC_Ax invalid (x =
0...10) FSMC_NCE4_1 high (x = 4_1/4_2) to FSMC_Ax
2.5 ns
invalid (x = 0...10)
FSMC_NCEx low to FSMC_NREG valid FSMC_NCE4_1
low to FSMC_NREG valid
FSMC_NCEx high to FSMC_NREG invalid FSMC_NCE4_1
high to FSMC_NREG invalid
t
HCLK
FSMC_NCE4_1 low to FSMC_NOE low 5t
FSMC_NOE low width 8t
FSMC_NOE high to FSMC_NCE4_1 high 5t
HCLK
HCLK
+ 3 ns
+ 2 ns
5 ns
HCLK
–1.5 8t
HCLK
FSMC_D[15:0] valid data before FSMC_NOE high 25 ns
FSMC_D[15:0] valid data after FSMC_NOE high 15 ns
FSMC_NWE low width 8t
FSMC_NWE high to FSMC_NCE4_1 high 5t
FSMC_NCE4_1 low to FSMC_NWE low 5t
– 1 8t
HCLK
+ 2 ns
HCLK
HCLK
HCLK
FSMC_NWE low to FSMC_D[15:0] valid 0 ns
FSMC_NWE high to FSMC_D[15:0] invalid 11t
FSMC_D[15:0] valid before FSMC_NWE high 13t
Doc ID 14611 Rev 8 79/130
HCLK
HCLK
+ 2 ns
+ 1 ns
+ 2 ns
+ 1.5 ns
ns
ns
Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE
Table 39. Switching characteristics for PC Card/CF read and write cycles
(1)(2)
(continued)
Symbol Parameter Min Max Unit
t
w(NIOWR)
t
v(NIOWR-D)
t
h(NIOWR-D)
t
d(NCE4_1-NIOWR)
t
h(NCEx-NIOWR)
t
h(NCE4_1-NIOWR)
t
d(NIORD-NCEx)
t
d(NIORD-NCE4_1)
t
h(NCEx-NIORD)
t
h(NCE4_1-NIORD)
t
su(D-NIORD)
t
d(NIORD-D)
t
w(NIORD)
1. CL = 15 pF.
2. Based on characterization, not tested in production.
FSMC_NIOWR low width 8t
FSMC_NIOWR low to FSMC_D[15:0] valid 5t
FSMC_NIOWR high to FSMC_D[15:0] invalid 11t
FSMC_NCE4_1 low to FSMC_NIOWR valid 5t
FSMC_NCEx high to FSMC_NIOWR invalid
FSMC_NCE4_1 high to FSMC_NIOWR invalid
FSMC_NCEx low to FSMC_NIORD valid FSMC_NCE4_1
low to FSMC_NIORD valid
FSMC_NCEx high to FSMC_NIORD invalid
FSMC_NCE4_1 high to FSMC_NIORD invalid
+ 3 ns
HCLK
HCLK
HCLK
HCLK
– 5 ns
5t
HCLK
5t
HCLK
5t
– 5 ns
HCLK
+1 ns
+3ns ns
+ 2.5 ns
FSMC_D[15:0] valid before FSMC_NIORD high 4.5 ns
FSMC_D[15:0] valid after FSMC_NIORD high 9 ns
FSMC_NIORD low width 8t
+ 2 ns
HCLK
NAND controller waveforms and timings
ns
Figure 38 through Figure 41 represent synchronous waveforms and Ta bl e 4 0 provides the
corresponding timings. The results shown in this table are obtained with the following FSMC
configuration:
● COM.FSMC_SetupTime = 0x01;
● COM.FSMC_WaitSetupTime = 0x03;
● COM.FSMC_HoldSetupTime = 0x02;
● COM.FSMC_HiZSetupTime = 0x01;
● ATT.FSMC_SetupTime = 0x01;
● ATT.FSMC_WaitSetupTime = 0x03;
● ATT.FSMC_HoldSetupTime = 0x02;
● ATT.FSMC_HiZSetupTime = 0x01;
● Bank = FSMC_Bank_NAND;
● MemoryDataWidth = FSMC_MemoryDataWidth_16b;
● ECC = FSMC_ECC_Enable;
● ECCPageSize = FSMC_ECCPageSize_512Bytes;
● TCLRSetupTime = 0;
● TARSetupTime = 0;
80/130 Doc ID 14611 Rev 8
STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics
FSMC_NWE
FSMC_NOE (NRE)
FSMC_D[15:0]
t
su(D-NOE)
t
h(NOE-D)
ai14901b
ALE (FSMC_A17)
CLE (FSMC_A16)
FSMC_NCEx
Low
t
d(ALE-NOE)th(NOE-ALE)
t
h(NWE-D)
t
v(NWE-D)
ai14902b
FSMC_NWE
FSMC_NOE (NRE)
FSMC_D[15:0]
ALE (FSMC_A17)
CLE (FSMC_A16)
FSMC_NCEx
Low
t
d(ALE-NWE)th(NWE-ALE)
Figure 38. NAND controller waveforms for read access
Figure 39. NAND controller waveforms for write access
Figure 40. NAND controller waveforms for common memory read access
FSMC_NCEx
ALE (FSMC_A17)
CLE (FSMC_A16)
FSMC_NWE
FSMC_N
FSMC_D[15:0]
Low
OE
t
d(ALE-NOE)
t
w(NOE)
t
su(D-NOE)
t
h(NOE-ALE)
t
h(NOE-D)
Doc ID 14611 Rev 8 81/130
ai14912b
Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE
t
w(NWE)
t
h(NWE-D)
t
v(NWE-D)
ai14913b
FSMC_NWE
FSMC_N
OE
FSMC_D[15:0]
t
d(D-NWE)
ALE (FSMC_A17)
CLE (FSMC_A16)
FSMC_NCEx
Low
t
d(ALE-NWE)
t
h(NWE-ALE)
Figure 41. NAND controller waveforms for common memory write access
Table 40. Switching characteristics for NAND Flash read and write cycles
(1)
Symbol Parameter Min Max Unit
(2)
t
d(D-NWE)
t
w(NOE)
t
su(D-NOE)
t
h(NOE-D)
t
w(NWE)
t
v(NWE-D)
t
h(NWE-D)
t
d(ALE-NWE)
t
h(NWE-ALE)
t
d(ALE-NOE)
t
h(NOE-ALE)
= 15 pF.
1. C
L
(2)
FSMC_D[15:0] valid before FSMC_NWE high 5t
FSMC_NOE low width 4t
FSMC_D[15:0] valid data before FSMC_NOE
(2)
high
(2)
FSMC_D[15:0] valid data after FSMC_NOE high 7 ns
(2)
FSMC_NWE low width 4t
(2)
FSMC_NWE low to FSMC_D[15:0] valid 0 ns
(2)
FSMC_NWE high to FSMC_D[15:0] invalid 2t
(3)
FSMC_ALE valid before FSMC_NWE low 3t
(3)
FSMC_NWE high to FSMC_ALE invalid 3t
(3)
FSMC_ALE valid before FSMC_NOE low 3t
(3)
FSMC_NWE high to FSMC_ALE invalid 3t
2. Based on characterization, not tested in production.
3. Guaranteed by design, not tested in production.
+ 12 ns
HCLK
HCLK
– 1.5 4t
HCLK
+ 1.5 ns
25 ns
– 1 4t
HCLK
+ 4ns ns
HCLK
+ 4.5 ns
HCLK
+ 4.5 ns
HCLK
HCLK
HCLK
HCLK
+ 2.5 ns
+ 1.5 ns
+ 2 ns
82/130 Doc ID 14611 Rev 8
STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics
5.3.11 EMC characteristics
Susceptibility tests are performed on a sample basis during device characterization.
Functional EMS (electromagnetic susceptibility)
While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the
device is stressed by two electromagnetic events until a failure occurs. The failure is
indicated by the LEDs:
● Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until
a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.
● FTB: A Burst of Fast Transient voltage (positive and negative) is applied to V
V
through a 100 pF capacitor, until a functional disturbance occurs. This test is
SS
compliant with the IEC 61000-4-4 standard.
A device reset allows normal operations to be resumed.
The test results are given in Tab l e 4 1 . They are based on the EMS levels and classes
defined in application note AN1709.
Table 41. EMS characteristics
DD
and
Symbol Parameter Conditions
= 3.3 V, LQFP144, TA = +25 °C,
V
V
V
FESD
EFTB
Voltage limits to be applied on any I/O pin to
induce a functional disturbance
Fast transient voltage burst limits to be
applied through 100 pF on VDD and V
SS
pins to induce a functional disturbance
DD
f
= 72 MHz
HCLK
conforms to IEC 61000-4-2
V
= 3.3 V, LQFP144, TA = +25 °C,
DD
f
= 72 MHz
HCLK
conforms to IEC 61000-4-4
Level/
Class
2B
4A
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
Software recommendations
The software flowchart must include the management of runaway conditions such as:
● Corrupted program counter
● Unexpected reset
● Critical Data corruption (control registers...)
Doc ID 14611 Rev 8 83/130
Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1
second.
To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring (see application note AN1015).
Electromagnetic Interference (EMI)
The electromagnetic field emitted by the device are monitored while a simple application is
executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with
IEC 61967-2 standard which specifies the test board and the pin loading.
Table 42. EMI characteristics
Symbol Parameter Conditions
Monitored
frequency band
0.1 to 30 MHz 8 12
= 3.3 V, TA = 25 °C,
V
DD
S
EMI
Peak level
LQFP144 package
compliant with IEC
61967-2
130 MHz to 1GHz 28 33
SAE EMI Level 4 4 -
5.3.12 Absolute maximum ratings (electrical sensitivity)
Based on three different tests (ESD, LU) using specific measurement methods, the device is
stressed in order to determine its performance in terms of electrical sensitivity.
Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test
conforms to the JESD22-A114/C101 standard.
Table 43. ESD absolute maximum ratings
Symbol Ratings Conditions Class Maximum value
Max vs. [f
HSE/fHCLK
8/48 MHz 8/72 MHz
]
Unit
dBµV30 to 130 MHz 31 21
(1)
Unit
V
ESD(HBM)
V
ESD(CDM)
1. Based on characterization results, not tested in production.
Electrostatic discharge
voltage (human body model)
Electrostatic discharge
voltage (charge device model)
84/130 Doc ID 14611 Rev 8
TA = +25 °C, conforming
to JESD22-A114
TA = +25 °C, conforming
to JESD22-C101
22000
V
II 500
STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics
Static latch-up
Two complementary static tests are required on six parts to assess the latch-up
performance:
● A supply overvoltage is applied to each power supply pin
● A current injection is applied to each input, output and configurable I/O pin
These tests are compliant with EIA/JESD 78A IC latch-up standard.
Table 44. Electrical sensitivities
Symbol Parameter Conditions Class
LU Static latch-up class T
= +105 °C conforming to JESD78A II level A
A
5.3.13 I/O current injection characteristics
As a general rule, current injection to the I/O pins, due to external voltage below VSS or
above V
operation. However, in order to give an indication of the robustness of the microcontroller in
cases when abnormal injection accidentally happens, susceptibility tests are performed on a
sample basis during device characterization.
Functional susceptibilty to I/O current injection
While a simple application is executed on the device, the device is stressed by injecting
current into the I/O pins programmed in floating input mode. While current is injected into the
I/O pin, one at a time, the device is checked for functional failures.
The failure is indicated by an out of range parameter: ADC error above a certain limit (>5
LSB TUE), out of spec current injection on adjacent pins or other functional failure (for
example reset, oscillator frequency deviation).
The test results are given in Tab l e 4 5
Table 45. I/O current injection susceptibility
Symbol Description
(for standard, 3 V-capable I/O pins) should be avoided during normal product
DD
Functional susceptibility
Negative
injection
Positive
injection
Unit
I
INJ
Injected current on OSC_IN32,
OSC_OUT32, PA4, PA5, PC13
Injected current on all FT pins -5 +0
-0 +0
mA
Injected current on any other pin -5 +5
Doc ID 14611 Rev 8 85/130
Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE
5.3.14 I/O port characteristics
General input/output characteristics
Unless otherwise specified, the parameters given in Ta bl e 4 6 are derived from tests
performed under the conditions summarized in Tab l e 1 0 . All I/Os are CMOS and TTL
compliant.
Table 46. I/O static characteristics
Symbol Parameter Conditions Min Typ
Max Unit
Standard IO input low
level voltage
V
IL
IO FT
(1)
voltage
Standard IO input high
level voltage
V
IH
IO FT
(1)
voltage
input low level
input high level
–0.3 0.28*(V
–0.3 0.32*(V
0.41*(V
> 2 V
V
DD
V
≤ 2 V 5.2
DD
0.42*(V
-2 V)+1.3 V VDD+0.3 V
DD
-2 V)+1 V
DD
-2 V)+0.8 V V
DD
-2 V)+0.75 V V
DD
5.5
Standard IO Schmitt
trigger voltage
hys
hysteresis
V
IO FT Schmitt trigger
voltage hysteresis
I
Input leakage current
lkg
R
R
C
1. FT = Five-volt tolerant. In order to sustain a voltage higher than VDD+0.3 the internal pull-up/pull-down resistors must be
Weak pull-up equivalent
PU
resistor
Weak pull-down
PD
equivalent resistor
I/O pin capacitance 5 pF
IO
disabled.
(5)
(2)
(2)
(5)
V
(4)
V
≤ VIN≤ V
SS
DD
Standard I/Os
= 5 V, I/O FT 3
IN
V
= V
IN
SS
V
= V
IN
DD
2. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization, not tested in production.
3. With a minimum of 100 mV.
4. Leakage could be higher than max. if negative current is injected on adjacent pins.
5. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This
MOS/NMOS contribution
to the series resistance is minimum (~10% order).
200 mV
DD
(3)
5% V
±1
30 40 50 kΩ
30 40 50 kΩ
V
mV
µA
All I/Os are CMOS and TTL compliant (no software configuration required). Their
characteristics cover more than the strict CMOS-technology or TTL parameters. The
coverage of these requirements is shown in Figure 42 and Figure 43 for standard I/Os, and
86/130 Doc ID 14611 Rev 8
in Figure 44 and Figure 45 for 5 V tolerant I/Os.
STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics
AIB
6$$6
)NPUTRANGE
NOTGUARANTEED
6
)(
6
$$
#-/3STANDARDREQUIREMENT6
)(
6
$$
6)(6),6
#-/3STANDARDREQUIREMENT6
),
6
$$
7
),MAX
7
)(MIN
6
$$
6
),
AI
)NPUTRANGE
NOTGUARANTEED
6)(6),6
44,REQUIREMENTS 6)(6
6
)(
6
$$
6
),
6
$$
44,REQUIREMENTS 6),6
6$$6
7
),MAX
7
)(MIN
Figure 42. Standard I/O input characteristics - CMOS port
Figure 43. Standard I/O input characteristics - TTL port
Doc ID 14611 Rev 8 87/130
Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE
6$$
#-/3STANDARDREQUIREMENTS6
)(
6
$$
#-/3STANDARDREQUIRMENT6
),
6
$$
6)(6),6
6$$6
)NPUTRANGE
NOTGUARANTEED
AIB
6
)(
6
$$
6
),
6
$$
NOTGUARANTEED
)NPUTRANGE
44,REQUIREMENT6)(6
6
)(
6
$$
6
),
6
$$
44,REQUIREMENTS6),6
6)(6),6
6$$6
7
),MAX
7
)(MIN
AI
Figure 44. 5 V tolerant I/O input characteristics - CMOS port
Figure 45. 5 V tolerant I/O input characteristics - TTL port
Output driving current
The GPIOs (general purpose input/outputs) can sink or source up to +/-8 mA, and sink or
source up to +/- 20 mA (with a relaxed V
In the user application, the number of I/O pins which can drive current must be limited to
respect the absolute maximum rating specified in Section 5.2:
● The sum of the currents sourced by all the I/Os on V
consumption of the MCU sourced on V
I
(see Ta bl e 8 ).
VDD
● The sum of the currents sunk by all the I/Os on V
consumption of the MCU sunk on V
I
(see Ta bl e 8 ).
VSS
88/130 Doc ID 14611 Rev 8
OL/VOH
SS
).
plus the maximum Run
cannot exceed the absolute maximum rating
DD,
DD,
plus the maximum Run
SS
cannot exceed the absolute maximum rating
STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics
Output voltage levels
Unless otherwise specified, the parameters given in Ta bl e 4 7 are derived from tests
performed under ambient temperature and V
Ta bl e 1 0 . All I/Os are CMOS and TTL compliant.
Table 47. Output voltage characteristics
Symbol Parameter Conditions Min Max Unit
Output low level voltage for an I/O pin
(1)
V
OL
V
OH
V
OL
V
OH
V
OL
V
OH
V
OL
V
OH
1. The IIO current sunk by the device must always respect the absolute maximum rating specified in Table 8
and the sum of I
2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.
3. The IIO current sourced by the device must always respect the absolute maximum rating specified in
Table 8 and the sum of I
4. Based on characterization data, not tested in production.
when 8 pins are sunk at same time
Output high level voltage for an I/O pin
(3)
when 8 pins are sourced at same time
Output low level voltage for an I/O pin
(1)
when 8 pins are sunk at same time
Output high level voltage for an I/O pin
(3)
when 8 pins are sourced at same time
Output low level voltage for an I/O pin
(1)(4)
when 8 pins are sunk at same time
Output high level voltage for an I/O pin
(3)(4)
when 8 pins are sourced at same time
Output low level voltage for an I/O pin
(1)(4)
when 8 pins are sunk at same time
Output high level voltage for an I/O pin
(3)(4)
when 8 pins are sourced at same time
(I/O ports and control pins) must not exceed I
IO
(I/O ports and control pins) must not exceed I
IO
supply voltage conditions summarized in
DD
CMOS port
I
IO
(2)
= +8 mA
2.7 V < VDD < 3.6 V
TTL port
I
IO
2.7 V < V
I
IO
2.7 V < V
I
IO
(2)
=+ 8mA
< 3.6 V
DD
= +20 mA
< 3.6 V
DD
= +6 mA
2 V < VDD < 2.7 V
.
VSS
VDD
–0.4
V
DD
2.4
–1.3
V
DD
–0.4
V
DD
.
0.4
0.4
1.3
0.4
V
V
V
V
Doc ID 14611 Rev 8 89/130
Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE
Input/output AC characteristics
The definition and values of input/output AC characteristics are given in Figure 46 and
Ta bl e 4 8 , respectively.
Unless otherwise specified, the parameters given in Ta bl e 4 8 are derived from tests
performed under ambient temperature and V
Ta bl e 1 0 .
Table 48. I/O AC characteristics
(1)
supply voltage conditions summarized in
DD
MODEx[1:0]
bit value
10
01
11
Symbol Parameter Conditions Min Max Unit
(1)
f
max(IO)out
t
f(IO)out
t
r(IO)out
f
max(IO)out
t
f(IO)out
t
r(IO)out
F
max(IO)out
t
f(IO)out
t
r(IO)out
Maximum frequency
Output high to low
level fall time
Output low to high
level rise time
Maximum frequency
Output high to low
level fall time
Output low to high
level rise time
Maximum frequency
Output high to low
level fall time
Output low to high
level rise time
(2)
CL = 50 pF, V
= 50 pF, V
C
L
(2)
CL = 50 pF, V
= 50 pF, V
C
L
CL = 30 pF, V
(2)
= 50 pF, VDD = 2.7 V to 3.6 V 30 MHz
C
L
= 50 pF, V
C
L
= 30 pF, V
C
L
= 50 pF, V
C
L
CL = 50 pF, V
= 30 pF, V
C
L
CL = 50 pF, V
CL = 50 pF, V
= 2 V to 3.6 V 2 MHz
DD
= 2 V to 3.6 V
DD
= 2 V to 3.6 V 10 MHz
DD
= 2 V to 3.6 V
DD
= 2.7 V to 3.6 V 50 MHz
DD
= 2 V to 2.7 V 20 MHz
DD
= 2.7 V to 3.6 V 5
DD
= 2.7 V to 3.6 V 8
DD
= 2 V to 2.7 V 12
DD
= 2.7 V to 3.6 V 5
DD
= 2.7 V to 3.6 V 8
DD
= 2 V to 2.7 V 12
DD
125
125
25
25
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(3)
Pulse width of
-t
EXTIpw
external signals
detected by the EXTI
10 ns
controller
1. The I/O speed is configured using the MODEx[1:0] bits. Refer to the STM32F10xxx reference manual for a
description of GPIO Port configuration register.
2. The maximum frequency is defined in Figure 46.
3. Guaranteed by design, not tested in production.
ns
ns
ns
90/130 Doc ID 14611 Rev 8
STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics
ai14131
10%
90%
50%
t
r(IO)out
OUTPUT
EXTERNAL
ON 50pF
Maximum fr equency is achieved if (tr + tf) ≤ 2/3) T and if the duty cycle is (45-55%)
10 %
50%
90%
when loaded by 50pF
T
t
r(IO)out
ai14132d
STM32F10xxx
R
PU
NRST
(2)
V
DD
Filter
Internal Reset
0.1 µF
External
reset circuit
(1)
Figure 46. I/O AC characteristics definition
5.3.15 NRST pin characteristics
The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up
resistor, R
Unless otherwise specified, the parameters given in Ta bl e 4 9 are derived from tests
performed under ambient temperature and V
Ta bl e 1 0 .
Table 49. NRST pin characteristics
(see Ta bl e 4 6 ).
PU
supply voltage conditions summarized in
DD
Symbol Parameter Conditions Min Typ Max Unit
(1)
V
IL(NRST)
V
IH(NRST)
V
hys(NRST)
R
V
F(NRST)
V
NF(NRST)
PU
NRST Input low level voltage –0.5 0.8
(1)
NRST Input high level voltage 2 VDD+0.5
NRST Schmitt trigger voltage
hysteresis
Weak pull-up equivalent resistor
(1)
NRST Input filtered pulse 100 ns
(1)
NRST Input not filtered pulse 300 ns
(2)
V
= V
IN
SS
200 mV
30 40 50 kΩ
1. Guaranteed by design, not tested in production.
2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution
to the series resistance must be minimum (~10% order).
Figure 47. Recommended NRST pin protection
V
1. The reset network protects the device against parasitic resets.
2. The user must ensure that the level on the NRST pin can go below the V
Table 49. Otherwise the reset will not be taken into account by the device.
Doc ID 14611 Rev 8 91/130
max level specified in
IL(NRST)
Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE
5.3.16 TIM timer characteristics
The parameters given in Tab l e 5 0 are guaranteed by design.
Refer to Section 5.3.14: I/O port characteristics for details on the input/output alternate
function characteristics (output compare, input capture, external clock, PWM output).
Table 50. TIMx
Symbol Parameter Conditions Min Max Unit
(1)
characteristics
t
res(TIM)
f
EXT
Res
TIM
t
COUNTER
t
MAX_COUNT
Timer resolution time
Timer external clock
frequency on CH1 to CH4
f
0
f
TIMxCLK
= 72 MHz 13.9 ns
TIMxCLK
= 72 MHz 0 36 MHz
Timer resolution 16 bit
16-bit counter clock period
when internal clock is
selected
f
= 72 MHz 0.0139 910 µs
TIMxCLK
Maximum possible count
f
= 72 MHz 59.6 s
TIMxCLK
1
1 65536
65536 × 65536
1. TIMx is used as a general term to refer to the TIM1, TIM2, TIM3 and TIM4 timers.
f
TIMxCLK
t
TIMxCLK
/2
MHz
t
TIMxCLK
t
TIMxCLK
92/130 Doc ID 14611 Rev 8
STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics
5.3.17 Communications interfaces
I2C interface characteristics
Unless otherwise specified, the parameters given in Ta bl e 5 1 are derived from tests
performed under ambient temperature, f
summarized in Ta bl e 1 0 .
frequency and VDD supply voltage conditions
PCLK1
The STM32F103xC, STM32F103xD and STM32F103xESTM32F103xF and STM32F103xG
performance line
2
I
C interface meets the requirements of the standard I2C communication
protocol with the following restrictions: the I/O pins SDA and SCL are mapped to are not
“true” open-drain. When configured as open-drain, the PMOS connected between the I/O
pin and V
2
The I
characteristics
and SCL)
Table 51. I2C characteristics
Symbol Parameter
t
w(SCLL)
t
w(SCLH)
t
su(SDA)
t
h(SDA)
t
r(SDA)
t
r(SCL)
t
f(SDA)
t
f(SCL)
t
h(STA)
t
su(STA)
is disabled, but is still present.
DD
C characteristics are described in Ta b le 5 1 . Refer also to Section 5.3.14: I/O port
for more details on the input/output alternate function characteristics (SDA
.
Standard mode I
2C(1)
Fast mode I2C
Min Max Min Max
SCL clock low time 4.7 1.3
SCL clock high time 4.0 0.6
SDA setup time 250 100
SDA data hold time 0
(3)
(4)
0
SDA and SCL rise time 1000 20 + 0.1C
SDA and SCL fall time 300 300
Start condition hold time 4.0 0.6
Repeated Start condition
setup time
4.7 0.6
(1)(2)
Unit
(3)
900
300
b
µs
ns
µs
t
su(STO)
t
w(STO:STA)
C
Guaranteed by design, not tested in production.
1.
2. f
PCLK1
to achieve the fast mode I
mode maximum clock speed of 400 kHz.
The maximum hold time of the Start condition has only to be met if the interface does not stretch the low
3.
period of SCL signal.
The device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the
4.
undefined region of the falling edge of SCL.
Stop condition setup time 4.0 0.6 μs
Stop to Start condition time
(bus free)
Capacitive load for each bus
b
line
must be higher than 2 MHz to achieve standard mode I2C frequencies. It must be higher than 4 MHz
2
C frequencies and it must be a multiple of 10 MHz in order to reach the I2C fast
4.7 1.3 μs
400 400 pF
Doc ID 14611 Rev 8 93/130
Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE
ai14149c
START
SD A
100
4.7k
I
2
C bus
4.7k
100
V
DD
V
DD
STM32F103xx
SDA
SCL
t
f(SDA)
t
r(SDA)
SCL
t
h(STA)
t
w(SCLH)
t
w(SCLL)
t
su(SDA)
t
r(SCL)
t
f(SCL)
t
h(SDA)
S TART REPEATED
START
t
su(STA)
t
su(STO)
S TOP
t
w(STO:STA)
Figure 48. I2C bus AC waveforms and measurement circuit
Measurement points are done at CMOS levels: 0.3V
1.
Table 52. SCL frequency (f
= 36 MHz.,VDD = 3.3 V)
PCLK1
and 0.7VDD.
DD
(1)(2)
I2C_CCR value
f
(kHz)
SCL
R
= 4.7 kΩ
P
400 0x801E
300 0x8028
200 0x803C
100 0x00B4
50 0x0168
20 0x0384
= External pull-up resistance, f
1. R
P
2. For speeds around 200 kHz, the tolerance on the achieved speed is of ±5%. For other speed ranges, the
tolerance on the achieved speed ±2%. These variations depend on the accuracy of the external
components used to design the application.
= I2C speed.
SCL
94/130 Doc ID 14611 Rev 8
STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics
I2S - SPI characteristics
Unless otherwise specified, the parameters given in Ta bl e 5 3 for SPI or in Ta bl e 5 4 for I2S
are derived from tests performed under ambient temperature, f
supply voltage conditions summarized in Ta b le 1 0.
frequency and VDD
PCLKx
Refer to Section 5.3.14: I/O port characteristics for more details on the input/output alternate
function characteristics (NSS, SCK, MOSI, MISO for SPI and WS, CK, SD for I
Table 53. SPI characteristics
Symbol Parameter Conditions Min Max Unit
f
SCK
1/t
c(SCK)
t
r(SCK)
t
f(SCK)
DuCy(SCK)
t
su(NSS)
t
h(NSS)
t
w(SCKH)
t
w(SCKL)
t
su(MI)
t
su(SI)
t
h(MI)
t
h(SI)
(1)(2)
t
a(SO)
t
dis(SO)
t
v(SO)
t
v(MO)
t
h(SO)
t
h(MO)
SPI clock frequency
SPI clock rise and fall
time
SPI slave input clock duty
cycle
(1)
NSS setup time Slave mode 4t
(1)
NSS hold time Slave mode 2t
(1)
SCK high and low time
(1)
(1)
Data input setup time
(1)
(1)
Data input hold time
(1)
Data output access time Slave mode, f
(1)(3)
Data output disable time Slave mode 2 10
(1)
Data output valid time Slave mode (after enable edge) 25
(1)
Data output valid time Master mode (after enable edge) 5
(1)
Data output hold time
(1)
1. Based on characterization, not tested in production.
2. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate
the data.
3. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put
the data in Hi-Z
Master mode 18
Slave mode 18
Capacitive load: C = 30 pF 8 ns
Slave mode 30 70 %
PCLK
PCLK
Master mode, f
presc = 4
PCLK
= 36 MHz,
50 60
Master mode 5
Slave mode 5
Master mode 5
Slave mode 4
= 20 MHz 0 3t
PCLK
Slave mode (after enable edge) 15
Master mode (after enable edge) 2
2
S).
PCLK
MHz
ns
Doc ID 14611 Rev 8 95/130
Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE
ai14134c
SCK Input
CPHA=0
MOSI
INPUT
MISO
OUT PUT
CPHA=0
MS B O U T
MSB IN
BI T6 OU T
LSB IN
LSB OUT
CPOL=0
CPOL=1
BIT1 IN
NSS input
t
SU(NSS)
t
c(SCK)
t
h(NSS)
t
a(SO)
t
w(SCKH)
t
w(SCKL)
t
v(SO)
t
h(SO)
t
r(SCK)
t
f(SCK)
t
dis(SO)
t
su(SI)
t
h(SI)
ai14135
SCK Input
CPHA=1
MOSI
INPUT
MISO
OUT PUT
CPHA=1
MS B O U T
MSB IN
BI T6 OU T
LSB IN
LSB OUT
CPOL=0
CPOL=1
BIT1 IN
t
SU(NSS)
t
c(SCK)
t
h(NSS)
t
a(SO)
t
w(SCKH)
t
w(SCKL)
t
v(SO)
t
h(SO)
t
r(SCK)
t
f(SCK)
t
dis(SO)
t
su(SI)
t
h(SI)
NSS input
Figure 49. SPI timing diagram - slave mode and CPHA = 0
Figure 50. SPI timing diagram - slave mode and CPHA = 1
1. Measurement points are done at CMOS levels: 0.3V
and 0.7V
DD
DD
.
(1)
96/130 Doc ID 14611 Rev 8
STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics
ai14136
SCK Input
CPHA=0
MOSI
OUTUT
MISO
INP UT
CPHA=0
MSBIN
M SB OUT
BIT6 IN
LSB OUT
LSB IN
CPOL=0
CPOL=1
B I T1 OUT
NSS input
t
c(SCK)
t
w(SCKH)
t
w(SCKL)
t
r(SCK)
t
f(SCK)
t
h(MI)
High
SCK Input
CPHA=1
CPHA=1
CPOL=0
CPOL=1
t
su(MI)
t
v(MO)
t
h(MO)
Figure 51. SPI timing diagram - master mode
(1)
1. Measurement points are done at CMOS levels: 0.3V
and 0.7V
DD
DD
.
Doc ID 14611 Rev 8 97/130
Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE
Table 54. I2S characteristics
Symbol Parameter Conditions Min Max Unit
DuCy(SCK)
f
CK
1/t
c(CK)
t
r(CK)
t
f(CK)
(1)
t
v(WS)
(1)
t
h(WS)
(1)
t
su(WS)
(1)
t
h(WS)
(1)
t
w(CKH)
(1)
t
w(CKL)
t
su(SD_MR)
t
su(SD_SR)
t
h(SD_MR)
t
h(SD_SR)
t
v(SD_ST)
t
h(SD_ST)
I2S slave input clock duty
cycle
I2S clock frequency
Slave mode 30 70 %
Master mode (data: 16 bits,
Audio frequency = 48 kHz)
1.522 1.525
Slave mode 0 6.5
I2S clock rise and fall time Capacitive load CL=50pF 8 ns
WS valid time Master mode 3
I2S2 2
WS hold time Master mode
I2S3 0
WS setup time Slave mode 4
WS hold time Slave mode 0
CK high and low time
(1)
Data input setup time Master receiver
Master f
frequency = 48 kHz
= 16 MHz, audio
PCLK
I2S2 2
312.5
345
I2S3 6.5
(1)
Data input setup time Slave receiver 1.5
(1)(2)
Data input hold time
(1)(2)
(1)(2)
Data output valid time
(1)
Data output hold time
Master receiver 0
Slave receiver 0.5
Slave transmitter (after enable
edge)
Slave transmitter (after enable
edge)
11
18
MHz
t
v(SD_MT)
t
h(SD_MT)
(1)(2)
Data output valid time
(1)
Data output hold time
Master transmitter (after enable
edge)
Master transmitter (after enable
edge)
1. Based on design simulation and/or characterization results, not tested in production.
2. Depends on f
. For example, if f
PCLK
=8 MHz, then T
PCLK
PCLK
= 1/f
PLCLK
98/130 Doc ID 14611 Rev 8
3
0
=125 ns.
STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics
CK Input
CPOL = 0
CPOL = 1
t
c(CK)
WS input
SD
transmit
SD
receive
t
w(CKH)
t
w(CKL)
t
su(WS)
t
v(SD_ST)
t
h(SD_ST)
t
h(WS)
t
su(SD_SR)
t
h(SD_SR)
MSB receive Bitn receive LSB receive
MSB transmit Bitn transmit LSB transmit
ai14881b
LSB receive
(2)
LSB transmit
(2)
CK output
CPOL = 0
CPOL = 1
t
c(CK)
WS output
SD
receive
SD
transmit
t
w(CKH)
t
w(CKL)
t
su(SD_MR)
t
v(SD_MT)
t
h(SD_MT)
t
h(WS)
t
h(SD_MR)
MSB receive Bitn receive LSB receive
MSB transmit Bitn transmit LSB transmit
ai14884b
t
f(CK)
t
r(CK)
t
v(WS)
LSB receive
(2)
LSB transmit
(2)
(1)
Figure 52. I2S slave timing diagram (Philips protocol)
1. Measurement points are done at CMOS levels: 0.3 × VDD and 0.7 × VDD.
2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.
Figure 53. I2S master timing diagram (Philips protocol)
1. Based on characterization, not tested in production.
2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.
Doc ID 14611 Rev 8 99/130
(1)
Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE
t
W(CKH)
CK
D, CMD
(output)
D, CMD
(input)
t
C
t
W(CKL)
t
OV
t
OH
t
ISU
t
IH
t
f
t
r
ai14887
CK
D, CMD
(output)
t
OVD
t
OHD
ai14888
SD/SDIO MMC card host interface (SDIO) characteristics
Unless otherwise specified, the parameters given in Ta bl e 5 5 are derived from tests
performed under ambient temperature, f
summarized in Ta bl e 1 0 .
Refer to Section 5.3.14: I/O port characteristics for more details on the input/output alternate
function characteristics (D[7:0], CMD, CK).
Figure 54. SDIO high-speed mode
frequency and VDD supply voltage conditions
PCLKx
Figure 55. SD default mode
100/130 Doc ID 14611 Rev 8
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