ST STM32F101 series, STM32F107 series, STM32F102 series, STM32F103 series, STM32F105 series Reference Manual

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RM0008

Reference manual

STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and

STM32F107xx advanced ARM

Introduction

This reference manual targets application developers. It provides complete information on how to use the STM32F101xx, STM32F102xx, STM32F103xx and STM32F105xx/STM32F107xx microcontroller memory and peripherals. The STM32F101xx, STM32F102xx, STM32F103xx and STM32F105xx/STM32F107xx will be referred to as STM32F10xxx throughout the document, unless otherwise specified.

The STM32F10xxx is a family of microcontrollers with different memory sizes, packages and peripherals.

For ordering information, mechanical and electrical device characteristics please refer to the low-, medium-, high- and XL-density STM32F101xx and STM32F103xx datasheets, to the low- and medium-density STM32F102xx datasheets and to the STM32F105xx/STM32F107xx connectivity line datasheet.

For information on programming, erasing and protection of the internal Flash memory please refer to:

• PM0075, the Flash programming manual for low-, medium- high-density and

connectivity line STM32F10xxx devices

• PM0068, the Flash programming manual for XL-density STM32F10xxx devices.

For information on the ARM M3 programming manual (PM0056).

Cortex®-M3 core, please refer to the STM32F10xxx Cortex®-

-based 32-bit MCUs

Related documents

Available from www.st.com:

• STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx/STM32F107xx and datasheets

• STM32F10xxx Cortex

• STM32F10xxx Flash programming manual (PM0075)

• STM32F10xxx XL-density Flash programming manual (PM0068)

June 2014 DocID13902 Rev 15 1/1128

-M3 programming manual (PM0056)

www.st.com

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RM0008 Contents

Contents

1 Overview of the manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

2 Documentation conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

2.1 List of abbreviations for registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

2.2 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

2.3 Peripheral availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

3 Memory and bus architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

3.1 System architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

3.2 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

3.3 Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

3.3.1 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

3.3.2 Bit banding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

3.3.3 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

3.4 Boot configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

4 CRC calculation unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

4.1 CRC introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

4.2 CRC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

4.3 CRC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

4.4 CRC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

4.4.1 Data register (CRC_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

4.4.2 Independent data register (CRC_IDR) . . . . . . . . . . . . . . . . . . . . . . . . . 65

4.4.3 Control register (CRC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

4.4.4 CRC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

5 Power control (PWR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

5.1 Power supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

5.1.1 Independent A/D and D/A converter supply and reference voltage . . . . 68

5.1.2 Battery backup domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

5.1.3 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

5.2 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

5.2.1 Power on reset (POR)/power down reset (PDR) . . . . . . . . . . . . . . . . . . 70

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5.2.2 Programmable voltage detector (PVD) . . . . . . . . . . . . . . . . . . . . . . . . . 70

5.3 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

5.3.1 Slowing down system clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

5.3.2 Peripheral clock gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

5.3.3 Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

5.3.4 Stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

5.3.5 Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

5.3.6 Auto-wakeup (AWU) from low-power mode . . . . . . . . . . . . . . . . . . . . . . 77

5.4 Power control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

5.4.1 Power control register (PWR_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

5.4.2 Power control/status register (PWR_CSR) . . . . . . . . . . . . . . . . . . . . . . 79

5.4.3 PWR register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

6 Backup registers (BKP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

6.1 BKP introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

6.2 BKP main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

6.3 BKP functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

6.3.1 Tamper detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

6.3.2 RTC calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

6.4 BKP registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

6.4.1 Backup data register x (BKP_DRx) (x = 1 ..42) . . . . . . . . . . . . . . . . . . . 83

6.4.2 RTC clock calibration register (BKP_RTCCR) . . . . . . . . . . . . . . . . . . . . 83

6.4.3 Backup control register (BKP_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

6.4.4 Backup control/status register (BKP_CSR) . . . . . . . . . . . . . . . . . . . . . . 84

6.4.5 BKP register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

7 Low-, medium-, high- and XL-density reset and clock

control (RCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

7.1 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

7.1.1 System reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

7.1.2 Power reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

7.1.3 Backup domain reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

7.2 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

7.2.1 HSE clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

7.2.2 HSI clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

7.2.3 PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

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7.2.4 LSE clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

7.2.5 LSI clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

7.2.6 System clock (SYSCLK) selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

7.2.7 Clock security system (CSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

7.2.8 RTC clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

7.2.9 Watchdog clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

7.2.10 Clock-out capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

7.3 RCC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

7.3.1 Clock control register (RCC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

7.3.2 Clock configuration register (RCC_CFGR) . . . . . . . . . . . . . . . . . . . . . 101

7.3.3 Clock interrupt register (RCC_CIR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

7.3.4 APB2 peripheral reset register (RCC_APB2RSTR) . . . . . . . . . . . . . . 106

7.3.5 APB1 peripheral reset register (RCC_APB1RSTR) . . . . . . . . . . . . . . 109

7.3.6 AHB peripheral clock enable register (RCC_AHBENR) . . . . . . . . . . . 111

7.3.7 APB2 peripheral clock enable register (RCC_APB2ENR) . . . . . . . . . . 112

7.3.8 APB1 peripheral clock enable register (RCC_APB1ENR) . . . . . . . . . . 115

7.3.9 Backup domain control register (RCC_BDCR) . . . . . . . . . . . . . . . . . . 118

7.3.10 Control/status register (RCC_CSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

7.3.11 RCC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

8 Connectivity line devices: reset and clock control (RCC) . . . . . . . . . 123

8.1 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

8.1.1 System reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

8.1.2 Power reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

8.1.3 Backup domain reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

8.2 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

8.2.1 HSE clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

8.2.2 HSI clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

8.2.3 PLLs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

8.2.4 LSE clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

8.2.5 LSI clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

8.2.6 System clock (SYSCLK) selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

8.2.7 Clock security system (CSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

8.2.8 RTC clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

8.2.9 Watchdog clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

8.2.10 Clock-out capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

8.3 RCC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

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8.3.1 Clock control register (RCC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

8.3.2 Clock configuration register (RCC_CFGR) . . . . . . . . . . . . . . . . . . . . . 134

8.3.3 Clock interrupt register (RCC_CIR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

8.3.4 APB2 peripheral reset register (RCC_APB2RSTR) . . . . . . . . . . . . . . 141

8.3.5 APB1 peripheral reset register (RCC_APB1RSTR) . . . . . . . . . . . . . . 142

8.3.6 AHB Peripheral Clock enable register (RCC_AHBENR) . . . . . . . . . . . 145

8.3.7 APB2 peripheral clock enable register (RCC_APB2ENR) . . . . . . . . . . 146

8.3.8 APB1 peripheral clock enable register (RCC_APB1ENR) . . . . . . . . . . 148

8.3.9 Backup domain control register (RCC_BDCR) . . . . . . . . . . . . . . . . . . 150

8.3.10 Control/status register (RCC_CSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

8.3.11 AHB peripheral clock reset register (RCC_AHBRSTR) . . . . . . . . . . . . 153

8.3.12 Clock configuration register2 (RCC_CFGR2) . . . . . . . . . . . . . . . . . . . 154

8.3.13 RCC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

9 General-purpose and alternate-function I/Os (GPIOs and AFIOs) . . 159

9.1 GPIO functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

9.1.1 General-purpose I/O (GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

9.1.2 Atomic bit set or reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

9.1.3 External interrupt/wakeup lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

9.1.4 Alternate functions (AF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

9.1.5 Software remapping of I/O alternate functions . . . . . . . . . . . . . . . . . . 162

9.1.6 GPIO locking mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

9.1.7 Input configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

9.1.8 Output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

9.1.9 Alternate function configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

9.1.10 Analog configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

9.1.11 GPIO configurations for device peripherals . . . . . . . . . . . . . . . . . . . . . 166

9.2 GPIO registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

9.2.1 Port configuration register low (GPIOx_CRL) (x=A..G) . . . . . . . . . . . . 171

9.2.2 Port configuration register high (GPIOx_CRH) (x=A..G) . . . . . . . . . . . 172

9.2.3 Port input data register (GPIOx_IDR) (x=A..G) . . . . . . . . . . . . . . . . . . 172

9.2.4 Port output data register (GPIOx_ODR) (x=A..G) . . . . . . . . . . . . . . . . 173

9.2.5 Port bit set/reset register (GPIOx_BSRR) (x=A..G) . . . . . . . . . . . . . . . 173

9.2.6 Port bit reset register (GPIOx_BRR) (x=A..G) . . . . . . . . . . . . . . . . . . . 174

9.2.7 Port configuration lock register (GPIOx_LCKR) (x=A..G) . . . . . . . . . . 174

9.3 Alternate function I/O and debug configuration (AFIO) . . . . . . . . . . . . . 175

9.3.1 Using OSC32_IN/OSC32_OUT pins as GPIO ports PC14/PC15 . . . . 175

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9.3.2 Using OSC_IN/OSC_OUT pins as GPIO ports PD0/PD1 . . . . . . . . . . 175

9.3.3 CAN1 alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

9.3.4 CAN2 alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

9.3.5 JTAG/SWD alternate function remapping . . . . . . . . . . . . . . . . . . . . . . 176

9.3.6 ADC alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

9.3.7 Timer alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . 178

9.3.8 USART alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . 180

9.3.9 I2C1 alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181

9.3.10 SPI1 alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . 181

9.3.11 SPI3/I2S3 alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . 181

9.3.12 Ethernet alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . 181

9.4 AFIO registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183

9.4.1 Event control register (AFIO_EVCR) . . . . . . . . . . . . . . . . . . . . . . . . . . 183

9.4.2 AF remap and debug I/O configuration register (AFIO_MAPR) . . . . . . 184

9.4.3 External interrupt configuration register 1 (AFIO_EXTICR1) . . . . . . . . 191

9.4.4 External interrupt configuration register 2 (AFIO_EXTICR2) . . . . . . . . 191

9.4.5 External interrupt configuration register 3 (AFIO_EXTICR3) . . . . . . . . 192

9.4.6 External interrupt configuration register 4 (AFIO_EXTICR4) . . . . . . . . 192

9.4.7 AF remap and debug I/O configuration register2 (AFIO_MAPR2) . . . . 193

9.5 GPIO and AFIO register maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194

10 Interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196

10.1 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 196

10.1.1 SysTick calibration value register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196

10.1.2 Interrupt and exception vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197

10.2 External interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . . 205

10.2.1 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206

10.2.2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206

10.2.3 Wakeup event management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206

10.2.4 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207

10.2.5 External interrupt/event line mapping . . . . . . . . . . . . . . . . . . . . . . . . . 208

10.3 EXTI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210

10.3.1 Interrupt mask register (EXTI_IMR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 210

10.3.2 Event mask register (EXTI_EMR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210

10.3.3 Rising trigger selection register (EXTI_RTSR) . . . . . . . . . . . . . . . . . . 211

10.3.4 Falling trigger selection register (EXTI_FTSR) . . . . . . . . . . . . . . . . . . 211

10.3.5 Software interrupt event register (EXTI_SWIER) . . . . . . . . . . . . . . . . . 212

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10.3.6 Pending register (EXTI_PR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212

10.3.7 EXTI register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213

11 Analog-to-digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214

11.1 ADC introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214

11.2 ADC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215

11.3 ADC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215

11.3.1 ADC on-off control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218

11.3.2 ADC clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218

11.3.3 Channel selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218

11.3.4 Single conversion mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218

11.3.5 Continuous conversion mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219

11.3.6 Timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219

11.3.7 Analog watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220

11.3.8 Scan mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220

11.3.9 Injected channel management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221

11.3.10 Discontinuous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222

11.4 Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222

11.5 Data alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223

11.6 Channel-by-channel programmable sample time . . . . . . . . . . . . . . . . . . 224

11.7 Conversion on external trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224

11.8 DMA request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226

11.9 Dual ADC mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227

11.9.1 Injected simultaneous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229

11.9.2 Regular simultaneous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229

11.9.3 Fast interleaved mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230

11.9.4 Slow interleaved mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230

11.9.5 Alternate trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231

11.9.6 Independent mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232

11.9.7 Combined regular/injected simultaneous mode . . . . . . . . . . . . . . . . . . 232

11.9.8 Combined regular simultaneous + alternate trigger mode . . . . . . . . . . 232

11.9.9 Combined injected simultaneous + interleaved . . . . . . . . . . . . . . . . . . 233

11.10 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234

11.11 ADC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235

11.12 ADC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236

11.12.1 ADC status register (ADC_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236

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11.12.2 ADC control register 1 (ADC_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 237

11.12.3 ADC control register 2 (ADC_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . 239

11.12.4 ADC sample time register 1 (ADC_SMPR1) . . . . . . . . . . . . . . . . . . . . 243

11.12.5 ADC sample time register 2 (ADC_SMPR2) . . . . . . . . . . . . . . . . . . . . 244

11.12.6 ADC injected channel data offset register x (ADC_JOFRx)(x=1..4) . . 244

11.12.7 ADC watchdog high threshold register (ADC_HTR) . . . . . . . . . . . . . . 245

11.12.8 ADC watchdog low threshold register (ADC_LTR) . . . . . . . . . . . . . . . 245

11.12.9 ADC regular sequence register 1 (ADC_SQR1) . . . . . . . . . . . . . . . . . 246

11.12.10 ADC regular sequence register 2 (ADC_SQR2) . . . . . . . . . . . . . . . . . 247

11.12.11 ADC regular sequence register 3 (ADC_SQR3) . . . . . . . . . . . . . . . . . 248

11.12.12 ADC injected sequence register (ADC_JSQR) . . . . . . . . . . . . . . . . . . 249

11.12.13 ADC injected data register x (ADC_JDRx) (x= 1..4) . . . . . . . . . . . . . . 250

11.12.14 ADC regular data register (ADC_DR) . . . . . . . . . . . . . . . . . . . . . . . . . 250

11.12.15 ADC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251

12 Digital-to-analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253

12.1 DAC introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253

12.2 DAC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253

12.3 DAC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255

12.3.1 DAC channel enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255

12.3.2 DAC output buffer enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255

12.3.3 DAC data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255

12.3.4 DAC conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256

12.3.5 DAC output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257

12.3.6 DAC trigger selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257

12.3.7 DMA request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258

12.3.8 Noise generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258

12.3.9 Triangle-wave generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259

12.4 Dual DAC channel conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260

12.4.1 Independent trigger without wave generation . . . . . . . . . . . . . . . . . . . 260

12.4.2 Independent trigger with same LFSR generation . . . . . . . . . . . . . . . . 261

12.4.3 Independent trigger with different LFSR generation . . . . . . . . . . . . . . 261

12.4.4 Independent trigger with same triangle generation . . . . . . . . . . . . . . . 261

12.4.5 Independent trigger with different triangle generation . . . . . . . . . . . . . 262

12.4.6 Simultaneous software start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262

12.4.7 Simultaneous trigger without wave generation . . . . . . . . . . . . . . . . . . 262

12.4.8 Simultaneous trigger with same LFSR generation . . . . . . . . . . . . . . . 263

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12.4.9 Simultaneous trigger with different LFSR generation . . . . . . . . . . . . . 263

12.4.10 Simultaneous trigger with same triangle generation . . . . . . . . . . . . . . 263

12.4.11 Simultaneous trigger with different triangle generation . . . . . . . . . . . . 264

12.5 DAC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264

12.5.1 DAC control register (DAC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264

12.5.2 DAC software trigger register (DAC_SWTRIGR) . . . . . . . . . . . . . . . . . 267

12.5.3 DAC channel1 12-bit right-aligned data holding register

(DAC_DHR12R1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268

12.5.4 DAC channel1 12-bit left aligned data holding register

(DAC_DHR12L1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268

12.5.5 DAC channel1 8-bit right aligned data holding register

(DAC_DHR8R1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268

12.5.6 DAC channel2 12-bit right aligned data holding register

(DAC_DHR12R2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269

12.5.7 DAC channel2 12-bit left aligned data holding register

(DAC_DHR12L2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269

12.5.8 DAC channel2 8-bit right-aligned data holding register

(DAC_DHR8R2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269

12.5.9 Dual DAC 12-bit right-aligned data holding register

(DAC_DHR12RD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270

12.5.10 DUAL DAC 12-bit left aligned data holding register

(DAC_DHR12LD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270

12.5.11 DUAL DAC 8-bit right aligned data holding register

(DAC_DHR8RD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271

12.5.12 DAC channel1 data output register (DAC_DOR1) . . . . . . . . . . . . . . . . 271

12.5.13 DAC channel2 data output register (DAC_DOR2) . . . . . . . . . . . . . . . . 271

12.5.14 DAC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272

13 Direct memory access controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . 273

13.1 DMA introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273

13.2 DMA main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273

13.3 DMA functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275

13.3.1 DMA transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275

13.3.2 Arbiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276

13.3.3 DMA channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276

13.3.4 Programmable data width, data alignment and endians . . . . . . . . . . . 278

13.3.5 Error management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279

13.3.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280

13.3.7 DMA request mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280

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13.4 DMA registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284

13.4.1 DMA interrupt status register (DMA_ISR) . . . . . . . . . . . . . . . . . . . . . . 284

13.4.2 DMA interrupt flag clear register (DMA_IFCR) . . . . . . . . . . . . . . . . . . 285

13.4.3 DMA channel x configuration register (DMA_CCRx) (x = 1..7,

where x = channel number) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286

13.4.4 DMA channel x number of data register (DMA_CNDTRx) (x = 1..7),

where x = channel number) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287

13.4.5 DMA channel x peripheral address register (DMA_CPARx) (x = 1..7),

where x = channel number) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288

13.4.6 DMA channel x memory address register (DMA_CMARx) (x = 1..7),

where x = channel number) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288

13.4.7 DMA register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289

14 Advanced-control timers (TIM1&TIM8) . . . . . . . . . . . . . . . . . . . . . . . . 292

14.1 TIM1&TIM8 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292

14.2 TIM1&TIM8 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293

14.3 TIM1&TIM8 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295

14.3.1 Time-base unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295

14.3.2 Counter modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296

14.3.3 Repetition counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304

14.3.4 Clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306

14.3.5 Capture/compare channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308

14.3.6 Input capture mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310

14.3.7 PWM input mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311

14.3.8 Forced output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312

14.3.9 Output compare mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313

14.3.10 PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314

14.3.11 Complementary outputs and dead-time insertion . . . . . . . . . . . . . . . . 317

14.3.12 Using the break function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318

14.3.13 Clearing the OCxREF signal on an external event . . . . . . . . . . . . . . . 321

14.3.14 6-step PWM generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322

14.3.15 One-pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323

14.3.16 Encoder interface mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324

14.3.17 Timer input XOR function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326

14.3.18 Interfacing with Hall sensors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327

14.3.19 TIMx and external trigger synchronization . . . . . . . . . . . . . . . . . . . . . . 329

14.3.20 Timer synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332

14.3.21 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332

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14.4 TIM1&TIM8 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333

14.4.1 TIM1&TIM8 control register 1 (TIMx_CR1) . . . . . . . . . . . . . . . . . . . . . 333

14.4.2 TIM1&TIM8 control register 2 (TIMx_CR2) . . . . . . . . . . . . . . . . . . . . . 334

14.4.3 TIM1&TIM8 slave mode control register (TIMx_SMCR) . . . . . . . . . . . 337

14.4.4 TIM1&TIM8 DMA/interrupt enable register (TIMx_DIER) . . . . . . . . . . 339

14.4.5 TIM1&TIM8 status register (TIMx_SR) . . . . . . . . . . . . . . . . . . . . . . . . 341

14.4.6 TIM1&TIM8 event generation register (TIMx_EGR) . . . . . . . . . . . . . . 342

14.4.7 TIM1&TIM8 capture/compare mode register 1 (TIMx_CCMR1) . . . . . 344

14.4.8 TIM1&TIM8 capture/compare mode register 2 (TIMx_CCMR2) . . . . . 347

14.4.9 TIM1&TIM8 capture/compare enable register (TIMx_CCER) . . . . . . . 348

14.4.10 TIM1&TIM8 counter (TIMx_CNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351

14.4.11 TIM1&TIM8 prescaler (TIMx_PSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 351

14.4.12 TIM1&TIM8 auto-reload register (TIMx_ARR) . . . . . . . . . . . . . . . . . . . 351

14.4.13 TIM1&TIM8 repetition counter register (TIMx_RCR) . . . . . . . . . . . . . . 352

14.4.14 TIM1&TIM8 capture/compare register 1 (TIMx_CCR1) . . . . . . . . . . . . 352

14.4.15 TIM1&TIM8 capture/compare register 2 (TIMx_CCR2) . . . . . . . . . . . . 353

14.4.16 TIM1&TIM8 capture/compare register 3 (TIMx_CCR3) . . . . . . . . . . . . 353

14.4.17 TIM1&TIM8 capture/compare register 4 (TIMx_CCR4) . . . . . . . . . . . . 354

14.4.18 TIM1&TIM8 break and dead-time register (TIMx_BDTR) . . . . . . . . . . 354

14.4.19 TIM1&TIM8 DMA control register (TIMx_DCR) . . . . . . . . . . . . . . . . . . 356

14.4.20 TIM1&TIM8 DMA address for full transfer (TIMx_DMAR) . . . . . . . . . . 357

14.4.21 TIM1&TIM8 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358

15 General-purpose timers (TIM2 to TIM5) . . . . . . . . . . . . . . . . . . . . . . . . 360

15.1 TIM2 to TIM5 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360

15.2 TIMx main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361

15.3 TIMx functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362

15.3.1 Time-base unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362

15.3.2 Counter modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364

15.3.3 Clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372

15.3.4 Capture/compare channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375

15.3.5 Input capture mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377

15.3.6 PWM input mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378

15.3.7 Forced output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379

15.3.8 Output compare mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379

15.3.9 PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380

15.3.10 One-pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383

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15.3.11 Clearing the OCxREF signal on an external event . . . . . . . . . . . . . . . 384

15.3.12 Encoder interface mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385

15.3.13 Timer input XOR function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388

15.3.14 Timers and external trigger synchronization . . . . . . . . . . . . . . . . . . . . 388

15.3.15 Timer synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391

15.3.16 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 396

15.4 TIMx2 to TIM5 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397

15.4.1 TIMx control register 1 (TIMx_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . 397

15.4.2 TIMx control register 2 (TIMx_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . 399

15.4.3 TIMx slave mode control register (TIMx_SMCR) . . . . . . . . . . . . . . . . . 400

15.4.4 TIMx DMA/Interrupt enable register (TIMx_DIER) . . . . . . . . . . . . . . . . 402

15.4.5 TIMx status register (TIMx_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 403

15.4.6 TIMx event generation register (TIMx_EGR) . . . . . . . . . . . . . . . . . . . . 405

15.4.7 TIMx capture/compare mode register 1 (TIMx_CCMR1) . . . . . . . . . . . 406

15.4.8 TIMx capture/compare mode register 2 (TIMx_CCMR2) . . . . . . . . . . . 409

15.4.9 TIMx capture/compare enable register (TIMx_CCER) . . . . . . . . . . . . . 410

15.4.10 TIMx counter (TIMx_CNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411

15.4.11 TIMx prescaler (TIMx_PSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412

15.4.12 TIMx auto-reload register (TIMx_ARR) . . . . . . . . . . . . . . . . . . . . . . . . 412

15.4.13 TIMx capture/compare register 1 (TIMx_CCR1) . . . . . . . . . . . . . . . . . 412

15.4.14 TIMx capture/compare register 2 (TIMx_CCR2) . . . . . . . . . . . . . . . . . 413

15.4.15 TIMx capture/compare register 3 (TIMx_CCR3) . . . . . . . . . . . . . . . . . 413

15.4.16 TIMx capture/compare register 4 (TIMx_CCR4) . . . . . . . . . . . . . . . . . 413

15.4.17 TIMx DMA control register (TIMx_DCR) . . . . . . . . . . . . . . . . . . . . . . . 414

15.4.18 TIMx DMA address for full transfer (TIMx_DMAR) . . . . . . . . . . . . . . . 414

15.4.19 TIMx register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416

16 General-purpose timers (TIM9 to TIM14) . . . . . . . . . . . . . . . . . . . . . . . 418

16.1 TIM9 to TIM14 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418

16.2 TIM9 to TIM14 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 419

16.2.1 TIM9/TIM12 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 419

16.2.2 TIM10/TIM11 and TIM13/TIM14 main features . . . . . . . . . . . . . . . . . . 420

16.3 TIM9 to TIM14 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . 421

16.3.1 Time-base unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421

16.3.2 Counter modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 422

16.3.3 Clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425

16.3.4 Capture/compare channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 427

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16.3.5 Input capture mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 428

16.3.6 PWM input mode (only for TIM9/12) . . . . . . . . . . . . . . . . . . . . . . . . . . 429

16.3.7 Forced output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 430

16.3.8 Output compare mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 431

16.3.9 PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 432

16.3.10 One-pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433

16.3.11 TIM9/12 external trigger synchronization . . . . . . . . . . . . . . . . . . . . . . . 434

16.3.12 Timer synchronization (TIM9/12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437

16.3.13 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437

16.4 TIM9 and TIM12 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437

16.4.1 TIM9/12 control register 1 (TIMx_CR1) . . . . . . . . . . . . . . . . . . . . . . . . 437

16.4.2 9/12TIM9/12 slave mode control register (TIMx_SMCR) . . . . . . . . . . . 439

16.4.3 TIM9/12 Interrupt enable register (TIMx_DIER) . . . . . . . . . . . . . . . . . 440

16.4.4 TIM9/12 status register (TIMx_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 441

16.4.5 TIM9/12 event generation register (TIMx_EGR) . . . . . . . . . . . . . . . . . 442

16.4.6 TIM9/12 capture/compare mode register 1 (TIMx_CCMR1) . . . . . . . . 444

16.4.7 TIM9/12 capture/compare enable register (TIMx_CCER) . . . . . . . . . . 447

16.4.8 TIM9/12 counter (TIMx_CNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 448

16.4.9 TIM9/12 prescaler (TIMx_PSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 448

16.4.10 TIM9/12 auto-reload register (TIMx_ARR) . . . . . . . . . . . . . . . . . . . . . 448

16.4.11 TIM9/12 capture/compare register 1 (TIMx_CCR1) . . . . . . . . . . . . . . 449

16.4.12 TIM9/12 capture/compare register 2 (TIMx_CCR2) . . . . . . . . . . . . . . 449

16.4.13 TIM9/12 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 449

16.5 TIM10/11/13/14 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 452

16.5.1 TIM10/11/13/14 control register 1 (TIMx_CR1) . . . . . . . . . . . . . . . . . . 452

16.5.2 TIM10/11/13/14 status register (TIMx_SR) . . . . . . . . . . . . . . . . . . . . . 453

16.5.3 TIM10/11/13/14 event generation register (TIMx_EGR) . . . . . . . . . . . 453

16.5.4 TIM10/11/13/14 capture/compare mode register 1

(TIMx_CCMR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 454

16.5.5 TIM10/11/13/14 capture/compare enable register

(TIMx_CCER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457

16.5.6 TIM10/11/13/14 counter (TIMx_CNT) . . . . . . . . . . . . . . . . . . . . . . . . . 458

16.5.7 TIM10/11/13/14 prescaler (TIMx_PSC) . . . . . . . . . . . . . . . . . . . . . . . . 458

16.5.8 TIM10/11/13/14 auto-reload register (TIMx_ARR) . . . . . . . . . . . . . . . 458

16.5.9 TIM10/11/13/14 capture/compare register 1 (TIMx_CCR1) . . . . . . . . 459

16.5.10 TIM10/11/13/14 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 459

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17 Basic timers (TIM6&TIM7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 461

17.1 TIM6&TIM7 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 461

17.2 TIM6&TIM7 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 461

17.3 TIM6&TIM7 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 462

17.3.1 Time-base unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 462

17.3.2 Counting mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 464

17.3.3 Clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 466

17.3.4 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 467

17.4 TIM6&TIM7 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 467

17.4.1 TIM6&TIM7 control register 1 (TIMx_CR1) . . . . . . . . . . . . . . . . . . . . . 467

17.4.2 TIM6&TIM7 control register 2 (TIMx_CR2) . . . . . . . . . . . . . . . . . . . . . 469

17.4.3 TIM6&TIM7 DMA/Interrupt enable register (TIMx_DIER) . . . . . . . . . . 469

17.4.4 TIM6&TIM7 status register (TIMx_SR) . . . . . . . . . . . . . . . . . . . . . . . . 470

17.4.5 TIM6&TIM7 event generation register (TIMx_EGR) . . . . . . . . . . . . . . 470

17.4.6 TIM6&TIM7 counter (TIMx_CNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470

17.4.7 TIM6&TIM7 prescaler (TIMx_PSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 471

17.4.8 TIM6&TIM7 auto-reload register (TIMx_ARR) . . . . . . . . . . . . . . . . . . . 471

17.4.9 TIM6&TIM7 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 472

18 Real-time clock (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 473

18.1 RTC introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 473

18.2 RTC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 474

18.3 RTC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 475

18.3.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 475

18.3.2 Resetting RTC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 476

18.3.3 Reading RTC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 476

18.3.4 Configuring RTC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 476

18.3.5 RTC flag assertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 477

18.4 RTC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 478

18.4.1 RTC control register high (RTC_CRH) . . . . . . . . . . . . . . . . . . . . . . . . 478

18.4.2 RTC control register low (RTC_CRL) . . . . . . . . . . . . . . . . . . . . . . . . . . 479

18.4.3 RTC prescaler load register (RTC_PRLH / RTC_PRLL) . . . . . . . . . . . 480

18.4.4 RTC prescaler divider register (RTC_DIVH / RTC_DIVL) . . . . . . . . . . 481

18.4.5 RTC counter register (RTC_CNTH / RTC_CNTL) . . . . . . . . . . . . . . . . 482

18.4.6 RTC alarm register high (RTC_ALRH / RTC_ALRL) . . . . . . . . . . . . . . 483

18.4.7 RTC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 484

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19 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485

19.1 IWDG introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485

19.2 IWDG main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485

19.3 IWDG functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485

19.3.1 Hardware watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 486

19.3.2 Register access protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 486

19.3.3 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 486

19.4 IWDG registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 487

19.4.1 Key register (IWDG_KR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 487

19.4.2 Prescaler register (IWDG_PR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 488

19.4.3 Reload register (IWDG_RLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 488

19.4.4 Status register (IWDG_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 488

19.4.5 IWDG register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 490

20 Window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 491

20.1 WWDG introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 491

20.2 WWDG main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 491

20.3 WWDG functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 491

20.4 How to program the watchdog timeout . . . . . . . . . . . . . . . . . . . . . . . . . . 493

20.5 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494

20.6 WWDG registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 495

20.6.1 Control register (WWDG_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 495

20.6.2 Configuration register (WWDG_CFR) . . . . . . . . . . . . . . . . . . . . . . . . . 496

20.6.3 Status register (WWDG_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 496

20.6.4 WWDG register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 497

21 Flexible static memory controller (FSMC) . . . . . . . . . . . . . . . . . . . . . 498

21.1 FSMC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 498

21.2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 499

21.3 AHB interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500

21.3.1 Supported memories and transactions . . . . . . . . . . . . . . . . . . . . . . . . 501

21.4 External device address mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 502

21.4.1 NOR/PSRAM address mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 502

21.4.2 NAND/PC Card address mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . 503

21.5 NOR Flash/PSRAM controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504

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21.5.1 External memory interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 505

21.5.2 Supported memories and transactions . . . . . . . . . . . . . . . . . . . . . . . . 506

21.5.3 General timing rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 508

21.5.4 NOR Flash/PSRAM controller asynchronous transactions . . . . . . . . . 508

21.5.5 Synchronous transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 526

21.5.6 NOR/PSRAM control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 532

21.6 NAND Flash/PC Card controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 538

21.6.1 External memory interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 539

21.6.2 NAND Flash / PC Card supported memories and transactions . . . . . . 541

21.6.3 Timing diagrams for NAND and PC Card . . . . . . . . . . . . . . . . . . . . . . 541

21.6.4 NAND Flash operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 542

21.6.5 NAND Flash pre-wait functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . 543

21.6.6 Computation of the error correction code (ECC)

in NAND Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 544

21.6.7 PC Card/CompactFlash operations . . . . . . . . . . . . . . . . . . . . . . . . . . . 545

21.6.8 NAND Flash/PC Card control registers . . . . . . . . . . . . . . . . . . . . . . . . 547

21.6.9 FSMC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 554

22 Secure digital input/output interface (SDIO) . . . . . . . . . . . . . . . . . . . . 556

22.1 SDIO main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 556

22.2 SDIO bus topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 557

22.3 SDIO functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 559

22.3.1 SDIO adapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 560

22.3.2 SDIO AHB interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 570

22.4 Card functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 571

22.4.1 Card identification mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 571

22.4.2 Card reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 571

22.4.3 Operating voltage range validation . . . . . . . . . . . . . . . . . . . . . . . . . . . 572

22.4.4 Card identification process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 572

22.4.5 Block write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 573

22.4.6 Block read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 574

22.4.7 Stream access, stream write and stream read (MultiMediaCard only) 574

22.4.8 Erase: group erase and sector erase . . . . . . . . . . . . . . . . . . . . . . . . . . 576

22.4.9 Wide bus selection or deselection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 577

22.4.10 Protection management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 577

22.4.11 Card status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 580

22.4.12 SD status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 583

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22.4.13 SD I/O mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 587

22.4.14 Commands and responses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 588

22.5 Response formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 591

22.5.1 R1 (normal response command) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 592

22.5.2 R1b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 592

22.5.3 R2 (CID, CSD register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 592

22.5.4 R3 (OCR register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 592

22.5.5 R4 (Fast I/O) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 593

22.5.6 R4b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 593

22.5.7 R5 (interrupt request) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 594

22.5.8 R6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 594

22.6 SDIO I/O card-specific operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 595

22.6.1 SDIO I/O read wait operation by SDIO_D2 signalling . . . . . . . . . . . . . 595

22.6.2 SDIO read wait operation by stopping SDIO_CK . . . . . . . . . . . . . . . . 595

22.6.3 SDIO suspend/resume operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 596

22.6.4 SDIO interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 596

22.7 CE-ATA specific operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 596

22.7.1 Command completion signal disable . . . . . . . . . . . . . . . . . . . . . . . . . . 596

22.7.2 Command completion signal enable . . . . . . . . . . . . . . . . . . . . . . . . . . 596

22.7.3 CE-ATA interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 597

22.7.4 Aborting CMD61 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 597

22.8 HW flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 597

22.9 SDIO registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 597

22.9.1 SDIO power control register (SDIO_POWER) . . . . . . . . . . . . . . . . . . . 598

22.9.2 SDI clock control register (SDIO_CLKCR) . . . . . . . . . . . . . . . . . . . . . . 598

22.9.3 SDIO argument register (SDIO_ARG) . . . . . . . . . . . . . . . . . . . . . . . . . 599

22.9.4 SDIO command register (SDIO_CMD) . . . . . . . . . . . . . . . . . . . . . . . . 600

22.9.5 SDIO command response register (SDIO_RESPCMD) . . . . . . . . . . . 601

22.9.6 SDIO response 1..4 register (SDIO_RESPx) . . . . . . . . . . . . . . . . . . . 601

22.9.7 SDIO data timer register (SDIO_DTIMER) . . . . . . . . . . . . . . . . . . . . . 602

22.9.8 SDIO data length register (SDIO_DLEN) . . . . . . . . . . . . . . . . . . . . . . 602

22.9.9 SDIO data control register (SDIO_DCTRL) . . . . . . . . . . . . . . . . . . . . . 603

22.9.10 SDIO data counter register (SDIO_DCOUNT) . . . . . . . . . . . . . . . . . . 604

22.9.11 SDIO status register (SDIO_STA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 605

22.9.12 SDIO interrupt clear register (SDIO_ICR) . . . . . . . . . . . . . . . . . . . . . . 606

22.9.13 SDIO mask register (SDIO_MASK) . . . . . . . . . . . . . . . . . . . . . . . . . . . 608

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22.9.14 SDIO FIFO counter register (SDIO_FIFOCNT) . . . . . . . . . . . . . . . . . . 610

22.9.15 SDIO data FIFO register (SDIO_FIFO) . . . . . . . . . . . . . . . . . . . . . . . . 611

22.9.16 SDIO register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 611

23 Universal serial bus full-speed device interface (USB) . . . . . . . . . . . 613

23.1 USB introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 613

23.2 USB main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 613

23.3 USB functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 613

23.3.1 Description of USB blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 615

23.4 Programming considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 616

23.4.1 Generic USB device programming . . . . . . . . . . . . . . . . . . . . . . . . . . . 616

23.4.2 System and power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 617

23.4.3 Double-buffered endpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 621

23.4.4 Isochronous transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 625

23.4.5 Suspend/Resume events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 626

23.5 USB registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 628

23.5.1 Common registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 628

23.5.2 Endpoint-specific registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 635

23.5.3 Buffer descriptor table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 640

23.5.4 USB register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 643

24 Controller area network (bxCAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 645

24.1 bxCAN introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 645

24.2 bxCAN main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 645

24.3 bxCAN general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 646

24.3.1 CAN 2.0B active core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 647

24.3.2 Control, status and configuration registers . . . . . . . . . . . . . . . . . . . . . 647

24.3.3 Tx mailboxes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 647

24.3.4 Acceptance filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 647

24.4 bxCAN operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 648

24.4.1 Initialization mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 649

24.4.2 Normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 649

24.4.3 Sleep mode (low power) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 649

24.5 Test mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 650

24.5.1 Silent mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 650

24.5.2 Loop back mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 651

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24.5.3 Loop back combined with silent mode . . . . . . . . . . . . . . . . . . . . . . . . . 651

24.6 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 652

24.7 bxCAN functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 652

24.7.1 Transmission handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 652

24.7.2 Time triggered communication mode . . . . . . . . . . . . . . . . . . . . . . . . . 654

24.7.3 Reception handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 654

24.7.4 Identifier filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 655

24.7.5 Message storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 659

24.7.6 Error management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 661

24.7.7 Bit timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 661

24.8 bxCAN interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 663

24.9 CAN registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 665

24.9.1 Register access protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 665

24.9.2 CAN control and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 665

24.9.3 CAN mailbox registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 675

24.9.4 CAN filter registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 682

24.9.5 bxCAN register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 686

25 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 690

25.1 SPI introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 690

25.2 SPI and I

25.2.1 SPI features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 691

25.2.2 I

25.3 SPI functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 693

25.3.1 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 693

25.3.2 Configuring the SPI in slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 696

25.3.3 Configuring the SPI in master mode . . . . . . . . . . . . . . . . . . . . . . . . . . 698

25.3.4 Configuring the SPI for half-duplex communication . . . . . . . . . . . . . . . 699

25.3.5 Data transmission and reception procedures . . . . . . . . . . . . . . . . . . . 699

25.3.6 CRC calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 706

25.3.7 Status flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 708

25.3.8 Disabling the SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 709

25.3.9 SPI communication using DMA (direct memory addressing) . . . . . . . 710

25.3.10 Error flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 712

S main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 691

S features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 692

25.3.11 SPI interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 713

25.4 I2S functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 714

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25.4.1 I2S general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 714

25.4.2 Supported audio protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 715

25.4.3 Clock generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 722

25.4.4 I

25.4.5 I

S master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 727

S slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 728

25.4.6 Status flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 730

25.4.7 Error flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 731

25.4.8 I

S interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 732

25.4.9 DMA features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 732

25.5 SPI and I2S registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 733

25.5.1 SPI control register 1 (SPI_CR1) (not used in I2S mode) . . . . . . . . . . 733

25.5.2 SPI control register 2 (SPI_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 735

25.5.3 SPI status register (SPI_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 736

25.5.4 SPI data register (SPI_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 737

25.5.5 SPI CRC polynomial register (SPI_CRCPR) (not used in I

mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 738

25.5.6 SPI RX CRC register (SPI_RXCRCR) (not used in I

25.5.7 SPI TX CRC register (SPI_TXCRCR) (not used in I

25.5.8 SPI_I

25.5.9 SPI_I

S configuration register (SPI_I2SCFGR) . . . . . . . . . . . . . . . . . . 739

S prescaler register (SPI_I2SPR) . . . . . . . . . . . . . . . . . . . . . . . 740

S mode) . . . . . . 738

25.5.10 SPI register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 742

26 Inter-integrated circuit (I2C) interface . . . . . . . . . . . . . . . . . . . . . . . . . 743

26.1 I2C introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 743

26.2 I

26.3 I

26.4 I2C interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 763

26.5 I

26.6 I

C main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 744

C functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 745

26.3.1 Mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 745

26.3.2 I2C slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 746

26.3.3 I2C master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 749

26.3.4 Error conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 757

26.3.5 SDA/SCL line control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 758

26.3.6 SMBus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 759

26.3.7 DMA requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 761

26.3.8 Packet error checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 763

C debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 765

C registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 765

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26.6.1 I2C Control register 1 (I2C_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 765

26.6.2 I

26.6.3 I

26.6.4 I

26.6.5 I

26.6.6 I

26.6.7 I

26.6.8 I

26.6.9 I

C Control register 2 (I2C_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 767

C Own address register 1 (I2C_OAR1) . . . . . . . . . . . . . . . . . . . . . . . 769

C Own address register 2 (I2C_OAR2) . . . . . . . . . . . . . . . . . . . . . . . 769

C Data register (I2C_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 770

C Status register 1 (I2C_SR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 770

C Status register 2 (I2C_SR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 774

C Clock control register (I2C_CCR) . . . . . . . . . . . . . . . . . . . . . . . . . 775

C TRISE register (I2C_TRISE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 776

26.6.10 I2C register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 777

27 Universal synchronous asynchronous receiver

transmitter (USART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 778

27.1 USART introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 778

27.2 USART main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 779

27.3 USART functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 780

27.3.1 USART character description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 783

27.3.2 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 784

27.3.3 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 787

27.3.4 Fractional baud rate generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 791

27.3.5 USART receiver’s tolerance to clock deviation . . . . . . . . . . . . . . . . . . 793

27.3.6 Multiprocessor communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 793

27.3.7 Parity control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 795

27.3.8 LIN (local interconnection network) mode . . . . . . . . . . . . . . . . . . . . . . 796

27.3.9 USART synchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 798

27.3.10 Single-wire half-duplex communication . . . . . . . . . . . . . . . . . . . . . . . . 800

27.3.11 Smartcard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 801

27.3.12 IrDA SIR ENDEC block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 803

27.3.13 Continuous communication using DMA . . . . . . . . . . . . . . . . . . . . . . . . 805

27.3.14 Hardware flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 808

27.4 USART interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 809

27.5 USART mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 810

27.6 USART registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 810

27.6.1 Status register (USART_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 811

27.6.2 Data register (USART_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 813

27.6.3 Baud rate register (USART_BRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 813

27.6.4 Control register 1 (USART_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 814

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27.6.5 Control register 2 (USART_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 816

27.6.6 Control register 3 (USART_CR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 817

27.6.7 Guard time and prescaler register (USART_GTPR) . . . . . . . . . . . . . . 819

27.6.8 USART register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 820

28 USB on-the-go full-speed (OTG_FS) . . . . . . . . . . . . . . . . . . . . . . . . . . 821

28.1 OTG_FS introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 821

28.2 OTG_FS main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 822

28.2.1 General features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 822

28.2.2 Host-mode features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 823

28.2.3 Peripheral-mode features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 823

28.3 OTG_FS functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 824

28.3.1 OTG full-speed core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 824

28.3.2 Full-speed OTG PHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 824

28.4 OTG dual role device (DRD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 825

28.4.1 ID line detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 826

28.4.2 HNP dual role device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 826

28.4.3 SRP dual role device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 826

28.5 USB peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 827

28.5.1 SRP-capable peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 827

28.5.2 Peripheral states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 828

28.5.3 Peripheral endpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 829

28.6 USB host . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 831

28.6.1 SRP-capable host . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 832

28.6.2 USB host states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 832

28.6.3 Host channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 834

28.6.4 Host scheduler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 835

28.7 SOF trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 836

28.7.1 Host SOFs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 836

28.7.2 Peripheral SOFs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 836

28.8 Power options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 837

28.9 Dynamic update of the OTG_FS_HFIR register . . . . . . . . . . . . . . . . . . . 838

28.10 USB data FIFOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 838

28.11 Peripheral FIFO architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 839

28.11.1 Peripheral Rx FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 839

28.11.2 Peripheral Tx FIFOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 840

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28.12 Host FIFO architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 840

28.12.1 Host Rx FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 840

28.12.2 Host Tx FIFOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 841

28.13 FIFO RAM allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 841

28.13.1 Device mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 841

28.13.2 Host mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 842

28.14 USB system performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 842

28.15 OTG_FS interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 843

28.16 OTG_FS control and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 844

28.16.1 CSR memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 845

28.16.2 OTG_FS global registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 850

28.16.3 Host-mode registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 871

28.16.4 Device-mode registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 882

28.16.5 OTG_FS power and clock gating control register

(OTG_FS_PCGCCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 904

28.16.6 OTG_FS register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 905

28.17 OTG_FS programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 912

28.17.1 Core initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 912

28.17.2 Host initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 913

28.17.3 Device initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 913

28.17.4 Host programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 914

28.17.5 Device programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 931

28.17.6 Operational model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 933

28.17.7 Worst case response time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 950

28.17.8 OTG programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 951

29 Ethernet (ETH): media access control (MAC) with

DMA controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 958

29.1 Ethernet introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 958

29.2 Ethernet main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 958

29.2.1 MAC core features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 959

29.2.2 DMA features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 960

29.2.3 PTP features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 960

29.3 Ethernet pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 961

29.4 Ethernet functional description: SMI, MII and RMII . . . . . . . . . . . . . . . . 962

29.4.1 Station management interface: SMI . . . . . . . . . . . . . . . . . . . . . . . . . . . 962

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29.4.2 Media-independent interface: MII . . . . . . . . . . . . . . . . . . . . . . . . . . . . 966

29.4.3 Reduced media-independent interface: RMII . . . . . . . . . . . . . . . . . . . 968

29.4.4 MII/RMII selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 969

29.5 Ethernet functional description: MAC 802.3 . . . . . . . . . . . . . . . . . . . . . . 970

29.5.1 MAC 802.3 frame format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 970

29.5.2 MAC frame transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 974

29.5.3 MAC frame reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 981

29.5.4 MAC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 987

29.5.5 MAC filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 987

29.5.6 MAC loopback mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 990

29.5.7 MAC management counters: MMC . . . . . . . . . . . . . . . . . . . . . . . . . . . 990

29.5.8 Power management: PMT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 991

29.5.9 Precision time protocol (IEEE1588 PTP) . . . . . . . . . . . . . . . . . . . . . . . 994

29.6 Ethernet functional description: DMA controller operation . . . . . . . . . . 1000

29.6.1 Initialization of a transfer using DMA . . . . . . . . . . . . . . . . . . . . . . . . . 1001

29.6.2 Host bus burst access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1001

29.6.3 Host data buffer alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1002

29.6.4 Buffer size calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1002

29.6.5 DMA arbiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1003

29.6.6 Error response to DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1003

29.6.7 Tx DMA configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1003

29.6.8 Rx DMA configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1012

29.6.9 DMA interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1020

29.7 Ethernet interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1021

29.8 Ethernet register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1022

29.8.1 MAC register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1022

29.8.2 MMC register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1039

29.8.3 IEEE 1588 time stamp registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1044

29.8.4 DMA register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1048

29.8.5 Ethernet register maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1061

30 Device electronic signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1065

30.1 Memory size registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1065

30.1.1 Flash size register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1065

30.2 Unique device ID register (96 bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1066

31 Debug support (DBG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1068

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31.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1068

31.2 Reference ARM® documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1070

31.3 SWJ debug port (serial wire and JTAG) . . . . . . . . . . . . . . . . . . . . . . . . 1070

31.3.1 Mechanism to select the JTAG-DP or the SW-DP . . . . . . . . . . . . . . . 1071

31.4 Pinout and debug port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1071

31.4.1 SWJ debug port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1072

31.4.2 Flexible SWJ-DP pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1072

31.4.3 Internal pull-up and pull-down on JTAG pins . . . . . . . . . . . . . . . . . . . 1073

31.4.4 Using serial wire and releasing the unused debug pins as GPIOs . . 1074

31.5 STM32F10xxx JTAG TAP connection . . . . . . . . . . . . . . . . . . . . . . . . . 1074

31.6 ID codes and locking mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1076

31.6.1 MCU device ID code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1076

31.6.2 Boundary scan TAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1077

31.6.3 Cortex

31.6.4 Cortex

-M3 TAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1078

-M3 JEDEC-106 ID code . . . . . . . . . . . . . . . . . . . . . . . . . . . 1078

31.7 JTAG debug port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1078

31.8 SW debug port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1080

31.8.1 SW protocol introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1080

31.8.2 SW protocol sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1080

31.8.3 SW-DP state machine (reset, idle states, ID code) . . . . . . . . . . . . . . 1081

31.8.4 DP and AP read/write accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1082

31.8.5 SW-DP registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1082

31.8.6 SW-AP registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1083

31.9 AHB-AP (AHB access port) - valid for both JTAG-DP

and SW-DP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1084

31.10 Core debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1085

31.11 Capability of the debugger host to connect under system reset . . . . . 1086

31.12 FPB (Flash patch breakpoint) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1086

31.13 DWT (data watchpoint trigger) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1087

31.14 ITM (instrumentation trace macrocell) . . . . . . . . . . . . . . . . . . . . . . . . . 1087

31.14.1 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1087

31.14.2 Time stamp packets, synchronization and overflow packets . . . . . . . 1087

31.15 ETM (Embedded trace macrocell) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1089

31.15.1 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1089

31.15.2 Signal protocol, packet types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1089

31.15.3 Main ETM registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1089

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31.15.4 Configuration example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1090

31.16 MCU debug component (DBGMCU) . . . . . . . . . . . . . . . . . . . . . . . . . . 1090

31.16.1 Debug support for low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . 1090

31.16.2 Debug support for timers, watchdog, bxCAN and I

C . . . . . . . . . . . . 1091

31.16.3 Debug MCU configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . 1091

31.17 TPIU (trace port interface unit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1093

31.17.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1093

31.17.2 TRACE pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1095

31.17.3 TPUI formatter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1096

31.17.4 TPUI frame synchronization packets . . . . . . . . . . . . . . . . . . . . . . . . . 1097

31.17.5 Transmission of the synchronization frame packet . . . . . . . . . . . . . . 1097

31.17.6 Synchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1097

31.17.7 Asynchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1098

31.17.8 TRACECLKIN connection inside the STM32F10xxx . . . . . . . . . . . . . 1098

31.17.9 TPIU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1098

31.17.10 Example of configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1099

31.18 DBG register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1100

32 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1101

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List of tables

Table 1. Sections related to each STM32F10xxx product . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Table 2. Sections related to each peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 3. Register boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Table 4. Flash module organization (low-density devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Table 5. Flash module organization (medium-density devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Table 6. Flash module organization (high-density devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Table 7. Flash module organization (connectivity line devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Table 8. XL-density Flash module organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Table 9. Boot modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Table 10. CRC calculation unit register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Table 11. Low-power mode summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Table 12. Sleep-now. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Table 13. Sleep-on-exit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Table 14. Stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Table 15. Standby mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Table 16. PWR register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Table 17. BKP register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Table 18. RCC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

Table 19. RCC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

Table 20. Port bit configuration table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

Table 21. Output MODE bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

Table 22. Advanced timers TIM1/TIM8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

Table 23. General-purpose timers TIM2/3/4/5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

Table 24. USARTs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

Table 25. SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

Table 26. I2S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

Table 27. I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

Table 28. BxCAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

Table 29. USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

Table 30. OTG_FS pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

Table 31. SDIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

Table 32. FSMC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

Table 33. Other IOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

Table 34. CAN1 alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

Table 35. CAN2 alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

Table 36. Debug interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

Table 37. Debug port mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

Table 38. ADC1 external trigger injected conversion alternate function remapping. . . . . . . . . . . . . 177

Table 39. ADC1 external trigger regular conversion alternate function remapping . . . . . . . . . . . . . 177

Table 40. ADC2 external trigger injected conversion alternate function remapping. . . . . . . . . . . . . 177

Table 41. ADC2 external trigger regular conversion alternate function remapping . . . . . . . . . . . . . 178

Table 42. TIM5 alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178

Table 43. TIM4 alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178

Table 44. TIM3 alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178

Table 45. TIM2 alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179

Table 46. TIM1 alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179

Table 47. TIM9 remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179

Table 48. TIM10 remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179

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Table 49. TIM11 remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180

Table 50. TIM13 remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180

Table 51. TIM14 remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180

Table 52. USART3 remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180

Table 53. USART2 remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180

Table 54. USART1 remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181

Table 55. I2C1 remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181

Table 56. SPI1 remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181

Table 57. SPI3/I2S3 remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181

Table 58. ETH remapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182

Table 59. GPIO register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194

Table 60. AFIO register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194

Table 61. Vector table for connectivity line devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197

Table 62. Vector table for XL-density devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200

Table 63. Vector table for other STM32F10xxx devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203

Table 64. External interrupt/event controller register map and reset values. . . . . . . . . . . . . . . . . . . 213

Table 65. ADC pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217

Table 66. Analog watchdog channel selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220

Table 67. External trigger for regular channels for ADC1 and ADC2 . . . . . . . . . . . . . . . . . . . . . . . . 224

Table 68. External trigger for injected channels for ADC1 and ADC2 . . . . . . . . . . . . . . . . . . . . . . . 225

Table 69. External trigger for regular channels for ADC3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225

Table 70. External trigger for injected channels for ADC3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225

Table 71. ADC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235

Table 72. ADC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251

Table 73. DAC pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254

Table 74. External triggers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257

Table 75. DAC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272

Table 76. Programmable data width & endian behavior (when bits PINC = MINC = 1) . . . . . . . . . . 278

Table 77. DMA interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280

Table 78. Summary of DMA1 requests for each channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282

Table 79. Summary of DMA2 requests for each channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283

Table 80. DMA register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289

Table 81. Counting direction versus encoder signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325

Table 82. TIMx Internal trigger connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339

Table 83. Output control bits for complementary OCx and OCxN channels with

break feature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350

Table 84. TIM1&TIM8 register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358

Table 85. Counting direction versus encoder signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386

Table 86. TIMx Internal trigger connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401

Table 87. Output control bit for standard OCx channels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411

Table 88. TIMx register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416

Table 89. TIMx internal trigger connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439

Table 90. Output control bit for standard OCx channels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 448

Table 91. TIM9/12 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450

Table 92. Output control bit for standard OCx channels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457

Table 93. TIM10/11/13/14 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 459

Table 94. TIM6&TIM7 register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 472

Table 95. RTC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 484

Table 96. Min/max IWDG timeout period at 40 kHz (LSI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 486

Table 97. IWDG register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 490

Table 98. Min-max timeout value @36 MHz (f

) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494

PCLK1

Table 99. WWDG register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 497

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Table 100. NOR/PSRAM bank selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 502

Table 101. External memory address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 503

Table 102. Memory mapping and timing registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 503

Table 103. NAND bank selections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504

Table 104. Programmable NOR/PSRAM access parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 505

Table 105. Nonmultiplexed I/O NOR Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 505

Table 106. Multiplexed I/O NOR Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 506

Table 107. Nonmultiplexed I/Os PSRAM/SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 506

Table 108. NOR Flash/PSRAM controller: example of supported memories

and transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 507

Table 109. FSMC_BCRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510

Table 110. FSMC_BTRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510

Table 111. FSMC_BCRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 512

Table 112. FSMC_BTRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 512

Table 113. FSMC_BWTRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 513

Table 114. FSMC_BCRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 515

Table 115. FSMC_BTRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 515

Table 116. FSMC_BWTRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 516

Table 117. FSMC_BCRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 517

Table 118. FSMC_BTRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 518

Table 119. FSMC_BWTRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 518

Table 120. FSMC_BCRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 520

Table 121. FSMC_BTRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 520

Table 122. FSMC_BWTRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 521

Table 123. FSMC_BCRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 522

Table 124. FSMC_BTRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 523

Table 125. FSMC_BCRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 528

Table 126. FSMC_BTRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 529

Table 127. FSMC_BCRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 530

Table 128. FSMC_BTRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 531

Table 129. Programmable NAND/PC Card access parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 539

Table 130. 8-bit NAND Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 539

Table 131. 16-bit NAND Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 540

Table 132. 16-bit PC Card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 540

Table 133. Supported memories and transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 541

Table 134. 16-bit PC-Card signals and access type. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 546

Table 135. ECC result relevant bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 553

Table 136. FSMC register map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 554

Table 137. SDIO I/O definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 560

Table 138. Command format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 564

Table 139. Short response format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 565

Table 140. Long response format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 565

Table 141. Command path status flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 565

Table 142. Data token format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 568

Table 143. Transmit FIFO status flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 569

Table 144. Receive FIFO status flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 570

Table 145. Card status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 581

Table 146. SD status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 583

Table 147. Speed class code field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 585

Table 148. Performance move field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 585

Table 149. AU_SIZE field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 585

Table 150. Maximum AU size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 586

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RM0008 List of tables

Table 151. Erase size field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 586

Table 152. Erase timeout field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 586

Table 153. Erase offset field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 587

Table 154. Block-oriented write commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 589

Table 155. Block-oriented write protection commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 590

Table 156. Erase commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 590

Table 157. I/O mode commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 590

Table 158. Lock card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 591

Table 159. Application-specific commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 591

Table 160. R1 response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 592

Table 161. R2 response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 592

Table 162. R3 response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 593

Table 163. R4 response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 593

Table 164. R4b response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 593

Table 165. R5 response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 594

Table 166. R6 response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 594

Table 167. Response type and SDIO_RESPx registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 601

Table 168. SDIO register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 611

Table 169. Double-buffering buffer flag definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 623

Table 170. Bulk double-buffering memory buffers usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 624

Table 171. Isochronous memory buffers usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 625

Table 172. Resume event detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 627

Table 173. Reception status encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 638

Table 174. Endpoint type encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 638

Table 175. Endpoint kind meaning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 639

Table 176. Transmission status encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 639

Table 177. Definition of allocated buffer memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 643

Table 178. USB register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 643

Table 179. Transmit mailbox mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 660

Table 180. Receive mailbox mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 660

Table 181. bxCAN register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 686

Table 182. SPI interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 713

Table 183. Audio-frequency precision using standard 8 MHz HSE (high-density and XL-density

devices only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 724

Table 184. Audio-frequency precision using standard 25 MHz and PLL3

(connectivity line devices only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 725

Table 185. Audio-frequency precision using standard 14.7456 MHz and PLL3

(connectivity line devices only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 726

Table 186. I

S interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 732

Table 187. SPI register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 742

Table 188. SMBus vs. I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 759

Table 189. I2C Interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 763

Table 190. I2C register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 777

Table 191. Noise detection from sampled data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 790

Table 192. Error calculation for programmed baud rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 792

Table 193. USART receiver’s tolerance when DIV_Fraction is 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 793

Table 195. USART receiver’s tolerance when DIV_Fraction is different from 0 . . . . . . . . . . . . . . . . . 793

Table 197. Frame formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 795

Table 198. USART interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 809

Table 199. USART mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 810

Table 200. USART register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 820

Table 201. Core global control and status registers (CSRs). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 846

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List of tables RM0008

Table 202. Host-mode control and status registers (CSRs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 847

Table 203. Device-mode control and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 848

Table 204. Data FIFO (DFIFO) access register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 850

Table 205. Power and clock gating control and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 850

Table 206. Minimum duration for soft disconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 884

Table 207. OTG_FS register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 905

Table 208. Ethernet pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 961

Table 209. Management frame format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 963

Table 210. Clock range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 965

Table 211. TX interface signal encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 967

Table 212. RX interface signal encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 967

Table 213. Frame statuses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 983

Table 214. Destination address filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 989

Table 215. Source address filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 990

Table 216. Receive descriptor 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1018

Table 217. Ethernet register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1062

Table 218. SWJ debug port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1072

Table 219. Flexible SWJ-DP pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1073

Table 220. JTAG debug port data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1078

Table 221. 32-bit debug port registers addressed through the shifted value A[3:2] . . . . . . . . . . . . . 1080

Table 222. Packet request (8-bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1081

Table 223. ACK response (3 bits). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1081

Table 224. DATA transfer (33 bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1081

Table 225. SW-DP registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1082

Table 226. Cortex

-M3 AHB-AP registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1084

Table 227. Core debug registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1085

Table 228. Main ITM registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1088

Table 229. Main ETM registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1089

Table 230. Asynchronous TRACE pin assignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1095

Table 231. Synchronous TRACE pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1095

Table 232. Flexible TRACE pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1096

Table 233. Important TPIU registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1098

Table 234. DBG register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1100

Table 235. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1101

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RM0008 List of figures

List of figures

Figure 1. System architecture (low-, medium-, XL-density devices) . . . . . . . . . . . . . . . . . . . . . . . . . 48

Figure 2. System architecture in connectivity line devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Figure 3. CRC calculation unit block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Figure 4. Power supply overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Figure 5. Power on reset/power down reset waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Figure 6. PVD thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Figure 7. Simplified diagram of the reset circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Figure 8. Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Figure 9. HSE/ LSE clock sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Figure 10. Simplified diagram of the reset circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

Figure 11. Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

Figure 12. HSE/ LSE clock sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

Figure 13. Basic structure of a standard I/O port bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160

Figure 14. Basic structure of a five-volt tolerant I/O port bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160

Figure 15. Input floating/pull up/pull down configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

Figure 16. Output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

Figure 17. Alternate function configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

Figure 18. High impedance-analog configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

Figure 19. ADC / DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

Figure 20. External interrupt/event controller block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206

Figure 21. External interrupt/event GPIO mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208

Figure 22. Single ADC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216

Figure 23. Timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219

Figure 24. Analog watchdog guarded area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220

Figure 25. Injected conversion latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221

Figure 26. Calibration timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223

Figure 27. Right alignment of data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223

Figure 28. Left alignment of data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223

Figure 29. Dual ADC block diagram

Figure 30. Injected simultaneous mode on 4 channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229

Figure 31. Regular simultaneous mode on 16 channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230

Figure 32. Fast interleaved mode on 1 channel in continuous conversion mode . . . . . . . . . . . . . . . 230

Figure 33. Slow interleaved mode on 1 channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231

Figure 34. Alternate trigger: injected channel group of each ADC. . . . . . . . . . . . . . . . . . . . . . . . . . . 231

Figure 35. Alternate trigger: 4 injected channels (each ADC) in discontinuous model . . . . . . . . . . . 232

Figure 36. Alternate + Regular simultaneous. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233

Figure 37. Case of trigger occurring during injected conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233

Figure 38. Interleaved single channel with injected sequence CH11, CH12 . . . . . . . . . . . . . . . . . . . 233

Figure 39. Temperature sensor and VREFINT channel block diagram . . . . . . . . . . . . . . . . . . . . . . 234

Figure 40. DAC channel block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254

Figure 41. Data registers in single DAC channel mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256

Figure 42. Data registers in dual DAC channel mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256

Figure 43. Timing diagram for conversion with trigger disabled TEN = 0 . . . . . . . . . . . . . . . . . . . . . 257

Figure 44. DAC LFSR register calculation algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258

Figure 45. DAC conversion (SW trigger enabled) with LFSR wave generation. . . . . . . . . . . . . . . . . 259

Figure 46. DAC triangle wave generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259

Figure 47. DAC conversion (SW trigger enabled) with triangle wave generation . . . . . . . . . . . . . . . 260

Figure 48. DMA block diagram in connectivity line devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274

(1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228

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Figure 49. DMA block diagram in low-, medium- high- and XL-density devices . . . . . . . . . . . . . . . . 275

Figure 50. DMA1 request mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281

Figure 51. DMA2 request mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283

Figure 52. Advanced-control timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294

Figure 53. Counter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . . 296

Figure 54. Counter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . . 296

Figure 55. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297

Figure 56. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297

Figure 57. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298

Figure 58. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298

Figure 59. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded) . . . . . 298

Figure 60. Counter timing diagram, update event when ARPE=1

(TIMx_ARR preloaded) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299

Figure 61. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300

Figure 62. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300

Figure 63. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300

Figure 64. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301

Figure 65. Counter timing diagram, update event when repetition counter

is not used . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301

Figure 66. Counter timing diagram, internal clock divided by 1, TIMx_ARR = 0x6 . . . . . . . . . . . . . . 302

Figure 67. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303

Figure 68. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . . . . . . . . . . . 303

Figure 69. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303

Figure 70. Counter timing diagram, update event with ARPE=1 (counter underflow) . . . . . . . . . . . . 304

Figure 71. Counter timing diagram, Update event with ARPE=1 (counter overflow). . . . . . . . . . . . . 304

Figure 72. Update rate examples depending on mode and TIMx_RCR register settings . . . . . . . . . 305

Figure 73. Control circuit in normal mode, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . 306

Figure 74. TI2 external clock connection example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306

Figure 75. Control circuit in external clock mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307

Figure 76. External trigger input block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307

Figure 77. Control circuit in external clock mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308

Figure 78. Capture/compare channel (example: channel 1 input stage) . . . . . . . . . . . . . . . . . . . . . . 309

Figure 79. Capture/compare channel 1 main circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309

Figure 80. Output stage of capture/compare channel (channel 1 to 3) . . . . . . . . . . . . . . . . . . . . . . . 310

Figure 81. Output stage of capture/compare channel (channel 4). . . . . . . . . . . . . . . . . . . . . . . . . . . 310

Figure 82. PWM input mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312

Figure 83. Output compare mode, toggle on OC1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314

Figure 84. Edge-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315

Figure 85. Center-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316

Figure 86. Complementary output with dead-time insertion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317

Figure 87. Dead-time waveforms with delay greater than the negative pulse. . . . . . . . . . . . . . . . . . 317

Figure 88. Dead-time waveforms with delay greater than the positive pulse. . . . . . . . . . . . . . . . . . . 318

Figure 89. Output behavior in response to a break.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320

Figure 90. Clearing TIMx OCxREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321

Figure 91. 6-step generation, COM example (OSSR=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322

Figure 92. Example of one pulse mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323

Figure 93. Example of counter operation in encoder interface mode. . . . . . . . . . . . . . . . . . . . . . . . . 326

Figure 94. Example of encoder interface mode with TI1FP1 polarity inverted. . . . . . . . . . . . . . . . . . 326

Figure 95. Example of hall sensor interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328

Figure 96. Control circuit in reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329

Figure 97. Control circuit in gated mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330

Figure 98. Control circuit in trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331

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Figure 99. Control circuit in external clock mode 2 + trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . 332

Figure 100. General-purpose timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362

Figure 101. Counter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . . 363

Figure 102. Counter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . . 364

Figure 103. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365

Figure 104. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365

Figure 105. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365

Figure 106. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366

Figure 107. Counter timing diagram, Update event when ARPE=0 (TIMx_ARR not preloaded). . . . . 366

Figure 108. Counter timing diagram, Update event when ARPE=1 (TIMx_ARR preloaded). . . . . . . . 367

Figure 109. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368

Figure 110. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368

Figure 111. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368

Figure 112. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369

Figure 113. Counter timing diagram, Update event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369

Figure 114. Counter timing diagram, internal clock divided by 1, TIMx_ARR=0x6 . . . . . . . . . . . . . . . 370

Figure 115. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371

Figure 116. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . . . . . . . . . . . 371

Figure 117. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371

Figure 118. Counter timing diagram, Update event with ARPE=1 (counter underflow). . . . . . . . . . . . 372

Figure 119. Counter timing diagram, Update event with ARPE=1 (counter overflow) . . . . . . . . . . . . . 372

Figure 120. Control circuit in normal mode, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . 373

Figure 121. TI2 external clock connection example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373

Figure 122. Control circuit in external clock mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374

Figure 123. External trigger input block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374

Figure 124. Control circuit in external clock mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375

Figure 125. Capture/compare channel (example: channel 1 input stage) . . . . . . . . . . . . . . . . . . . . . . 375

Figure 126. Capture/compare channel 1 main circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376

Figure 127. Output stage of capture/compare channel (channel 1). . . . . . . . . . . . . . . . . . . . . . . . . . . 376

Figure 128. PWM input mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378

Figure 129. Output compare mode, toggle on OC1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380

Figure 130. Edge-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381

Figure 131. Center-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382

Figure 132. Example of one-pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383

Figure 133. Clearing TIMx OCxREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385

Figure 134. Example of counter operation in encoder interface mode . . . . . . . . . . . . . . . . . . . . . . . . 387

Figure 135. Example of encoder interface mode with TI1FP1 polarity inverted . . . . . . . . . . . . . . . . . 387

Figure 136. Control circuit in reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388

Figure 137. Control circuit in gated mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389

Figure 138. Control circuit in trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390

Figure 139. Control circuit in external clock mode 2 + trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . 391

Figure 140. Master/Slave timer example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391

Figure 141. Gating timer 2 with OC1REF of timer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392

Figure 142. Gating timer 2 with Enable of timer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393

Figure 143. Triggering timer 2 with update of timer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394

Figure 144. Triggering timer 2 with Enable of timer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394

Figure 145. Triggering timer 1 and 2 with timer 1 TI1 input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 396

Figure 146. General-purpose timer block diagram (TIM9 and TIM12) . . . . . . . . . . . . . . . . . . . . . . . . 419

Figure 147. General-purpose timer block diagram (TIM10/11/13/14) . . . . . . . . . . . . . . . . . . . . . . . . 420

Figure 148. Counter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . . 422

Figure 149. Counter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . . 422

Figure 150. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423

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Figure 151. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423

Figure 152. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 424

Figure 153. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 424

Figure 154. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not

preloaded). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 424

Figure 155. Counter timing diagram, update event when ARPE=1 (TIMx_ARR

preloaded). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425

Figure 156. Control circuit in normal mode, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . 426

Figure 157. TI2 external clock connection example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 426

Figure 158. Control circuit in external clock mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 427

Figure 159. Capture/compare channel (example: channel 1 input stage) . . . . . . . . . . . . . . . . . . . . . . 427

Figure 160. Capture/compare channel 1 main circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 428

Figure 161. Output stage of capture/compare channel (channel 1). . . . . . . . . . . . . . . . . . . . . . . . . . . 428

Figure 162. PWM input mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 430

Figure 163. Output compare mode, toggle on OC1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 432

Figure 164. Edge-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433

Figure 165. Example of one pulse mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433

Figure 166. Control circuit in reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435

Figure 167. Control circuit in gated mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 436

Figure 168. Control circuit in trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 436

Figure 169. Basic timer block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 462

Figure 170. Counter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . . 463

Figure 171. Counter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . . 463

Figure 172. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 464

Figure 173. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 465

Figure 174. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 465

Figure 175. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 465

Figure 176. Counter timing diagram, update event when ARPE = 0 (TIMx_ARR not

preloaded). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 466

Figure 177. Counter timing diagram, update event when ARPE=1 (TIMx_ARR

preloaded). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 466

Figure 178. Control circuit in normal mode, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . 467

Figure 179. RTC simplified block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 475

Figure 180. RTC second and alarm waveform example with PR=0003, ALARM=00004 . . . . . . . . . . 477

Figure 181. RTC Overflow waveform example with PR=0003. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 477

Figure 182. Independent watchdog block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 486

Figure 183. Watchdog block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 492

Figure 184. Window watchdog timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 493

Figure 185. FSMC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500

Figure 186. FSMC memory banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 502

Figure 187. Mode1 read accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 509

Figure 188. Mode1 write accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 509

Figure 189. ModeA read accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 511

Figure 190. ModeA write accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 511

Figure 191. Mode2 and mode B read accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 513

Figure 192. Mode2 write accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 514

Figure 193. Mode B write accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 514

Figure 194. Mode C read accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 516

Figure 195. Mode C write accesses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 517

Figure 196. Mode D read accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 519

Figure 197. Multiplexed read accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 521

Figure 198. Multiplexed write accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 522

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Figure 199. Asynchronous wait during a read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 524

Figure 200. Asynchronous wait during a write access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 525

Figure 201. Wait configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 527

Figure 202. Synchronous multiplexed read mode - NOR, PSRAM (CRAM) . . . . . . . . . . . . . . . . . . . . 528

Figure 203. Synchronous multiplexed write mode - PSRAM (CRAM) . . . . . . . . . . . . . . . . . . . . . . . . . 530

Figure 204. NAND/PC Card controller timing for common memory access . . . . . . . . . . . . . . . . . . . 542

Figure 205. Access to non ‘CE don’t care’ NAND-Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 543

Figure 206. SDIO “no response” and “no data” operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 557

Figure 207. SDIO (multiple) block read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 557

Figure 208. SDIO (multiple) block write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 558

Figure 209. SDIO sequential read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 558

Figure 210. SDIO sequential write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 558

Figure 211. SDIO block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 559

Figure 212. SDIO adapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 560

Figure 213. Control unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 561

Figure 214. SDIO adapter command path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 562

Figure 215. Command path state machine (CPSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 563

Figure 216. SDIO command transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 564

Figure 217. Data path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 566

Figure 218. Data path state machine (DPSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 567

Figure 219. USB peripheral block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 614

Figure 220. Packet buffer areas with examples of buffer description table locations . . . . . . . . . . . . . 618

Figure 221. CAN network topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 647

Figure 222. Dual CAN block diagram (connectivity devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 648

Figure 223. bxCAN operating modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 650

Figure 224. bxCAN in silent mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 651

Figure 225. bxCAN in loop back mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 651

Figure 226. bxCAN in combined mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 652

Figure 227. Transmit mailbox states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 653

Figure 228. Receive FIFO states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 654

Figure 229. Filter bank scale configuration - register organization . . . . . . . . . . . . . . . . . . . . . . . . . . . 657

Figure 230. Example of filter numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 658

Figure 231. Filtering mechanism - example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 659

Figure 232. CAN error state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 660

Figure 233. Bit timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 662

Figure 234. CAN frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 663

Figure 235. Event flags and interrupt generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 664

Figure 236. RX and TX mailboxes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 675

Figure 237. SPI block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 693

Figure 238. Single master/ single slave application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 694

Figure 239. Data clock timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 696

Figure 240. TXE/RXNE/BSY behavior in Master / full-duplex mode (BIDIMODE=0 and

RXONLY=0) in the case of continuous transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 702

Figure 241. TXE/RXNE/BSY behavior in Slave / full-duplex mode (BIDIMODE=0,

RXONLY=0) in the case of continuous transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 702

Figure 242. TXE/BSY behavior in Master transmit-only mode (BIDIMODE=0 and RXONLY=0) in

case of continuous transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 703

Figure 243. TXE/BSY in Slave transmit-only mode (BIDIMODE=0 and RXONLY=0) in the case of

continuous transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 704

Figure 244. RXNE behavior in receive-only mode (BIDIRMODE=0 and RXONLY=1) in the case of

continuous transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 705

Figure 245. TXE/BSY behavior when transmitting (BIDIRMODE=0 and RXONLY=0) in the case of

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List of figures RM0008

discontinuous transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 706

Figure 246. Transmission using DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 711

Figure 247. Reception using DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 711

Figure 248. I Figure 249. I Figure 250. I

S block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 714

S Philips protocol waveforms (16/32-bit full accuracy, CPOL = 0) . . . . . . . . . . . . . . . . . 716

S Philips standard waveforms (24-bit frame with CPOL = 0) . . . . . . . . . . . . . . . . . . . . . 716

Figure 251. Transmitting 0x8EAA33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 717

Figure 252. Receiving 0x8EAA33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 717

Figure 253. I

S Philips standard (16-bit extended to 32-bit packet frame with CPOL = 0) . . . . . . . . . 717

Figure 254. Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 718

Figure 255. MSB Justified 16-bit or 32-bit full-accuracy length with CPOL = 0 . . . . . . . . . . . . . . . . . . 718

Figure 256. MSB Justified 24-bit frame length with CPOL = 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 719

Figure 257. MSB Justified 16-bit extended to 32-bit packet frame with CPOL = 0 . . . . . . . . . . . . . . . 719

Figure 258. LSB justified 16-bit or 32-bit full-accuracy with CPOL = 0 . . . . . . . . . . . . . . . . . . . . . . . . 719

Figure 259. LSB Justified 24-bit frame length with CPOL = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 720

Figure 260. Operations required to transmit 0x3478AE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 720

Figure 261. Operations required to receive 0x3478AE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 720

Figure 262. LSB justified 16-bit extended to 32-bit packet frame with CPOL = 0 . . . . . . . . . . . . . . . . 721

Figure 263. Example of LSB justified 16-bit extended to 32-bit packet frame . . . . . . . . . . . . . . . . . . . 721

Figure 264. PCM standard waveforms (16-bit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 722

Figure 265. PCM standard waveforms (16-bit extended to 32-bit packet frame). . . . . . . . . . . . . . . . . 722

Figure 266. Audio sampling frequency definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 723

Figure 267. I

S clock generator architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 723

Figure 268. I2C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 745

Figure 269. I2C block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 746

Figure 270. Transfer sequence diagram for slave transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 748

Figure 271. Transfer sequence diagram for slave receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 749

Figure 272. Transfer sequence diagram for master transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 752

Figure 273. Method 1: transfer sequence diagram for master receiver . . . . . . . . . . . . . . . . . . . . . . . 754

Figure 274. Method 2: transfer sequence diagram for master receiver when N>2 . . . . . . . . . . . . . . . 755

Figure 275. Method 2: transfer sequence diagram for master receiver when N=2 . . . . . . . . . . . . . . . 756

Figure 276. Method 2: transfer sequence diagram for master receiver when N=1 . . . . . . . . . . . . . . . 757

Figure 277. I2C interrupt mapping diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 764

Figure 278. USART block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 782

Figure 279. Word length programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 783

Figure 280. Configurable stop bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 785

Figure 281. TC/TXE behavior when transmitting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 786

Figure 282. Start bit detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 787

Figure 283. Data sampling for noise detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 789

Figure 284. Mute mode using Idle line detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 794

Figure 285. Mute mode using address mark detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 795

Figure 286. Break detection in LIN mode (11-bit break length - LBDL bit is set) . . . . . . . . . . . . . . . . . 797

Figure 287. Break detection in LIN mode vs. Framing error detection. . . . . . . . . . . . . . . . . . . . . . . . . 798

Figure 288. USART example of synchronous transmission. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 799

Figure 289. USART data clock timing diagram (M=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 799

Figure 290. USART data clock timing diagram (M=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 800

Figure 291. RX data setup/hold time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 800

Figure 292. ISO 7816-3 asynchronous protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 801

Figure 293. Parity error detection using the 1.5 stop bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 803

Figure 294. IrDA SIR ENDEC- block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 805

Figure 295. IrDA data modulation (3/16) -normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 805

Figure 296. Transmission using DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 806

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RM0008 List of figures

Figure 297. Reception using DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 807

Figure 298. Hardware flow control between two USARTs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 808

Figure 299. RTS flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 808

Figure 300. CTS flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 809

Figure 301. USART interrupt mapping diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 810

Figure 302. OTG full-speed block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 824

Figure 303. OTG A-B device connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 825

Figure 304. USB peripheral-only connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 827

Figure 305. USB host-only connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 832

Figure 306. SOF connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 836

Figure 307. Updating OTG_FS_HFIR dynamically . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 838

Figure 308. Device-mode FIFO address mapping and AHB FIFO access mapping . . . . . . . . . . . . . . 839

Figure 309. Host-mode FIFO address mapping and AHB FIFO access mapping . . . . . . . . . . . . . . . . 840

Figure 310. Interrupt hierarchy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 844

Figure 311. CSR memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 846

Figure 312. Transmit FIFO write task . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 915

Figure 313. Receive FIFO read task . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 916

Figure 314. Normal bulk/control OUT/SETUP and bulk/control IN transactions . . . . . . . . . . . . . . . . . 918

Figure 315. Bulk/control IN transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 921

Figure 316. Normal interrupt OUT/IN transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 923

Figure 317. Normal isochronous OUT/IN transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 928

Figure 318. Receive FIFO packet read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 934

Figure 319. Processing a SETUP packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 936

Figure 320. Bulk OUT transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 942

Figure 321. TRDT max timing case . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 951

Figure 322. A-device SRP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 952

Figure 323. B-device SRP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 953

Figure 324. A-device HNP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 954

Figure 325. B-device HNP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 956

Figure 326. ETH block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 962

Figure 327. SMI interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 963

Figure 328. MDIO timing and frame structure - Write cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 964

Figure 329. MDIO timing and frame structure - Read cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 965

Figure 330. Media independent interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 966

Figure 331. MII clock sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 968

Figure 332. Reduced media-independent interface signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 968

Figure 333. RMII clock sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 969

Figure 334. Clock scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 969

Figure 335. Address field format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 971

Figure 336. MAC frame format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 973

Figure 337. Tagged MAC frame format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 973

Figure 338. Transmission bit order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 980

Figure 339. Transmission with no collision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 980

Figure 340. Transmission with collision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 981

Figure 341. Frame transmission in MMI and RMII modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 981

Figure 342. Receive bit order. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 985

Figure 343. Reception with no error. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 986

Figure 344. Reception with errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 986

Figure 345. Reception with false carrier indication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 986

Figure 346. MAC core interrupt masking scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 987

Figure 347. Wakeup frame filter register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 992

Figure 348. Networked time synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 995

DocID13902 Rev 15 38/1128

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List of figures RM0008

Figure 349. System time update using the Fine correction method. . . . . . . . . . . . . . . . . . . . . . . . . . . 997

Figure 350. PTP trigger output to TIM2 ITR1 connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 999

Figure 351. PPS output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000

Figure 352. Descriptor ring and chain structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1001

Figure 353. TxDMA operation in Default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1005

Figure 354. TxDMA operation in OSF mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1007

Figure 355. ransmit descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1008

Figure 356. Receive DMA operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1014

Figure 357. Rx DMA descriptor structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1016

Figure 358. Interrupt scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1021

Figure 359. Ethernet MAC remote wakeup frame filter register (ETH_MACRWUFFR). . . . . . . . . . . 1031

Figure 360. Block diagram of STM32 MCU and Cortex

-M3-level

debug support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1069

Figure 361. SWJ debug port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1070

Figure 362. JTAG TAP connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1075

Figure 363. TPIU block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1094

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RM0008 Overview of the manual

1 Overview of the manual

Legend for Tabl e 1:

The section in each row applies to products in columns marked with “

Section 2: Documentation conventions

Section 3: Memory and bus architecture

Section 4: CRC calculation unit

Table 1. Sections related to each STM32F10xxx product

•"

Low-density STM32F101xx

STM32F105xx

Medium-density STM32F101xx

High and XL-density STM32F101x

Low-density STM32F102xx

Medium-density STM32F102xx

Low-density STM32F103xx

Medium-density STM32F103xx

High and XL-density STM32F103xx

STM32F107xx

••••••••••

Section 5: Power control (PWR)

Section 6: Backup registers (BKP)

Section 7: Low-, medium-, high- and XL-density reset and clock control (RCC)

Section 8: Connectivity line devices: reset and clock control (RCC)

Section 9: Generalpurpose and alternatefunction I/Os (GPIOs and AFIOs)

Section 10: Interrupts and events

Section 13: Direct memory access controller (DMA)

••••••••••

••••••••

••

••••••••••

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Overview of the manual RM0008

Table 1. Sections related to each STM32F10xxx product (continued)

Section 11: Analog-todigital converter (ADC)

Section 12: Digital-toanalog converter (DAC)

Section 14: Advancedcontrol timers (TIM1&TIM8)

Section 15: Generalpurpose timers (TIM2 to TIM5)

Section 16: Generalpurpose timers (TIM9 to TIM14)

Section 17: Basic timers (TIM6&TIM7)

Section 18: Real-time clock (RTC)

Low-density STM32F101xx

Medium-density STM32F101xx

STM32F105xx

Low-density STM32F102xx

High and XL-density STM32F101x

Medium-density STM32F102xx

Low-density STM32F103xx

Medium-density STM32F103xx

High and XL-density STM32F103xx

STM32F107xx

••••••••••

• •••

• •••••

••••••••••

•

(1)

•

(1)

• •••

••••••••••

Section 19: Independent watchdog (IWDG)

Section 20: Window watchdog (WWDG)

Section 21: Flexible static memory controller (FSMC)

Section 1: Secure digital input/output interface (SDIO)

Section 23: Universal serial bus full-speed device interface (USB)

41/1128 DocID13902 Rev 15

••••••••••

··

·····

Page 42

RM0008 Overview of the manual

Table 1. Sections related to each STM32F10xxx product (continued)

Section 24: Controller area network (bxCAN)

Section 25: Serial peripheral interface (SPI)

Section 26: Interintegrated circuit (I2C) interface

Section 27: Universal synchronous asynchronous receiver transmitter (USART)

Section 28: USB on-thego full-speed (OTG_FS)

Section 29: Ethernet (ETH): media access control (MAC) with DMA controller

Low-density STM32F101xx

Medium-density STM32F101xx

STM32F105xx

Low-density STM32F102xx

High and XL-density STM32F101x

Medium-density STM32F102xx

Low-density STM32F103xx

·····

Medium-density STM32F103xx

High and XL-density STM32F103xx

STM32F107xx

••••••••••

··

Section 30: Device electronic signature

Section 31: Debug support (DBG)

••••••••••

Note: Available only on XL-density devices.

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Overview of the manual RM0008

Legend for Tabl e 2:

•

The section in this row must be read when using the peripherals in columns marked with “

•"



The section in this row can optionally be read when using the peripherals in columns marked with

“"

Table 2. Sections related to each peripheral

USART

Backup registers (BKP)

General-purpose I/Os (GPIOs)

Digital-to-analog converter (DAC)

Analog-to-digital converter (ADC)

Advanced-control timers (TIM1&TIM8)

General-purpose timers (TIM2 to TIM5)

General-purpose timers (TIM9 to TIM14)

Basic timers (TIM6&TIM7)

Real-time clock (RTC)

Independent watchdog (IWDG)

Window watchdog (WWDG)

Flexible static memory controller (FSMC)

Secure digital input/output interface (SDIO)

USB full-speed device (USB)

Controller area network (bxCAN)

Serial peripheral interface (SPI)

Inter-integrated circuit (I2C) interface

USB on-the-go full-speed (OTG_FS)

Ethernet (ETH)

Section 2: Documentation conventions

Section 3: Memory and bus architecture

Section 4: CRC calculation unit

Section 5: Power control (PWR)

Section 6: Backup registers (BKP)

Section 7: Low-, medium-, high- and XLdensity reset and clock control (RCC)

Section 8: Connectivity line devices: reset and clock control (RCC)

••••••••• •••••••••••

•••••••••••••••••••·

• 

••••••••• •••••••••••

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RM0008 Overview of the manual

Table 2. Sections related to each peripheral (continued)

USART

Backup registers (BKP)

General-purpose I/Os (GPIOs)

Digital-to-analog converter (DAC)

Analog-to-digital converter (ADC)

Advanced-control timers (TIM1&TIM8)

General-purpose timers (TIM2 to TIM5)

General-purpose timers (TIM9 to TIM14)

Real-time clock (RTC)

Basic timers (TIM6&TIM7)

Window watchdog (WWDG)

Independent watchdog (IWDG)

Flexible static memory controller (FSMC)

USB full-speed device (USB)

Controller area network (bxCAN)

Secure digital input/output interface (SDIO)

Serial peripheral interface (SPI)

Inter-integrated circuit (I2C) interface

USB on-the-go full-speed (OTG_FS)

Ethernet (ETH)

Section 9: Generalpurpose and alternatefunction I/Os (GPIOs and AFIOs)

Section 10: Interrupts and events

Section 13: Direct memory access controller (DMA)

Section 11: Analog-todigital converter (ADC)

Section 12: Digital-toanalog converter (DAC)

Section 14: Advancedcontrol timers (TIM1&TIM8)

Section 15: Generalpurpose timers (TIM2 to TIM5)

Section 16: Generalpurpose timers (TIM9 to TIM14)

 •••••• à •••••••••••

 

    

·

 ·

Section 17: Basic timers (TIM6&TIM7)

Section 18: Real-time clock (RTC)

 ·

··

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Overview of the manual RM0008

Table 2. Sections related to each peripheral (continued)

USART

Backup registers (BKP)

General-purpose I/Os (GPIOs)

Digital-to-analog converter (DAC)

Analog-to-digital converter (ADC)

Advanced-control timers (TIM1&TIM8)

General-purpose timers (TIM2 to TIM5)

General-purpose timers (TIM9 to TIM14)

Real-time clock (RTC)

Basic timers (TIM6&TIM7)

Window watchdog (WWDG)

Independent watchdog (IWDG)

Flexible static memory controller (FSMC)

USB full-speed device (USB)

Controller area network (bxCAN)

Secure digital input/output interface (SDIO)

Serial peripheral interface (SPI)

Inter-integrated circuit (I2C) interface

USB on-the-go full-speed (OTG_FS)

Ethernet (ETH)

Section 19: Independent watchdog (IWDG)

Section 20: Window watchdog (WWDG)

Section 21: Flexible static memory controller (FSMC)

Section 1: Secure digital input/output interface (SDIO)

Section 23: Universal serial bus full-speed device interface (USB)

Section 24: Controller area network (bxCAN)

Section 25: Serial peripheral interface (SPI)

Section 26: Interintegrated circuit (I2C) interface

Section 27: Universal synchronous asynchronous receiver transmitter (USART)

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RM0008 Overview of the manual

Table 2. Sections related to each peripheral (continued)

USART

Backup registers (BKP)

General-purpose I/Os (GPIOs)

Digital-to-analog converter (DAC)

Analog-to-digital converter (ADC)

Advanced-control timers (TIM1&TIM8)

General-purpose timers (TIM2 to TIM5)

General-purpose timers (TIM9 to TIM14)

Real-time clock (RTC)

Basic timers (TIM6&TIM7)

Window watchdog (WWDG)

Independent watchdog (IWDG)

Flexible static memory controller (FSMC)

USB full-speed device (USB)

Controller area network (bxCAN)

Secure digital input/output interface (SDIO)

Serial peripheral interface (SPI)

Inter-integrated circuit (I2C) interface

USB on-the-go full-speed (OTG_FS)

Ethernet (ETH)

Section 28: USB onthe-go full-speed (OTG_FS)

Section 29: Ethernet (ETH): media access control (MAC) with DMA controller

Section 30: Device electronic signature

Section 31: Debug support (DBG)



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Documentation conventions RM0008

2 Documentation conventions

2.1 List of abbreviations for registers

The following abbreviations are used in register descriptions:

read/write (rw) Software can read and write to these bits.

read-only (r) Software can only read these bits.

write-only (w) Software can only write to this bit. Reading the bit returns the reset value.

read/clear (rc_w1) Software can read as well as clear this bit by writing 1. Writing ‘0’ has no effect on

the bit value.

read/clear (rc_w0) Software can read as well as clear this bit by writing 0. Writing ‘1’ has no effect on

the bit value.

read/clear by read (rc_r)

read/set (rs) Software can read as well as set this bit. Writing ‘0’ has no effect on the bit value.

read-only write trigger (rt_w)

toggle (t) Software can only toggle this bit by writing ‘1’. Writing ‘0’ has no effect.

Reserved (Res.) Reserved bit, must be kept at reset value.

Software can read this bit. Reading this bit automatically clears it to ‘0’. Writing ‘0’ has no effect on the bit value.

Software can read this bit. Writing ‘0’ or ‘1’ triggers an event but has no effect on the bit value.

2.2 Glossary

• Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx

microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.

• Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx

microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.

• High-density devices are STM32F101xx and STM32F103xx microcontrollers where

the Flash memory density ranges between 256 and 512 Kbytes.

• XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the

Flash memory density ranges between 768 Kbytes and 1 Mbyte.

• Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.

• Word: data of 32-bit length.

• Half-word: data of 16-bit length.

• Byte: data of 8-bit length.

2.3 Peripheral availability

For peripheral availability and number across all STM32F10xxx sales types, please refer to

the low-, medium-, high- and XL-density STM32F101xx and STM32F103xx datasheets, to

the low- and medium-density STM32F102xx datasheets and to the connectivity line devices,

STM32F105xx/STM32F107xx.

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RM0008 Memory and bus architecture

FLITF

Ch.1

Ch.2

Ch.7

Cor tex-M3

DMA1

ICode

DCode

System

AHB system bus

DMA Request

APB 1

Flash

Bridge 2

Bridge 1

Ch.1

Ch.2

Ch.5

DMA2

SRAM

FSMC

SDIO

APB2

DMA request

ADC3

GPIOC

USART1

TIM8

SPI1 TIM1

ADC2

ADC1

GPIOG

GPIOF

GPIOE

GPIOD

GPIOB

GPIOA

EXTI

AFIO

DAC SPI3/I2S

TIM2

PWR BKP bxCAN USB I2C2 I2C1 UART5 UART4 USART3 USART2

SPI2/I2S

IWDG

WWDG

RTC TIM7 TIM6 TIM5 TIM4 TIM3

ai14800c

Bus matrix

DMA

Reset & clock control (RCC)

3 Memory and bus architecture

3.1 System architecture

In low-, medium-, high- and XL-density devices, the main system consists of:

• Four masters:

–Cortex

– GP-DMA1 & 2 (general-purpose DMA)

• Four slaves:

– Internal SRAM

– Internal Flash memory

–FSMC

– AHB to APBx (APB1 or APB2), which connect all the APB peripherals

These are interconnected using a multilayer AHB bus architecture as shown in Figure 1:

-M3 core DCode bus (D-bus) and System bus (S-bus)

Figure 1. System architecture (low-, medium-, XL-density devices)

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Memory and bus architecture RM0008

FLITF

Ch.1

Ch.2

Ch.7

Cor tex-M3

DMA1

ICode

DCode

System

DMA request

APB 1

Flash

Bridge 2

Bridge 1

Ch.1

Ch.2

Ch.5

DMA2

SRAM

APB2

GPIOC

USART1

SPI1 TIM1

ADC2

ADC1

GPIOE

GPIOD

GPIOB

GPIOA

EXTI

AFIO

DAC

SPI3/I2S

TIM2

PWR BKP CAN1 CAN2

I2C2 I2C1 UART5 UART4 USART3 USART2

SPI2/I2S

IWDG

WWDG

RTC TIM7 TIM6 TIM5 TIM4 TIM3

ai15810

Bus matrix

DMA

Reset & clock control (RCC)

USB OTG FS

AHB system bus

Ethernet MAC

DMA

DMA request

In connectivity line devices the main system consists of:

• Five masters:

–Cortex

-M3 core DCode bus (D-bus) and System bus (S-bus)

– GP-DMA1 & 2 (general-purpose DMA)

– Ethernet DMA

• Three slaves:

– Internal SRAM

– Internal Flash memory

– AHB to APB bridges (AHB to APBx), which connect all the APB peripherals

These are interconnected using a multilayer AHB bus architecture as shown in Figure 2:

Figure 2. System architecture in connectivity line devices

ICode bus

This bus connects the Instruction bus of the Cortex®-M3 core to the Flash memory instruction interface. Prefetching is performed on this bus.

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RM0008 Memory and bus architecture

DCode bus

This bus connects the DCode bus (literal load and debug access) of the Cortex®-M3 core to the Flash memory Data interface.

System bus

This bus connects the system bus of the Cortex®-M3 core (peripherals bus) to a BusMatrix which manages the arbitration between the core and the DMA.

DMA bus

This bus connects the AHB master interface of the DMA to the BusMatrix which manages the access of CPU DCode and DMA to SRAM, Flash memory and peripherals.

BusMatrix

The BusMatrix manages the access arbitration between the core system bus and the DMA master bus. The arbitration uses a Round Robin algorithm. In connectivity line devices, the BusMatrix is composed of five masters (CPU DCode, System bus, Ethernet DMA, DMA1 and DMA2 bus) and three slaves (FLITF, SRAM and AHB2APB bridges). In other devices, the BusMatrix is composed of four masters (CPU DCode, System bus, DMA1 bus and DMA2 bus) and four slaves (FLITF, SRAM, FSMC and AHB2APB bridges).

AHB peripherals are connected on system bus through a BusMatrix to allow DMA access.

AHB/APB bridges (APB)

The two AHB/APB bridges provide full synchronous connections between the AHB and the 2 APB buses. APB1 is limited to 36 MHz, APB2 operates at full speed (up to 72 MHz depending on the device).

Refer to Table 3 on page 51 for the address mapping of the peripherals connected to each bridge.

After each device reset, all peripheral clocks are disabled (except for the SRAM and FLITF). Before using a peripheral you have to enable its clock in the RCC_AHBENR, RCC_APB2ENR or RCC_APB1ENR register.

Note: When a 16- or 8-bit access is performed on an APB register, the access is transformed into

a 32-bit access: the bridge duplicates the 16- or 8-bit data to feed the 32-bit vector.

3.2 Memory organization

Program memory, data memory, registers and I/O ports are organized within the same linear 4-Gbyte address space.

The bytes are coded in memory in Little Endian format. The lowest numbered byte in a word is considered the word’s least significant byte and the highest numbered byte the most significant.

For the detailed mapping of peripheral registers, please refer to the related chapters.

The addressable memory space is divided into 8 main blocks, each of 512 MB.

All the memory areas that are not allocated to on-chip memories and peripherals are considered “Reserved”). Refer to the Memory map figure in the corresponding product datasheet.

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Memory and bus architecture RM0008

3.3 Memory map

See the datasheet corresponding to your device for a comprehensive diagram of the memory map. Tab le 3 gives the boundary addresses of the peripherals available in all STM32F10xxx devices.

Boundary address Peripheral Bus Register map

Table 3. Register boundary addresses

0xA000 0000 - 0xA000 0FFF FSMC

0x5000 0000 - 0x5003 FFFF USB OTG FS Section 28.16.6 on page 905

0x4003 0000 - 0x4FFF FFFF Reserved

0x4002 8000 - 0x4002 9FFF Ethernet Section 29.8.5 on page 1061

0x4002 3400 - 0x4002 7FFF Reserved

0x4002 3000 - 0x4002 33FF CRC Section 4.4.4 on page 66

0x4002 2000 - 0x4002 23FF Flash memory interface

AHB

0x4002 1400 - 0x4002 1FFF Reserved

0x4002 1000 - 0x4002 13FF Reset and clock control RCC Section 7.3.11 on page 121

0x4002 0800 - 0x4002 0FFF Reserved

0x4002 0400 - 0x4002 07FF DMA2 Section 13.4.7 on page 289

0x4002 0000 - 0x4002 03FF DMA1 Section 13.4.7 on page 289

0x4001 8400 - 0x4001 FFFF Reserved

0x4001 8000 - 0x4001 83FF SDIO Section 1.9.16 on page 656

Section 21.6.9 on page 554

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RM0008 Memory and bus architecture

Table 3. Register boundary addresses (continued)

Boundary address Peripheral Bus Register map

0x4001 5800 - 0x4001 7FFF Reserved

0x4001 5400 - 0x4001 57FF TIM11 timer Section 16.5.10 on page 459

0x4001 5000 - 0x4001 53FF TIM10 timer Section 16.5.10 on page 459

0x4001 4C00 - 0x4001 4FFF TIM9 timer Section 16.4.13 on page 449

0x4001 4000 - 0x4001 4BFF Reserved

0x4001 3C00 - 0x4001 3FFF ADC3 Section 11.12.15 on page 251

0x4001 3800 - 0x4001 3BFF USART1 Section 27.6.8 on page 820

0x4001 3400 - 0x4001 37FF TIM8 timer Section 14.4.21 on page 358

0x4001 3000 - 0x4001 33FF SPI1 Section 25.5 on page 733

0x4001 2C00 - 0x4001 2FFF TIM1 timer Section 14.4.21 on page 358

0x4001 2800 - 0x4001 2BFF ADC2 Section 11.12.15 on page 251

APB2

0x4001 2400 - 0x4001 27FF ADC1 Section 11.12.15 on page 251

0x4001 2000 - 0x4001 23FF GPIO Port G Section 9.5 on page 194

0x4001 1C00 - 0x4001 1FFF GPIO Port F Section 9.5 on page 194

0x4001 1800 - 0x4001 1BFF GPIO Port E Section 9.5 on page 194

0x4001 1400 - 0x4001 17FF GPIO Port D Section 9.5 on page 194

0x4001 1000 - 0x4001 13FF GPIO Port C Section 9.5 on page 194

0x4001 0C00 - 0x4001 0FFF GPIO Port B Section 9.5 on page 194

0x4001 0800 - 0x4001 0BFF GPIO Port A Section 9.5 on page 194

0x4001 0400 - 0x4001 07FF EXTI Section 10.3.7 on page 213

0x4001 0000 - 0x4001 03FF AFIO Section 9.5 on page 194

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Memory and bus architecture RM0008

Table 3. Register boundary addresses (continued)

Boundary address Peripheral Bus Register map

0x4000 7800 - 0x4000 FFFF Reserved

0x4000 7400 - 0x4000 77FF DAC Section 12.5.14 on page 272

0x4000 7000 - 0x4000 73FF Power control PWR Section 5.4.3 on page 80

0x4000 6C00 - 0x4000 6FFF Backup registers (BKP) Section 6.4.5 on page 85

0x4000 6400 - 0x4000 67FF bxCAN1 Section 24.9.5 on page 686

0x4000 6800 - 0x4000 6BFF bxCAN2 Section 24.9.5 on page 686

(1)

0x4000 6000

0x4000 5C00 - 0x4000 5FFF USB device FS registers Section 23.5.4 on page 643

0x4000 5800 - 0x4000 5BFF I2C2 Section 26.6.10 on page 777

0x4000 5400 - 0x4000 57FF I2C1 Section 26.6.10 on page 777

0x4000 5000 - 0x4000 53FF UART5 Section 27.6.8 on page 820

0x4000 4C00 - 0x4000 4FFF UART4 Section 27.6.8 on page 820

0x4000 4800 - 0x4000 4BFF USART3 Section 27.6.8 on page 820

0x4000 4400 - 0x4000 47FF USART2 Section 27.6.8 on page 820

0x4000 4000 - 0x4000 43FF Reserved

- 0x4000 63FF Shared USB/CAN SRAM 512 bytes

0x4000 3C00 - 0x4000 3FFF SPI3/I2S Section 25.5 on page 733

APB1

0x4000 3800 - 0x4000 3BFF SPI2/I2S Section 25.5 on page 733

0x4000 3400 - 0x4000 37FF Reserved

0x4000 3000 - 0x4000 33FF Independent watchdog (IWDG) Section 19.4.5 on page 490

0x4000 2C00 - 0x4000 2FFF Window watchdog (WWDG) Section 20.6.4 on page 497

0x4000 2800 - 0x4000 2BFF RTC Section 18.4.7 on page 484

0x4000 2400 - 0x4000 27FF Reserved

0x4000 2000 - 0x4000 23FF TIM14 timer Section 16.5.10 on page 459

0x4000 1C00 - 0x4000 1FFF TIM13 timer Section 16.5.10 on page 459

0x4000 1800 - 0x4000 1BFF TIM12 timer Section 16.4.13 on page 449

0x4000 1400 - 0x4000 17FF TIM7 timer Section 17.4.9 on page 472

0x4000 1000 - 0x4000 13FF TIM6 timer Section 17.4.9 on page 472

0x4000 0C00 - 0x4000 0FFF TIM5 timer Section 15.4.19 on page 416

0x4000 0800 - 0x4000 0BFF TIM4 timer Section 15.4.19 on page 416

0x4000 0400 - 0x4000 07FF TIM3 timer Section 15.4.19 on page 416

0x4000 0000 - 0x4000 03FF TIM2 timer Section 15.4.19 on page 416

1. This shared SRAM can be fully accessed only in low-, medium-, high- and XL-density devices, not in connectivity line devices.

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RM0008 Memory and bus architecture

3.3.1 Embedded SRAM

The STM32F10xxx features up to 96 Kbytes of static SRAM. It can be accessed as bytes, half-words (16 bits) or full words (32 bits). The SRAM start address is 0x2000 0000.

3.3.2 Bit banding

The Cortex®-M3 memory map includes two bit-band regions. These regions map each word in an alias region of memory to a bit in a bit-band region of memory. Writing to a word in the alias region has the same effect as a read-modify-write operation on the targeted bit in the bit-band region.

In the STM32F10xxx both peripheral registers and SRAM are mapped in a bit-band region. This allows single bit-band write and read operations to be performed. The operations are only available for Cortex

A mapping formula shows how to reference each word in the alias region to a corresponding bit in the bit-band region. The mapping formula is:

bit_word_addr = bit_band_base + (byte_offset x 32) + (bit_number × 4)

where:

bit_word_addr is the address of the word in the alias memory region that maps to the targeted bit.

bit_band_base is the starting address of the alias region

byte_offset is the number of the byte in the bit-band region that contains the targeted

bit

bit_number is the bit position (0-7) of the targeted bit.

-M3 accesses, not from other bus masters (e.g. DMA).

Example:

The following example shows how to map bit 2 of the byte located at SRAM address 0x20000300 in the alias region:

0x22006008 = 0x22000000 + (0x300*32) + (2*4).

Writing to address 0x22006008 has the same effect as a read-modify-write operation on bit 2 of the byte at SRAM address 0x20000300.

Reading address 0x22006008 returns the value (0x01 or 0x00) of bit 2 of the byte at SRAM address 0x20000300 (0x01: bit set; 0x00: bit reset).

For more information on Bit-Banding, please refer to the Cortex

-M3 Technical Reference

Manual.

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Memory and bus architecture RM0008

3.3.3 Embedded Flash memory

The high-performance Flash memory module has the following key features:

• For XL-density devices: density of up to 1 Mbyte with dual bank architecture for readwhile-write (RWW) capability:

– bank 1: fixed size of 512 Kbytes

– bank 2: up to 512 Kbytes

• For other devices: density of up to 512 Kbytes

• Memory organization: the Flash memory is organized as a main block and an

information block:

– Main memory block of size:

up to 128 Kbytes × 64 bits divided into 512 pages of 2 Kbytes each (see Tab le 8 ) for XL-density devices

up to 4 Kb × 64 bits divided into 32 pages of 1 Kbyte each for low-density devices (see Tabl e 4)

up to 16 Kb × 64 bits divided into 128 pages of 1 Kbyte each for medium-density devices (see Tabl e 5 )

up to 64 Kb × 64 bits divided into 256 pages of 2 Kbytes each (see Tab le 6) for high-density devices

up to 32 Kbit × 64 bits divided into 128 pages of 2 Kbytes each (see Tab le 7 ) for connectivity line devices

– Information block of size:

770 × 64 bits for XL-density devices (see Tab l e 8)

2360 × 64 bits for connectivity line devices (see Tab le 7 )

258 × 64 bits for other devices (see Table 4, Tabl e 5 and Tabl e 6)

The Flash memory interface (FLITF) features:

• Read interface with prefetch buffer (2x64-bit words)

• Option byte Loader

• Flash Program / Erase operation

• Read / Write protection

Block Name Base addresses Size (bytes)

Main memory

Table 4. Flash module organization (low-density devices)

Page 0 0x0800 0000 - 0x0800 03FF 1 Kbyte

Page 1 0x0800 0400 - 0x0800 07FF 1 Kbyte

Page 2 0x0800 0800 - 0x0800 0BFF 1 Kbyte

Page 3 0x0800 0C00 - 0x0800 0FFF 1 Kbyte

Page 4 0x0800 1000 - 0x0800 13FF 1 Kbyte

. . .

Page 31 0x0800 7C00 - 0x0800 7FFF 1 Kbyte

. . .

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RM0008 Memory and bus architecture

Table 4. Flash module organization (low-density devices) (continued)

Block Name Base addresses Size (bytes)

Information block

System memory 0x1FFF F000 - 0x1FFF F7FF 2 Kbytes

Option Bytes 0x1FFF F800 - 0x1FFF F80F 16

FLASH_ACR 0x4002 2000 - 0x4002 2003 4

FLASH_KEYR 0x4002 2004 - 0x4002 2007 4

FLASH_OPTKEYR 0x4002 2008 - 0x4002 200B 4

Flash memory

interface registers

FLASH_SR 0x4002 200C - 0x4002 200F 4

FLASH_CR 0x4002 2010 - 0x4002 2013 4

FLASH_AR 0x4002 2014 - 0x4002 2017 4

Reserved 0x4002 2018 - 0x4002 201B 4

FLASH_OBR 0x4002 201C - 0x4002 201F 4

FLASH_WRPR 0x4002 2020 - 0x4002 2023 4

Table 5. Flash module organization (medium-density devices)

Block Name Base addresses Size (bytes)

Page 0 0x0800 0000 - 0x0800 03FF 1 Kbyte

Page 1 0x0800 0400 - 0x0800 07FF 1 Kbyte

Page 2 0x0800 0800 - 0x0800 0BFF 1 Kbyte

Page 3 0x0800 0C00 - 0x0800 0FFF 1 Kbyte

Main memory

Page 4 0x0800 1000 - 0x0800 13FF 1 Kbyte

. . .

Page 127 0x0801 FC00 - 0x0801 FFFF 1 Kbyte

System memory 0x1FFF F000 - 0x1FFF F7FF 2 Kbytes

Information block

Option Bytes 0x1FFF F800 - 0x1FFF F80F 16

FLASH_ACR 0x4002 2000 - 0x4002 2003 4

FLASH_KEYR 0x4002 2004 - 0x4002 2007 4

. . .

Flash memory

interface registers

FLASH_OPTKEYR 0x4002 2008 - 0x4002 200B 4

FLASH_SR 0x4002 200C - 0x4002 200F 4

FLASH_CR 0x4002 2010 - 0x4002 2013 4

FLASH_AR 0x4002 2014 - 0x4002 2017 4

Reserved 0x4002 2018 - 0x4002 201B 4

FLASH_OBR 0x4002 201C - 0x4002 201F 4

FLASH_WRPR 0x4002 2020 - 0x4002 2023 4

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Memory and bus architecture RM0008

Table 6. Flash module organization (high-density devices)

Block Name Base addresses Size (bytes)

Page 0 0x0800 0000 - 0x0800 07FF 2 Kbytes

Page 1 0x0800 0800 - 0x0800 0FFF 2 Kbytes

Page 2 0x0800 1000 - 0x0800 17FF 2 Kbytes

Main memory

Page 3 0x0800 1800 - 0x0800 1FFF 2 Kbytes

. . .

Page 255 0x0807 F800 - 0x0807 FFFF 2 Kbytes

System memory 0x1FFF F000 - 0x1FFF F7FF 2 Kbytes

Information block

Option Bytes 0x1FFF F800 - 0x1FFF F80F 16

FLASH_ACR 0x4002 2000 - 0x4002 2003 4

FLASH_KEYR 0x4002 2004 - 0x4002 2007 4

FLASH_OPTKEYR 0x4002 2008 - 0x4002 200B 4

Flash memory

interface registers

FLASH_SR 0x4002 200C - 0x4002 200F 4

FLASH_CR 0x4002 2010 - 0x4002 2013 4

FLASH_AR 0x4002 2014 - 0x4002 2017 4

Reserved 0x4002 2018 - 0x4002 201B 4

. . .

FLASH_OBR 0x4002 201C - 0x4002 201F 4

FLASH_WRPR 0x4002 2020 - 0x4002 2023 4

Table 7. Flash module organization (connectivity line devices)

Block Name Base addresses Size (bytes)

Page 0 0x0800 0000 - 0x0800 07FF 2 Kbytes

Page 1 0x0800 0800 - 0x0800 0FFF 2 Kbytes

Page 2 0x0800 1000 - 0x0800 17FF 2 Kbytes

Main memory

Page 3 0x0800 1800 - 0x0800 1FFF 2 Kbytes

. . .

Page 127 0x0803 F800 - 0x0803 FFFF 2 Kbytes

System memory 0x1FFF B000 - 0x1FFF F7FF 18 Kbytes

Information block

Option Bytes 0x1FFF F800 - 0x1FFF F80F 16

. . .

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RM0008 Memory and bus architecture

Table 7. Flash module organization (connectivity line devices) (continued)

Block Name Base addresses Size (bytes)

FLASH_ACR 0x4002 2000 - 0x4002 2003 4

FLASH_KEYR 0x4002 2004 - 0x4002 2007 4

FLASH_OPTKEYR 0x4002 2008 - 0x4002 200B 4

Flash memory

interface registers

FLASH_SR 0x4002 200C - 0x4002 200F 4

FLASH_CR 0x4002 2010 - 0x4002 2013 4

FLASH_AR 0x4002 2014 - 0x4002 2017 4

Reserved 0x4002 2018 - 0x4002 201B 4

FLASH_OBR 0x4002 201C - 0x4002 201F 4

FLASH_WRPR 0x4002 2020 - 0x4002 2023 4

Block Name Base addresses Size (bytes)

Main memory

Information block

Table 8. XL-density Flash module organization

Page 0 0x0800 0000 - 0x0800 07FF 2 Kbytes

Bank 1

Bank 2

Page 1 0x0800 0800 - 0x0800 0FFF 2 Kbytes

... ... ...

Page 255 0x0807 F800 - 0x0807 FFFF 2 Kbytes

Page 256 0x0808 0000 - 0x0808 07FF 2 Kbytes

Page 257 0x0808 0800 - 0x0808 0FFF 2 Kbytes

Page 511 0x080F F800 - 0x080F FFFF 2 Kbytes

System memory 0x1FFF E000 - 0x1FFF F7FF 6 Kbytes

Option bytes 0x1FFF F800 - 0x1FFF F80F 16

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Memory and bus architecture RM0008

Table 8. XL-density Flash module organization (continued)

Block Name Base addresses Size (bytes)

FLASH_ACR 0x4002 2000 - 0x4002 2003 4

FLASH_KEYR 0x4002 2004 - 0x4002 2007 4

FLASH_OPTKEYR 0x4002 2008 - 0x4002 200B 4

FLASH_SR 0x4002 200C - 0x4002 200F 4

FLASH_CR 0x4002 2010 - 0x4002 2013 4

FLASH_AR 0x4002 2014 - 0x4002 2017 4

Reserved 0x4002 2018 - 0x4002 201B 4

Flash memory interface

registers

FLASH_OBR 0x4002 201C - 0x4002 201F 4

FLASH_WRPR 0x4002 2020 - 0x4002 2023 4

Reserved 0x4002 2024 - 0x4002 2043 32

FLASH_KEYR2 0x4002 2044 - 0x4002 2047 4

Reserved 0x4002 2048 - 0x4002 204B 4

FLASH_SR2 0x4002 204C - 0x4002 204F 4

FLASH_CR2 0x4002 2050 - 0x4002 2053 4

FLASH_AR2 0x4002 2054 - 0x4002 2057 4

Note: For further information on the Flash memory interface registers, please refer to the:

“STM32F10xxx XL-density Flash programming manual” (PM0068) for XL-density devices

“STM32F10xxx Flash programming manual” (PM0075) for other devices

Reading the Flash memory

Flash memory instructions and data access are performed through the AHB bus. The prefetch block is used for instruction fetches through the ICode bus. Arbitration is performed in the Flash memory interface, and priority is given to data access on the DCode bus.

Read accesses can be performed with the following configuration options:

• Latency: number of wait states for a read operation programmed on-the-fly

• Prefetch buffer (2 x 64-bit blocks): it is enabled after reset; a whole block can be

replaced with a single read from the Flash memory as the size of the block matches the bandwidth of the Flash memory. Thanks to the prefetch buffer, faster CPU execution is possible as the CPU fetches one word at a time with the next word readily available in the prefetch buffer

• Half cycle: for power optimization

Note: These options should be used in accordance with the Flash memory access time. The wait

states represent the ratio of the SYSCLK (system clock) period to the Flash memory access time: zero wait state, if 0 < SYSCLK one wait state, if 24 MHz < SYSCLK two wait states, if 48 MHz < SYSCLK

Half cycle configuration is not available in combination with a prescaler on the AHB. The system clock (SYSCLK) should be equal to the HCLK clock. This feature can therefore be

≤

24 MHz

≤

48 MHz

72 MHz

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RM0008 Memory and bus architecture

used only with a low-frequency clock of 8 MHz or less. It can be generated from the HSI or the HSE but not from the PLL.

The prefetch buffer must be kept on when using a prescaler different from 1 on the AHB clock.

The prefetch buffer must be switched on/off only when SYSCLK is lower than 24 MHz and no prescaler is applied on the AHB clock (SYSCLK must be equal to HCLK). The prefetch buffer is usually switched on/off during the initialization routine, while the microcontroller is running on the internal 8 MHz RC (HSI) oscillator.

Using DMA: DMA accesses Flash memory on the DCode bus and has priority over ICode instructions. The DMA provides one free cycle after each transfer. Some instructions can be performed together with DMA transfer.

Programming and erasing the Flash memory

The Flash memory can be programmed 16 bits (half words) at a time.

For write and erase operations on the Flash memory (write/erase), the internal RC oscillator (HSI) must be ON.

The Flash memory erase operation can be performed at page level or on the whole Flash area (mass-erase). The mass-erase does not affect the information blocks.

To ensure that there is no over-programming, the Flash Programming and Erase Controller blocks are clocked by a fixed clock.

The End of write operation (programming or erasing) can trigger an interrupt. This interrupt can be used to exit from WFI mode, only if the FLITF clock is enabled. Otherwise, the interrupt is served only after an exit from WFI.

The FLASH_ACR register is used to enable/disable prefetch and half cycle access, and to control the Flash memory access time according to the CPU frequency. The tables below provide the bit map and bit descriptions for this register.

For complete information on Flash memory operations and register configurations, please refer to the STM32F10xxx Flash programming manual (PM0075) or to the XL STM32F10xxx Flash programming manual (PM0068).

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Memory and bus architecture RM0008

Flash access control register (FLASH_ACR)

Address offset: 0x00

Reset value: 0x0000 0030

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

Bits 31:6 Reserved, must be kept at reset value.

Bit 5 PRFTBS: Prefetch buffer status

This bit provides the status of the prefetch buffer. 0: Prefetch buffer is disabled 1: Prefetch buffer is enabled

Bit 4 PRFTBE: Prefetch buffer enable

0: Prefetch is disabled 1: Prefetch is enabled

PRFTBS PRFTBE HLFCYA LATENCY

rrwrwrwrwrw

Bit 3 HLFCYA: Flash half cycle access enable

0: Half cycle is disabled 1: Half cycle is enabled

Bits 2:0 LATENCY: Latency

These bits represent the ratio of the SYSCLK (system clock) period to the Flash access time. 000 Zero wait state, if 0 < SYSCLK≤ 24 MHz 001 One wait state, if 24 MHz < SYSCLK ≤ 48 MHz 010 Two wait states, if 48 MHz < SYSCLK ≤ 72 MHz

3.4 Boot configuration

In the STM32F10xxx, 3 different boot modes can be selected through BOOT[1:0] pins as shown in Tab le 9.

Boot mode selection pins

Boot mode Aliasing

BOOT1 BOOT0

x 0 Main Flash memory Main Flash memory is selected as boot space

0 1 System memory System memory is selected as boot space

1 1 Embedded SRAM Embedded SRAM is selected as boot space

Table 9. Boot modes

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RM0008 Memory and bus architecture

The values on the BOOT pins are latched on the 4th rising edge of SYSCLK after a reset. It is up to the user to set the BOOT1 and BOOT0 pins after Reset to select the required boot mode.

The BOOT pins are also re-sampled when exiting from Standby mode. Consequently they must be kept in the required Boot mode configuration in Standby mode. After this startup delay has elapsed, the CPU fetches the top-of-stack value from address 0x0000 0000, then starts code execution from the boot memory starting from 0x0000 0004.

Due to its fixed memory map, the code area starts from address 0x0000 0000 (accessed through the ICode/DCode buses) while the data area (SRAM) starts from address 0x2000 0000 (accessed through the system bus). The Cortex

-M3 CPU always fetches the reset vector on the ICode bus, which implies to have the boot space available only in the code area (typically, Flash memory). STM32F10xxx microcontrollers implement a special mechanism to be able to boot also from SRAM and not only from main Flash memory and System memory.

Depending on the selected boot mode, main Flash memory, system memory or SRAM is accessible as follows:

• Boot from main Flash memory: the main Flash memory is aliased in the boot memory

space (0x0000 0000), but still accessible from its original memory space (0x800 0000). In other words, the Flash memory contents can be accessed starting from address 0x0000 0000 or 0x800 0000.

• Boot from system memory: the system memory is aliased in the boot memory space

(0x0000 0000), but still accessible from its original memory space (0x1FFF B000 in connectivity line devices, 0x1FFF F000 in other devices).

• Boot from the embedded SRAM: SRAM is accessible only at address 0x2000 0000.

Note: When booting from SRAM, in the application initialization code, you have to relocate the

vector table in SRAM using the NVIC exception table and offset register.

For XL-density devices, when booting from the main Flash memory, you have an option to boot from any of two memory banks. By default, boot from Flash memory bank 1 is selected. You can choose to boot from Flash memory bank 2 by clearing the BFB2 bit in the user option bytes. When this bit is cleared and the boot pins are in the boot from main Flash memory configuration, the device boots from system memory, and the boot loader jumps to execute the user application programmed in Flash memory bank 2. For further details, please refer to AN2606.

Note: When booting from Bank2 in the applications initialization code, relocate the vector table to

the Bank2 base address. (0x0808 0000) using the NVIC exception table and offset register.

Embedded boot loader

The embedded boot loader is located in the System memory, programmed by ST during production. It is used to reprogram the Flash memory with one of the available serial interfaces:

• In low-, medium- and high-density devices the bootoader is activated through the

USART1 interface.

• In XL-density devices the boot loader is activated through the following interfaces:

USART1 or USART2 (remapped).

• In connectivity line devices the boot loader can be activated through one of the

following interfaces: USART1, USART2 (remapped), CAN2 (remapped) or USB OTG FS in Device mode (DFU: device firmware upgrade).

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Memory and bus architecture RM0008

The USART peripheral operates with the internal 8 MHz oscillator (HSI). The CAN and USB OTG FS, however, can only function if an external 8 MHz, 14.7456 MHz or 25 MHz clock (HSE) is present.

Note: For further details, please refer to AN2606.

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RM0008 CRC calculation unit

4 CRC calculation unit

Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx

microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.

Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.

High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.

XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 768 Kbytes and 1 Mbyte.

Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.

4.1 CRC introduction

The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit data word and a fixed generator polynomial.

Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of the software during runtime, to be compared with a reference signature generated at linktime and stored at a given memory location.

4.2 CRC main features

• Uses CRC-32 (Ethernet) polynomial: 0x4C11DB7

–X

• Single input/output 32-bit data register

• CRC computation done in 4 AHB clock cycles (HCLK)

• General-purpose 8-bit register (can be used for temporary storage)

The block diagram is shown in Figure 3.

+ X26 + X23 + X22 + X16 + X12 + X11 + X10 +X8 + X7 + X5 + X4 + X2+ X +1

Figure 3. CRC calculation unit block diagram

32-bit (write access)

AHB bus

32-bit (read access)

Data register (output)

CRC computation (polynomial: 0x4C11DB7)

Data register (input)

ai14968

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CRC calculation unit RM0008

4.3 CRC functional description

The CRC calculation unit mainly consists of a single 32-bit data register, which:

• is used as an input register to enter new data in the CRC calculator (when writing into

the register)

• holds the result of the previous CRC calculation (when reading the register)

Each write operation into the data register creates a combination of the previous CRC value and the new one (CRC computation is done on the whole 32-bit data word, and not byte per byte).

The write operation is stalled until the end of the CRC computation, thus allowing back-toback write accesses or consecutive write and read accesses.

The CRC calculator can be reset to 0xFFFF FFFF with the RESET control bit in the CRC_CR register. This operation does not affect the contents of the CRC_IDR register.

4.4 CRC registers

The CRC calculation unit contains two data registers and a control register.The peripheral The CRC registers have to be accessed by words (32 bits).

4.4.1 Data register (CRC_DR)

Address offset: 0x00

Reset value: 0xFFFF FFFF

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

DR [31:16]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

1514131211109876543210

DR [15:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 Data register bits

Used as an input register when writing new data into the CRC calculator. Holds the previous CRC calculation result when it is read.

4.4.2 Independent data register (CRC_IDR)

Address offset: 0x04

Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

1514131211109876543210

Reserved

rw rw rw rw rw rw rw rw

IDR[7:0]

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RM0008 CRC calculation unit

Bits 31:8 Reserved, must be kept at reset value.

Bits 7:0 General-purpose 8-bit data register bits

Can be used as a temporary storage location for one byte. This register is not affected by CRC resets generated by the RESET bit in the CRC_CR

4.4.3 Control register (CRC_CR)

Address offset: 0x08

Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

1514131211109876543210

Reserved

Bits 31:1 Reserved, must be kept at reset value.

Bit 0 RESET bit

Resets the CRC calculation unit and sets the data register to 0xFFFF FFFF. This bit can only be set, it is automatically cleared by hardware.

RESET

4.4.4 CRC register map

The following table the CRC register map and reset values.

Offset Register 31-24 23-16 15-8 7 6 5 4 3 2 1 0

0x00

0x04

0x08

Table 10. CRC calculation unit register map and reset values

CRC_DR Data register

Reset

value

CRC_IDR

Reset

value

CRC_CR

Reset

value

0xFFFF FFFF

Independent data register

Reserved

0x00

RESET

Reserved

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5 Power control (PWR)

Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx

microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.

Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.

High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.

XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 768 Kbytes and 1 Mbyte.

Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.

This section applies to the whole STM32F101xx family, unless otherwise specified.

5.1 Power supplies

The device requires a 2.0-to-3.6 V operating voltage supply (VDD). An embedded regulator is used to supply the internal 1.8 V digital power.

The real-time clock (RTC) and backup registers can be powered from the V when the main V

supply is powered off.

BAT

voltage

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RM0008 Power control (PWR)

A/D converter

DDA

SSA

REF+

BAT

I/O Ring

)

(from 2.4 V up to V

DDA

)

BKP registers

Temp. sensor Reset block

Standby circuitry

PLL

(Wakeup logic, IWDG)

RTC

Voltage Regulator

Core

Memories

digital

peripherals

Low voltage detector

REF-

DDA

domain

1.8 V domain

Backup domain

LSE crystal 32K osc

RCC BDCR register

SSA

)

D/A converter

Figure 4. Power supply overview

5.1.1 Independent A/D and D/A converter supply and reference voltage

1. V

DDA

and V

must be connected to VDD and VSS, respectively.

SSA

To improve conversion accuracy, the ADC and the DAC have an independent power supply which can be separately filtered and shielded from noise on the PCB.

• The ADC and DAC voltage supply input is available on a separate V

• An isolated supply ground connection is provided on pin V

When available (according to package), V

On 100-pin and 144-pin packages

To ensure a better accuracy on low-voltage inputs and outputs, the user can connect a separate external reference voltage on V the full scale value, for an analog input (ADC) or output (DAC) signal. The voltage on V can range from 2.4 V to V

DDA

must be tied to V

REF-

. V

REF+

is the highest voltage, represented by

SSA

DDA

pin.

On 64-pin packages and packages with less pins

The V

REF+

and V

voltage supply (V

pins are not available, they are internally connected to the ADC

REF-

) and ground (V

DDA

SSA

REF+

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5.1.2 Battery backup domain

To retain the content of the Backup registers and supply the RTC function when V turned off, V

pin can be connected to an optional standby voltage supplied by a battery

BAT

or by another source.

The V the RTC to operate even when the main digital supply (V V

BAT

pin powers the RTC unit, the LSE oscillator and the PC13 to PC15 IOs, allowing

BAT

) is turned off. The switch to the

supply is controlled by the Power Down Reset embedded in the Reset block.

Warning: During t

is detected, the power switch between V connected to V During the startup phase, if V t

RSTTEMPO

and V

through an internal diode connected between V power switch (V If the power supply/battery connected to the V

RSTTEMPO

(Refer to the datasheet for the value of t

> V

(temporization at VDD startup) or after a PDR

and VDD remains

BAT

+ 0.6 V, a current may be injected into V

BAT

is established in less than

BAT

pin cannot

BAT

RSTTEMPO

BAT

and the

)

support this current injection, it is strongly recommended to connect an external low-drop diode between this power supply and the V

If no external battery is used in the application, it is recommended to connect V

BAT

pin.

BAT

externally to VDD with a 100 nF external ceramic decoupling capacitor (for more details refer to AN2586).

When the backup domain is supplied by V

(analog switch connected to VDD), the

following functions are available:

• PC14 and PC15 can be used as either GPIO or LSE pins

• PC13 can be used as GPIO, TAMPER pin, RTC Calibration Clock, RTC Alarm or

second output (refer to Section 6: Backup registers (BKP) on page 81)

Note: Due to the fact that the switch only sinks a limited amount of current (3 mA), the use of

GPIOs PC13 to PC15 in output mode is restricted: the speed has to be limited to 2 MHz with a maximum load of 30 pF and these IOs must not be used as a current source (e.g. to drive an LED).

When the backup domain is supplied by V V

is not present), the following functions are available:

(analog switch connected to V

BAT

because

BAT

• PC14 and PC15 can be used as LSE pins only

• PC13 can be used as TAMPER pin, RTC Alarm or Second output (refer to section

Section 6.4.2: RTC clock calibration register (BKP_RTCCR) on page 83).

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RM0008 Power control (PWR)

VDD/V

DDA

Reset

40 mV

hysteresis

POR

PDR

Temporization t

RSTTEMPO

5.1.3 Voltage regulator

The voltage regulator is always enabled after Reset. It works in three different modes depending on the application modes.

• In Run mode, the regulator supplies full power to the 1.8 V domain (core, memories

and digital peripherals).

• In Stop mode the regulator supplies low-power to the 1.8 V domain, preserving

contents of registers and SRAM

• In Standby Mode, the regulator is powered off. The contents of the registers and SRAM

are lost except for the Standby circuitry and the Backup Domain.

5.2 Power supply supervisor

5.2.1 Power on reset (POR)/power down reset (PDR)

The device has an integrated POR/PDR circuitry that allows proper operation starting from/down to 2 V.

The device remains in Reset mode when V V

POR/PDR

, without the need for an external reset circuit. For more details concerning the

DD/VDDA

is below a specified threshold,

power on/power down reset threshold, refer to the electrical characteristics of the datasheet.

Figure 5. Power on reset/power down reset waveform

5.2.2 Programmable voltage detector (PVD)

You can use the PVD to monitor the VDD/V selected by the PLS[2:0] bits in the Power control register (PWR_CR).

The PVD is enabled by setting the PVDE bit.

A PVDO flag is available, in the Power control/status register (PWR_CSR), to indicate if V

DD/VDDA

is higher or lower than the PVD threshold. This event is internally connected to

the EXTI line16 and can generate an interrupt if enabled through the EXTI registers. The

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DDA

power supply by comparing it to a threshold

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Power control (PWR) RM0008

VDD/V

DDA

PVD output

100 mV hysteresis

PVD threshold

PVD output interrupt can be generated when VDD/V and/or when V

DD/VDDA

rises above the PVD threshold depending on EXTI line16

drops below the PVD threshold

DDA

rising/falling edge configuration. As an example the service routine could perform emergency shutdown tasks.

Figure 6. PVD thresholds

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RM0008 Power control (PWR)

5.3 Low-power modes

By default, the microcontroller is in Run mode after a system or a power Reset. Several lowpower modes are available to save power when the CPU does not need to be kept running, for example when waiting for an external event. It is up to the user to select the mode that gives the best compromise between low-power consumption, short startup time and available wakeup sources.

The STM32F10xxx devices feature three low-power modes:

• Sleep mode (CPU clock off, all peripherals including Cortex

NVIC, SysTick, etc. are kept running)

• Stop mode (all clocks are stopped)

• Standby mode (1.8V domain powered-off)

In addition, the power consumption in Run mode can be reduce by one of the following means:

• Slowing down the system clocks

• Gating the clocks to the APB and AHB peripherals when they are unused.

Mode name Entry wakeup

Table 11. Low-power mode summary

Effect on 1.8V

domain clocks

-M3 core peripherals like

Effect on

domain

clocks

Voltage

regulator

Sleep (Sleep now or

Sleep-on exit)

Stop

Standby

WFI Any interrupt CPU clock OFF

WFE Wakeup event

PDDS and LPDS bits + SLEEPDEEP bit + WFI or WFE

PDDS bit + SLEEPDEEP bit + WFI or WFE

Any EXTI line (configured in the EXTI registers)

WKUP pin rising edge, RTC alarm, external reset in NRST pin, IWDG reset

5.3.1 Slowing down system clocks

In Run mode the speed of the system clocks (SYSCLK, HCLK, PCLK1, PCLK2) can be reduced by programming the prescaler registers. These prescalers can also be used to slow down peripherals before entering Sleep mode.

For more details refer to Section 7.3.2: Clock configuration register (RCC_CFGR).

no effect on other clocks or analog clock sources

All 1.8V domain clocks OFF

None ON

ON or in lowpower mode

(depends on

HSI and HSE oscillators OFF

Power control register (PWR_CR))

OFF

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Power control (PWR) RM0008

5.3.2 Peripheral clock gating

In Run mode, the HCLK and PCLKx for individual peripherals and memories can be stopped at any time to reduce power consumption.

To further reduce power consumption in Sleep mode the peripheral clocks can be disabled prior to executing the WFI or WFE instructions.

Peripheral clock gating is controlled by the AHB peripheral clock enable register

(RCC_AHBENR), APB1 peripheral clock enable register (RCC_APB1ENR) and APB2 peripheral clock enable register (RCC_APB2ENR).

5.3.3 Sleep mode

Entering Sleep mode

The Sleep mode is entered by executing the WFI (Wait For Interrupt) or WFE (Wait for Event) instructions. Two options are available to select the Sleep mode entry mechanism, depending on the SLEEPONEXIT bit in the Cortex

• Sleep-now: if the SLEEPONEXIT bit is cleared, the MCU enters Sleep mode as soon

as WFI or WFE instruction is executed.

• Sleep-on-exit: if the SLEEPONEXIT bit is set, the MCU enters Sleep mode as soon as

it exits the lowest priority ISR.

-M3 System Control register:

In the Sleep mode, all I/O pins keep the same state as in the Run mode.

Refer to Tab le 1 2 and Table 13 for details on how to enter Sleep mode.

Exiting Sleep mode

If the WFI instruction is used to enter Sleep mode, any peripheral interrupt acknowledged by the nested vectored interrupt controller (NVIC) can wake up the device from Sleep mode.

If the WFE instruction is used to enter Sleep mode, the MCU exits Sleep mode as soon as an event occurs. The wakeup event can be generated either by:

• enabling an interrupt in the peripheral control register but not in the NVIC, and enabling

the SEVONPEND bit in the Cortex resumes from WFE, the peripheral interrupt pending bit and the peripheral NVIC IRQ channel pending bit (in the NVIC interrupt clear pending register) have to be cleared.

• or configuring an external or internal EXTI line in event mode. When the CPU resumes

from WFE, it is not necessary to clear the peripheral interrupt pending bit or the NVIC IRQ channel pending bit as the pending bit corresponding to the event line is not set.

This mode offers the lowest wakeup time as no time is wasted in interrupt entry/exit.

Refer to Tab le 1 2 and Table 13 for more details on how to exit Sleep mode.

-M3 System Control register. When the MCU

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RM0008 Power control (PWR)

Sleep-now mode Description

WFI (Wait for Interrupt) or WFE (Wait for Event) while:

Mode entry

Mode exit

Wakeup latency None

Sleep-on-exit Description

Mode entry

Mode exit

Wakeup latency None

– SLEEPDEEP = 0 and – SLEEPONEXIT = 0 Refer to the Cortex

If WFI was used for entry:

Interrupt: Refer to Section 10.1.2: Interrupt and exception vectors on

page 197

If WFE was used for entry

Wakeup event: Refer to Section 10.2.3: Wakeup event management

WFI (wait for interrupt) while: – SLEEPDEEP = 0 and – SLEEPONEXIT = 1 Refer to the Cortex

Interrupt: refer to Section 10.1.2: Interrupt and exception vectors on

page 197.

Table 12. Sleep-now

-M3 System Control register.

Table 13. Sleep-on-exit

-M3 System Control register.

5.3.4 Stop mode

The Stop mode is based on the Cortex®-M3 deepsleep mode combined with peripheral clock gating. The voltage regulator can be configured either in normal or low-power mode. In Stop mode, all clocks in the 1.8 V domain are stopped, the PLL, the HSI and the HSE RC oscillators are disabled. SRAM and register contents are preserved.

In the Stop mode, all I/O pins keep the same state as in the Run mode.

Entering Stop mode

Refer to Tab le 1 4 for details on how to enter the Stop mode.

To further reduce power consumption in Stop mode, the internal voltage regulator can be put in low-power mode. This is configured by the LPDS bit of the Power control register

(PWR_CR).

If Flash memory programming is ongoing, the Stop mode entry is delayed until the memory access is finished.

If an access to the APB domain is ongoing, The Stop mode entry is delayed until the APB access is finished.

In Stop mode, the following features can be selected by programming individual control bits:

• Independent watchdog (IWDG): the IWDG is started by writing to its Key register or by

hardware option. Once started it cannot be stopped except by a Reset. See

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Power control (PWR) RM0008

Section 19.3: IWDG functional description in Section 19: Independent watchdog (IWDG).

• real-time clock (RTC): this is configured by the RTCEN bit in the Backup domain

control register (RCC_BDCR)

• Internal RC oscillator (LSI RC): this is configured by the LSION bit in the Control/status

• External 32.768 kHz oscillator (LSE OSC): this is configured by the LSEON bit in the

Backup domain control register (RCC_BDCR).

The ADC or DAC can also consume power during the Stop mode, unless they are disabled before entering it. To disable them, the ADON bit in the ADC_CR2 register and the ENx bit in the DAC_CR register must both be written to 0.

Note: If the application needs to disable the external clock before entering Stop mode, the HSEON

bit must first be disabled and the system clock switched to HSI. Otherwise, if the HSEON bit remains enabled and the external clock (external oscillator) is removed when entering Stop mode, the clock security system (CSS) feature must be enabled to detect any external oscillator failure and avoid a malfunction behavior when entering stop mode.

Exiting Stop mode

Refer to Tab le 1 4 for more details on how to exit Stop mode.

When exiting Stop mode by issuing an interrupt or a wakeup event, the HSI RC oscillator is selected as system clock.

When the voltage regulator operates in low-power mode, an additional startup delay is incurred when waking up from Stop mode. By keeping the internal regulator ON during Stop mode, the consumption is higher although the startup time is reduced.

Stop mode Description

WFI (Wait for Interrupt) or WFE (Wait for Event) while: – Set SLEEPDEEP bit in Cortex – Clear PDDS bit in Power Control register (PWR_CR)

Mode entry

Mode exit

Wakeup latency HSI RC wakeup time + regulator wakeup time from Low-power mode

– Select the voltage regulator mode by configuring LPDS bit in PWR_CR

Note: To enter Stop mode, all EXTI Line pending bits (in Pending register

(EXTI_PR)), all peripheral interrupt pending bits, and RTC Alarm flag must

be reset. Otherwise, the Stop mode entry procedure is ignored and program execution continues.

If WFI was used for entry:

Any EXTI Line configured in Interrupt mode (the corresponding EXTI Interrupt vector must be enabled in the NVIC). Refer to Section 10.1.2:

Interrupt and exception vectors on page 197.

If WFE was used for entry:

Any EXTI Line configured in event mode. Refer to Section 10.2.3:

Wakeup event management on page 206

Table 14. Stop mode

-M3 System Control register

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RM0008 Power control (PWR)

5.3.5 Standby mode

The Standby mode allows to achieve the lowest power consumption. It is based on the

Cortex consequently powered off. The PLL, the HSI oscillator and the HSE oscillator are also switched off. SRAM and register contents are lost except for registers in the Backup domain and Standby circuitry (see Figure 4).

Entering Standby mode

Refer to Tab le 1 5 for more details on how to enter Standby mode.

In Standby mode, the following features can be selected by programming individual control bits:

• Independent watchdog (IWDG): the IWDG is started by writing to its Key register or by

• real-time clock (RTC): this is configured by the RTCEN bit in the Backup domain

• Internal RC oscillator (LSI RC): this is configured by the LSION bit in the Control/status

• External 32.768 kHz oscillator (LSE OSC): this is configured by the LSEON bit in the

-M3 deepsleep mode, with the voltage regulator disabled. The 1.8 V domain is

hardware option. Once started it cannot be stopped except by a reset. See

Section 19.3: IWDG functional description in Section 19: Independent watchdog (IWDG).

control register (RCC_BDCR)

Backup domain control register (RCC_BDCR)

Exiting Standby mode

The microcontroller exits the Standby mode when an external reset (NRST pin), an IWDG reset, a rising edge on the WKUP pin or the rising edge of an RTC alarm occurs (see

Figure 179: RTC simplified block diagram). All registers are reset after wakeup from

Standby except for Power control/status register (PWR_CSR).

After waking up from Standby mode, program execution restarts in the same way as after a Reset (boot pins sampling, vector reset is fetched, etc.). The SBF status flag in the Power

control/status register (PWR_CSR) indicates that the MCU was in Standby mode.

Refer to Tab le 1 5 for more details on how to exit Standby mode.

Standby mode Description

WFI (Wait for Interrupt) or WFE (Wait for Event) while:

Mode entry

Mode exit

Wakeup latency Reset phase

– Set SLEEPDEEP in Cortex – Set PDDS bit in Power Control register (PWR_CR) – Clear WUF bit in Power Control/Status register (PWR_CSR)

WKUP pin rising edge, RTC alarm event’s rising edge, external Reset in

NRST pin, IWDG Reset.

Table 15. Standby mode

-M3 System Control register

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Power control (PWR) RM0008

I/O states in Standby mode

In Standby mode, all I/O pins are high impedance except:

• Reset pad (still available)

• TAMPER pin if configured for tamper or calibration out

• WKUP pin, if enabled

Debug mode

By default, the debug connection is lost if the application puts the MCU in Stop or Standby mode while the debug features are used. This is due to the fact that the Cortex no longer clocked.

However, by setting some configuration bits in the DBGMCU_CR register, the software can be debugged even when using the low-power modes extensively. For more details, refer to

Section 31.16.1: Debug support for low-power modes.

5.3.6 Auto-wakeup (AWU) from low-power mode

The RTC can be used to wakeup the MCU from low-power mode without depending on an external interrupt (Auto-wakeup mode). The RTC provides a programmable time base for waking up from Stop or Standby mode at regular intervals. For this purpose, two of the three alternative RTC clock sources can be selected by programming the RTCSEL[1:0] bits in the

Backup domain control register (RCC_BDCR):

• Low-power 32.768 kHz external crystal oscillator (LSE OSC).

This clock source provides a precise time base with very low-power consumption (less than 1µA added consumption in typical conditions)

• Low-power internal RC Oscillator (LSI RC)

This clock source has the advantage of saving the cost of the 32.768 kHz crystal. This internal RC Oscillator is designed to add minimum power consumption.

To wakeup from Stop mode with an RTC alarm event, it is necessary to:

• Configure the EXTI Line 17 to be sensitive to rising edge

• Configure the RTC to generate the RTC alarm

-M3 core is

To wakeup from Standby mode, there is no need to configure the EXTI Line 17.

5.4 Power control registers

The peripheral registers can be accessed by half-words (16-bit) or words (32-bit).

5.4.1 Power control register (PWR_CR)

Address offset: 0x00

Reset value: 0x0000 0000 (reset by wakeup from Standby mode)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

1514131211109876543210

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Reserved

DBP PLS[2:0] PVDE CSBF CWUF PDDS LPDS

rw rw rw rw rw rc_w1 rc_w1 rw rw

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RM0008 Power control (PWR)

Bits 31:9 Reserved, must be kept at reset value..

Bit 8 DBP: Disable backup domain write protection.

In reset state, the RTC and backup registers are protected against parasitic write access. This bit must be set to enable write access to these registers. 0: Access to RTC and Backup registers disabled 1: Access to RTC and Backup registers enabled

Note: If the HSE divided by 128 is used as the RTC clock, this bit must remain set to 1.

Bits 7:5 PLS[2:0]: PVD level selection.

These bits are written by software to select the voltage threshold detected by the Power Voltage Detector

000: 2.2V 001: 2.3V 010: 2.4V 011: 2.5V 100: 2.6V 101: 2.7V 110: 2.8V 111: 2.9V

Note: Refer to the electrical characteristics of the datasheet for more details.

Bit 4 PVDE: Power voltage detector enable.

This bit is set and cleared by software.

0: PVD disabled 1: PVD enabled

Bit 3 CSBF: Clear standby flag.

This bit is always read as 0.

0: No effect 1: Clear the SBF Standby Flag (write).

Bit 2 CWUF: Clear wakeup flag.

This bit is always read as 0.

0: No effect 1: Clear the WUF Wakeup Flag after 2 System clock cycles. (write)

Bit 1 PDDS: Power down deepsleep.

This bit is set and cleared by software. It works together with the LPDS bit.

0: Enter Stop mode when the CPU enters Deepsleep. The regulator status depends on the LPDS bit. 1: Enter Standby mode when the CPU enters Deepsleep.

Bit 0 LPDS: Low-power deepsleep.

This bit is set and cleared by software. It works together with the PDDS bit.

0: Voltage regulator on during Stop mode 1: Voltage regulator in low-power mode during Stop mode

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Power control (PWR) RM0008

5.4.2 Power control/status register (PWR_CSR)

Address offset: 0x04

Reset value: 0x0000 0000 (not reset by wakeup from Standby mode)

Additional APB cycles are needed to read this register versus a standard APB read.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

1514131211109876543210

Reserved

EWUP

rw r r r

Bits 31:9 Reserved, must be kept at reset value.

Bit 8 EWUP: Enable WKUP pin

This bit is set and cleared by software.

0: WKUP pin is used for general purpose I/O. An event on the WKUP pin does not wakeup the device from Standby mode.

1: WKUP pin is used for wakeup from Standby mode and forced in input pull down configuration (rising edge on WKUP pin wakes-up the system from Standby mode).

Note: This bit is reset by a system Reset.

Reserved

PVDO SBF WUF

Bits 7:3 Reserved, must be kept at reset value.

Bit 2 PVDO: PVD output

This bit is set and cleared by hardware. It is valid only if PVD is enabled by the PVDE bit.

0: V 1: V

DD/VDDA

is higher than the PVD threshold selected with the PLS[2:0] bits. is lower than the PVD threshold selected with the PLS[2:0] bits.

Note: The PVD is stopped by Standby mode. For this reason, this bit is equal to 0 after

Standby or reset until the PVDE bit is set.

Bit 1 SBF: Standby flag

This bit is set by hardware and cleared only by a POR/PDR (power on reset/power down reset) or by setting the CSBF bit in the Power control register (PWR_CR)

0: Device has not been in Standby mode 1: Device has been in Standby mode

Bit 0 WUF: Wakeup flag

This bit is set by hardware and cleared by hardware, by a system reset or by setting the CWUF bit in the Power control register (PWR_CR) 0: No wakeup event occurred 1: A wakeup event was received from the WKUP pin or from the RTC alarm

Note: An additional wakeup event is detected if the WKUP pin is enabled (by setting the

EWUP bit) when the WKUP pin level is already high.

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RM0008 Power control (PWR)

5.4.3 PWR register map

The following table summarizes the PWR registers.

Table 16. PWR register map and reset values

Offset Register

0x000

PWR_CR

Reset value 000000000

0x004

PWR_CSR

Reset value 0 0 0 0

Refer to Table 3 on page 51 for the register boundary addresses.

31302928272625242322212019181716151413

Reserved

121110

987654321

PLS [2:0]

DBP

Reserved

EWUP

CSBF

PVDE

CWUF

PVDO

LPDS

PDDS

SBF

WUF

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Backup registers (BKP) RM0008

6 Backup registers (BKP)

Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx

microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.

Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.

High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.

XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 768 Kbytes and 1 Mbyte.

Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.

This section applies to the whole STM32F101xx family, unless otherwise specified.

6.1 BKP introduction

The backup registers are forty two 16-bit registers for storing 84 bytes of user application data.

They are implemented in the backup domain that remains powered on by V V

power is switched off. They are not reset when the device wakes up from Standby

mode or by a system reset or power reset.

In addition, the BKP control registers are used to manage the Tamper detection feature and RTC calibration.

After reset, access to the Backup registers and RTC is disabled and the Backup domain (BKP) is protected against possible parasitic write access. To enable access to the Backup registers and the RTC, proceed as follows:

• enable the power and backup interface clocks by setting the PWREN and BKPEN bits

in the RCC_APB1ENR register

• set the DBP bit the Power Control Register (PWR_CR) to enable access to the Backup

registers and RTC.

6.2 BKP main features

• 20-byte data registers (in medium-density and low-density devices) or 84-byte data

registers (in high-density, XL-density and connectivity line devices)

• Status/control register for managing tamper detection with interrupt capability

• Calibration register for storing the RTC calibration value

• Possibility to output the RTC Calibration Clock, RTC Alarm pulse or Second pulse on

TAMPER pin PC13 (when this pin is not used for tamper detection)

when the

BAT

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RM0008 Backup registers (BKP)

6.3 BKP functional description

6.3.1 Tamper detection

The TAMPER pin generates a Tamper detection event when the pin changes from 0 to 1 or from 1 to 0 depending on the TPAL bit in the Backup control register (BKP_CR). A tamper detection event resets all data backup registers.

However to avoid losing Tamper events, the signal used for edge detection is logically ANDed with the Tamper enable in order to detect a Tamper event in case it occurs before the TAMPER pin is enabled.

• When TPAL=0: If the TAMPER pin is already high before it is enabled (by setting TPE

bit), an extra Tamper event is detected as soon as the TAMPER pin is enabled (while there was no rising edge on the TAMPER pin after TPE was set)

• When TPAL=1: If the TAMPER pin is already low before it is enabled (by setting the

TPE bit), an extra Tamper event is detected as soon as the TAMPER pin is enabled (while there was no falling edge on the TAMPER pin after TPE was set)

By setting the TPIE bit in the BKP_CSR register, an interrupt is generated when a Tamper detection event occurs.

After a Tamper event has been detected and cleared, the TAMPER pin should be disabled and then re-enabled with TPE before writing to the backup data registers (BKP_DRx) again. This prevents software from writing to the backup data registers (BKP_DRx), while the TAMPER pin value still indicates a Tamper detection. This is equivalent to a level detection on the TAMPER pin.

Note: Tamper detection is still active when V

of the data backup registers, the TAMPER pin should be externally tied to the correct level.

6.3.2 RTC calibration

For measurement purposes, the RTC clock with a frequency divided by 64 can be output on the TAMPER pin. This is enabled by setting the CCO bit in the RTC clock calibration register

(BKP_RTCCR).

The clock can be slowed down by up to 121 ppm by configuring CAL[6:0] bits.

For more details about RTC calibration and how to use it to improve timekeeping accuracy, please refer to AN2604 "STM32F101xx and STM32F103xx RTC calibration”.

power is switched off. To avoid unwanted resetting

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Backup registers (BKP) RM0008

6.4 BKP registers

Refer to Section 2.1 on page 47 for a list of abbreviations used in register descriptions.

The peripheral registers can be accessed by half-words (16-bit) or words (32-bit).

6.4.1 Backup data register x (BKP_DRx) (x = 1 ..42)

Address offset: 0x04 to 0x28, 0x40 to 0xBC

Reset value: 0x0000 0000

15 14131211109876543210

D[15:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 15:0 D[15:0] Backup data

These bits can be written with user data.

Note: The BKP_DRx registers are not reset by a System reset or Power reset or when the

device wakes up from Standby mode. They are reset by a Backup Domain reset or by a TAMPER pin event (if the TAMPER pin function is activated).

6.4.2 RTC clock calibration register (BKP_RTCCR)

Address offset: 0x2C

Reset value: 0x0000 0000

1514131211109876543210

Reserved

Bits 15:10 Reserved, must be kept at reset value.

Bit 9 ASOS: Alarm or second output selection

When the ASOE bit is set, the ASOS bit can be used to select whether the signal output on the TAMPER pin is the RTC Second pulse signal or the Alarm pulse signal:

0: RTC Alarm pulse output selected 1: RTC Second pulse output selected

Note: This bit is reset only by a Backup domain reset.

ASOS ASOE CCO CAL[6:0]

rw rw rw rw rw rw rw rw rw rw

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RM0008 Backup registers (BKP)

Bit 8 ASOE: Alarm or second output enable

Setting this bit outputs either the RTC Alarm pulse signal or the Second pulse signal on the TAMPER pin depending on the ASOS bit. The output pulse duration is one RTC clock period. The TAMPER pin must not be enabled while the ASOE bit is set.

Note: This bit is reset only by a Backup domain reset.

Bit 7 CCO: Calibration clock output

0: No effect 1: Setting this bit outputs the RTC clock with a frequency divided by 64 on the TAMPER pin.

The TAMPER pin must not be enabled while the CCO bit is set in order to avoid unwanted Tamper detection.

Note: This bit is reset when the V

supply is powered off.

Bit 6:0 CAL[6:0]: Calibration value

This value indicates the number of clock pulses that will be ignored every 2^20 clock pulses. This allows the calibration of the RTC, slowing down the clock by steps of 1000000/2^20 PPM. The clock of the RTC can be slowed down from 0 to 121PPM.

6.4.3 Backup control register (BKP_CR)

Address offset: 0x30

Reset value: 0x0000 0000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

TPAL TPE

rw rw

Bits 15:2 Reserved, must be kept at reset value.

Bit 1 TPAL: TAMPER pin active level

0: A high level on the TAMPER pin resets all data backup registers (if TPE bit is set). 1: A low level on the TAMPER pin resets all data backup registers (if TPE bit is set).

Bit 0 TPE: TAMPER pin enable

0: The TAMPER pin is free for general purpose I/O 1: Tamper alternate I/O function is activated.

Note: Setting the TPAL and TPE bits at the same time is always safe, however resetting both at

the same time can generate a spurious Tamper event. For this reason it is recommended to change the TPAL bit only when the TPE bit is reset.

6.4.4 Backup control/status register (BKP_CSR)

Address offset: 0x34

Reset value: 0x0000 0000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

TIF TEF

rr rwww

Reserved

TPIE CTI CTE

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Backup registers (BKP) RM0008

Bits 15:10 Reserved, must be kept at reset value.

Bit 9 TIF: Tamper interrupt flag

This bit is set by hardware when a Tamper event is detected and the TPIE bit is set. It is cleared by writing 1 to the CTI bit (also clears the interrupt). It is also cleared if the TPIE bit is reset.

0: No Tamper interrupt 1: A Tamper interrupt occurred

Note: This bit is reset only by a system reset and wakeup from Standby mode.

Bit 8 TEF: Tamper event flag

This bit is set by hardware when a Tamper event is detected. It is cleared by writing 1 to the CTE bit.

0: No Tamper event 1: A Tamper event occurred

Note: A Tamper event resets all the BKP_DRx registers. They are held in reset as long as the

TEF bit is set. If a write to the BKP_DRx registers is performed while this bit is set, the value will not be stored.

Bits 7:3 Reserved, must be kept at reset value.

Bit 2 TPIE: TAMPER pin interrupt enable

0: Tamper interrupt disabled 1: Tamper interrupt enabled (the TPE bit must also be set in the BKP_CR register

Note: A Tamper interrupt does not wake up the core from low-power modes.

This bit is reset only by a system reset and wakeup from Standby mode.

Bit 1 CTI: Clear tamper interrupt

This bit is write only, and is always read as 0. 0: No effect 1: Clear the Tamper interrupt and the TIF Tamper interrupt flag.

Bit 0 CTE: Clear tamper event

This bit is write only, and is always read as 0. 0: No effect 1: Reset the TEF Tamper event flag (and the Tamper detector)

6.4.5 BKP register map

BKP registers are mapped as 16-bit addressable registers as described in the table below:

Offset Register

0x00 Reserved

0x04

BKP_DR1

Reset value

85/1128 DocID13902 Rev 15

Table 17. BKP register map and reset values

31302928272625242322212019181716151413

Reserved

121110

987654321

D[15:0]

0000000000000000

Page 86

RM0008 Backup registers (BKP)

Table 17. BKP register map and reset values (continued)

Offset Register

0x08

0x0C

0x10

0x14

0x18

0x1C

0x20

BKP_DR2

Reset value

BKP_DR3

Reset value

BKP_DR4

Reset value

BKP_DR5

Reset value

BKP_DR6

Reset value

BKP_DR7

Reset value

BKP_DR8

Reset value

31302928272625242322212019181716151413

Reserved

0000000000000000

Reserved

0000000000000000

Reserved

0000000000000000

Reserved

0000000000000000

Reserved

0000000000000000

Reserved

0000000000000000

Reserved

0000000000000000

121110

987654321

D[15:0]

0x24

0x28

0x2

0x30

0x34

0x38 Reserved

0x3C Reserved

0x40

BKP_DR9

Reset value

BKP_DR10

Reset value

BKP_RTCCR

Reset value

BKP_CR

Reset value 00

BKP_CSR

Reset value 00 000

BKP_DR11

Reset value

Reserved

D[15:0]

0000000000000000

D[15:0]

0000000000000000

CAL[6:0]

ASOS

ASOE

CCO

0000000000

TPE

TPAL

TIF

D[15:0]

TEF

Reserved

TPIE

CTI

CTE

0000000000000000

DocID13902 Rev 15 86/1128

Page 87

Backup registers (BKP) RM0008

Table 17. BKP register map and reset values (continued)

Offset Register

0x44

0x48

0x4C

0x50

0x54

0x58

0x5C

BKP_DR12

Reset value

BKP_DR13

Reset value

BKP_DR14

Reset value

BKP_DR15

Reset value

BKP_DR16

Reset value

BKP_DR17

Reset value

BKP_DR18

Reset value

31302928272625242322212019181716151413

Reserved

0000000000000000

Reserved

0000000000000000

Reserved

0000000000000000

Reserved

0000000000000000

Reserved

0000000000000000

Reserved

0000000000000000

Reserved

0000000000000000

121110

987654321

D[15:0]

0x60 BKP_DR19

Reset value

0x64

0x68

0x6C

0x70

0x74

0x78

BKP_DR20

Reset value

BKP_DR21

Reset value

BKP_DR22

Reset value 0000000000000000

BKP_DR23

Reset value 0000000000000000

BKP_DR24

Reset value

BKP_DR25

Reset value

Reserved

D[15:0]

0000000000000000

D[15:0]

0000000000000000

D[15:0]

0000000000000000

D[15:0]

0000000000000000

D[15:0]

0000000000000000

87/1128 DocID13902 Rev 15

Page 88

RM0008 Backup registers (BKP)

Table 17. BKP register map and reset values (continued)

Offset Register

0x7C

0x80

0x84

0x88 BKP_DR29

0x8C

0x90

0x94

BKP_DR26

Reset value

BKP_DR27

Reset value

BKP_DR28

Reset value

BKP_DR30

Reset value

BKP_DR31

Reset value

BKP_DR32

Reset value

31302928272625242322212019181716151413

Reserved

0000000000000000

Reserved

0000000000000000

Reserved

0000000000000000

Reserved

0000000000000000

Reserved

0000000000000000

Reserved

0000000000000000

Reserved

0000000000000000

121110

987654321

D[15:0]

0x98

0x9C

0xA0

0xA4

0xA8

0xAC

0xB0 BKP_DR39

BKP_DR33

Reset value

BKP_DR34

Reset value

BKP_DR35

Reset value

BKP_DR36

Reset value 0000000000000000

BKP_DR37

Reset value 0000000000000000

BKP_DR38

Reset value

Reserved

D[15:0]

0000000000000000

D[15:0]

0000000000000000

D[15:0]

0000000000000000

D[15:0]

0000000000000000

D[15:0]

0000000000000000

DocID13902 Rev 15 88/1128

Page 89

Backup registers (BKP) RM0008

Table 17. BKP register map and reset values (continued)

Offset Register

0xB4

0xB8 BKP_DR41

0xBC

BKP_DR40

Reset value

BKP_DR42

Reset value

Refer to Table 3 on page 51 for the register boundary addresses.

31302928272625242322212019181716151413

Reserved

0000000000000000

Reserved

0000000000000000

Reserved

0000000000000000

121110

987654321

D[15:0]

89/1128 DocID13902 Rev 15

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RM0008 Low-, medium-, high- and XL-density reset and clock control (RCC)

7 Low-, medium-, high- and XL-density reset and clock

control (RCC)

Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx

microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.

Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.

High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.

XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 768 Kbytes and 1 Mbyte.

Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.

This Section applies to low-, medium-, high- and XL-density STM32F10xxx devices. Connectivity line devices are discussed in a separate section (refer to Connectivity line

devices: reset and clock control (RCC) on page 123).

7.1 Reset

There are three types of reset, defined as system reset, power reset and backup domain reset.

7.1.1 System reset

A system reset sets all registers to their reset values except the reset flags in the clock controller CSR register and the registers in the Backup domain (see Figure 4).

A system reset is generated when one of the following events occurs:

1. A low level on the NRST pin (external reset)

2. Window watchdog end of count condition (WWDG reset)

3. Independent watchdog end of count condition (IWDG reset)

4. A software reset (SW reset) (see Software reset)

5. Low-power management reset (see Low-power management reset)

The reset source can be identified by checking the reset flags in the Control/Status register, RCC_CSR (see Section 7.3.10: Control/status register (RCC_CSR)).

Software reset

The SYSRESETREQ bit in Cortex®-M3 Application Interrupt and Reset Control Register must be set to force a software reset on the device. Refer to the STM32F10xxx Cortex

programming manual (see Related documents on page 1) for more details.

-M3

DocID13902 Rev 15 90/1128

122

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Low-, medium-, high- and XL-density reset and clock control (RCC) RM0008

1567

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There are two ways to generate a low-power management reset:

1. Reset generated when entering Standby mode:

This type of reset is enabled by resetting nRST_STDBY bit in User Option Bytes. In this case, whenever a Standby mode entry sequence is successfully executed, the device is reset instead of entering Standby mode.

2. Reset when entering Stop mode:

This type of reset is enabled by resetting nRST_STOP bit in User Option Bytes. In this case, whenever a Stop mode entry sequence is successfully executed, the device is reset instead of entering Stop mode.

For further information on the User Option Bytes, refer to the STM32F10xxx Flash programming manual.

7.1.2 Power reset

A power reset is generated when one of the following events occurs:

1. Power-on/power-down reset (POR/PDR reset)

2. When exiting Standby mode

A power reset sets all registers to their reset values except the Backup domain (see

Figure 4)

These sources act on the NRST pin and it is always kept low during the delay phase. The RESET service routine vector is fixed at address

0x0000_0004 in the memory map.

The system reset signal provided to the device is output on the NRST pin. The pulse generator guarantees a minimum reset pulse duration of 20 µs for each reset source (external or internal reset). In case of an external reset, the reset pulse is generated while the NRST pin is asserted low.

Figure 7. Simplified diagram of the reset circuit

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RM0008 Low-, medium-, high- and XL-density reset and clock control (RCC)

7.1.3 Backup domain reset

The backup domain has two specific resets that affect only the backup domain (see

Figure 4).

A backup domain reset is generated when one of the following events occurs:

1. Software reset, triggered by setting the BDRST bit in the Backup domain control

2. V

or V

power on, if both supplies have previously been powered off.

BAT

7.2 Clocks

Three different clock sources can be used to drive the system clock (SYSCLK):

• HSI oscillator clock

• HSE oscillator clock

• PLL clock

The devices have the following two secondary clock sources:

• 40 kHz low speed internal RC (LSI RC) which drives the independent watchdog and

optionally the RTC used for Auto-wakeup from Stop/Standby mode.

• 32.768 kHz low speed external crystal (LSE crystal) which optionally drives the real-

time clock (RTCCLK)

Each clock source can be switched on or off independently when it is not used, to optimize power consumption.

DocID13902 Rev 15 92/1128

122

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Low-, medium-, high- and XL-density reset and clock control (RCC) RM0008

Figure 8. Clock tree

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1. When the HSI is used as a PLL clock input, the maximum system clock frequency that can be achieved is 64 MHz.

2. For full details about the internal and external clock source characteristics, please refer to the “Electrical characteristics” section in your device datasheet.

Several prescalers allow the configuration of the AHB frequency, the high speed APB (APB2) and the low speed APB (APB1) domains. The maximum frequency of the AHB and the APB2 domains is 72 MHz. The maximum allowed frequency of the APB1 domain is 36 MHz. The SDIO AHB interface is clocked with a fixed frequency equal to HCLK/2

The RCC feeds the Cortex

System Timer (SysTick) external clock with the AHB clock (HCLK) divided by 8. The SysTick can work either with this clock or with the Cortex (HCLK), configurable in the SysTick Control and Status Register. The ADCs are clocked by the clock of the High Speed domain (APB2) divided by 2, 4, 6 or 8.

The Flash memory programming interface clock (FLITFCLK) is always the HSI clock.

93/1128 DocID13902 Rev 15

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clock

Page 94

RM0008 Low-, medium-, high- and XL-density reset and clock control (RCC)

OSC_OUT

External

source

(HiZ)

OSC_IN OSC_OUT

Load

capacitors

The timer clock frequencies are automatically fixed by hardware. There are two cases:

1. if the APB prescaler is 1, the timer clock frequencies are set to the same frequency as

that of the APB domain to which the timers are connected.

2. otherwise, they are set to twice (×2) the frequency of the APB domain to which the

timers are connected.

FCLK acts as Cortex

-M3’s free-running clock. For more details refer to the ARM®

Cortex™-M3 r1p1 Technical Reference Manual (TRM).

7.2.1 HSE clock

The high speed external clock signal (HSE) can be generated from two possible clock sources:

• HSE external crystal/ceramic resonator

• HSE user external clock

The resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. The loading capacitance values must be adjusted according to the selected oscillator.

Clock source Hardware configuration

Figure 9. HSE/ LSE clock sources

External clock

Crystal/Ceramic

resonators

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Low-, medium-, high- and XL-density reset and clock control (RCC) RM0008

External source (HSE bypass)

In this mode, an external clock source must be provided. It can have a frequency of up to 25 MHz. You select this mode by setting the HSEBYP and HSEON

cycle has to drive the OSC_IN pin while the OSC_OUT pin should be left hi-Z. See Figure 9.

bits in the Clock control

External crystal/ceramic resonator (HSE crystal)

The 4 to 16 MHz external oscillator has the advantage of producing a very accurate rate on the main clock.

The associated hardware configuration is shown in Figure 9. Refer to the electrical characteristics section of the datasheet for more details.

The HSERDY flag in the Clock control register (RCC_CR) indicates if the high-speed external oscillator is stable or not. At startup, the clock is not released until this bit is set by hardware. An interrupt can be generated if enabled in the Clock interrupt register

(RCC_CIR).

The HSE Crystal can be switched on and off using the HSEON bit in the Clock control

7.2.2 HSI clock

The HSI clock signal is generated from an internal 8 MHz RC Oscillator and can be used directly as a system clock or divided by 2 to be used as PLL input.

The HSI RC oscillator has the advantage of providing a clock source at low cost (no external components). It also has a faster startup time than the HSE crystal oscillator however, even with calibration the frequency is less accurate than an external crystal oscillator or ceramic resonator.

Calibration

RC oscillator frequencies can vary from one chip to another due to manufacturing process variations, this is why each device is factory calibrated by ST for 1% accuracy at T

After reset, the factory calibration value is loaded in the HSICAL[7:0] bits in the Clock control

If the application is subject to voltage or temperature variations this may affect the RC oscillator speed. You can trim the HSI frequency in the application using the HSITRIM[4:0] bits in the Clock control register (RCC_CR).

The HSIRDY flag in the Clock control register (RCC_CR) indicates if the HSI RC is stable or not. At startup, the HSI RC output clock is not released until this bit is set by hardware.

The HSI RC can be switched on and off using the HSION bit in the Clock control register

(RCC_CR).

The HSI signal can also be used as a backup source (Auxiliary clock) if the HSE crystal oscillator fails. Refer to Section 7.2.7: Clock security system (CSS) on page 97.

=25°C.

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RM0008 Low-, medium-, high- and XL-density reset and clock control (RCC)

7.2.3 PLL

The internal PLL can be used to multiply the HSI RC output or HSE crystal output clock frequency. Refer to Figure 8 and Clock control register (RCC_CR).

The PLL configuration (selection of HSI oscillator divided by 2 or HSE oscillator for PLL input clock, and multiplication factor) must be done before enabling the PLL. Once the PLL enabled, these parameters cannot be changed.

An interrupt can be generated when the PLL is ready if enabled in the Clock interrupt

If the USB interface is used in the application, the PLL must be programmed to output 48 or 72 MHz. This is needed to provide a 48 MHz USBCLK.

7.2.4 LSE clock

The LSE crystal is a 32.768 kHz Low Speed External crystal or ceramic resonator. It has the advantage providing a low-power but highly accurate clock source to the real-time clock peripheral (RTC) for clock/calendar or other timing functions.

The LSE crystal is switched on and off using the LSEON bit in Backup domain control

The LSERDY flag in the Backup domain control register (RCC_BDCR) indicates if the LSE crystal is stable or not. At startup, the LSE crystal output clock signal is not released until this bit is set by hardware. An interrupt can be generated if enabled in the Clock interrupt

External source (LSE bypass)

In this mode, an external clock source must be provided. It can have a frequency of up to 1 MHz. You select this mode by setting the LSEBYP and LSEON bits in the Backup domain

control register (RCC_BDCR). The external clock signal (square, sinus or triangle) with

~50% duty cycle has to drive the OSC32_IN pin while the OSC32_OUT pin should be left Hi-Z. See Figure 9.

7.2.5 LSI clock

The LSI RC acts as an low-power clock source that can be kept running in Stop and Standby mode for the independent watchdog (IWDG) and Auto-wakeup unit (AWU). The clock frequency is around 40 kHz (between 30 kHz and 60 kHz). For more details, refer to the electrical characteristics section of the datasheets.

The LSI RC can be switched on and off using the LSION bit in the Control/status register

(RCC_CSR).

The LSIRDY flag in the Control/status register (RCC_CSR) indicates if the low-speed internal oscillator is stable or not. At startup, the clock is not released until this bit is set by hardware. An interrupt can be generated if enabled in the Clock interrupt register

(RCC_CIR).

Note: LSI calibration is only available on high-density, XL-density and connectivity line devices.

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Low-, medium-, high- and XL-density reset and clock control (RCC) RM0008

LSI calibration

The frequency dispersion of the Low Speed Internal RC (LSI) oscillator can be calibrated to have accurate RTC time base and/or IWDG timeout (when LSI is used as clock source for these peripherals) with an acceptable accuracy.

This calibration is performed by measuring the LSI clock frequency with respect to TIM5 input clock (TIM5CLK). According to this measurement done at the precision of the HSE oscillator, the software can adjust the programmable 20-bit prescaler of the RTC to get an accurate time base or can compute accurate IWDG timeout.

Use the following procedure to calibrate the LSI:

1. Enable TIM5 timer and configure channel4 in input capture mode

2. Set the TIM5CH4_IREMAP bit in the AFIO_MAPR register to connect the LSI clock

internally to TIM5 channel4 input capture for calibration purpose.

3. Measure the frequency of LSI clock using the TIM5 Capture/compare 4 event or

interrupt.

4. Use the measured LSI frequency to update the 20-bit prescaler of the RTC depending

on the desired time base and/or to compute the IWDG timeout.

7.2.6 System clock (SYSCLK) selection

After a system reset, the HSI oscillator is selected as system clock. When a clock source is used directly or through the PLL as system clock, it is not possible to stop it.

A switch from one clock source to another occurs only if the target clock source is ready (clock stable after startup delay or PLL locked). If a clock source which is not yet ready is selected, the switch will occur when the clock source will be ready. Status bits in the Clock

control register (RCC_CR) indicate which clock(s) is (are) ready and which clock is currently

used as system clock.

7.2.7 Clock security system (CSS)

Clock Security System can be activated by software. In this case, the clock detector is enabled after the HSE oscillator startup delay, and disabled when this oscillator is stopped.

If a failure is detected on the HSE clock, the HSE oscillator is automatically disabled, a clock failure event is sent to the break input of the advanced-control timers (TIM1 and TIM8) and an interrupt is generated to inform the software about the failure (Clock Security System Interrupt CSSI), allowing the MCU to perform rescue operations. The CSSI is linked to the

Cortex

Note: Once the CSS is enabled and if the HSE clock fails, the CSS interrupt occurs and an NMI is

automatically generated. The NMI will be executed indefinitely unless the CSS interrupt pending bit is cleared. As a consequence, in the NMI ISR user must clear the CSS interrupt by setting the CSSC bit in the Clock interrupt register (RCC_CIR).

If the HSE oscillator is used directly or indirectly as the system clock (indirectly means: it is used as PLL input clock, and the PLL clock is used as system clock), a detected failure causes a switch of the system clock to the HSI oscillator and the disabling of the HSE oscillator. If the HSE clock (divided or not) is the clock entry of the PLL used as system clock when the failure occurs, the PLL is disabled too.

-M3 NMI (Non-Maskable Interrupt) exception vector.

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RM0008 Low-, medium-, high- and XL-density reset and clock control (RCC)

7.2.8 RTC clock

The RTCCLK clock source can be either the HSE/128, LSE or LSI clocks. This is selected by programming the RTCSEL[1:0] bits in the Backup domain control register (RCC_BDCR). This selection cannot be modified without resetting the Backup domain.

The LSE clock is in the Backup domain, whereas the HSE and LSI clocks are not. Consequently:

• If LSE is selected as RTC clock:

– The RTC continues to work even if the V

supply is maintained.

BAT

• If LSI is selected as Auto-Wakeup unit (AWU) clock:

– The AWU state is not guaranteed if the V

Section 7.2.5: LSI clock on page 96 for more details on LSI calibration.

• If the HSE clock divided by 128 is used as the RTC clock:

– The RTC state is not guaranteed if the V

voltage regulator is powered off (removing power from the 1.8 V domain).

– The DPB bit (disable backup domain write protection) in the Power controller

(PWR_CR)).

supply is switched off, provided the

supply is powered off. Refer to

supply is powered off or if the internal

7.2.9 Watchdog clock

If the Independent watchdog (IWDG) is started by either hardware option or software access, the LSI oscillator is forced ON and cannot be disabled. After the LSI oscillator temporization, the clock is provided to the IWDG.

7.2.10 Clock-out capability

The microcontroller clock output (MCO) capability allows the clock to be output onto the external MCO pin. The configuration registers of the corresponding GPIO port must be programmed in alternate function mode. One of 4 clock signals can be selected as the MCO clock.

• SYSCLK

• HSI

• HSE

• PLL clock divided by 2

The selection is controlled by the MCO[2:0] bits of the Clock configuration register

(RCC_CFGR).

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Low-, medium-, high- and XL-density reset and clock control (RCC) RM0008

7.3 RCC registers

Refer to Section 2.1 on page 47 for a list of abbreviations used in register descriptions.

7.3.1 Clock control register (RCC_CR)

Address offset: 0x00

Reset value: 0x0000 XX83 where X is undefined.

Access: no wait state, word, half-word and byte access

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

rrrrrrr rrwrwrwrwrw rrw

PLL

PLLON

Reserved

HSICAL[7:0] HSITRIM[4:0]

RDY

rrw rwrwrrw

Bits 31:26 Reserved, must be kept at reset value.

Bit 25 PLLRDY: PLL clock ready flag

Set by hardware to indicate that the PLL is locked. 0: PLL unlocked 1: PLL locked

Reserved

CSS ONHSE

BYP

Res.

HSE RDY

HSI

RDY

HSE

HSION

Bit 24 PLLON: PLL enable

Set and cleared by software to enable PLL. Cleared by hardware when entering Stop or Standby mode. This bit can not be reset if the PLL clock is used as system clock or is selected to become the system clock. 0: PLL OFF 1: PLL ON

Bits 23:20 Reserved, must be kept at reset value.

Bit 19 CSSON: Clock security system enable

Set and cleared by software to enable the clock security system. When CSSON is set, the clock detector is enabled by hardware when the HSE oscillator is ready, and disabled by hardware if a HSE clock failure is detected.

0: Clock detector OFF 1: Clock detector ON (Clock detector ON if the HSE oscillator is ready , OFF if not).

Bit 18 HSEBYP: External high-speed clock bypass

Set and cleared by software to bypass the oscillator with an external clock. The external clock must be enabled with the HSEON bit set, to be used by the device. The HSEBYP bit can be written only if the HSE oscillator is disabled.

0: external 4-16 MHz oscillator not bypassed 1: external 4-16 MHz oscillator bypassed with external clock

Bit 17 HSERDY: External high-speed clock ready flag

Set by hardware to indicate that the HSE oscillator is stable. This bit needs 6 cycles of the HSE oscillator clock to fall down after HSEON reset. 0: HSE oscillator not ready 1: HSE oscillator ready

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RM0008 Low-, medium-, high- and XL-density reset and clock control (RCC)

Bit 16 HSEON: HSE clock enable

Set and cleared by software. Cleared by hardware to stop the HSE oscillator when entering Stop or Standby mode. This bit cannot be reset if the HSE oscillator is used directly or indirectly as the system clock. 0: HSE oscillator OFF 1: HSE oscillator ON

Bits 15:8 HSICAL[7:0]: Internal high-speed clock calibration

These bits are initialized automatically at startup.

Bits 7:3 HSITRIM[4:0]: Internal high-speed clock trimming

These bits provide an additional user-programmable trimming value that is added to the HSICAL[7:0] bits. It can be programmed to adjust to variations in voltage and temperature that influence the frequency of the internal HSI RC.

The default value is 16, which, when added to the HSICAL value, should trim the HSI to 8 MHz ± 1%. The trimming step (F steps.

Bit 2 Reserved, must be kept at reset value.

Bit 1 HSIRDY: Internal high-speed clock ready flag

Set by hardware to indicate that internal 8 MHz RC oscillator is stable. After the HSION bit is cleared, HSIRDY goes low after 6 internal 8 MHz RC oscillator clock cycles.

0: internal 8 MHz RC oscillator not ready 1: internal 8 MHz RC oscillator ready

Bit 0 HSION: Internal high-speed clock enable

Set and cleared by software. Set by hardware to force the internal 8 MHz RC oscillator ON when leaving Stop or Standby

mode or in case of failure of the external 4-16 MHz oscillator used directly or indirectly as system clock. This bit cannot be reset if the internal 8 MHz RC is used directly or indirectly as system clock or is selected to become the system clock. 0: internal 8 MHz RC oscillator OFF 1: internal 8 MHz RC oscillator ON

) is around 40 kHz between two consecutive HSICAL

hsitrim

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